JP2017122625A - Data logging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data logging device with which it is possible to achieve the downsizing of the device and the flexibility of data logging.SOLUTION: The data logging device includes: a first semiconductor chip in which is formed an integrated circuit where an amplifier for amplifying a sensor signal outputted from a sensor, an analog-digital converter for converting the sensor signal amplified by the amplifier into a digital signal, a recording control logic circuit for controlling the recording of a digital value, and a communication control logic circuit for controlling communication to and from an external device are integrated; a memory constituted as a separate entity from the first semiconductor chip, in which digital values are recorded under control of the recording control logic circuit; a communication module for communicating with the external device under control by the communication control logic circuit, and constituted as a separate entity from the first semiconductor chip; and a central arithmetic processing device for giving a command to the recording control logic circuit.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a data recording apparatus.

  There is known a data recording device that converts a sensor signal, which is an analog signal output from a sensor, into a digital value and records the value in a memory. For example, Patent Document 1 describes a data recording device that records a signal input by a signal input unit in a storage unit when a trigger signal supplied from the outside is detected.

  Also, an integrated circuit is known in which an analog circuit block, an analog / digital converter, a memory, a CPU, a communication interface, and the like are integrated into one chip and an internal circuit can be changed (for example, Non-Patent Document 1, Non-Patent Document 1, Non-Patent Document 1, Patent Document 2).

JP 2005-274223 A

Smart Analog MCU (RL78 / G1E), [online], [Search September 2, 2015], Internet <URL: http://japan.renesas.com/products/smart_analog/smart_analog_mcu/index.jsp> PSoC 5LP: CY8C58LP Family Datasheet, [online], July 15, 2015, [Search September 2, 2015], Internet <URL: http://japan.cypress.com/file/45906/download>

  As in the integrated circuits disclosed in Non-Patent Documents 1 and 2, by making a plurality of circuit blocks into one chip, it is possible to reduce the size of the device. However, since many functional elements are included in one chip, the number and capacity of individual elements are small. Therefore, the individual functional elements only hold general processing functions, and data as a data recording device It is difficult to configure various functions of recording and to increase the number of channels. Further, when all functions are accommodated in one chip, it is difficult to flexibly cope with an increase in data recording capacity, that is, an increase in memory capacity and an increase in memory elements. Furthermore, it is difficult to flexibly cope with changes in communication specifications such as higher communication speed and lower power consumption. Further, in an integrated circuit having a variable circuit configuration as described in Non-Patent Document 2, redundancy by a programmable switch element or the like is given to a detailed element inside the integrated circuit, and as a result, circuit area and consumption are increased. Power increases.

  The present invention has been made in view of the above points, and provides a data recording apparatus capable of achieving both the downsizing of the apparatus and the flexibility and expandability of the apparatus configuration in accordance with various data recording needs. For the purpose.

  A data recording apparatus according to the present invention controls an amplifier that amplifies a sensor signal output from a sensor, an analog / digital converter that converts the sensor signal amplified by the amplifier into a digital value, and records the digital value A first semiconductor chip on which an integrated circuit in which a recording control logic circuit and a communication control logic circuit for controlling communication with an external device are integrated is formed separately from the first semiconductor chip; and A memory in which the digital value is recorded under the control of the recording control logic circuit and the first semiconductor chip are configured separately from each other, and communicates with the external device under the control of the communication control logic circuit. And a central processing unit for giving a command to the recording control logic circuit.

  The central processing unit may be formed on the first semiconductor chip, or may be formed on a second semiconductor chip different from the first semiconductor chip.

  In the case where the central processing unit is formed on a second semiconductor chip different from the first semiconductor chip, the memory is a third different from the first semiconductor chip and the second semiconductor chip. The first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are different regions of at least one substrate in a bare chip state that is not covered with a mold resin. It may be mounted on. The first semiconductor chip, the second semiconductor chip, and the third semiconductor chip may be mounted on different substrate surfaces, or may be mounted on the same substrate surface. The first semiconductor chip and the second semiconductor chip are mounted on a first substrate surface, and the third semiconductor chip is mounted on a second substrate surface different from the first substrate surface. May be. The first substrate surface and the second substrate surface may be provided on a single substrate, the first substrate surface is provided on the first substrate, and the second substrate surface is The first substrate may be provided on a second substrate different from the first substrate. The data recording apparatus may be configured by stacking a substrate on which the first semiconductor chip and the second semiconductor chip are mounted and a plurality of substrates each having the third semiconductor chip mounted thereon.

  In the case where the central processing unit is formed on the first semiconductor chip, the memory is formed on a third semiconductor chip different from the first semiconductor chip, and the first semiconductor chip and the first semiconductor chip The third semiconductor chips may be mounted in different regions of at least one substrate in a bare chip state that is not covered with the mold resin. Further, the first semiconductor chip and the third semiconductor chip may be mounted on different substrate surfaces, or may be mounted on the same substrate surface.

  Note that the number of the first semiconductor chip and the third semiconductor chip need not be single, and may be increased as necessary. For example, a plurality of first semiconductor chips may be juxtaposed on the first substrate surface. Further, a plurality of substrates each mounting the first semiconductor chip may be stacked. Similarly, a plurality of substrates each mounting a third semiconductor chip may be stacked.

  The integrated circuit further includes a plurality of amplifiers that amplify each of a plurality of sensor signals output from each of a plurality of sensors, and each of the plurality of sensor signals amplified by each of the plurality of amplifiers is the analog. Can be supplied to a digital converter. The integrated circuit may further include a multiplexer that sequentially supplies each of the plurality of sensor signals amplified by each of the plurality of amplifiers to the analog-to-digital converter. The integrated circuit may further include a plurality of filters that remove a predetermined frequency component from each of the plurality of sensor signals amplified by each of the plurality of amplifiers.

  The integrated circuit may have an input port for receiving an input of a trigger signal supplied from the outside. In this case, the recording control logic circuit may start or stop recording the digital value in the memory in accordance with the trigger signal.

  The trigger signal may include additional information. When recording the digital value in the memory in response to the trigger signal, the recording control logic circuit may add the additional information corresponding to each of the digital values and record it in the memory.

  The recording control logic circuit may record status information indicating continuation, interruption, and termination of recording of the digital value in the memory together with the digital value in the memory.

  The recording control logic circuit may control a recording order of the plurality of digital values sequentially supplied from the analog / digital converter to the memory.

  The data recording apparatus according to the present invention may further include a plurality of registers provided corresponding to the amplifier, the filter, the multiplexer, and the analog / digital converter. The amplifier may amplify the sensor signal with an amplification degree corresponding to a set value set in a corresponding register among the plurality of registers. The filter may filter the sensor signal with a frequency characteristic corresponding to a set value set in a corresponding register among the plurality of registers. The multiplexer may supply the sensor signal to the analog / digital converter in an order corresponding to a set value set in a corresponding register among the plurality of registers. The analog / digital converter may convert the sensor signal into a digital value at a cycle according to a set value set in a corresponding register among the plurality of registers.

  A data recording apparatus according to the present invention is provided corresponding to the power supply circuit and at least one power supply circuit for supplying power to each of the amplifier, the filter, the multiplexer, and the analog / digital converter. And a power supply control register. The power supply circuit may be turned on / off in accordance with a set value set in the power supply control register.

  According to the data recording apparatus of the present invention, it is possible to achieve both the downsizing of the apparatus and the flexibility and expandability of the apparatus configuration in accordance with various data recording needs.

1 is a perspective view showing a schematic configuration of a data recording apparatus according to an embodiment of the present invention. It is a circuit block diagram which shows an example of the circuit structure of the data recording device which concerns on embodiment of this invention. It is a circuit block diagram which shows the power supply structure of the instrumentation amplifier which concerns on embodiment of this invention, a low-pass filter, a multiplexer, and AD converter. It is a circuit block diagram which shows the structure for implement | achieving the setting change regarding the characteristic, function, or operation | movement of the instrumentation amplifier which concerns on embodiment of this invention, a low-pass filter, a multiplexer, and AD converter. It is a circuit block diagram which shows an example of the circuit structure of the data recording device which concerns on embodiment of this invention. It is a circuit block diagram which shows an example of the circuit structure of the data recording device which concerns on embodiment of this invention. It is a perspective view which shows the structure of the outline of the data recording device which concerns on other embodiment of this invention. It is a perspective view which shows the structure of the outline of the data recording device which concerns on other embodiment of this invention. It is a perspective view which shows the structure of the outline of the data recording device which concerns on other embodiment of this invention. It is a perspective view which shows the structure of the outline of the data recording device which concerns on other embodiment of this invention. It is a circuit block diagram which shows an example of the circuit structure of the data recording device which concerns on other embodiment of this invention. It is a perspective view which shows the structure of the outline of the data recording device which concerns on other embodiment of this invention. It is a circuit block diagram which shows an example of the circuit structure of the data recording device which concerns on other embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals.

  FIG. 1 is a perspective view showing a schematic configuration of a data recording device 100 according to the first embodiment of the present invention. The data recording apparatus 100 includes an LSI (Large Scale Integration) 10, an RF (Radio Frequency) communication module 41, a UART (Universal Asynchronous Receiver Transmitter) 42, a CPU (Central Processing Unit) 50 and a memory 60 mounted on the wiring board 1. It is comprised including.

  Among the above components, the LSI 10, the CPU 50, and the memory 60 are configured on separate semiconductor chips and mounted on the wiring board 1 in a bare chip state that is not covered with a mold resin. The LSI 10, the CPU 50, and the memory 60 may be covered with a protective film made of resin or the like for protecting them from mechanical stress and thermal stress, respectively. The RF communication module 41 and the UART 42 are configured as package parts separate from the semiconductor chips constituting the LSI 10, the CPU 50 and the memory 60, and are mounted on the wiring board 1. Note that the RF communication module 41 and the UART 42 may be in a bare chip state. In the present embodiment, the LSI 10, the RF communication module 41, the UART 42 and the CPU 50 are mounted on the first substrate surface S 1 of the wiring substrate 1, and the memory 60 having a larger area than these is the first substrate surface of the wiring substrate 1. It is mounted on the second substrate surface S2 opposite to S1.

  The LSI 10, the RF communication module 41, the UART 42, the CPU 50, and the memory 60 are each connected to the wiring board 1 through bumps formed on the bonding surface with the wiring board 1. The wiring board 1 has a single-layer or multi-layer wiring layer, and each component mounted on the wiring board 1 is electrically connected to each other via a wiring formed on the wiring board 1. In addition, you may connect between each component mounted in the wiring board 1 with a wire. Or the wiring of the wiring board 1 may be directly connected to each bare chip terminal part.

  FIG. 2 is a circuit block diagram illustrating an example of a circuit configuration of the data recording device 100. In FIG. 2, a plurality of sensors 12 connected to the data recording device 100 are shown together with the data recording device 100.

  The data recording device 100 converts the sensor signal output from the sensor 12 into a digital value, records it in the memory 60, and responds to a request from an external device (for example, a personal computer that is communicably connected to the data recording device 100). Accordingly, the main function is to transmit the sensor signal value recorded in the memory 60 to the external device. Any sensor such as a pressure sensor, an acceleration sensor, a displacement sensor, and a voltage sensor can be used as the sensor 12 connected to the data recording apparatus 100.

  The LSI 10 integrates an instrumentation amplifier 21, a low-pass filter 22, a multiplexer 23, an analog / digital converter (hereinafter referred to as an AD converter) 24, a recording control logic circuit 30, and a communication control logic circuit 40 on a single semiconductor chip. Integrated circuit. For example, the LSI 10 has 16 sensor signal input channels, and can connect 16 sensors 12. The sensor signal output from each of the plurality of sensors 12 is input to the LSI 10 via the sensor signal input port 91.

  The instrumentation amplifier 21 and the low pass filter 22 are provided corresponding to each of the 16 sensors 12. Each of the instrumentation amplifiers 21 amplifies the sensor signal output from the corresponding sensor 12. The low pass filter 22 removes a high frequency component (noise) from the corresponding sensor signal amplified by the instrumentation amplifier 21. Note that the low-pass filter 22 may be omitted if the high-frequency component does not matter from the sensor signal.

  One multiplexer 23 and one AD converter 24 are provided for every four input channels. Each of the multiplexers 23 sequentially selects the sensor signals output from the corresponding four low-pass filters 22 and supplies the selected sensor signals to the AD converter 24.

  The AD converter 24 converts the sensor signal, which is an analog signal sequentially supplied from the multiplexer 23, into a digital value. The sensor signal value converted into a digital value by the AD converter 24 is supplied to the recording control logic circuit 30. The AD converter 24 is not shared by a plurality of input channels, but the AD converter 24 is provided for each input channel, and the corresponding AD converter 24 directly receives the sensor signal output from the low-pass filter 22. It is good also as a structure. In this case, the multiplexer 23 becomes unnecessary.

  The recording control logic circuit 30 performs various operations based on commands supplied from the CPU 50. The recording control logic circuit 30 operates by supplying control signals to the multiplexer 23 and the AD converter 24 when a command for data recording is issued from the CPU 50, and sequentially supplies them from the AD converter 24. The sensor signal value to be recorded is recorded in the memory 60. On the other hand, when a command to read data is issued from the CPU 50, the recording control logic circuit 30 reads the sensor signal value recorded in the memory 60, and causes the communication control logic circuit 40 and the RF communication module 41 or UART 42 to operate. The sensor signal value read out via is transmitted to the external device.

  The communication control logic circuit 40 is a circuit block that controls communication with an external device. For example, the communication control logic circuit 40 transmits the sensor signal value read from the memory 60 supplied from the recording control logic circuit 30 to the external device via the RF communication module 41 or the UART 42 according to a predetermined communication protocol. The communication control logic circuit 40 transmits a sensor signal value to an external device via one or both of the RF communication module 41 and the UART 42 based on a command from the CPU 50. Further, the communication control logic circuit 40 supplies a command and information supplied from an external device via the RF communication module 41 or the UART 42 to the CPU 50.

  The memory 60 is a recording medium for recording the sensor signal value output from the sensor 12 and converted into a digital value. The memory 60 is a nonvolatile recording medium in which data can be written, erased, and rewritten. The memory 60 may be, for example, a NAND flash memory. The memory 60 is configured as a semiconductor chip separate from the semiconductor chip constituting the LSI 10, and is connected to the recording control logic circuit 30 via the data input / output port 93 of the LSI 10.

  The RF communication module 41 is a communication module for performing wireless communication with an external device under the control of the communication control logic circuit 40. The RF communication module 41 can be configured as a separate package component from the semiconductor chip constituting the LSI 10. The RF communication module 41 is connected to the communication control logic circuit 40 via the communication port 95 of the LSI 10.

  The UART 42 is a communication module for performing wired communication with an external device under the control of the communication control logic circuit 40. The UART 42 has a function of mutually converting serial transfer type data and parallel transfer type data. The UART 42 can be configured as a separate package component from the semiconductor chip that constitutes the LSI 10. The UART 42 is connected to the communication control logic circuit 40 via the communication port 96 of the LSI 10. In the present embodiment, a configuration including both the RF communication module 41 and the UART 42 is illustrated as a communication module for performing communication with an external device, but a configuration including only one of the RF communication module 41 and the UART 42 is illustrated. It is good.

  The CPU 50 is a central processing unit that comprehensively controls the operation of the data recording device 100. The CPU 50 controls data recording and data reading by sending commands to the recording control logic circuit 30. Further, the CPU 50 controls communication with an external device by sending a command to the communication control logic circuit 40. The CPU 50 is configured as a semiconductor chip separate from the semiconductor chip that constitutes the LSI 10. The CPU 50 is connected to the communication control logic circuit 40 via the communication port 97 of the LSI 10, and is connected to the recording control logic circuit 30 via the communication port 98 of the LSI 10.

  Hereinafter, various functions provided in the data recording apparatus 100 will be described.

  The data recording apparatus 100 can perform a synchronization process for matching the stored data with an external device (for example, another data recording apparatus) connected via the communication port 92. .

  Further, the data recording apparatus 100 can control the timing of starting and stopping data recording from the outside by supplying the trigger signal St from the outside. The LSI 10 has a trigger signal input port 94 that receives an input of a trigger signal St supplied from an external device. The trigger signal St input to the LSI 10 via the port 94 is received by the recording control logic circuit 30. The recording control logic circuit 30 starts or stops recording of sensor signal values according to the received trigger signal St.

  The trigger signal St can include additional information, and this additional information can be recorded in the memory 60 together with the sensor signal value. Examples of the additional information include time information, environmental information such as temperature, humidity, and atmospheric pressure of an object sensed by the sensor 12 (hereinafter referred to as a sensing object), information on the state of the sensing object, and the like. For example, when the sensing object is a moving body that moves on a predetermined moving path, position information indicating the position of the sensing object on the moving path can be included in the trigger signal as additional information. The additional information may be a digital signal integrated with the trigger signal, and may be supplied to the data recording device 100 in the form of an optical signal or a wireless signal, for example.

  When recording the sensor signal value in the memory 60 in response to the trigger signal St including additional information, the recording control logic circuit 30 outputs additional information corresponding to each of the sensor signal values sequentially supplied from the AD converter 24. In addition, it is recorded in the memory 60. Thus, by including additional information in each sensor signal value recorded in the memory 60, it is possible to record additional information together with the sensor signal value at the time of acquisition of the sensor signal sequentially output from the sensor 12. Become. Note that a plurality of sensor signal values supplied from the AD converter 24 within a predetermined period may be recorded in the memory 60 as one data set by adding one common additional information. According to this aspect, the amount of data recorded in the memory 60 can be reduced as compared with the case where additional information is included in each sensor signal value.

  Further, the recording control logic circuit 30 records status information indicating continuation, interruption and end of recording of the sensor signal value supplied from the AD converter 24 in the memory 60 together with the sensor signal value. Commands relating to continuation, interruption and termination of recording of the sensor signal values in the memory 60 are supplied from the CPU 50 to the recording control logic circuit 30.

  The recording control logic circuit 30 adds status information indicating “continuing” of data recording to the sensor signal value supplied from the AD converter 24 while a command to continue data recording is issued from the CPU 50. Then, the sensor signal value is recorded in the memory 60. When a command to interrupt data recording is issued from the CPU 50, the recording control logic circuit 30 adds status information indicating “interruption” of data recording to the sensor signal value supplied from the AD converter 24, After the sensor signal value is recorded in the memory 60, data recording is interrupted. That is, status information indicating “interruption” of data recording is added to the sensor signal value recorded in the memory 60 immediately before interrupting data recording. The recording control logic circuit 30 adds status information indicating “end” of data recording to the sensor signal value supplied from the AD converter 24 when a command to end data recording is issued from the CPU 50. After the sensor signal value is recorded in the memory 60, data recording is terminated. That is, status information indicating “end” of data recording is added to the sensor signal value recorded in the memory 60 immediately before the end of data recording.

  Thus, by including status information in each sensor signal value recorded in the memory 60, it becomes possible to record the data recording history together with the sensor signal value. When recording the sensor signal value in the memory 60 in response to the trigger signal St including the additional information, the recording control logic circuit 30 generates a data set including one or more sensor signal values, additional information, and status information. Record in the memory 60. In this case, the CPU 50 determines continuation, interruption, and termination of data recording in cooperation with an external device that outputs the trigger signal St.

  Further, the recording control logic circuit 30 controls the recording order of the plurality of sensor signal values sequentially supplied from each of the AD converters 24 to the memory 60 based on a command from the CPU 50. That is, the recording control logic circuit 30 can record a plurality of sensor signal values in the memory 60 in an order different from the order supplied from each of the AD converters 24.

  FIG. 3 is a circuit block diagram showing the power supply configuration of the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23 and the AD converter 24 built in the LSI 10. The LSI 10 includes power supply circuits 21P, 22P, 23P, and 24P that supply power to the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24, respectively. The recording control logic circuit 30 has power control registers 31a, 31b, 31c and 31d corresponding to the power circuits 21P, 22P, 23P and 24P, respectively. The power supply circuits 21P, 22P, 23P and 24P are turned on / off according to the set values written in the registers 31a, 31b, 31c and 31d corresponding to the power circuits 21P, 22P, 23P and 24P. The recording control logic circuit 30 itself writes the set values to the registers 31a, 31b, 31c and 31d based on a command from the CPU 50. Note that the CPU 50 may directly write the set values to the registers 31a, 31b, 31c and 31d.

  Based on a command from the CPU 50, the recording control logic circuit 30 writes a set value for turning on the power supply circuits 21P, 22P, 23P, and 24P in the registers 31a, 31b, 31c, and 31d during the data recording period. As a result, during the data recording period, power is supplied to the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24, and these components become operable. On the other hand, the recording control logic circuit 30 sets the set values for turning off the power supply circuits 21P, 22P, 23P, and 24P during the period other than the data recording period based on a command from the CPU 50, in the registers 31a, 31b, 31c and Write to 31d. As a result, during the period other than the data recording period, power supply to the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24 is lost, and these components are stopped. Thus, power consumption can be suppressed by turning off the power supply circuits 21P, 22P, 23P, and 24P during periods other than the data recording period.

  In this embodiment, the registers 31a, 31b, 31c and 31d are arranged in the recording control logic circuit 30, but the present invention is not limited to this mode. For example, the registers 31a, 31b, 31c, and 31d may be disposed in the vicinity of the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24, respectively. In the present embodiment, the case where individual power supply circuits are provided for the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24 is illustrated, but the present invention is not limited to this mode. In other words, one power supply circuit and one register that are commonly used for the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24 may be provided.

  The instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24 built in the LSI 10 can be changed in settings regarding their characteristics, functions, and operations. FIG. 4 is a circuit block diagram showing a configuration for realizing a setting change regarding characteristics, functions, or operations of the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24.

  The recording control logic circuit 30 includes setting change registers 32a, 32b, 33c, and 33d corresponding to the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24, respectively.

  The instrumentation amplifier 21 amplifies the sensor signal with an amplification degree corresponding to the set value written in the register 32a. That is, the amplification degree of the instrumentation amplifier 21 can be changed according to the set value written to the register 32a.

  The low-pass filter 22 performs signal filtering with a frequency characteristic corresponding to the frequency of the pulse signal supplied from the frequency divider 25. The frequency divider 25 has a plurality of frequency dividing circuits (not shown) that divide the input basic clock at different frequency dividing ratios. The frequency divider 25 supplies the low-pass filter 22 with a pulse signal output from one frequency divider circuit selected according to the set value written in the register 32b. That is, the frequency characteristic of the low-pass filter 22 can be changed according to the setting value written to the register 32b.

  The multiplexer 23 supplies the input four sensor signals to the AD converter in the order corresponding to the set value written in the register 32c. That is, it is possible to change the selection order of the sensor signals in the multiplexer 23, that is, the supply order of the sensor signals to the AD converter 24, according to the set value written in the register 32c.

  The AD converter 24 converts the sensor signal into a digital value at a period corresponding to the frequency of the pulse signal supplied from the frequency divider 26. The frequency divider 26 has a plurality of frequency dividing circuits (not shown) that divide the input basic clock at different frequency dividing ratios. The frequency divider 26 supplies the AD converter 24 with a pulse signal output from one frequency divider circuit selected according to the set value written in the register 32d. That is, the AD conversion cycle in the AD converter 24 can be changed according to the setting value written in the register 32d.

  The recording control logic circuit 30 itself writes the set values to the registers 32a, 33b, 33c, and 33d based on a command from the CPU 50. Note that the CPU 50 may directly write the set values to the registers 32a, 32b, 32c and 32d. In this embodiment, the configuration in which the registers 32a, 32b, 32c, and 32d are arranged in the recording control logic circuit 30 is illustrated, but the present invention is not limited to this mode. For example, the registers 32a, 32b, 32c, and 32d may be arranged in the vicinity of the instrumentation amplifier 21, the low-pass filter 22, the multiplexer 23, and the AD converter 24, respectively.

  According to the data recording apparatus 100 according to the present embodiment, since the memory 60 is configured separately from the LSI 10, compared with the case where the memory 60 is accommodated in the LSI 10, the data recording capacity is increased and It becomes possible to flexibly cope with the reduction. Further, since the RF communication module 41 and the UART 42 are configured separately from the LSI 10, the communication speed is increased and the communication method is changed as compared with the case where these communication modules are accommodated in the LSI 10. Etc. can be dealt with flexibly. On the other hand, components that are assumed not to be changed or expanded basically (instrumentation amplifier 21, low-pass filter 22, multiplexer 23, AD converter 24, recording control logic circuit 30, and communication control logic circuit) With regard to 40), it is possible to reduce the size of the apparatus without sacrificing flexibility by integrating the LSI 10. Further, by mounting the LSI 10, the CPU 50, and the memory 60 on the wiring board 1 in a bare chip state, it is possible to reduce the size of the apparatus as compared with the case where these parts are configured as package parts covered with a mold resin. Is possible.

  Further, according to the data recording apparatus 100 according to the present embodiment, the amplification degree of the instrumentation amplifier 21, the frequency characteristics of the low-pass filter 22, the selection order of sensor signals in the multiplexer 23, and the AD conversion cycle in the AD converter are variable. Therefore, it is possible to flexibly cope with various sensors and various events.

  In addition, since the sensor signal output from the sensor 12 is amplified using the instrumentation amplifier 21 that is not specialized for a specific sensor, it is possible to deal with various sensors. Further, for example, when the signal amplification is insufficient with only the instrumentation amplifier 21 and a sensor signal having a sufficient signal level cannot be obtained, the instrumentation amplifier 21 outside the LSI 10 is provided as shown in FIG. This can be dealt with by providing a preamplifier 13 in the previous stage.

  Further, as shown in FIG. 6, a sensor driving circuit 14 for supplying a driving signal to the sensor 12 is provided outside the LSI 10 for a sensor that requires an external driving signal to be supplied. An example of a sensor that needs to be supplied with a drive signal is an eddy current displacement sensor. An eddy current displacement sensor generates an eddy current on the surface of a sensing object by causing a high-frequency current to flow through the sensor coil and changes the impedance of the sensor coil depending on the distance between the sensor coil and the sensing object. The change of is detected. In the eddy current type displacement sensor, it is necessary to supply a high-frequency current flowing through the sensor coil from the outside as the drive signal.

  As described above, according to the data recording apparatus 100 according to the embodiment of the present invention, it is possible to achieve both the downsizing of the apparatus and the flexibility of data recording.

  FIG. 7A is a perspective view showing a schematic configuration of a data recording device 100A according to the second embodiment of the present invention. The data recording apparatus 100A according to the second embodiment is different from the data recording apparatus 100 according to the first embodiment in that semiconductor chips constituting the memory 60 are stacked on the semiconductor chips constituting the LSI 10. . According to the data recording apparatus 100A according to the second embodiment, since it is not necessary to form wiring on both surfaces of the wiring board 1, the configuration of the wiring board 1 can be simplified.

  FIG. 7B is a perspective view showing a configuration of a data recording device 100B according to the third embodiment of the present invention. The data recording apparatus 100B according to the third embodiment includes a semiconductor chip constituting the LSI 10, a semiconductor chip constituting the CPU 50, a semiconductor chip constituting the memory 60, the RF communication module 41, and the UART 42, respectively. It differs from the data recording device according to the first embodiment in that it is juxtaposed in different areas on the surface S1. According to the data recording device 100B according to the third embodiment, the configuration of the wiring board 1 can be simplified and each semiconductor chip can be easily mounted.

  FIG. 7C is a perspective view showing a configuration of a data recording device 100C according to the fourth embodiment of the present invention. In the data recording apparatus 100C according to the fourth embodiment, the semiconductor chip constituting the LSI 10, the semiconductor chip constituting the CPU 50, and the semiconductor chip constituting the memory 60 are different from each other on the substrate surfaces S1, S2, and S3 of the wiring board. Is different from the data recording apparatus according to the first embodiment. More specifically, the semiconductor chip constituting the CPU 50, the RF communication module 41 and the UART 42 are mounted on the substrate surface S1 of the wiring substrate 1A, and the semiconductor chip constituting the LSI 10 is opposite to the substrate surface S1 of the wiring substrate 1A. It is mounted on the side substrate surface S2. A semiconductor chip constituting the memory 60 is mounted on a substrate surface S3 of a wiring substrate 1B different from the wiring substrate 1A. The data recording device 100C is configured by laminating wiring boards 1A and 1B. According to the data recording apparatus 100C according to the fourth embodiment, it is possible to further reduce the size of the data recording apparatus.

  FIG. 7D is a perspective view showing a configuration of a data recording device 100D according to the fifth embodiment of the present invention. A data recording device 100D according to the fifth embodiment includes two memories 60A and 60B. More specifically, the semiconductor chip constituting the CPU 50, the semiconductor chip constituting the LSI 10, the RF communication module 41, and the UART 42 are mounted on the substrate surface S1 of the wiring board 1A. A semiconductor chip constituting the memory 60A is mounted on the substrate surface S3 of the wiring substrate 1B different from the wiring substrate 1A. A semiconductor chip constituting the memory 60B is mounted on the substrate surface S4 of the wiring substrate 1C different from the wiring substrates 1A and 1B. The data recording device 100D is configured by laminating wiring boards 1A, 1B, and 1C. According to the data recording device 100D according to the fifth embodiment, it is possible to increase the memory capacity while suppressing an increase in the size of the data recording device.

  FIG. 8 is a circuit block diagram showing an example of a circuit configuration of the data recording device 100D according to the fifth embodiment. The recording control logic circuit 30 controls recording and reading of data with respect to the memories 60A and 60B based on a command from the CPU 50. In the present embodiment, the number of memory chips mounted is two, but a configuration in which three or more memory chips are mounted may be employed.

  FIG. 9 is a perspective view showing a schematic configuration of a data recording device 100E according to the sixth embodiment of the present invention. FIG. 10 is a circuit block diagram showing an example of a circuit configuration of a data recording device 100E according to the sixth embodiment. In FIG. 10, a plurality of sensors 12 connected to the data recording device 100E are shown together with the data recording device 100E. The data recording apparatus 100E according to the sixth embodiment is different from the data recording apparatus 100 according to the first embodiment in that the CPU 50 is accommodated in a semiconductor chip constituting the LSI 10. In the example shown in FIG. 9, the semiconductor chip including the CPU 50 and the LSI 10 is mounted on the substrate surface S1 of the wiring substrate 1, and the semiconductor chip constituting the memory 60 is the surface S2 on the opposite side of the substrate surface S1 of the wiring substrate 1. It is mounted on. According to the data recording device 100E according to the sixth embodiment, since the number of parts can be reduced as compared with the data recording device 100 according to the first embodiment, man-hour reduction and further downsizing of the device can be achieved. It becomes possible to plan. 7A, a semiconductor chip constituting the memory 60 may be stacked on the semiconductor chip including the CPU 50 and the LSI 10. 7B, the semiconductor chip including the CPU 50 and the LSI 10 and the semiconductor chip constituting the memory 60 may be juxtaposed on the same substrate surface 1A of the wiring board 1. Further, following the example shown in FIG. 7C, a semiconductor chip including the CPU 50 and the LSI 10 is mounted on the substrate surface S1 of the wiring substrate 1A, and the semiconductor chip constituting the memory 60 is a substrate of the wiring substrate 1B different from the wiring substrate 1A. You may mount in surface S3. 7D, a wiring board on which a semiconductor chip including the CPU 50 and the LSI 10 is mounted, a wiring board 1B on which the memory 60A is mounted, and a wiring board 1C on which the memory 60B is mounted may be stacked.

1 Wiring board 10 LSI
12 Sensor 21 Instrumentation amplifier 22 Low pass filter 23 Multiplexer 24 AD converter 30 Recording control logic 31a to 31d, 32a to 32d Register 41 RF communication module 42 UART
50 CPU
60 Memory 100, 100A, 100B, 100C, 100D, 100E Data recording device

Claims (20)

An amplifier that amplifies a sensor signal output from the sensor, an analog / digital converter that converts the sensor signal amplified by the amplifier into a digital value, a recording control logic circuit that controls recording of the digital value, and an external device; A first semiconductor chip on which an integrated circuit in which a communication control logic circuit for controlling communication between the two is integrated;
A memory configured separately from the first semiconductor chip and having the digital value recorded under control of the recording control logic circuit;
A communication module configured separately from the first semiconductor chip and communicating with the external device under the control of the communication control logic circuit;
A central processing unit for giving a command to the recording control logic circuit;
Including data recording device. The data recording apparatus according to claim 1, wherein the central processing unit is formed on the first semiconductor chip. The data recording apparatus according to claim 1, wherein the central processing unit is formed on a second semiconductor chip different from the first semiconductor chip. The memory is formed on a third semiconductor chip different from the first semiconductor chip and the second semiconductor chip,
The first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are mounted in different regions of at least one substrate in a bare chip state that is not covered with a mold resin. 3. The data recording device described in 3. The data recording apparatus according to claim 4, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are mounted on different substrate surfaces. The data recording apparatus according to claim 4, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are mounted on the same substrate surface. The first semiconductor chip and the second semiconductor chip are mounted on a first substrate surface, and the third semiconductor chip is mounted on a second substrate surface different from the first substrate surface. Item 5. The data recording device according to Item 4. The data recording apparatus according to claim 4, wherein a substrate on which the first semiconductor chip and the second semiconductor chip are mounted and a plurality of substrates each having the third semiconductor chip mounted thereon are stacked. The memory is formed on a third semiconductor chip different from the first semiconductor chip,
The data recording apparatus according to claim 2, wherein the first semiconductor chip and the third semiconductor chip are mounted in different regions of at least one substrate in a bare chip state that is not covered with a mold resin. . The data recording apparatus according to claim 9, wherein the first semiconductor chip and the third semiconductor chip are mounted on different substrate surfaces. The data recording apparatus according to claim 9, wherein the first semiconductor chip and the third semiconductor chip are mounted on the same substrate surface. The integrated circuit comprises:
A plurality of amplifiers for amplifying each of the plurality of sensor signals output from each of the plurality of sensors;
The data recording device according to any one of claims 1 to 11, wherein each of the plurality of sensor signals amplified by each of the plurality of amplifiers is supplied to the analog-digital converter. The integrated circuit comprises:
The data recording apparatus according to claim 12, further comprising a multiplexer that sequentially supplies each of the plurality of sensor signals amplified by each of the plurality of amplifiers to the analog / digital converter. The data recording apparatus according to claim 12, wherein the integrated circuit further includes a plurality of filters that remove predetermined frequency components from each of the plurality of sensor signals amplified by each of the plurality of amplifiers. The integrated circuit has an input port for receiving an input of a trigger signal supplied from the outside,
The data recording apparatus according to any one of claims 1 to 14, wherein the recording control logic circuit starts or stops recording of the digital value in the memory in accordance with the trigger signal. The trigger signal includes additional information;
The recording control logic circuit adds the additional information corresponding to each of the digital values and records it in the memory when recording the digital values in the memory in response to the trigger signal. Data recording device. The recording control logic circuit records status information indicating continuation, interruption, and termination of recording of the digital value in the memory together with the digital value in the memory. The data recording device described. The data recording according to any one of claims 1 to 17, wherein the recording control logic circuit controls a recording order of the plurality of digital values sequentially supplied from the analog / digital converter to the memory. apparatus. The integrated circuit further includes a plurality of filters that remove a predetermined frequency component from each of the plurality of sensor signals amplified by each of the plurality of amplifiers,
A plurality of registers provided corresponding to the amplifier, the filter, the multiplexer, and the analog-digital converter;
The amplifier performs amplification of the sensor signal with an amplification degree according to a setting value set in a corresponding register among the plurality of registers,
The filter performs filtering of the sensor signal with a frequency characteristic according to a set value set in a corresponding register among the plurality of registers,
The multiplexer supplies the sensor signal to the analog / digital converter in an order according to a set value set in a corresponding register among the plurality of registers,
The data recording apparatus according to claim 13, wherein the analog / digital converter converts the sensor signal into a digital value at a period corresponding to a set value set in a corresponding register among the plurality of registers. The integrated circuit further includes a plurality of filters that remove a predetermined frequency component from each of the plurality of sensor signals amplified by each of the plurality of amplifiers,
And at least one power supply circuit for supplying power to each of the amplifier, the filter, the multiplexer, and the analog / digital converter, and a power supply control register provided corresponding to the power supply circuit. Including
The data recording apparatus according to claim 13, wherein the power supply circuit is turned on / off according to a set value set in the power supply control register.

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