JP2017111569A - Information processing device, arithmetic processing unit, and method for controlling information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the possibility of being able to continue an operation by updating management information of a main memory even in the case that a contradiction occurs in the control of a cache due to an intermittent failure or the like between an arithmetic processing unit for managing the main memory and an arithmetic processing unit for taking out data of the main memory.SOLUTION: A first arithmetic processing unit includes: a management information storage part for holding management information showing a management state including the existence/non-existence of a change in data taken out of a main storage device to a second arithmetic processing unit; a reception part for receiving an update request that requests update of the management information; a check part for determining whether the management state shown by the management information and the received update request satisfy a prescribed relationship; and a response packet transmission part for transmitting a completion response showing that the update request normally ends to the second arithmetic processing unit in the case that information showing a retry is attached to the update request, that the received update request updates the management state from a first state to a second state, and that the management information shows that it has already been updated to the second state.SELECTED DRAWING: Figure 11

Description

  The present invention relates to an information processing device, an arithmetic processing device, and a control method for the information processing device.

  An information processing device, a computer, and the like have a CPU (also referred to as an arithmetic processing device) that executes arithmetic processing and a main memory such as a dual inline memory module (DIMM). In a computer system, a main memory stores data, and a CPU accesses the main memory to refer to data or rewrite data.

  Since the DIMM used as the main memory is slow in reading and writing, the CPU includes a storage medium called a cache inside. The CPU stores part of the data in the main memory in the cache, so if the data to be processed exists in the cache, it reads the data from the cache without accessing the main memory, and speeds up access to the data. To do.

  When a read request from the CPU causes a cache miss, the requested data is newly registered in the cache. However, if there is no free space in the cache, the data already stored in the cache is moved out for replacement. When data is moved out for replacement, the cache control unit temporarily stores the data and control signal, and performs control to send the data to the Home-CPU. Here, the Home-CPU is a CPU having a main memory to be moved out. Note that the data is not moved out of the cache when the cache has no free space. In some cases, the data is explicitly moved out even when the cache has free space. The following move-out includes both a case where there is no space in the cache and a case where the cache is free and is executed explicitly.

  FIG. 1 illustrates cache control in a multiprocessor system. The multiprocessor system of FIG. 1 has a Local-CPU and a Home-CPU. In the example of FIG. 1, it is assumed that the Local-CPU is a request source and is a CPU different from the Home-CPU. The Home-CPU is a CPU that manages a main memory in which data to be moved out is stored. Although omitted in FIG. 1, the Home-CPU in FIG. 2 may also have a cache control unit, like the Local-CPU. Also, the Local-CPU in FIG. 2 may manage its own main memory in the same manner as the Home-CPU.

  If the data to be moved out has been changed, the local-CPU cache control unit that is the request source sends a write-back (WRBK) request packet with data to the Home-CPU. On the other hand, if the data to be moved out has not been changed, the cache control unit of the Local-CPU sends a flashback (FLBK) request packet with no data to the Home-CPU.

  As shown in FIG. 1, when the Home-CPU receives a request packet (WRBK / FLBK) for write back (WRBK) or flashback (FLBK), it performs a protocol check, updates management information, and writes back (WRBK). Alternatively, a flashback (FLBK) complete (CPLT) packet (WRBK / FLBK-CPLT) is sent to the Local-CPU.

FIG. 2 exemplifies WRBK / FLBK control by the Local-CPU. In a multiprocessor system typified by cache-coherent NonUniform Memory Access (cc-NUMA), cache take-out information (directory) is held in a form accompanying data on a DIMM used as a main memory. The Home-CPU reads the directory together with the data when accessing the memory and checks the cache coherency (cache coherency). Such cache control is called directory-based cache coherency control.

  In the process of FIG. 2, the Local-CPU issues WRBK / FLBK to the Home-CPU and starts a timer (A1). Then, the Local-CPU determines whether or not a response packet (WRBK / FLBK-CPLT) has been received from the Home-CPU before the timer reaches the threshold (A2). If the determination of A2 is YES, the Local-CPU normally ends the WRBK / FLBK control. On the other hand, if the determination of A2 is NO, the Local-CPU notifies the error control unit that a Fatal error has been detected (A3). Here, the Fatal error is an error in which the operation cannot be continued. The error control unit is, for example, a CPU monitoring dedicated processor or firmware provided for each CPU. When receiving the notification that the Fatal error is detected, the error control unit further reports the Fatal error to the management device outside the CPU.

  FIG. 3 illustrates a flowchart of the Home-CPU that processes a WRBK / FLBK request packet. In this process, the Home-CPU receives a WRBK / FLBK request packet (WRBK / FLBK) from the Local-CPU (B1). When receiving the request packet (WRBK / FLBK), the Home-CPU performs a protocol check based on management information (directory etc.) stored on the Home-CPU or DIMM (B2). If there is no error in the protocol check, the Home-CPU executes processing corresponding to the request packet (WRBK / FLBK). For example, if the Home-CPU is a write-back request, the Home-CPU updates the data in the main memory and updates the management information (B3). Further, when the Home-CPU completes the processing for the request packet (WRBK / FLBK), it returns a response packet (WRBK / FLBK-CPLT) to the Local-CPU (B4). On the other hand, if there is an error in the protocol check, the Home-CPU notifies the error control unit that a Fatal error has been detected (B5).

Japanese National Patent Publication No. 11-511634

By the way, in a multiprocessor system, a transmitted packet may be lost due to an intermittent failure between arithmetic processing units. This is called packet lost. In the above conventional technique, when the arithmetic processing unit that has taken out data sends a request packet (WRBK / FLBK) to the arithmetic processing unit that manages the main memory, or the arithmetic processing unit that manages the main memory has taken out the data When transmitting a response packet (WRBK / FLBK-CPLT) to the arithmetic processing unit, the response to the packet lost is not sufficient, and there are the following problems.
(1) Since the management information of the main memory is not updated, a contradiction occurs in the cache control, and the arithmetic processing unit cannot continue the operation.
(2) In the arithmetic processing unit that manages data in the main memory, the move-out data to be written back to the main memory is lost, and the arithmetic processing unit fails to update the data.
Of these, the problem (2) can be solved by retrying the processing unit that has taken out the data again when the failure is not a fixed failure but an intermittent failure or the like. On the other hand, the problem (1) may not be adequately addressed.

  According to the present invention, inconsistency occurs in cache control due to an intermittent failure or the like between an arithmetic processing unit (Home-CPU) that manages main memory and an arithmetic processing unit (Local-CPU) that takes out data in the main memory. Even in such a case, it is an object to update the management information of the main memory and increase the possibility that the operation can be continued.

  One aspect of the present invention is exemplified by the following information processing apparatus. That is, the information processing apparatus includes a first arithmetic processing device having a main memory control device that controls the main memory device, and a second arithmetic processing device connected to the first arithmetic processing device. The first arithmetic processing unit includes a management information storage unit that holds management information indicating a management state including whether or not the data taken out from the main storage unit to the second arithmetic processing unit is changed; A receiving unit that receives an update request for requesting an update; a check unit that determines whether or not the management state indicated by the management information and the received update request satisfy a predetermined relationship; and indicates a retry to the update request If the information is added, the received update request updates the management state from the first state to the second state, and the management information indicates that the management state has already been updated to the second state, the second A response packet transmission unit that transmits a completion response indicating that the update request has been normally completed to the arithmetic processing unit.

  According to this arithmetic processing unit, even if there is a contradiction in cache control due to an intermittent failure or the like between the arithmetic processing unit that manages the main memory and the arithmetic processing unit that takes out the data of the main memory, The management information can be updated, and the possibility that the operation can be continued can be increased.

It is a figure which illustrates control of the cache in a multiprocessor system. It is a figure which illustrates control of WRBK / FLBK by Local-CPU. It is a flowchart which illustrates the process of Home-CPU which processes a request packet (WRBK / FLBK). It is a figure which illustrates the solution method by packet lost and the retry in the path | route from Local-CPU to Home-CPU. It is a figure which illustrates the subject at the time of packet lost and retry in the path | route from Home-CPU to Local-CPU. It is a flowchart of the process in Home-CPU of a comparative example. It is a figure which illustrates the case of the presence or absence of the error at the time of request packet processing, and the classification | category of an error. It is a figure which illustrates the composition of an information processor. It is a figure which illustrates the process of WRBK / FLBK lost case. It is a figure which illustrates the process of WRBK / FLBK-CPLT lost case. It is a figure which illustrates the flowchart of a process of the information processing apparatus containing Local-CPU and Home-CPU. It is a figure which illustrates the flowchart of a process of Local-CPU. It is a figure which illustrates the flowchart of a process of Home-CPU. It is a figure which illustrates the classification | category of an error. It is a figure which illustrates the control circuit which performs processing of Local-CPU. It is a figure which illustrates the control circuit which performs processing of Home-CPU.

  Hereinafter, an information processing apparatus according to an embodiment will be described with reference to the drawings.

[Comparative example]
A computer according to a comparative example will be described with reference to FIGS. In the comparative example, the computer has a Local-CPU and a Home-CPU. In the example of FIG. 4, the Home-CPU is a CPU that manages a main memory in which data to be moved out is stored. Further, it is assumed that the Local-CPU takes out data from the main memory managed by the Home-CPU and holds it in a cache in the Local-CPU. Further, although omitted in FIG. 4 and subsequent figures, the Home-CPU has a cache control unit as well as the Local-CPU. In addition, the Local-CPU in FIG. 4 and below manages its own main memory as well as the Home-CPU. In the conventional configuration, when the Local-CPU transmits a request packet (WRBK / FLBK) to the Home-CPU, or when the Home-CPU transmits a response packet (WRBK / FLBK-CPLT) to the Local-CPU, the packet Response to lost is not enough. As an improvement to packet lost, it is conceivable to simply transmit (retry) the transmitted packet once more. Note that WRBK / FLBK represents write back or flash back.

FIG. 4 is a diagram exemplifying a packet lost (hereinafter referred to as WRBK / FLBK lost case) route on the path from the Local-CPU to the Home-CPU and a solution by retry. In FIG. 4, the cache control unit of the Local-CPU transmits a WRBK request packet or a FLBK request packet to the Home-CPU. However, in FIG. 4, the WRBK / FLBK request packet is lost, that is, packet lost occurs on the path from the Local-CPU to the Home-CPU.

In the example of FIG. 4, since the request packet does not reach the Home-CPU, the Home-CPU does nothing. That is, the Home-CPU does not execute a process such as a protocol check using management information or a response packet transmission based on the result of the protocol check. On the other hand, the cache control unit of the Local-CPU starts a timer and waits for a response packet. However, since no response packet is sent from the Home-CPU,
A timeout occurs in the Local-CPU.

In the computer of the comparative example, when a timeout occurs for the request packet, the cache control unit of the Local-CPU executes a retry. That is, the cache control unit sets the retry flag in the WRBK / FLBK request packet again and transmits it. The retry flag is, for example, 1-bit information such as 0 at the time of initial issue, 1 at the time of issue of retry, and the like.

  If the cause of the packet loss of the request packet (WRBK / FLBK) that caused the timeout is intermittent or temporary, the request packet (WRBK / FLBK) is returned to Home- Reach the CPU.

Then, Home-CPU receives a request packet (WRBK / FLBK). Since the Home-CPU has not received the request packet (WRBK / FLBK) when the timeout occurs in the Local-CPU, the protocol check is performed according to the request packet (WRBK / FLBK) by the retry, and the main memory is updated or Processing such as management information update may be executed. And Home-CPU
After the processing is completed, a response packet (WRBK / FLBK-CPLT) may be transmitted to the Local-CPU.

FIG. 5 shows a packet lost (hereinafter, referred to as “lost packet”) route from the Home-CPU to the Local-CPU.
(WRBK / FLBK-CPLT lost case) and a problem at the time of retry.
In the example of FIG. 5, the request packet (WRBK / FLBK) reaches the Home-CPU, and the Home-CPU performs a protocol check, updates the main memory or management information, and responds with a response packet (WRBK / FLBK-CPLT). ) To the Local-CPU. However, the response packet (WRBK / FLBK-CPLT) is lost on the path from the Home-CPU to the Local-CPU, and the packet loss of the response packet occurs. In the case of FIG. 5, as in the case of FIG. 4, a timeout occurs in the Local-CPU.

Even when the response packet is lost, the cache control unit of the Local-CPU transmits the request packet (WRBK / FLBK) again. However, in Home-CPU,
Processing for the request packet (WRBK / FLBK) has already been completed. For this reason, even if the Home-CPU receives a request packet (WRBK / FLBK) by retry, there is a contradiction between the request packet (WRBK / FLBK) and the current management information, and the protocol check cannot be executed normally. Therefore, in the WRBK / FLBK-CPLT lost case, there is a problem in executing the protocol check normally and returning the management information to the original normal state.

FIG. 6 illustrates a flowchart of processing in the home-CPU of the comparative example. In this processing, the Home-CPU receives a request packet (WRBK / FLBK) for normal processing that is not a retry from the Local-CPU (C1). Next, the Home-CPU determines whether or not there is an error by a protocol check based on the management information (C2). The determination of C2 is a conventional protocol check, for example, a check based on the Modified, Exclusive, Shared, Invalid (MESI) protocol. In the check by the MESI protocol, for example, Home-CPU, L
For the data that ocal-CPU brought to the cache with Shared (S), WR
When a BK write-back request is received, it can be determined that an error has occurred. In the present embodiment, the protocol check conventionally performed is not limited to the check using the MESI protocol. For example, the conventional protocol check may be a check by the MSI protocol, which is a cache protocol that does not have an exclusive state. Further, the conventional protocol check may be a check by the MOSI protocol in which the Owned state is added to the MSI protocol. Further, the conventional protocol check may be a check by the MOESI protocol in which the Owned state is added to the MESI protocol. In the present embodiment, the protocol check used in the determination of C2 as exemplified above is called a conventional protocol check.

If it is determined in C2 that there is no error in the protocol check, the Home-CPU may execute processing according to WRBK / FLBK without depending on the value of the retry flag (C3). That is, the Home-CPU updates main memory data and management information in response to a WRBK request packet. In addition, the Home-CPU updates the management information without updating the data in the main memory in response to the FLBK request packet. Further, the Home-CPU sends a response packet (WRBK / FLBK-CPL) to the Local-CPU.
T) is transmitted (C4). In C4, the Home-CPU adds a retry flag having the same value as the retry flag (0, 1) of the received request packet (WRBK / FLBK), and transmits a response packet (WRBK / FLBK-CPLT). Therefore, if there is no protocol error in the determination of C2, the process ends normally regardless of the retry flag setting.

On the other hand, if there is an error in the protocol check in the determination of C2, the Home-CPU
It is determined whether the retry flag of the request packet (WRBK / FLBK) is 0 (C
5). If the retry flag is 0 in the determination of C5, that is, if the request packet is not a retry, the Home-CPU notifies the error control unit that a Fatal error has been detected (C6). The error control unit transmits a report corresponding to the Fatal error, for example, to the management computer. Therefore, if the retry flag is 0 in C5, the process results in a Fatal error transmission.
Further, if the retry flag is 1 in the determination of C5, that is, the request packet is a retry, the Home-CPU cannot determine whether or not it is a Fatal error (C7
). In this embodiment, an error that is not a fatal error is a recoverable error and is called a pseudo error. If the Home-CPU can detect a Fatal error, the Home-CPU may proceed to C6. If Home-CPU can detect a pseudo error,
Processing corresponding to the request packet (WRBK / FLBK) is executed (C8), and a response packet (WRBK / FLBK-CPLT) may be transmitted to the Local-CPU.

  FIG. 7 is a diagram exemplifying an error presence / absence case and error classification during request packet processing. If there is no error in the protocol check according to the conventional MESI protocol or the like, there is no error even in the request packet between the Local-CPU and the Home-CPU of the comparative example. However, even if there is no error, the computer of the comparative example can have a retry flag = 0 (not a retry) or a retry flag = 1 (a retry). That is, when the request packet (WRBK / FLBK) becomes a packet lost in the path from the Local-CPU to the Home-CPU, the request packet does not reach the Home-CPU. Therefore, when the Local-CPU retransmits the request packet (WRBK / FLBK) and the request packet reaches the Home-CPU, the request packet excludes that the retry flag is set for the Home-CPU. Then, it is a normal packet. Therefore, a request packet having no error in the conventional protocol check is processed as normal regardless of whether or not there is a retry.

On the other hand, when there is an error in a conventional protocol check such as MESI, the error may be a fatal error or a repairable pseudo error. For example, when there is an error in a conventional protocol check such as MESI, for example, a request packet that is inconsistent with the MESI information currently held in the Home-CPU is returned to Home-
This is a case where the CPU has received it. In the following, pseudo errors and fatal errors will be considered separately. (A) Error due to lost response packet (pseudo error)
An example of an inconsistent request packet that has already occurred is Home-CP.
Response packet (WRBK / FLBK-) for request packet processed in U
It can be assumed that (CPLT) becomes packet lost in the path from the Home-CPU to the Local-CPU.

In such a lost response packet, the response packet does not reach the Local-CPU even though the processing for the request packet is normally completed in the Home-CPU. For this reason, the Local-CPU executes the retry process without knowing the state of the Home-CPU. In this case, inconsistency between the request packet and the management information may occur in the processing of the next request packet even though the processing of the request packet in the Home-CPU is normally completed. Such an error is because processing in the Home-CPU for a past request packet has been completed normally.
It can be called a pseudo error.

However, as in the computer of the comparative example, the contradiction between the request packet and the management information cannot be resolved simply by setting the retry flag and transmitting the request packet by the Local-CPU. Therefore, in the process of the comparative example, the management information inconsistency due to the lost response packet cannot be resolved.
(B) Error due to a cause other than the lost response packet (Fatal error)
A protocol check error may occur for various reasons other than the lost response packet. For example, this is a case where a Local-CPU taken out to the cache in a state such as I (Invalid) or S (Shared) transmits a write-back (WRBK) packet to the Home-CPU. In the case of an error due to a cause other than the lost response packet, the Home-CPU of the comparative example detects a Fatal error.

However, the home-CPU of the comparative example cannot distinguish between the error due to the (A) lost response packet and the error due to a cause other than the lost (B) response packet.

[Embodiment]
The information processing apparatus according to the embodiment will be described below. In this embodiment, the cache control unit of the Local-CPU sets a retry flag (1 bit) in the request packet (WRBK / FLBK), issues it to the Home-CPU, and starts a timer. If the timer exceeds a specified value before receiving a response packet (WRBK / FLBK-CPLT) to the issued request packet, the Local-CPU determines that a packet lost has occurred. Further, the Local-CPU determines whether or not the cause of the packet loss is a home-CPU fixed failure or a fixed route failure. The Local-CPU reissues the request packet when determining that the packet lost is not due to a fixed failure but due to a temporary intermittent failure or the like. Reissuing a request packet is also called a retry. If the Local-CPU determines that the packet lost is due to a fixed failure, no retry is performed. This is because when a fixed failure occurs, it will fail again even if it is retried.

  When a retry request packet (WRBK / FLBK) is transmitted, there are cases where the processing corresponding to the Home-CPU request packet (WRBK / FLBK) has already been executed and cases where it has not been executed. The Home-CPU discriminates whether or not the above processing has been executed by a protocol check between the request packet (WRBK / FLBK) received from the Local-CPU and the management information, and if it has been executed, the request packet (WRBK / The process corresponding to the request packet (WRBK / FLBK) is executed when the process corresponding to FLBK) is not executed. Home-CPU is an example of a first arithmetic processing unit. The Local-CPU is an example of a second arithmetic processing device.

FIG. 8 illustrates the configuration of the information processing apparatus according to the present embodiment. The information processing apparatus can be referred to as a multiprocessor system. The information processing apparatus includes a plurality of CPUs 1 and a plurality of main memories 2. The CPU 1 is an example of an arithmetic processing device. The plurality of CPUs 1 and the plurality of main memories 2 are individually connected to the CPUs 1-0, 1-1,. . . , 1-n, main memory 2-0, 2-1,. . . , 2-n, etc. The main memory 2 includes, for example, a plurality of dual inline memory modules (DIMMs). Crossbar L between CPU1
Connected via network such as SI and interconnect. In FIG. 8, a plurality of CPUs 1 are connected in series, but the topology between the CPUs 1 is not limited to a linear shape. Various topologies such as buses, meshes, and toruses can be applied. CPU 1-0, 1-1,. . . , 1-n is an example of the first arithmetic processing device and the second arithmetic processing device. For example, the CPU 1-1 is an example of a second arithmetic processing device connected to the first arithmetic processing device. The main memory 2-1 is an example of a main storage device.

Each CPU 1 includes a core 11, a cache 12, a cache control unit 13, and a memory control unit 14. In addition, the core 11, the cache 12, the cache control unit 13, and the memory control unit 14
Respectively, the cores 11-0, 11-1,. . . , 11-n, caches 12-0, 12-1,. . . , 12-n, cache control units 13-0, 13-1,. . . , 13-n, memory control units 14-0, 14-1,. . . , 14-n, etc. The core 11 or the CPU 1 is also called a processor or an arithmetic processing unit.

  The core 11 executes control of the CPU 1 and data processing. The cache 12 temporarily stores data on the main memory 2. The cache control unit 13 manages data in the cache 12 and exchanges data with other CPUs 1. The memory control unit 14 accesses the main memory 2 and reads / writes data from / to the main memory 2. In the following embodiments, the CPUs 1-0, 1-1,. . . , 1-n can be a Local-CPU and a Home-CPU. The memory control unit 14-1 is an example of a main memory control device.

  FIG. 9 illustrates the processing of the WRBK / FLBK lost case. The WRBK / FLBK lost case is a case where a packet lost occurs on the path from the Local-CPU to the Home-CPU. In the WRBK / FLBK lost case, the Home-CPU does not receive the request packet (WRBK / FLBK), and therefore, nothing is executed as in the case of the comparative example (FIG. 4). Therefore, a timeout occurs in the Local-CPU. Then, the Local-CPU determines that packet loss has occurred. Further, the Local-CPU determines whether the cause of the packet loss is a fixed failure or a temporary intermittent failure. If the Local-CPU determines that the cause of the packet loss is a temporary intermittent failure, the Local-CPU executes a retry. When the Home-CPU receives the request packet (WRBK / FLBK) due to the retry, the Home-CPU executes the same operation as in the normal case, and transmits a response packet (WRBK / FLBK-CPLT) to the Local-CPU.

  FIG. 10 illustrates processing of the WRBK / FLBK-CPLT lost case. The WRBK / FLBK-CPLT lost case is a case where a packet lost occurs on the path from the Home-CPU to the Local-CPU. In the WRBK / FLBK-CPLT lost case, the Home-CPU has received the request packet (WRBK / FLBK), and thus the same operation as that in the normal case has been normally executed.

  In the present embodiment, the Home-CPU does not execute the same operation as the normal case when the Home-CPU receives the retry packet, even though the processing for the request packet (WRBK / FLBK) has been executed. That is, the Home-CPU transmits a response packet (WRBK / FLBK-CPLT) to the Local-CPU without executing processing corresponding to the request packet.

  FIG. 11 illustrates a flowchart of processing of an information processing apparatus including a Local-CPU and a Home-CPU. Hereinafter, FIG. 11, FIG. 12, and FIG. 13 illustrate the processing procedure of the information processing apparatus. In the information processing apparatus of this embodiment, each process is basically performed by a dedicated hardware circuit (FIG. 15, FIG. (See FIG. 16). However, the processor may execute part of FIGS. 11, 12, and 13 according to a computer program.

In the processing of FIG. 11, the Local-CPU sets a retry flag and issues a request packet (WRBK / FLBK) to the Home-CPU. Further, the Local-CPU starts a timer (L0). First request packet (WRBK
/ FLBK), the Local-CPU sets the retry flag to 0. Further, when the next request packet (WRBK / FLBK) is issued after a timeout occurs in the first request packet (WRBK / FLBK), the Local-CPU sets the retry flag to 1. The Home-CPU -Request packet from CPU (WRBK / FLB
K) is received (H1). Then, the Home-CPU performs a protocol check of the request packet (WRBK / FLBK) received from the Local-CPU based on the management information of the Home-CPU (H2). The protocol check of H2 is a conventional protocol check, for example, a check by MESI protocol, a check by MSI protocol, a check by MOSI protocol, a check by MOESI protocol, or the like.

  If there is no error in the H2 protocol check, the Home-CPU executes processing corresponding to the request packet (WRBK / FLBK) (H3). For example, the Home-CPU updates the data and management information on the main memory in response to the WRBK request. Further, for example, the Home-CPU updates the management information in response to the FLBK request. “No error in the H2 protocol check” is an example in which, as a result of the check by the check unit, the management state and the received update request are in accordance with a predetermined standard. The process of H3 is an example of a process of a data updating unit that rewrites data in the main storage device when it includes a data rewrite instruction of the main storage device.

  Then, the Home-CPU transmits a response packet (WRBK / FLBK-CPLT) to the Local-CPU (H4). The retry flag of the response packet is set to the same value as the received request packet (WRBK / FLBK). And Home-CPU complete | finishes a process normally. The process H4 is an example of transmitting a completion response indicating that the update request has been normally completed to the second arithmetic processing unit. Further, the process of H4 indicates that the update request has been normally completed to the second arithmetic processing unit regardless of whether or not the response packet transmission unit is provided with information indicating retry in the update request. It is also an example of sending a completion response.

  On the other hand, if there is an error in the protocol check of H2 (NO in H2) and the retry flag in the request packet (WRBK / FLBK) received from the Local-CPU is 0 (YES in H5), Home -The CPU determines that a fatal protocol contradiction has occurred, notifies the error control unit of a fatal error, and terminates the process abnormally. Here, the Fatal error is an error in which the operation cannot be continued. When there is an error in the H2 protocol check, as a result of the check by the check unit, it is an example that the management state and the received update request are not in a relationship that matches the predetermined criteria. The case of YES in H5 is an example of the case where information indicating retry is not given to the received update request.

  Further, if there is an error in the H2 protocol check (NO in H2) and the retry flag in the request packet (WRBK / FLBK) received from the Local-CPU is 1 (NO in H5), Fatal Two types of errors are considered: an error and a pseudo error due to the WRBK / FLBK-CPLT lost case. In the case of NO in H5, this is an example that information indicating retry is added to the update request.

  In the present embodiment, the Home-CPU determines whether or not the processing for the request packet (WRBK / FLBK) at the time of initial packet reception has been processed (H6). The first packet is the same request packet (WRBK / FLBK) received before the previous time when the request packet (WRBK / FLBK) currently being processed is the second or subsequent request packet (WRBK / FLBK) reception. Say.

If it is in the processed state in the determination of H6, the Home-CPU determines that it is the “WRBK / FLBK-CPLT lost case”. That is, the Home-CPU (a) there is an error in the protocol check of H2 (b) the retry flag in the request packet (WRBK / FLBK) received from the Local-CPU is 1 (c) processing by the initial packet reception If the three conditions that are completed are satisfied, the detected error is ignored because it is not actually a problem. When ignoring the error, the Home-CPU does not execute anything and transmits a response packet (WRBK / FLBK-CPLT) to the Local-CPU (H4). The retry flag of the response packet is set to the same value as the received WRBK / FLBK. Then, the Home-CPU ends the process normally. Here, an error when the conditions (a), (b), and (c) are satisfied is referred to as a pseudo error. The state that has been processed in the determination of H6 means that the received update request updates the management state from the first state to the second state, and the management information has already been updated to the second state. This is an example of a case where it has been completed.

  On the other hand, if the processing for the request packet at the time of initial packet reception has not been processed in H6 processing (NO in H6), the Home-CPU determines that the detected error is an unexpected event. Then, the Home-CPU notifies the error control unit of the Fatal error and terminates the process abnormally. Details of Home-CPU processing including abnormal termination will be described later with reference to FIG.

  The Local-CPU determines whether or not a response packet (WRBK / FLBK-CPLT) has been received from the Home-CPU before the timer reaches the threshold (L3). When the Local-CPU fails to receive the response packet (WRBK / FLBK-CPLT), it executes error processing (L2). If the retry is possible, the Local-CPU returns the control to L0. On the other hand, if it is determined in L3 that the Local-CPU has received the response packet (WRBK / FLBK-CPLT), it executes an end process (L4). Details of the processing of the Local-CPU including the processing of L2 and L4 will be described later according to FIG.

  FIG. 12 illustrates a flowchart of processing of the Local-CPU. In this process, the Local-CPU first sets a retry flag in the request packet (WRBK / FLBK) to a value 0 (L11). Next, the Local-CPU issues a request packet (WRBK / FLBK) to the Home-CPU and starts a timer (L12). Then, as described in FIG. 11, the Local-CPU determines whether or not a response packet (WRBK / FLBK-CPLT) has been received from the Home-CPU before the timer reaches the threshold (L13).

  If the response packet (WRBK / FLBK-CPLT) is received from the Home-CPU, the Local-CPU is obtained from the retry flag set in the request packet (WRBK / FLBK) and the response packet (WRBK / FLBK-CPLT). It is determined whether or not the retry flags match (L14). If it is determined in L14 that both retry flags match, the Local-CPU ends the process normally. On the other hand, if both the retry flags do not match in the determination of L14, the Local-CPU notifies the error control unit (see FIG. 15) that a Fatal error has been detected, and ends the processing abnormally (L17). .

  When the response packet (WRBK / FLBK-CPLT) has not been received from the Home-CPU, the Local-CPU determines the cause of the packet lost (L15). That is, (i) the cause of packet lost is a Home-CPU fixed failure, fixed route failure, etc. (ii) the cause of packet lost is a temporary intermittent failure, and the failure can be recovered by retry Are selectively determined.

Since there is a case that cannot be resolved even after retrying, such as disconnection of the path between CPUs or CPU failure, it is determined whether or not the case can be recovered by retrying. Various determination methods are conceivable. For example, the Local-CPU may execute a retry when any of the following conditions (1) to (3) is satisfied.
(1) The first case is when a new error is detected.
(2) The second is the case of an error until the number of retries is counted and the threshold is reached.
(3) The third is a case where the path between CPUs is made redundant, and the current time corresponds to the time when the degeneration sequence of the redundant path is executed. This is because there is a possibility that packet loss may occur temporarily when the degeneration sequence is executed.

  The Local-CPU sets a retry flag in the request packet (WRBK / FLBK) in order to allow the Home-CPU to change the operation depending on whether or not to retry. That is, the Local-CPU sets the retry flag to 0 when transmitting the request packet (WRBK / FLBK) for the first time, and sets the retry flag to 1 when transmitting the request packet by retry.

  As a result of the above determination, when the Local-CPU determines that the cause of the packet loss is a temporary intermittent failure as shown in (ii), it sets the retry flag to 1 (L16) and performs the processing. Return to L12. When the Local-CPU determines in L15 that the case can be restored by retrying and executing the processing in L16, the next update request in which information indicating retry is set is transmitted to the first arithmetic processing. This is an example of repeating the retry process up to a predetermined limit. Further, in the determination of L15, the determination of (1) to (3) above includes the number of retries and the connection state between the first arithmetic processing device and the second arithmetic processing device. This is an example of determination based on at least one of the operating states. The “degenerate sequence execution” is an example of an operating state of the information processing device including a connection state between the first arithmetic processing device and the second arithmetic processing device. On the other hand, if the Local-CPU determines that the cause of the packet loss is a fixed failure as in (i), for example, the Local-CPU notifies the error control unit that the Home-CPU has a fixed failure (L18). The process ends abnormally.

  FIG. 13 illustrates a flowchart of processing of the Home-CPU. In FIG. 13, the processing from H1 to H6 is the same as H1 to H6 in FIG. If the retry flag set in the request packet (WRBK / FLBK) is 0 in the determination of H5, the Home-CPU notifies the error control unit (see FIG. 16) that a Fatal error has been detected (H7). ), Terminate the process abnormally. When the retry flag is 0, it is an example in the case where information indicating retry is not given to the received update request. The process of H7 is an example of notifying an error to a predetermined notification destination.

  Further, when there is an error in the protocol check of H2 (NO in H2) and the retry flag in the request packet (WRBK / FLBK) received from the Local-CPU is 1 (NO in H5), The Home-CPU executes the determination of H6. In other words, if the processing for the request packet (WRBK / FLBK) at the time of initial packet reception is not processed in the determination of H6 (NO in H6), as described in FIG. It is determined that this is an event. Then, the Home-CPU notifies the error control unit of the Fatal error (H7) and terminates the process abnormally. The process of H7 is an example in which the response packet transmission unit notifies an error to a predetermined notification destination.

On the other hand, if the process for the request packet at the time of receiving the initial packet has been processed in the determination of H6 (YES in H6), the Home-CPU skips the execution of the process corresponding to the request packet (WRBK / FLBK). That is, the Home-CPU skips updating of data on the main memory, updating of management information, etc. (H8). Then, the Home-CPU sets the same value as the received request packet (WRBK / FLBK) in the retry flag of the response packet (WRBK / FLBK-CPLT), transmits it to the Local-CPU (H9), and terminates the processing normally. To do. The process H9 is an example of transmitting a completion response indicating that the update request has been normally completed to the second arithmetic processing unit.

FIG. 14 illustrates error classification according to the present embodiment. In FIG. 14, in the classification of FIG. 7, the classification that was “error in conventional protocol check” is further classified into two. That is, in the classification of FIG. 14, a “state that cannot occur by packet reception” is newly added. Here, the “state that cannot occur by packet reception” is the state exemplified in the above “(2) Error due to cause other than lost response packet (Fatal error)”. For example, this is a case where the Local-CPU that has taken the data in the memory 2 to the cache 12 in a state such as I (Invalid), S (Shared), etc. has transmitted a write-back (WRBK) packet. Such a Fatal error can occur in any of the retry flag values (0, 1). Further, such a Fatal error can occur both when the Home-CPU receives the first request packet and when it receives a request packet again by retry. In the case of the WRBK lost case, the Home-CPU may receive the first request packet with the retry flag = 1 setting.

  Further, in the classification that was “error occurred in the conventional protocol check”, the classification other than “state that cannot occur by packet reception” includes two more cases. That is, the first is a Fatal error when the retry flag is 0. The second is a pseudo error when the retry flag is 1. When the retry flag is 1, a pseudo error occurs in the response packet (WRBK / FLBK-CPLT) lost case. The Home-CPU of this embodiment can detect a pseudo error when the retry flag is 1. That is, when there is an error in the conventional protocol check such as the MESI protocol, the Home-CPU of this embodiment, as exemplified in the determination of H6 in FIG. (WRBK / FLBK-CPLT lost case) can be distinguished.

  FIG. 15 illustrates a control circuit that executes processing of the Local-CPU. FIG. 16 illustrates a control circuit that executes processing of the Home-CPU. However, as described with reference to FIG. 8, since the CPU 1 can be a Local-CPU or a Home-CPU, each CPU 1 may have both the circuits of FIG. 15 and FIG. 16. That is, FIG. 15 illustrates a portion of a control circuit that executes processing of the Local-CPU in the processing circuit of the CPU 1. FIG. 16 illustrates a portion of the control circuit that executes the processing of the Home-CPU among the processing circuits of the CPU 1.

  In FIG. 15, the cache control unit 13 and the error control unit 3-L of the Local-CPU are illustrated. The cache control unit 13 includes a control information storage unit 131, a data storage unit 132, a request packet transmission unit 133, a response packet reception unit 134, a timeout detection unit 135, a protocol check unit 136, a retry possibility determination unit 137, and a fixed failure notification unit 138. Have

  The control information storage unit 131 stores control information for executing cache control according to a command from the core 11. The data storage unit 132 stores, for example, cache data to be written back to the main memory 2. The request packet transmission unit 133 extracts control information including a retry flag from the control information storage unit 131. In addition, when the request packet to be transmitted to the Home-CPU is a request packet accompanied by data to the main memory 2 of the Home-CPU such as WRBK, the request packet transmission unit 133 extracts data from the data storage unit 132. Then, the request packet transmission unit 133 generates a request packet (WRBK / FLBK) including a retry flag and transmits the request packet to the Home-CPU.

  The response packet receiving unit 134 receives a response packet (WRBK / FLBK-CPLT) generated by the Home-CPU that has received the request packet (WRBK / FLBK).

  The timeout detector 135 starts a timer when transmitting a request packet (WRBK / FLBK), and clears the timer when receiving a response packet (WRBK / FLBK-CPLT). When the timer reaches a threshold value set before receiving the response packet (WRBK / FLBK-CPLT), timeout detection unit 135 detects a timeout.

  The protocol check unit 136 performs a protocol check by comparing the retry flag of the response packet (WRBK / FLBK-CPLT) received from the Home-CPU with the retry flag of the control information storage unit 131. If the two retry flags match as a result of the protocol check, the protocol check unit 136 determines that there is no error. If the two retry flags do not match, the protocol check unit 136 determines that the error is a fatal error and notifies the error control unit 3-L of the fatal error. For example, the protocol check unit 136 sets an error bit in a predetermined register of the error control unit 3-L.

  The retry availability determination unit 137 refers to retry availability determination information when a timeout is detected. The retry possibility determination information is, for example, a register indicating a fixed failure for each CPU, an external notification signal indicating that a failure has occurred between CPUs, or the like. If it is determined that a retry is impossible due to a fixed failure of the destination Home-CPU or a fixed failure of the route, the retry possibility determination unit 137 notifies the fixed failure notification unit 138 that the destination Home-CPU has a fixed failure. . When the retry possibility determination unit 137 determines that retry is possible, it sets a retry flag in the control information storage unit and starts packet reissue control. If the retry failure is impossible, the fixed failure notification unit 138 determines that the Home-CPU has a fixed failure, and notifies the error control unit 3-L that the Home-CPU has a fixed failure.

  The error control unit 3-L collects errors detected by hardware in the entire Local-CPU including the cache control unit 13, and performs error control. For example, the error control unit 3-L notifies the management apparatus that manages the information processing apparatus including the plurality of CPUs 1 of the occurrence of an error, the location where the error has occurred, the type of error, the cause of the error, and the like.

  In FIG. 16, the memory control unit 14 and the error control unit 3-H of the Home-CPU are illustrated. The memory control unit 14 includes a request packet reception unit 141, a management information storage unit 142, a protocol check unit 143, a management information update unit 144, a main memory data update unit 145, and a response packet transmission unit 146.

The request packet receiving unit 141 receives a request packet (WRBK / FLBK) transmitted by the Local-CPU. The request packet receiving unit 141 is an example of a receiving unit that receives an update request for requesting an update of management information. The management information storage unit 142 stores management information related to taking out data from the main memory 2. The management information storage unit 142 is an example of a management information storage unit that holds management information indicating a management state including whether or not the data taken out to the second arithmetic processing unit is changed. The protocol check unit 143 compares the request packet (WRBK / FLBK) received from the Local-CPU with the management information in the management information storage unit 142 to perform a protocol check. The protocol check unit 143 determines one of a fatal error, a pseudo error in the retry packet, and no error by the protocol check. The protocol check unit 143 is an example of a check unit that determines whether or not the management state indicated by the management information and the received update request satisfy a predetermined relationship.

  The management information update unit 144 updates the management information when the request packet (WRBK / FLBK) has no error in the protocol check unit 143. The main memory data update unit 145 updates the data on the main memory when the request packet with data (WRBK) has no error in the protocol check unit 143. The management information updating unit 144 is configured as follows: “A data updating unit that rewrites data in the main storage device when the update request having a matching relationship according to a predetermined standard includes a data rewrite instruction (WRBK) of the main storage device”. It is an example. The response packet transmission unit 146 generates a response packet (WRBK / FLBK-CPLT) including a retry flag when the request packet (WRBK / FLBK) has no error in the protocol check unit 143 or is a pseudo error in the retry packet. Transmit to Local-CPU. The response packet transmission unit 146 is an example of a response packet transmission unit that transmits a completion response indicating that the update request has been normally completed to the second arithmetic processing unit.

  The error control unit 3-H collects errors detected by hardware in the entire Home-CPU including the memory control unit 14, and performs error control. The process of the error control unit 3-H is the same as that of the error control unit 3-L in FIG.

  As illustrated in FIG. 8, an interconnect such as a crossbar LSI is provided between the plurality of CPUs 1. That is, it is assumed that the Local-CPU and the Home-CPU are connected by an interconnect. In this case, the Local-CPU and the Home-CPU may be mounted in different housings, or may be mounted in the same housing. That is, even when the Local-CPU and the Home-CPU are mounted in different housings and are mounted in the same housing, the information processing apparatus has the configuration shown in FIGS. Protocol checking and pseudo-error detection according to embodiments can be performed.

  By adopting the mechanism as described above, this information processing apparatus reduces the possibility of management information contradiction and data loss even in the response packet (WRBK / FLBK-CPLT) lost case, and generates a pseudo error. It can be detected. That is, in the write-back control (WRBK / FLBK) of the data taken out to the cache 12 of the Local-CPU to the main memory, the information processing apparatus cannot correctly transfer the request packet due to an intermittent failure between the CPUs. In addition, it is possible to increase the possibility of returning to normal operation without causing control contradiction or data loss.

  In addition, when there is no error in the conventional protocol check based on the management information in the determination of H2 in FIG. 11 or FIG. 13, the information processing apparatus determines that it is normal regardless of the state indicated by the retry flag. In the WRBK / FLBK lost case, the Home-CPU can complete the processing normally (H4 in FIG. 11, H9 in FIG. 13).

  In addition, in this information processing apparatus, in the determination of H2 in FIG. 11 or FIG. 13, if there is an error in the conventional protocol check based on the management information and the retry flag indicates that it is not a retry, a fatal error occurs. Can be determined.

  Further, in the information processing apparatus, in the determination of H2 in FIG. 11 or FIG. 13, when there is an error in the conventional protocol check based on the management information and the retry flag indicates retry, the process by the first packet reception is performed. If it has not been processed (NO in H6), it can be determined that a Fatal error has occurred.

  Further, in this information processing apparatus, the Local-CPU can appropriately perform the retry by determining the cause of the packet lost as indicated by L15 in FIG. Further, the Local-CPU can repeat the retry process up to a predetermined limit.

  Also, the Local-CPU of this information processing apparatus determines whether a new error is detected, the number of retries reaches the threshold, or the path between CPUs is made redundant, as indicated by L15 in FIG. If you can, you can retry properly.

1 CPU
2 Main memory 11 Core 12 Cache 13 Cache control unit 14 Memory control unit 131 Control information storage unit 132 Data storage unit 133 Request packet transmission unit 134 Response packet transmission unit 135 Timeout detection unit 136 Protocol check unit 137 Retry availability determination unit 138 Fixed failure Detection unit 141 Request packet reception unit 142 Management information storage unit 143 Protocol check unit 144 Management information update unit 145 Main memory data update unit 146 Response packet transmission unit

Claims (8)

In an information processing apparatus comprising: a first arithmetic processing device having a main memory control device that controls a main storage device; and a second arithmetic processing device connected to the first arithmetic processing device.
The first arithmetic processing unit includes a management information storage unit that holds management information indicating a management state including presence / absence of change of data taken out from the main storage unit to the second arithmetic processing unit;
A receiving unit for receiving an update request for requesting an update of the management information;
A check unit that determines whether the management state indicated by the management information and the received update request satisfy a predetermined relationship;
Information indicating retry is added to the update request, the received update request updates the management state from the first state to the second state, and the management information has already been updated to the second state. A response packet transmitter that transmits a completion response indicating that the update request has been normally completed to the second arithmetic processing unit,
An information processing apparatus.   As a result of the check by the check unit, if the management state and the received update request are in a matching relationship based on a predetermined criterion, is the response packet transmission unit given information indicating retry to the update request? 2. The information processing apparatus according to claim 1, wherein the information processing apparatus transmits a completion response indicating that the update request has ended normally to the second arithmetic processing apparatus regardless of whether or not.   As a result of checking by the check unit, when the management state and the received update request are not in a relationship that matches the predetermined criteria, and information indicating retry is not given to the received update request The information processing apparatus according to claim 2, wherein the response packet transmission unit notifies an error to a predetermined notification destination.   As a result of the check by the check unit, the management state and the received update request are not in a relationship that matches with the predetermined criterion, information indicating retry is given to the update request, and the management information is The information processing apparatus according to claim 2 or 3, wherein the response packet transmission unit notifies an error to a predetermined notification destination when it has not been updated to the second state. In the arithmetic processing device that operates as the first arithmetic processing device connected to the second arithmetic processing device,
A main memory control device for controlling the main memory device;
A management information storage unit for holding management information indicating a management state including the presence / absence of change of data taken out from the main storage device to the second arithmetic processing unit;
A receiving unit for receiving an update request for requesting an update of the management information;
A check unit that determines whether the management state indicated by the management information and the received update request satisfy a predetermined relationship;
Information indicating retry is given to the update request, the received update request updates the management state from the first state to the second state, and the management information has already been updated to the second state. A response packet transmitter that transmits a completion response indicating that the update request has been normally completed to the second arithmetic processing unit,
An arithmetic processing unit having In a method for controlling an information processing apparatus, comprising: a first arithmetic processing device having a main memory control device that controls a main storage device; and a second arithmetic processing device connected to the first arithmetic processing device. 1 arithmetic processing unit,
Holding management information indicating a management state including whether or not the data taken out from the main storage device to the second arithmetic processing unit is changed;
Receiving an update request for updating the management information;
Determining whether the management state indicated by the management information and the received update request satisfy a predetermined relationship;
Information indicating retry is given to the update request, the received update request updates the management state from the first state to the second state, and the management information has already been updated to the second state. If so, a control method for the information processing apparatus that transmits a completion response indicating that the update request has been normally completed to the second arithmetic processing apparatus.   The second arithmetic processing unit transmits an update request for updating the state information to the first arithmetic processing unit, and a completion response to the transmitted update request is not obtained from the first arithmetic processing. 7. The information processing apparatus control method according to claim 6, wherein a retry process for transmitting a next update request in which information indicating retry is set to the first arithmetic process is repeated up to a predetermined limit.   8. The predetermined limit is determined by at least one of the number of retries and an operating state of the information processing apparatus including a connection state between the first arithmetic processing apparatus and the second arithmetic processing apparatus. A method for controlling the information processing apparatus according to claim 1.

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