JP2017103279A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of outputting a large current with a high level of safety.SOLUTION: A semiconductor device according to an embodiment includes: a first conductor; a semiconductor chip one surface of which has a first electrode and the other surface of which has a second electrode; a conductive first joint material that is provided between the first conductor and first electrode; a second conductor that includes a first part having a first surface and a second part having a second surface which is provided between the first part and semiconductor chip and whose area is narrower than the area of the first surface; a conductive second joint material that is provided between the second electrode and second surface; and a resin member that is provided so as to cover at least a peripheral edge part of the semiconductor chip.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a semiconductor device.

  In semiconductor devices that handle high voltages of several kilovolts (kV) and large currents of several kiloamperes (kA), it is necessary to suppress the temperature rise during operation as much as possible, and there are cases where a large number of switching elements are connected in parallel. is there.

  There is a semiconductor module in which a plurality of switching elements connected in parallel are mounted in a single package. In such a semiconductor module, it is necessary to realize low thermal resistance and ensure high safety.

JP-A-8-330338

  An object of the embodiment is to provide a semiconductor device capable of high current output with high safety.

  The semiconductor device according to the embodiment includes a first conductor, a semiconductor chip having a first electrode on one surface and a second electrode on the other surface, and between the first conductor and the first electrode. A conductive first bonding material provided; a first portion having a first surface; and a second surface having a smaller area than the first surface provided between the first portion and the semiconductor chip. A second conductor having a second conductor, a conductive second bonding material provided between the second electrode and the second surface, and at least a peripheral portion of the semiconductor chip. A resin member.

1A and 1B are diagrams illustrating a semiconductor device according to a first embodiment. FIG. 1A is a front view, FIG. 1B is a plan view, and FIG. 1C is a bottom view. Fig.2 (a) is AA 'arrow sectional drawing of FIG.1 (b). FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG. FIG. 3A is a plan view of the semiconductor chip, and FIG. 3B is a bottom view of the semiconductor chip. FIG.3 (c) is the C section enlarged view of Fig.2 (a). It is a bottom view of the gate wiring board of a semiconductor device. FIG. 5A is a perspective view illustrating the semiconductor device of the first embodiment, and FIG. 5B is an exploded view of the semiconductor device of FIG. FIG. 6A is a cross-sectional view illustrating a semiconductor device according to the second embodiment, and FIG. 6B is a cross-sectional view taken along line DD ′ in FIG. It is a perspective view which illustrates the cover for the 1st resin member of the semiconductor device of a 2nd embodiment. It is a figure which illustrates the semiconductor device which concerns on 3rd Embodiment. 8A is a cross-sectional view taken along the line EE ′ of FIG. 8B, FIG. 8B is a plan view, and FIG. 8C is a bottom view. It is a figure which illustrates the semiconductor device concerning a 4th embodiment, and Drawing 9 (a) is a FF 'arrow sectional view of Drawing 9 (b), and Drawing 9 (b) is a top view. FIG. 9C is a bottom view. FIG. 10A is a bottom view of the gate wiring substrate of the semiconductor device of the fifth embodiment. FIG. 10B is a bottom view illustrating the second conductor of the semiconductor device according to the fifth embodiment. FIG.10 (c) is GG 'arrow sectional drawing of FIG.10 (b). FIG. 10D is a cross-sectional view taken along the line HH ′ of FIG. FIG. 11A is a bottom view illustrating a state in which the gate wiring substrate is disposed on the second conductor of the semiconductor device of the fifth embodiment. FIG.11 (b) is KK 'arrow sectional drawing of Fig.11 (a). FIGS. 12A and 12B are enlarged views of a part of a semiconductor device according to a sixth embodiment, FIG. 12A and FIG. 12B are front views, and FIG. 12C is a plan view of FIG. It is. It is a figure which illustrates the semiconductor device concerning a 7th embodiment, and Drawing 13 (a) is a top view and Drawing 13 (b) is a MM 'arrow sectional view of Drawing 13 (a). is there. FIG. 14A is a cross-sectional view illustrating a semiconductor element of the semiconductor device of the seventh embodiment. FIG. 14B is a plan view illustrating a gate wiring substrate of the semiconductor device of the seventh embodiment. 10 is a partially exploded view illustrating a semiconductor device according to a seventh embodiment; FIG. It is a figure which illustrates the semiconductor device of 8th Embodiment, Fig.16 (a) is a top view, FIG.16 (b) is NN 'arrow sectional drawing of Fig.16 (a). FIG. 17A is a cross-sectional view taken along the line PP ′ of FIG. FIG. 17B is a cross-sectional view taken along the line QQ ′ of FIG. FIG. 17C is a cross-sectional view taken along the line RR ′. FIG. 17 is a cross-sectional view illustrating a part of the semiconductor device according to the eighth embodiment and corresponding to a cross section taken along line NN ′ of FIG. It is a perspective view which illustrates a part of semiconductor device of 8th Embodiment. FIG. 20A to FIG. 20D are cross-sectional views illustrating variations of the conductive elastic member of the semiconductor device of the eighth embodiment. FIG. 20 (e) is a plan view of FIG. 20 (d). It is a top view which illustrates the short circuit board of the semiconductor device of 8th Embodiment. It is sectional drawing for demonstrating operation | movement of the semiconductor device of 8th Embodiment. FIG. 17 is a cross-sectional view corresponding to the cross section taken along the line RR ′ of FIG. It is a perspective view which illustrates some semiconductor devices of a 9th embodiment. FIG. 17 is a cross-sectional view corresponding to the cross section taken along the line NN ′ of FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
1A to 1C are a front view (FIG. 1A), a plan view (FIG. 1B), and a bottom view (FIG. 1) illustrating the semiconductor device according to the first embodiment. 1 (c)).
Fig.2 (a) is AA 'arrow sectional drawing of FIG.1 (b). FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG.
FIG. 3A is a plan view of the semiconductor chip, and FIG. 3B is a bottom view of the semiconductor chip. FIG.3 (c) is the C section enlarged view of Fig.2 (a).
FIG. 4 is a bottom view of the gate wiring substrate of the semiconductor device.
FIG. 5A is a perspective view illustrating the semiconductor device of the first embodiment, and FIG. 5B is an exploded view of the semiconductor device of FIG.
As shown in FIG. 1A to FIG. 1C, FIG. 2A, and FIG. 2B, the semiconductor device 1 of this embodiment includes a first conductor 10, a semiconductor chip 12, and conductivity. The bonding materials 14 and 18, the second conductor 16, and the resin member 20 are provided. The semiconductor device 1 further includes a gate wiring substrate 22. The semiconductor device 1 includes a collector extraction electrode 31, an emitter extraction electrode 30, and a gate extraction electrode 32. The collector extraction electrode 31 is electrically connected to the first conductor 10. The emitter lead electrode 30 is electrically connected to the second conductor 16. The gate extraction electrode 32 is electrically connected to the gate wiring substrate 22 inside. The collector extraction electrode 31, the emitter extraction electrode 30, and the gate extraction electrode 32 are electrically connected to the respective electrodes of the semiconductor chip 12 in the semiconductor device 1 through these. These extraction electrodes are used for connection with an external circuit. The collector extraction electrode 31 and the emitter extraction electrode 30 may be provided with a bolt insertion port at substantially the center of the extraction portion so that connection with an external circuit can be made by a bolt or the like. As will be described later, the first conductor 10 and the second conductor 16 are electrically connected to the collector electrode 12b and the emitter electrode 12c of the semiconductor chip 12, respectively. The semiconductor device 1 includes the first conductor 10 and the second conductor. 16 may be connected to an external circuit. The first conductor 10 and the second conductor 16 reduce the thermal resistance and transient thermal resistance of the semiconductor device 1 by connecting a heat sink (not shown) to the surface exposed to the outside. The semiconductor device 1 includes a plurality of semiconductor chips 12. Hereinafter, Z-axis and Y-axis orthogonal to each other in the direction parallel to the surface of the semiconductor chip 12 are taken, and the direction orthogonal to the X-axis and Y-axis and going from the collector electrode 12b of the semiconductor chip to the emitter electrode 12c is positive. An orthogonal coordinate system with axes is used.

  As shown in FIG. 1B, FIG. 1C, and FIG. 2B, the semiconductor chip 12 has three 3 × 3 matrices along the X-axis direction and three along the Y-axis direction. Are arranged in a shape. As shown in FIGS. 2A and 2B, the semiconductor chips 12 are arranged in substantially the same XY plane. The number of semiconductor chips 12 included in the semiconductor device 1 is not limited to 3 × 3, and can be arbitrarily set according to, for example, a required output current capacity. The number in the X-axis direction and the number in the Y-axis direction may be different. For example, a matrix of 1 × 3, 6 × 7, or the like may be used.

  The semiconductor chip 12 is a power semiconductor chip, for example, a switching element having a control electrode such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor chip 12 may be a diode such as FRD (Fast Recovery Diode). These semiconductor chips 12 may not all be the same chip, and a chip of a switching element such as IGBT and a chip of a diode such as FRD may be mixed.

  Hereinafter, a case where the semiconductor chip 12 is an IGBT chip will be described. As shown in FIGS. 3A and 3B, the semiconductor chip 12 includes a semiconductor substrate 12a, a collector electrode 12b, an emitter electrode 12c, and a gate electrode 12d. The semiconductor substrate 12a is, for example, silicon (Si). Although not shown, in the case of an IGBT chip, a p layer, an n layer provided on the p layer, an active region provided in the n layer, and the like Is included. In addition to Si, the semiconductor substrate 12a may be silicon carbide (SiC), gallium nitride (GaN), or the like. The collector electrode 12b is provided on one surface of the semiconductor substrate 12a. For the collector electrode 12b, for example, an alloy containing nickel (Ni), gold (Au) or the like is plated on one surface of the semiconductor substrate 12a and is in ohmic contact with the semiconductor substrate 12a. The emitter electrode 12c and the gate electrode 12d are provided on the surface of the semiconductor substrate 12a opposite to the collector electrode 12b. Since the gate electrode 12d is a control electrode, almost no current flows, so the area of the gate electrode 12d is smaller than the area of the emitter electrode 12c. A gate conductor 13 is connected to the gate electrode 12d in order to be electrically connected to the gate wiring substrate 22, and the area of the gate electrode 13d can be connected to the end of the gate conductor 13. In this example, the gate electrode 12 d is provided in the vicinity of one of the four corners of the semiconductor chip 12. The emitter electrode 12c and the gate electrode 12d are formed on the active layer of the semiconductor chip 12 by using, for example, aluminum (Al) or the like by vapor deposition or sputtering. The emitter electrode 12c and the gate electrode 12d are electrically insulated by the insulating layer 12e.

  As shown in FIG. 3C, the collector electrode 12 b is bonded to the first conductor 10 via the conductive bonding material 14 and is electrically connected to the first conductor 10. The emitter electrode 12 c of the semiconductor chip 12 is bonded to the second conductor 16 via the conductive bonding material 18 and is electrically connected to the second conductor 16. The semiconductor chip 12 is sandwiched between the first conductor 10 and the second conductor 16, and is held at a position between the first conductor 10 and the second conductor 16 by the conductive bonding materials 14 and 18. . The semiconductor chip 12 is at least peripherally covered with the resin member 20. The resin member 20 covers the periphery and the periphery of the semiconductor chip 12 so that the semiconductor chip 12 does not come into contact with air. The resin member 20 is a thermosetting resin such as a melamine resin. Since the resin member 20 covers at least the periphery of the semiconductor chip 12 in close contact, when the semiconductor chip 12 suddenly generates heat, air and bubbles around the semiconductor chip 12 expand and the semiconductor device 1 explodes. To prevent.

  The first conductor 10 includes a flat plate 10a and a post portion 10b. The flat plate 10a is a flat plate-like portion having a first main surface 17a substantially parallel to the XY plane. The post portion 10b is a prismatic portion extending in the positive direction of the Z-axis from the surface opposite to the first main surface 17a of the flat plate 10a. A second main surface 17b substantially parallel to the XY plane is provided at the open end of the post portion 10b. The second main surface 17b of the post portion 10b has a substantially square shape and is bonded to the collector electrode 12b of the semiconductor chip 12 via the conductive bonding material 14. For the first conductor 10, for example, a metal material having high conductivity and high thermal conductivity including copper or an alloy containing copper is used.

  The second conductor 16 includes a flat plate 16a and a post portion 16b. The flat plate 16a is a flat plate-like portion having a first main surface 19a substantially parallel to the XY plane. The post portion 16b is a prismatic portion extending in the negative direction of the Z-axis from the surface opposite to the first main surface 19a of the flat plate 16a. A second main surface 19b substantially parallel to the XY plane is provided at the open end of the post portion 16b. The second main surface 19b of the post portion 16b has a substantially square shape, and is bonded to the emitter electrode 12c of the semiconductor chip 12 via the conductive bonding material 18. Therefore, the emitter electrode 12 c is electrically connected to the second conductor 16. For the second conductor 16, the same metal material as that of the first conductor 10 is used. For example, copper or an alloy containing copper is used.

  The second conductor 16 may have the same shape as the first conductor 10 or may have a different shape. For example, the area of the second main surface 17b of the post portion 10b of the first conductor 10 and the area of the second main surface 19b of the post portion 16b of the second conductor 16 may be set differently. In general, since the area of the collector electrode 12b of the semiconductor chip 12 is larger than the area of the emitter electrode 12c, sufficient bonding can be achieved by setting the areas of the second main surfaces 17b and 19b according to the respective areas. It is possible to secure the area and facilitate the assembly process. Further, the post portions 10b and 16b are not limited to the case where the respective connecting portions with the flat plates 10a and 16a are provided at a right angle, but the connecting portions are provided with a curvature or connected with a surface having an obtuse angle. Or you may. The shape of the post portions 10b and 16b is not limited to a prism, and may be a polygonal column or a cylinder. As described in detail in the description of the manufacturing method, since the resin member 20 is filled between the adjacent post portions 10b and 16b, the connecting portion between the flat plate 10a and the post portion 10b has a curvature or an obtuse angle. The resin member 20 can be uniformly filled by forming the surface to have. Further, the lengths (heights) of the post portions 10b and 16b in the Z-axis direction may be the same or different. Moreover, either the 1st conductor 10 or the 2nd conductor 16 does not have a post part, and may be only a flat plate.

  A conductive bonding material 14 is used for bonding the first conductor 10 and the collector electrode 12 b of the semiconductor chip 12. A conductive bonding material 18 is used for bonding the second conductor 16 and the second conductor 16 of the semiconductor chip 12. For example, solder is used for the conductive bonding materials 14 and 18. In addition to the solder, a conductive adhesive containing conductive particles such as silver particles is used. As the materials of the conductive bonding materials 14 and 18, different conductive bonding materials may be used depending on the materials of the collector electrode 12b and the emitter electrode 12c, or the same material may be used.

  The plurality of semiconductor chips 12 arranged in a matrix on the XY plane are electrically connected to the first conductor 10 by the collector electrode 12b and electrically connected to the second conductor 16 by the emitter electrode 12c. The semiconductor chip 12 is sandwiched between the first conductor 10 and the second conductor 16 and is held at a position between the first conductor 10 and the second conductor 16.

  The gate electrode 12 d of the semiconductor chip 12 is connected to the gate wiring substrate 22 through the gate conductor 13. The gate conductor 13 is, for example, an alloy wire containing Al. One end of the gate conductor 13 is connected to the gate electrode 12d using ultrasonic crimping or the like.

  The gate electrode 12d of the semiconductor chip 12 is connected to the gate wiring substrate 22 via the gate conductor 13 extending in the Z-axis direction. As shown in FIG. 4, the gate wiring substrate 22 includes a substrate 22a, wirings 22b, and connection pads 22d. The substrate 22a has an opening 22c. The opening 22c is a portion opened in a cross-sectional shape parallel to the XY plane of the post portion 16b of the second conductor 16, and is provided at a position corresponding to the post portion 16b. The substrate 22a is a flexible substrate using, for example, an insulating material made of polyimide. The gate wiring substrate 22 is not limited to a flexible substrate, and an epoxy substrate, a ceramic substrate, or the like may be used. The wiring 22b is provided on the substrate 22a. The wiring 22b includes wirings 22b1 to 22b3 parallel to the X-axis direction and wiring 22b4 parallel to the Y-axis. The wirings 22b1 to 22b3 are arranged at substantially equal intervals in the Y-axis direction. One end of the wirings 22b1 to 22b3 is connected to the wiring 22b4. The connection pad 22d is provided at a position corresponding to the position of the gate electrode 12d of the semiconductor chip 12. In this example, since the semiconductor chips 12 are arranged in a 3 × 3 matrix, 3 × 3 = 9 connection pads 22d are provided. The wirings 22b1 to 22b3 are connected to connection pads 22d arranged in the X-axis direction, respectively. That is, the connection pad 22d is drawn out to one side of the substrate 22a by the wirings 22b1 to 22b3 in the X-axis direction. The drawn wires are connected to each other by a wire 22b4. A connection pad 22f for the gate extraction electrode 32 is provided on one side of the substrate 22a. A wiring 22b5 is provided between the connection pad 22f and the wiring 22b4, and the wiring 22b4 is electrically connected to the connection pad 22f. As will be described later, a gate extraction electrode 32 is connected to the connection pad 22f by solder bonding or the like, and the gate electrodes 12d of a plurality of semiconductor chips 12 provided in the semiconductor device 1 are connected to each other. 32 is electrically connected.

  The arrangement of the wiring 22b and the connection pad 22d provided on the substrate 22a of the gate wiring board 22 can be arbitrarily set according to the arrangement of the electrodes of the semiconductor chip 12 and the like. Further, when switching a plurality of semiconductor chips 12, in order to balance the switching speed of each semiconductor chip 12, the width and length of the wiring 22b are changed depending on the position of the semiconductor chip 12, or adjacent connection pads are used. An impedance element such as a resistor can be added between 22d.

  The semiconductor device 1 of this embodiment further includes a case 24. The case 24 is provided so as to surround the outer peripheral portions of the flat plate 10 a of the first conductor 10 and the flat plate 16 a of the second conductor 16. The case 24 is a cylindrical body having a square or rectangular cross section parallel to the XY plane. An injection hole 26 for injecting resin is provided on one surface of the case 24. The injection hole 26 is opened in a rectangular shape at the approximate center of one surface of the case 24, for example. The shape of the opening is not limited to a rectangular shape, and may be a square, a circle, or the like. The injection hole 26 is an opening for filling the inner space surrounded by the first conductor 10, the second conductor 16, and the case 24 with a thermosetting resin. The case 24 defines an area where the resin member 20 is filled when the resin member 20 is filled. In addition, a terminal extraction hole 28 for the gate extraction electrode 32 is opened on one surface of the case 24. These openings are provided on the same surface of the case 24 in this example, but can be provided on any surface and position. For the case 24, for example, a heat-resistant synthetic resin such as polycarbonate or polyimide is used.

  In this way, the semiconductor device 1 in which a plurality of semiconductor chips 12 are connected in parallel can be configured.

Next, a method for manufacturing the semiconductor device of this embodiment will be described.
As shown in FIG. 5A, the semiconductor device 1 of this embodiment has a rectangular parallelepiped shape in which a plane parallel to the XY plane includes a substantially rectangular shape. The semiconductor device 1 includes a first conductor 10 and a second conductor 16 on two sides parallel to the XY plane. A side surface of the semiconductor device 1 is surrounded by a case 24, and includes an emitter extraction electrode 30, a gate extraction electrode 32, and a collector extraction electrode 31 on one surface parallel to the YZ plane.

  As shown in FIG. 5B, the semiconductor chip 12 is connected to the second main surface 17 b of the post portion 10 b of the first conductor 10 via the conductive bonding material 14. The conductive bonding material 14 is, for example, solder, but an appropriate bonding material is selected depending on the material of the collector electrode 12b of the semiconductor chip 12 and the like.

  The post portion 16 b of the second conductor 16 is inserted into the opening portion 22 c of the gate wiring substrate 22. The second conductor 16 is connected to the substrate 22a of the gate wiring substrate 22 on the surface of the flat plate 16a opposite to the first main surface 19a. For the connection between the second conductor 16 and the gate wiring substrate 22, for example, a thermosetting adhesive or the like is used.

  In the semiconductor chip 12, the collector electrode 12 b is connected to the post portion 10 b of the first conductor 10. The emitter electrode 12c is connected to the second main surface 19b of the post portion 16b of the second conductor 16 by a conductive bonding material 18 such as solder. One end of a gate conductor 13 is connected to the gate electrode 12 d of the semiconductor chip 12. The other end of the gate conductor 13 is connected to the connection pad 22d of the gate wiring substrate 22 by solder or the like. For the conductive bonding material 18 for the emitter electrode 12c and the gate electrode 12d, an appropriate bonding material is selected according to the material of these electrodes.

  The case 24 is divided into two parts 24a and 24b. A part of the terminal extraction hole 28 for the gate extraction electrode 32 is opened on one divided surface of the portion 24a. The gate extraction electrode 32 is inserted into the terminal extraction hole 28 and connected to the gate electrode 12 d through the gate wiring substrate 22. The gate extraction electrode 32 is connected to the connection pad 22f of the gate wiring substrate 22 by solder or the like. The remaining part of the terminal extraction hole 28 for the gate extraction electrode 32 is opened on one side of the portion 24b of the case 24 divided. When the portion 24b of the case 24 is connected to the portion 24a, the portion 24a and the portion 24b are joined so as to align the extraction hole so that the injection hole 26 and the terminal extraction hole 28 are opened. The portions 24a and 24b of the case 24 are connected with, for example, an adhesive. The portions 24a and 24b are connected to the first conductor 10 and the second conductor 16 with, for example, an adhesive. The adhesive may be, for example, a thermosetting adhesive or an ultraviolet curable adhesive. The collector extraction electrode 31 and the emitter extraction electrode 30 are provided so as to protrude outward from the case 24 for connection to an external circuit. Each of the collector extraction electrode 31 and the emitter extraction electrode 30 may be provided with a bolt insertion hole for connection to an external circuit. The collector extraction electrode 31 is provided so as to extend in the X-axis direction from the end portion of the flat plate 10a, and the emitter extraction electrode 30 is provided so as to extend in the X-axis direction from the end portion of the flat plate 16a. The collector extraction electrode 31 and the emitter extraction electrode 30 may be integrally formed with the first conductor 10 and the second conductor 16, for example, and are connected to the first conductor 10 and the second conductor 16 by welding or the like, respectively. Also good. The collector lead electrode 31 may be formed integrally with the first conductor 10, for example, or may be connected to the first conductor 10 by welding or the like.

  Resin is injected from an injection hole 26 opened in the case 24. The injected resin is filled in the space surrounded by the first conductor 10, the second conductor 16, and the case 24. For filling the resin, for example, by using a vacuum casting technique, it is possible to prevent bubbles from remaining between the resin member 20 and the member such as the first conductor 10 surrounding the resin member 20. Therefore, the resin member 20 can be brought into close contact with the semiconductor chip 12, the conductive bonding materials 14, 18 and the like, and explosion caused by bubbles during rapid heating can be prevented.

  In the semiconductor device 1 assembled as described above, the collector electrodes 12 b of the plurality of semiconductor chips 12 are connected to each other by the first conductor 10. The emitter electrodes 12 c of the plurality of semiconductor chips 12 are connected to each other by the second conductor 16. The gate electrodes 12 d of the plurality of semiconductor chips 12 are connected to each other by a wiring 22 b and a connection pad 22 d provided on the gate wiring substrate 22. As described above, the semiconductor device 1 in which a plurality of semiconductor chips 12 are connected in parallel can be manufactured.

Next, operations and effects of the semiconductor device 1 of the present embodiment will be described.
In order to obtain a large current, a pressure contact type package is known as a method of connecting a plurality of semiconductor chips in parallel to form one package. The pressure-welding type package achieves both low electrical resistance and low thermal resistance by pressing a large number of semiconductor chips together and pressing each semiconductor chip evenly. In the case of a pressure contact type package, in order to maintain the pressure contact state, a stack structure is required in which a load is applied to the pressure contact type package by a disc spring. Therefore, there is a limit to reducing the member cost, and it is difficult to reduce the weight. In addition, in order to press a large number of semiconductor chips uniformly and collectively, each component of the package is required to have high processing accuracy and assembly accuracy, and there is a high barrier to mass productivity.

  On the other hand, in a semiconductor device that handles a large current, when a failure or breakage occurs, it suddenly generates heat. Therefore, if air or bubbles remain inside the semiconductor device, the semiconductor device may explode. Therefore, it is necessary to take an explosion-proof measure for the package of the semiconductor device. As an explosion-proof package for a semiconductor device, there is a method of using a ceramic material or the like, which is a high-strength and high-rigidity material, for an envelope, but this hinders cost reduction of members. In addition, a structure in which a spring member is used in combination with the pressure contact structure is known. However, a more complicated structure is added to the pressure contact structure, which causes further difficulty in reducing the manufacturing cost as well as mass productivity. Furthermore, since the spring member is inserted into the heat dissipation path, it is difficult to reduce the thermal resistance. According to the resin sealing by the transfer mold, the internal bubbles can be removed, so that an explosion-proof package can be realized at a relatively low cost. However, when the transfer molding technique is used, it is difficult to realize a large package, and it is necessary to connect a plurality of transfer molded products in parallel. Further, in the case of sealing by transfer molding, since electrical connection between the semiconductor chip and the extraction electrode is performed using a bonding wire, a lead frame, or the like, there are restrictions on low electric resistance and low thermal resistance.

  In the semiconductor device 1 of this embodiment, the semiconductor chip 12 is sandwiched between the first conductor 10 and the second conductor 16. The semiconductor chip 12 and the first conductor 10 are connected by a conductive bonding material 14 such as solder, and the semiconductor chip 12 and the second conductor 16 are connected by a conductive bonding material 18 such as solder. Therefore, the semiconductor device 1 can be manufactured using an existing assembly technique without requiring high processing accuracy and assembly accuracy unlike the press-contact type package. Since the semiconductor chips 12 are electrically connected to each other by the first conductor 10 and the second conductor 16 without using a bonding wire or the like, low electrical resistance can be realized. Since the heat capacities of the first conductor 10 and the second conductor 16 can be increased, transient thermal resistance can also be reduced.

  In the semiconductor device 1 according to the present embodiment, since the resin member 20 covers at least the peripheral portion of the semiconductor chip 12, even if the semiconductor chip 12 suddenly generates heat, there is an explosion around the semiconductor chip 12. Because there is no air or air bubbles, it will not explode.

  The first conductor 10 has a flat plate 10a and a post portion 10b, and the second conductor 16 has a flat plate 16a and a post portion 16b. Since the resin member 20 is filled in the space formed by these members and the semiconductor chip 12, air and bubbles are almost completely removed from the inside of the semiconductor device 1. Therefore, in the semiconductor device 1, good explosion-proof performance is realized, and mechanical strength against external force can be ensured.

  In the semiconductor device 1 of the present embodiment, the case 24 surrounding the outer circumferences of the first conductor 10 and the second conductor 16 is further provided, so that the first conductor 10, the second conductor 16, and the semiconductor chip 12 are formed. The resin member 20 can be easily filled into the space. Therefore, the semiconductor device 1 that achieves the desired explosion-proof performance is easily realized.

  The first conductor 10 and the second conductor 16 can be manufactured using a known metal material processing technique. For example, a member having an arbitrary size can be easily realized by using techniques such as sheet metal extrusion, punching, casting, and forging. The case 24 can be easily manufactured according to the dimensions of the first conductor 10 and the second conductor 16. Therefore, in the semiconductor device 1 of the present embodiment, the number of semiconductor chips mounted and connected in parallel can be arbitrarily set, and a large package that cannot be realized by transfer molding can be manufactured.

  By using a resin material having high thermal conductivity as the resin member 20, it is possible to further reduce the thermal resistance.

  In the above description, the semiconductor chip 12 is an IGBT. However, the semiconductor chip 12 is not limited to an IGBT. A MOSFET can be used as the semiconductor chip 12 by using the collector electrode as the drain electrode and the emitter electrode as the source electrode. Further, by using the collector electrode as an anode electrode and the emitter electrode as a cathode electrode, the semiconductor chip 12 can be used as a diode such as FRD. When a diode is used as the semiconductor chip 12, the gate wiring substrate 22 may or may not be present. Furthermore, a switching control element such as an IGBT and a diode can be mounted together.

  In the above description, one semiconductor chip 12 is disposed between each of the post portion 10b and the post portion 16b. However, a plurality of semiconductors are provided between the post portion 10b and the post portion 16b. Of course, a chip may be arranged. In this case, the same post portion 10b, 16b is not limited to the case where the same type of semiconductor chip is provided, and different types of semiconductor chips may be provided. For example, the IGBT chip and the FRD chip may be arranged on the same post portion 10b, 16b.

(Second Embodiment)
The resin member 20 provided around the semiconductor chip 12 may include a plurality of types of resin members.
FIG. 6A is a cross-sectional view illustrating the semiconductor device according to this embodiment, and FIG. 6B is a cross-sectional view taken along the line DD ′ in FIG.
FIG. 7 is a perspective view illustrating a cover for the first resin member of the semiconductor device of this embodiment.
As shown in FIGS. 6A and 6B, the semiconductor device 1a of the present embodiment further includes a cover 56. The resin member 20 of the semiconductor device 1a includes a first resin member 20a and a second resin member 20b. The first resin member 20 a is filled in the cover 56. The other components of the semiconductor device 1a are the same as the components of the semiconductor device 1 of the first embodiment, and detailed description thereof is omitted.

  As shown in FIG. 7, the cover 56 for the first resin member is divided into two portions 56a and 56c. One portion 56a has an opening 56b having a shape and an area substantially the same as the cross-sectional shape and area parallel to the XY plane of the post portion 10b at a position corresponding to the post portion 10b of the first conductor 10. The four edges of the portion 56a are bent by approximately 90 ° in the positive direction of the Z-axis, and the portion 56a is convex downward (in the negative direction of the Z-axis). The other portion 56c has a shape and area substantially the same as the shape and area of the cross section parallel to the XY plane of the post portion 16b at a position corresponding to the post portion 16b and the gate conductor 13 of the second conductor 16, and the gate conductor 13 Has an opening 56d having an area for insertion. The four edges of the portion 56c are bent by approximately 90 ° in the negative direction of the Z axis, and the portion 56c is convex upward (in the positive direction of the Z axis). A space for the first resin member 20a is formed inside the cover 56 by aligning the edges of the portions 56a and 56c. The first resin member 20 a is filled in the cover 56. The cover 56 is formed using, for example, a thermosetting resin such as polyimide. An injection hole 58 for the first resin member 20a is opened at the bent edge of the portion 56c of the cover 56.

  In the cover 56, the post portion 10b of the first conductor 10 is inserted into the opening 56b of the portion 56a, and the post portion 16b of the second conductor 16 is inserted into the opening 56d of the portion 56c. Therefore, the semiconductor chip 12 is arranged in the space inside the cover 56. The inside of the cover 56 in which the semiconductor chip 12 is disposed is filled with the first resin member 20a. Between the cover 56 and the case 24, the second resin member 20b is filled. The compressive strength of the first resin member 20a is smaller than the compressive strength of the second resin member 20b. The compressive strength of the first resin member 20a is, for example, 150 MPa in the case of an epoxy resin, and the compressive strength of the second resin member 20b is, for example, 200 MPa in the case of a melamine resin.

Next, a method for manufacturing the semiconductor device 1a of this embodiment will be described.
The semiconductor device 1a of this embodiment can be manufactured by adding several processes to the manufacturing process of the semiconductor device 1 of the first embodiment. Detailed description of the same manufacturing process is omitted.
In the semiconductor device 1a of the present embodiment, the opening 56b of the portion 56a of the cover 56 is inserted into the post portion 10b before the semiconductor chip 12 is connected to the second main surface 17b of the post portion 10b of the first conductor 10. At this time, in order to position the portion 56a of the cover 56 in the Z-axis direction, a flange fp may be provided at an appropriate position around the post portion 10b.

  The semiconductor chip 12 is connected by applying a conductive bonding material 14 such as solder to the second main surface 17b of the post portion 10b.

  The portion 56c of the cover 56 is disposed on the portion 56a so that the position of the opening 56d corresponds to the position of the post portion 16b of the second conductor 16, and the portions 56a and 56c are connected to each other. The portions 56a and 56c can be connected to each other with, for example, an ultraviolet curable adhesive.

  Before connecting the first conductor 10 and the second conductor 16 and connecting the case 24, the first resin member 20a is injected from the injection hole 58, and the inside of the cover 56 is filled with the first resin member 20a and cured. Let

  Thereafter, the semiconductor device 1a can be manufactured by performing the same process as the manufacturing method of the semiconductor device 1 of the first embodiment.

The operation and effect of the semiconductor device 1a of this embodiment will be described below.
In the semiconductor device 1a of this embodiment, the periphery of the semiconductor chip 12 is filled with the first resin member 20a, and the outer side thereof is filled with the second resin member 20b. When the semiconductor chip 12 suddenly generates heat, the semiconductor chip 12, the conductive bonding materials 14, 18 such as solder, the first conductor 10, and the second conductor 16 are thermally expanded by their respective expansion coefficients. When the expansion coefficients of these materials are different, stress concentrates on a specific portion of the semiconductor chip 12 or the conductive bonding materials 14 and 18, and cracks, peeling, or the like may occur at that portion. And even if the cause of heat generation is removed, there is a risk that problems such as the performance of the semiconductor device not returning will occur. In the semiconductor device 1a of the present embodiment, at least the periphery of the semiconductor chip 12 and the outside thereof are covered with resin members having different compressive strengths. In the semiconductor device 1a of the present embodiment, the resin member is selected so that the compressive strength increases from the semiconductor chip 12 toward the first conductor 10 and from the semiconductor chip 12 toward the second conductor 16. . Therefore, the two types of resin members absorb the difference in thermal expansion coefficient between the semiconductor chip 12 and other members. Therefore, in the semiconductor device 1a of the present embodiment, the stress concentration as described above is alleviated and irreversible failures are avoided.

(Third embodiment)
8A and 8B are diagrams illustrating a semiconductor device according to the third embodiment. FIG. 8A is a cross-sectional view taken along the line EE ′ of FIG. 8B, and FIG. FIG. 8 (c) is a bottom view.
In the semiconductor devices 1 and 1a of the above-described embodiment, the case 24 is connected to the first conductor 10 and the second conductor 16 with an adhesive or the like, for example. It may be exposed to severe installation environment such as temperature fluctuation. Therefore, as shown in FIGS. 8A to 8C, the semiconductor device 1b of the present embodiment further includes a screw 36. The case 24 has an insertion hole 34 through which the screw 36 is inserted. The first conductor 10 and the second conductor 16 need to be cut in advance with female screws 37 at respective positions corresponding to the insertion holes 34 of the case 24. The number and mounting positions of the screws 36 can be appropriately and arbitrarily set according to the dimensions and required strength of the semiconductor device 1b. The number of insertion holes 34 opened in the case 24 and the number of female screws 37 of the first conductor 10 and the second conductor 16 are determined by the number of screws 36. In the case of using a self-tapping screw that advances while cutting a female screw when the screw is inserted, it is not necessary to cut the female screw in advance in the first conductor 10 and the second conductor 16.

The operation and effect of the semiconductor device 1b of this embodiment will be described.
In the semiconductor device 1b of the present embodiment, the semiconductor chip 12 is sandwiched between the first conductor 10 and the second conductor 16 and connected via the conductive bonding materials 14 and 18, so that the semiconductor device of the above-described embodiment. Like 1 and 1a, it has high strength against stress including force in the Z-axis direction. In addition, in the semiconductor device 1b, the case 24 and the first conductor 10 are connected by a screw 36, and the case 24 and the second conductor 16 are connected by a screw 36. Further, in the semiconductor device 1b, the case 24 is supported from the periphery of the first conductor 10 and the second conductor 16, that is, from the side surfaces, and is fastened by screws 36 in the X-axis direction and the Y-axis direction. Therefore, in the semiconductor device 1b, the strength can be improved against a stress including a force parallel to the XY plane. In this way, the semiconductor device 1b of this embodiment has high mechanical strength even in an installation environment such as outdoors, and can improve reliability.

(Fourth embodiment)
FIG. 9 is a diagram illustrating the semiconductor device according to this embodiment. FIG. 9A is a cross-sectional view taken along the line FF ′ of FIG. 9B, and FIG. FIG. 9C is a bottom view.
The first main surface 17a of the first conductor 10 and the first main surface 19a of the second conductor 16 including the semiconductor devices 1 to 1b of the above-described embodiments are thermally connected to the heat sink, and are generated in the semiconductor chip 12. Efficiently dissipates the generated heat. In the semiconductor device 1c of this embodiment, the shapes of the first conductor 10 and the second conductor 16 are different from those of the semiconductor devices 1 to 1b of the other embodiments described above so that the semiconductor device 1c can be easily attached to the heat sink.

  As shown in FIGS. 9A to 9C, the semiconductor device 1 c according to this embodiment includes a first conductor 10 and a second conductor 16. The first conductor 10 includes a flat plate 10a and a post portion 10b. A flange 10c is provided on the outer periphery of the flat plate 10a. The flange 10c is provided on the outer periphery of the flat plate 10a. The flange 10 c extends in the X-axis and Y-axis directions from the position of the surface of the case 24 when the first conductor 10 is combined with the second conductor 16 and the case 24. The flange 10c includes insertion holes 10d for a plurality of mounting screws opened in the Z-axis direction. After the first main surface 17a of the first conductor 10 is brought into close contact with the heat sink (not shown) in the insertion hole 10d, a screw is inserted to fix the first conductor 10 and the heat sink. The second conductor 16 includes a flat plate 16a and a post portion 16b. The flat plate 16a includes a flange 16c. The flange 16c is provided on the outer periphery of the flat plate 16a. The flange 16 c extends from the position of the surface of the case 24 in the X-axis direction and the Y-axis direction when the second conductor 16 is combined with the first conductor 10 and the case 24. The flange 16c includes a plurality of insertion holes 16d opened in the Z-axis direction for mounting screws. The first main surface 19a of the second conductor 16 is brought into close contact with the heat sink (not shown) in the insertion hole 16d, and then a screw (not shown) is inserted to fix the second conductor 16 and the heat sink.

  The semiconductor device 1c of the present embodiment includes insertion holes 10d and 16d in the flange 10c of the first conductor 10 and the flange 16c of the second conductor 16, respectively. Therefore, the semiconductor device 1c can be easily attached and fixed with a heat sink. By screwing the semiconductor device 1c to the heat sink, the thermal resistance between the first conductor 10 and the heat sink and the thermal resistance between the second conductor 16 and the heat sink can be reduced.

(Fifth embodiment)
FIG. 10A is a bottom view of the gate wiring substrate of the semiconductor device of this embodiment. FIG. 10B is a bottom view illustrating the second conductor of the semiconductor device of this embodiment. FIG.10 (c) is GG 'arrow sectional drawing of FIG.10 (b). FIG. 10D is a cross-sectional view taken along the line HH ′ of FIG.
FIG. 11A is a bottom view illustrating a state in which the gate wiring substrate is disposed on the second conductor of the semiconductor device of this embodiment. FIG.11 (b) is KK 'arrow sectional drawing of Fig.11 (a).
In the semiconductor devices 1 to 1c described above, the gate wiring substrate 22 is used to connect the gate electrodes 12d of the respective semiconductor chips 12 to each other. The gate wiring substrate 22 includes an insulating substrate 22 a having an opening 22 c at a shape and position corresponding to the post portion 16 b of the second conductor 16. A connection pad 22d is provided on the substrate 22a at a position corresponding to the gate electrode 12d of each semiconductor chip 12, and the connection pads 22d are connected by a connection wiring 22e. Each connection pad 22 d is connected to the gate electrode 12 d of each semiconductor chip 12 through the gate conductor 13. The semiconductor device of this embodiment includes a gate wiring substrate 52 having a shape different from that of the other embodiments. Since the material of the substrate is the same as that of the semiconductor device 1 of the first embodiment, detailed description thereof is omitted.

  As shown in FIG. 10A, the gate wiring substrate 52 of the semiconductor device of this embodiment includes a substrate 52a, wiring 52b, and connection pads 52d and 52f. A conductor is provided on the entire surface of one surface of the substrate 52a to form a wiring 52b. Therefore, the shape of the wiring 52b is the same as the shape of the substrate 52a, and will be described below as the shape of the substrate 52a. The substrate 52a includes a first portion 52a1, a second portion 52a2, and a third portion 52a3. The first portion 52a1 extends in the X-axis direction. The second portion 52a2 has substantially the same length as the first portion 52a1, and extends substantially parallel to the first portion 52a1. The third portion 52a3 is connected to one end of the first portion 52a1 and the second portion 52a2 at both ends, and extends in the Y-axis direction. The first portion 52a1 has a plurality of connection pads 52d protruding in the Y-axis direction at the edge parallel to the X-axis. The second portion 52a2 has a plurality of connection pads 52d protruding in the Y-axis direction at the edge parallel to the X-axis. The connection pads 52d are disposed at positions corresponding to the gate electrodes 12d of the semiconductor chip 12, respectively. The gate wiring substrate 52 further includes a fourth portion 52a4 between the connection pad 52f and the third portion 52a3. Each connection pad 52d is drawn out by the first portion 52a1, the second portion 52a2, the third portion 52a3, and the fourth portion 52a4 of the substrate 52a, and is electrically connected to the connection pad 52f.

  As shown in FIGS. 10B to 10D, the post portion 16b of the second conductor 16 has a notch 16e at one corner on the second main surface 19b side. The notch 16e is provided at a position corresponding to the gate electrode 12d of the semiconductor chip 12. The depth of the notch 16e in the Z-axis direction is set to about the thickness of the gate wiring substrate 52. The shape and area of the notch 16e on the XY plane are set to be approximately the same as the shape and area of the connection pad 22d of the gate wiring substrate 22. As in the case of the above-described embodiment, three post portions 16b are provided on the surface of the flat plate 16a opposite to the first main surface 19a in the X-axis direction and three in the Y-axis direction. Are arranged in a matrix. Here, the signs of the post portion 16b are 16b1 to 16b9 in order from the upper left toward the positive direction of the X axis and toward the positive direction of the Y axis. The position of the notch 16e differs depending on the positions of the post portions 16b1 to 16b9. The post portions 16b1 to 16b6 are provided at the lower right corner of the drawing, and the post portions 16b7 to 16b9 are provided at the upper left corner of the drawing. When the gate electrode 12d of the semiconductor chip 12 is arranged at the corner of the semiconductor substrate 12a, the position of the gate electrode 12d can be changed by changing the arrangement angle of the semiconductor chip 12. In the semiconductor device of this embodiment, the second portion 52a2 of the gate wiring substrate 52 is set to be wider than the first portion 52a1, and is commonly used for the semiconductor chips 12 arranged in the post portions 16b4 to 16b9. Therefore, the mounting angle of the semiconductor chip 12 disposed in the post portions 16b7 to 16b9 is rotated by 180 ° in the clockwise direction in the bottom view with respect to the mounting angle of the semiconductor chip 12 disposed in the other post portions 16b1 to 16b8. Yes.

  As shown in FIG. 11A, the gate wiring substrate 52 is disposed on the post portion 16b side of the second conductor 16 so that the conductor portions such as the connection pads 52d are directed in the negative direction in the Z-axis direction. The gate wiring substrate 52 is disposed such that the connection pad 52d is fitted into the notch 16e of the post portion 16b. The connection pad 52d and the notch 16e are connected by, for example, an ultraviolet curable adhesive.

  As shown in FIG. 11B, when the collector electrode 12b and the emitter electrode 12c of the semiconductor chip 12 are soldered to the post portions 10b and 16b, respectively, the gate electrode 12d is soldered to the connection pad 52d. . The gate electrode 12d of the semiconductor chip 12 is connected to the connection pad 52d through the solder 54, connected to the gate electrode 12d of the other semiconductor chip 12 through the wiring 52b, and connected to an external circuit through the connection pad 52f. .

  According to the semiconductor device of the above-described embodiment, the gate electrode 12d and the gate wiring substrate 52 can be directly connected without using the gate conductor 13. Therefore, there is less risk of connection failure due to the gate conductor 13 being flowed at the resin injection pressure when the resin member 20 is injected, and the manufacturing process can be simplified. Further, the amount of the member of the substrate 52a of the gate wiring substrate 52 can be reduced, and the cost can be reduced.

(Sixth embodiment)
12A is a front view of the post portion of the first conductor, FIG. 12B is a front view of the post portion of the second conductor, and FIG. 12C is a plan view of the post portion of the first conductor. It is. The bottom view of the post portion of the second conductor is the same as the plan view of the post portion of the first conductor.
The first conductor 10 of the semiconductor device according to the present embodiment includes a flat plate 10a and a post portion 10b. As shown to Fig.12 (a), the convex part 10f which protrudes from the surface is provided in the side surface of the post part 10b. The convex portion 10f surrounds the periphery of the side surface of the post portion 10b in a screw thread shape. Also for the second conductor 16 of the semiconductor device, the post portion 16b is provided with a convex portion 16f. As shown in FIG. 12B, the convex portion 16f surrounds the periphery of the post portion 16b in a screw thread shape. As shown in FIGS. 12A to 12C, the surfaces 10g and 16g of the convex portions 10f and 16f include components of normal vectors parallel to the Z axis.

  Since the convex portions 10f and 16f are respectively formed on the side surfaces of the post portions 10b and 16b, the surface areas of the post portions 10b and 16b are increased. Therefore, the contact area between the side surfaces of the post portions 10b and 16b and the resin member 20 increases. Therefore, the bonding strength between the post portions 10b and 16b and the resin member 20 is increased, and the reliability such as moisture resistance is improved. Further, the contact thermal resistance between the post portions 10b and 16b and the resin member 20 is reduced, and the heat dissipation performance of the semiconductor device is improved. Furthermore, the convex portions 10f and 16f have surfaces 10g and 16g including a normal component parallel to the Z axis. Therefore, since the surfaces 10g and 16g are subjected to stress with respect to the force in the Z-axis direction, the bonding strength is improved as compared with the case where there are no protrusions 10f and 16f. Accordingly, the adhesion between the post portions 10b and 16b and the resin member 20 is improved, and the resistance and mechanical strength due to the temperature cycle and thermal shock are improved in the semiconductor device.

(Seventh embodiment)
13A and 13B are diagrams illustrating the semiconductor device according to this embodiment. FIG. 13A is a plan view, and FIG. 13B is a cross-sectional view taken along line MM ′ in FIG. FIG.
FIG. 14A is a cross-sectional view illustrating a portion of the semiconductor element of the semiconductor device of this embodiment. FIG. 14B is a plan view illustrating a gate wiring substrate of the semiconductor device of this embodiment.
FIG. 15 is a partially exploded view illustrating the semiconductor device of this embodiment.
As shown in FIGS. 13A and 13B, the semiconductor device 70 of this embodiment includes a semiconductor element 72 and conductive bonding materials 74 and 76.

  As shown in FIG. 14A, the semiconductor element 72 includes a first conductor 80, a semiconductor chip 12, conductive bonding materials 84 and 88, a second conductor 86, and a resin member 90a. The semiconductor chip 12 is the same as in the other embodiments described above, and detailed description thereof is omitted. The first conductor 80 includes a flat plate 80a and a post portion 80b. The post portion 80b is provided on the surface opposite to the first main surface 87a of the flat plate 80a. The collector electrode 12b of the semiconductor chip 12 is connected to the second main surface 87b, which is an open surface of the post portion 80b. The second conductor 86 includes a flat plate 86a and a post portion 86b. The post portion 86b is provided on the surface of the flat plate 86a opposite to the first main surface 89a. The second main surface 89b, which is an open surface of the post portion 86b, is connected to the emitter electrode 12c of the semiconductor chip 12. Therefore, the semiconductor chip 12 is bonded to and electrically connected to the first conductor 80 via the conductive bonding material 84. The semiconductor chip 12 is bonded to and electrically connected to the second conductor 86 via the conductive bonding material 88. As described above, the semiconductor chip 12 is sandwiched between the first conductor 80 and the second conductor 86 via the conductive bonding materials 84 and 88 and fixed by the conductive bonding materials 84 and 88. The semiconductor chip 12 is covered so that at least the peripheral edge thereof is not exposed to air by the resin member 90a. The resin member 90a is preferably a low stress resin member having a low compressive strength. One end of a gate conductor 13 is connected to the gate electrode 12d of the semiconductor chip 12, and the other end of the gate electrode is open. The semiconductor elements 72 are configured as described above, and a plurality of the semiconductor elements 72 are arranged in a matrix on the XY plane, and the flat plates 80a of the first conductors 80 of the adjacent semiconductor elements 72 are connected to each other by the conductive bonding material 74. . The flat plates 80 a of the second conductor 86 are also connected to each other by the conductive bonding material 76. The conductive bonding materials 74 and 76 are conductive conductive bonding materials, and the first conductor 80 and the second conductor 86 of all the semiconductor elements 72 are electrically connected to each other. The conductive bonding materials 74 and 76 are, for example, a conductive adhesive containing conductive particles.

  The gate wiring substrate 52 shown in FIG. 14B is the same as the gate wiring substrate described in the fifth embodiment.

A method for manufacturing the semiconductor device 70 of this embodiment will be described.
The required number of semiconductor elements 72 are manufactured as follows.

  The collector electrode 12b of the semiconductor chip 12 is bonded to and electrically connected to the first conductor 80 by a conductive bonding material 84 such as solder applied on the second main surface 87b of the post portion 80b of the first conductor 80. The

  The emitter electrode 12c is joined to and electrically connected to the second conductor 86 by a conductive joining material 88 such as solder applied on the second main surface 89b of the post portion 86b of the second conductor 86.

  The first resin member 90 a is formed on the periphery of the semiconductor chip 12 by an encapsulating mold (not shown) provided so as to cover the periphery of the semiconductor chip 12.

  After the necessary number of the semiconductor elements 72 are manufactured, the semiconductor elements 72 are arranged in a 3 × 3 matrix on the XY plane, and are bonded to each other by the conductive bonding materials 84 and 86. Reference numerals of the semiconductor elements arranged in a matrix are denoted as 721 to 729 in order in the positive direction of the X axis and in the positive direction of the Y axis.

  As shown in FIG. 15, a gate wiring substrate 52 is inserted between adjacent post portions 16b of semiconductor elements 72 arranged in a matrix. In the case of this example, the first portion 52a1 of the substrate 52a is inserted between the post portions of the semiconductor elements 721, 724, 727 and the post portions of the semiconductor elements 722, 725, 728. A second portion 52a2 of the substrate 52a is inserted between the post portions of the semiconductor elements 722, 725, 728 and the post portions of the semiconductor elements 723, 726, 729. The gate wiring substrate 52 is inserted so that the position of the connection pad 52d of the gate wiring substrate 52 matches the position of the other end of the gate conductor 13 connected to the gate electrode 12d of each semiconductor chip 12. After the positioning, the connection pad 52d and the other end of the gate conductor 13 are soldered.

  Thereafter, the divided cases are connected, resin is injected, and the resin member 90b is filled. The resin member 90b is a resin material having a higher compressive strength than the resin member 90a.

  In the semiconductor device 70 of the present embodiment, since the semiconductor elements 72 are bonded after individually manufacturing the same semiconductor elements 72, a higher yield can be expected as compared with the other embodiments in which all the semiconductor chips are mounted simultaneously. . Further, since a large number of the same semiconductor elements 72 are manufactured, the cost can be reduced due to the mass production effect.

  When the first resin member 90a is provided around the semiconductor chip 12, the use of a dedicated resin injection mold eliminates the need for a cover for the first resin member, thereby reducing the cost.

  The semiconductor device 70 can be configured by using only the semiconductor element 72, and an arbitrary number of matrices can be configured without newly designing the first conductor and the second conductor. High degree.

(Eighth embodiment)
16A and 16B are diagrams illustrating the semiconductor device of this embodiment. FIG. 16A is a plan view, and FIG. 16B is a cross-sectional view taken along line NN ′ of FIG.
FIG. 17A is a cross-sectional view taken along the line PP ′ of FIG. FIG. 17B is a cross-sectional view taken along the line QQ ′ of FIG. FIG. 17C is a cross-sectional view taken along the line RR ′.
FIG. 18 is a cross-sectional view illustrating a part of the semiconductor device of this embodiment and corresponding to a cross section taken along line NN ′ of FIG.
FIG. 19 is a perspective view illustrating a part of the semiconductor device of this embodiment.
FIG. 20A to FIG. 20D are cross-sectional views illustrating variations of the conductive elastic member of the semiconductor device of this embodiment.
FIG. 21 is a plan view illustrating a short-circuit plate of the semiconductor device of this embodiment.
FIG. 22 is a cross-sectional view for explaining the operation of the semiconductor device of this embodiment.
As shown in FIGS. 16A and 16B, the semiconductor device 100 of this embodiment includes a plurality of first conductors 110, a plurality of second conductors 116, elastic members 120 and 122, and a semiconductor chip. 12, a resin member 20, conductive members 130 and 134 having elastic portions, and short-circuit plates 132 and 136.

  Each of the plurality of first conductors 110 includes a flat plate 110a and a post portion 110b. The flat plate 110a is a substantially rectangular or rectangular plate-like body having a first main surface 117a parallel to the XY plane, and each side of the rectangular or rectangular shape is disposed along the X axis and the Y axis. In this example, the first conductors 110 are arranged in a matrix of 3 in the X-axis direction and 3 in the Y-axis direction, that is, 3 × 3. The post portion 110b is a columnar body that extends from the surface of the flat plate 110a opposite to the first main surface 117a in the substantially central portion of the flat plate 110a in the positive direction of the Z axis. Each side of the side surface of the columnar body is arranged in parallel to the X axis and the Y axis. The first conductor 110 is, for example, copper or an alloy containing copper as a main component, and is a good electrical and thermal conductor.

  An elastic member 120 is provided between the side surfaces of the flat plates 110a of the adjacent first conductors 110 arranged in a matrix. The elastic member 120 is a material having a sufficiently small elastic modulus as compared with the metal such as the first conductor 110, and is a material having a sufficiently small elastic modulus after being cured, such as heat curable adhesive silicon. It is. As will be described later, since the electrical and thermal connection between the adjacent first conductors is ensured by the conductive member 130 and the short-circuit plate 132, the elastic member 120 itself is not necessarily required to have electrical conductivity or thermal conductivity. The elastic member 120 may of course use a conductive resin material containing conductive particles such as silver, but priority is given to resistance to deformation due to repeated stress absorption.

  Peripheral conductors 140, 141, 142 are provided around the plurality of first conductors 110 arranged in a matrix. The peripheral conductor 140 is provided along the X-axis direction, and the peripheral conductor 142 is provided along the Y-axis direction. The peripheral conductor 141 is provided so as to be adjacent to both the peripheral conductor 140 and the peripheral conductor 142. That is, the peripheral conductor 140 is arranged on the side of the plurality of first conductors 110 that does not have the first conductor 110 adjacent to the side along the X axis, and the first conductor 110 adjacent to the side along the Y axis is arranged. The peripheral conductors 142 are arranged on the side not having them. The peripheral conductor 141 is provided at a corner where the first conductor 110 and the peripheral conductors 140 and 142 are arranged. These peripheral conductors 140 to 142 are also connected to adjacent conductors by the elastic member 120 in the same manner as the first conductor 110. The peripheral conductors 140 to 142 are made of the same metal material as the first conductor 110. The peripheral conductors 140 to 142, together with the first conductor 110, provide a path for current and heat flow, and thus are connected to a conductive member 130 and a short-circuit plate 132 described later. The peripheral conductors 140 to 142 may not be used. When the peripheral conductors 140 to 142 are not used, the semiconductor device 1 can be reduced in size.

  As shown in FIGS. 17A to 17C, the conductive member 130 is disposed so as to surround the periphery of the side surface of the post portion 110b. A lower end 131b (FIG. 19) of the conductive member 130 is connected to a surface of the flat plate 110a opposite to the first main surface 117a. The short-circuit plate 132 is provided so as to pass through the post portion 110b. The short-circuit plate 132 is connected to the upper end 131 a of the conductive member 130. That is, the upper end 131a (FIG. 19) of the conductive member 130 is electrically and thermally connected by the short-circuit plate 132, and the lower end 131b of the conductive member 130 is electrically and thermally connected to the first conductor. ing. Therefore, the adjacent first conductors 110 are electrically and thermally connected by the conductive member 130 and the short-circuit plate 132. Therefore, as shown in FIG. 18, the plurality of first conductors 110, the conductive member 130, and the short-circuit plate 132 form one electrical and thermal conductor 102.

  As shown in FIG. 19, the conductive member 130 is provided so as to surround the post portion 110 b of the first conductor 110. The side surface of the post portion 110b and the conductive member 130 may be disposed in close contact with each other. However, when considering a margin of accuracy for connection between the conductive member 130 and the short-circuit plate 132, the conductive member 130 is It is preferable to arrange so that the outer periphery of the post part 110b is surrounded with a certain clearance.

  The conductive member 130 includes an upper end 131a, a lower end 131b, and a side surface 131c. The conductive member 130 is a closed cylindrical body having a side surface 131c. The upper end 131a is included in one XY plane, and is electrically and thermally connected to the short-circuit plate 132 in the XY plane. The lower end 131b is included in another XY plane, and is electrically and thermally connected to the first conductor 110 in the XY plane. The side 131c includes a bellows structure having one mountain fold 131d surrounding the side 131c, as shown in FIG. The mountain fold 131d is a portion that is bent toward the outside of the side surface 131c that is a cylindrical body. The bent portion may be bent at an acute angle or may be curved. Since the side surface 131c includes the bellows structure, the side surface 131c can freely follow the displacement in each direction of XYZ. That is, the side surface 131c can absorb a stress including components in each direction of XYZ. Since the side surface 131c of the conductive member 130 has a structure that absorbs displacement such as a bellows structure, even if the elastic member 120 is displaced under stress due to thermal expansion of the first conductor 110, the side surface 131c is elastic. It functions as a member having the same elastic modulus as the member 120.

  The shape of the side surface of the conductive member only needs to be able to absorb stress including components in each direction of XYZ, and some shape variations are considered. As shown in FIG. 20B, the conductive member 130a includes an upper end 132a, a lower end 132b, and a side surface 132c, and the side surface 132c includes a bellows structure having one valley fold 132d. The valley fold 132d is a portion that bends toward the inside of the side surface 132c that is a cylindrical body. Similar to the mountain fold portion, the bent portion may be an acute angle or a curved surface. Even if it replaces with the mountain fold part 131d as the valley fold part 132d, the electrically-conductive member 130a can follow freely to the displacement of each direction of XYZ. As another variation, as shown in FIG. 20 (c), the conductive member 130b includes an upper end 133a, a lower end 133b, and a side surface 133c, and the side surface 133c includes two mountain folds 133d and one valley. An accordion structure having a folding part 133e may be used. In the bellows structure of the conductive member, the number of mountain folds and valley folds can be set appropriately and arbitrarily. Thus, in the bellows structure, it is sufficient that at least one of the mountain fold portion and the valley fold portion is included. However, as the number of the mountain fold portion and the valley fold portion increases, it can follow a minute displacement. it can. The conductive member only needs to have a shape that absorbs stress including components in each direction of XYZ, and the shape is not limited to the bellows structure. As shown in FIGS. 20D and 20E, the conductive member 130c includes a strip-shaped side member 134c. The side member 134c is processed so as to expand toward the lower end 134b, and the upper end 134a. The shape etc. which were connected by may be sufficient. By using the side member 134c processed into a curved surface, the conductive member 130c can follow the displacement in each of the XYZ directions. The curved surface processing can be S-shaped as shown or other shapes.

  The conductive member 130 is made of a material having high conductivity and high thermal conductivity, such as copper or an alloy containing copper as a main component. The conductive member 130 is formed by using a bellows-shaped extrusion die or the like from a thin plate of copper or an alloy containing copper as a main component.

  As shown in FIG. 21, the short-circuit plate 132 has openings 172 provided at the positions where the post portions 110b are provided as many as the number of the post portions 110b. The opening 172 is opened so as to be approximately equal to the shape and area of the cross section along the XY plane of the post portion 110b. The short-circuit plate 132 is made of a material having high electrical conductivity and thermal conductivity, such as copper or an alloy containing copper as a main component.

  In the above description, the conductive member 130 and the short-circuit plate 132 have been described as different members.

  Each of the plurality of second conductors 116 includes a flat plate 116a and a post portion 116b. The flat plate 116a is a substantially rectangular or rectangular plate body having a plane parallel to the XY plane, and each side of the square or rectangle is arranged along the X axis and the Y axis. In this example, they are arranged in a 3 × 3 matrix like the first conductor. An elastic member 122 is provided between the side surfaces of the flat plates 116 a of the adjacent second conductors 116. The post part 116b is a columnar body extending in the negative direction of the Z-axis at a substantially central part of the flat plate 116a from the surface opposite to the first main surface 119a of the flat plate 116a. Each side of the side surface of the columnar body is parallel to the X axis and the Y axis. The conductive member 134 is arranged so as to surround the periphery of the side surface of the post portion 116b. A lower end 135b of the conductive member 134 is connected to a surface of the flat plate 116a opposite to the first main surface 119a. The short-circuit plate 136 is provided so as to be inserted through the post portion 116b. The short-circuit plate 136 is connected to the upper end 135 a of the conductive member 134. As shown in FIGS. 16 and 18, the second conductor 116, the conductive member 134, and the short-circuit plate 136 are formed substantially the same as the first conductor 110, the conductive member 134, and the short-circuit plate 136. In addition, a thermal conductor 104 is formed.

  The conductive member 134 and the short-circuit plate 136 can be formed in the same manner as the conductive member 130 and the short-circuit plate 132 described above.

  Other components are the same as those of the semiconductor device of the fifth embodiment, for example, and are given the same reference numerals and detailed description thereof is omitted.

Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described.
First, a plurality of first conductors 110 are arranged in a 3 × 3 matrix in this example, and are connected to each other by an elastic member 120 that is an adhesive.

  After the elastic member 120 is cured, the conductive member 130 is disposed so as to pass through the 3 × 3 post portions 110b, and the flat plate 110a and the lower end 131b of the conductive member 130 are joined by solder or the like.

  The post portion 110b is inserted into each opening 172 of the short-circuit plate 132, and the upper end 131a of the conductive member 130 and the short-circuit plate 132 are joined by solder or the like.

  It should be noted that the connection between the conductive member 130 and the flat plate 110a or the short-circuit plate 132 is not limited to solder, and a known connection technique such as a conductive adhesive can be used.

  Similar to the first conductor 110, the plurality of second conductors 116 are arranged in a 3 × 3 matrix and are connected to each other by the elastic member 122.

  After the elastic member 122 is cured, the conductive member 134 is disposed so that the 3 × 3 post portions 116b are inserted, and the flat plate 116a and the lower end 135b of the conductive member 134 are joined by solder or the like.

  The post portion 116b is inserted into each opening 176 of the short-circuit plate 136, and the upper end 135a of the conductive member 134 and the short-circuit plate 136 are joined by solder or the like.

  The semiconductor chip 12 is disposed on the second main surface 117b of the post portion 110b via a conductive bonding material 14 such as solder, and the post portion 110b and the collector electrode 12b of the semiconductor chip 12 are connected. As shown in FIG. 18, the second main surface 117b of the post portion 110b is a surface opposite to the first main surface 117a of the first conductor 110.

  The emitter electrode 12c of the semiconductor chip 12 is connected to the second main surface 119b of the post portion 116b via a conductive bonding material 18 such as solder.

  The gate wiring substrate 52 is inserted between the post portions 110b and 116b, and each gate electrode 12d of the semiconductor chip 12 and each connection pad 52d on the gate wiring substrate 52 are connected by solder or the like.

  A case 24 is attached around the above-described components.

  Resin is injected from the injection hole 26 opened in the case 24 and cured.

  In the semiconductor device 100 assembled as described above, the collector electrodes 12b of the plurality of semiconductor chips 12 are connected to each other by the conductor 102 including the first conductor 110, the conductive member 130, and the short-circuit plate 132. The emitter electrodes 12 c of the plurality of semiconductor chips 12 are connected to each other by a conductor 104 including a second conductor 116, a conductive member 134, and a short-circuit plate 136. The gate electrodes 12 d of the plurality of semiconductor chips 12 are connected to each other by a wiring 52 b and a connection pad 52 d provided on the gate wiring substrate 52. As described above, the semiconductor device 100 in which the plurality of semiconductor chips 12 are connected in parallel can be manufactured.

Next, the operation of the semiconductor device 100 of this embodiment will be described.
In many cases, the semiconductor device 100 can be operated with a large current and low loss by using it together with a cooler. As shown in FIG. 22, the cooler 150 includes two cooling plates 152 and 154. The cooler 150 may be either air-cooled or liquid-cooled. In the case of an air-cooled cooler, for example, a large number of fins are formed on the heat radiation side of the two cooling plates 152 and 154, and in the case of liquid cooling, for example, inside the cooling plates 152 and 154 A heat pipe through which a cooling medium flows is formed. The upper and lower cooling plates 152 and 154 are fixed so as to be in close contact with the first main surfaces 117a and 119a of the first conductor 110 and the second conductor 116, respectively, in order to reduce thermal resistance. In the case of a cooler for a flat semiconductor element, the upper and lower cooling plates 152 and 154 are brought into close contact with the first main surfaces 117a and 119a by tightening them in the Z-axis direction using bolts and nuts insulated from each other. To achieve a low thermal resistance. That is, once the cooling plates 152 and 154 are attached, they cannot move substantially in the Z-axis direction.

  With the cooler 150 attached as described above, the semiconductor chips 12 connected in parallel are energized. The first conductor 110 and the second conductor 116 expand in response to the heat generated by the semiconductor chip 12. The first conductor 110 and the second conductor 116 try to expand evenly in the XYZ directions. However, since the cooling plates 152 and 154 of the cooler 150 are fixed in the Z-axis direction, the displacement in this direction The expansion amount corresponding to is in the other direction. Stress based on the amount of expansion in the Z-axis direction is applied to the semiconductor chip 12 as indicated by arrows a1 to a3 and a11 to a13 in FIG. On the other hand, the side surfaces of the post portions 110b and 116b expand toward the direction in which the resin member 20 is filled. Since the resin member 20 has a smaller elastic modulus than the semiconductor chip 12 and the conductive bonding materials 14 and 18, the resin member 20 can absorb some stress due to expansion. Furthermore, since the elastic members 120 and 122 have a smaller elastic modulus than the resin member 20, the stress that is not absorbed by the resin member 20 is absorbed by the elastic members 120 and 122. That is, some of the stresses in the directions of the arrows a1 to a3 and a11 to a13 are in the direction of the X axis (not shown because of the sectional view in FIG. 22 but the Y axis) as indicated by arrows a4 to a9 and a14 to a19 The component is mainly applied to the elastic members 120 and 122. The stress generated based on the thermal expansion is absorbed by the elasticity of the elastic members 120 and 122.

  The adjacent first conductor 110 and second conductor 116 are electrically and thermally connected by conductive members 130 and 134 and short-circuit plates 132 and 136 each having a low elastic modulus portion. The lower ends 131 b and 135 b of the conductive members 130 and 134 are connected across the elastic members 120 and 122, but the bellows structure of the side surfaces 131 c and 135 c of the conductive members 130 and 134 is about the same as the elastic members 120 and 122. The elastic members 120 and 122 and the resin member 20 are displaced so as to absorb the displacement difference due to the difference in elasticity. Therefore, the state of a good electrical and thermal conductor between the plurality of first conductors 110 and the plurality of second conductors 116 is maintained.

  Hereinafter, the operation of the semiconductor device 100 will be described more quantitatively. The first conductor 110 or the second conductor 116 of the semiconductor device 100 is made of copper, and the first conductor 110 or the second conductor 116 is increased by 55 ° C. (in the case of the initial temperature t0 = 25 ° C., the temperature is increased to t = 80 ° C.). Considering the case, the thermal stress σ at that time can be obtained by the following equation (1).

σ = α · (t−t0) · E (1)
Here, α is a linear expansion coefficient, and E is a Young's modulus.

Below, the physical constant of copper is used as a linear expansion coefficient and a Young's modulus.
σ = 17.7 × 10 ⁻⁶ [° C. ⁻¹ ] × 55 [° C.] × 129.8 [GPa]
≒ 0.1 [GPa]

  That is, a stress of about 0.1 GPa is applied to the semiconductor chip 12, and the semiconductor chip 12 may have problems such as cracking and peeling due to this stress.

On the other hand, when the amount of expansion ΔL of the first conductor 110 or the second conductor 116 is calculated from the linear expansion coefficient α of copper, the result is as follows.
ΔL = 17.7 × 10 ⁻⁶ [° C. ⁻¹ ] × 55 [° C.] × L × 100 [%]
≒ 0.1 [%] × L

  If the length of the first conductor 110 or the second conductor 116 in the Z-axis direction is, for example, L = 20 [mm], ΔL = 20 [μm]. Therefore, the elastic members 120 and 122 only need to have an elastic modulus that can absorb a displacement of about 20 μm. More specifically, the Young's modulus of the elastic members 120 and 122 needs to be 1/1000 or less of the Young's modulus of copper. The Young's modulus of general silicone rubber or the like is about several MPa to several tens of MPa, and can sufficiently satisfy the above-described requirements.

Next, functions and effects of the semiconductor device 100 of this embodiment will be described.
As described above, the semiconductor device 100 of this embodiment includes the elastic members 120 and 122 between the adjacent first conductor 110 and second conductor 116, respectively. Therefore, the displacement due to the thermal expansion of the first conductor 110 and the second conductor 116 is absorbed by the elastic members 120 and 122. The conductive members 130 and 134 that electrically and thermally connect the adjacent first conductors 110 and the second conductors 116 have side surfaces 131c and 135c having a low elastic modulus structure such as a bellows structure. . Therefore, the conductors 102 and 104 can maintain an electrical and thermal connection state. Therefore, a highly reliable semiconductor device with high current can be realized.

  Generally, current deviation occurs depending on the arrangement of the semiconductor chip 12, and there are variations in the on-voltage, switching speed, etc. of the semiconductor chip 12 itself. In such a state, the amount of expansion of the first conductor 110 and the second conductor 116 that are directly thermally coupled to the semiconductor chip 12 that generates a large amount of heat is larger than the others. It is considered that there is a high risk of occurrence of defects. Such a situation needs to be considered regardless of the presence or absence of the cooler 150. In the semiconductor device 100 of the present embodiment, the elastic members 120 and 122 and the conductive members 130 and 134 can absorb displacement according to the amount of expansion, so that a highly reliable semiconductor device is realized.

(Ninth embodiment)
FIG. 23 is a cross-sectional view illustrating the semiconductor device of this embodiment and corresponding to the cross section taken along the line RR ′ of FIG.
FIG. 24 is a perspective view illustrating a part of the semiconductor device of this embodiment.
In the semiconductor device 100 of the above-described embodiment, the conductive members 130 and 134 are arranged so as to surround the respective post portions 110b and 116b of the first conductor 110 and the second conductor 116. Good.

  As shown in FIG. 23, the conductive member 130 f is disposed between the opposite corner portions of the post portions 110 b of the adjacent first conductors 110. As shown in FIG. 24, the lower end 135b of the conductive member 130f is connected to the flat plate 110a of the adjacent first conductor 110 by solder or the like. Although not shown, the upper end 135a of the conductive member 130f is connected to the short-circuit plate 132 by solder or the like.

  As described above, the conductive members 130f and 134f can be connected to the short-circuit plates 132 and 136 at appropriate and arbitrary positions. The conductive members 130f and 134f and the short-circuit plates 132 and 136 are constituent members for the plurality of first conductors 110 and the plurality of second conductors 116 to form the single conductors 102 and 104, respectively, and are connected in parallel. It can be a current path when a current imbalance between the plurality of semiconductor chips 12 occurs. Various causes of current imbalance among the plurality of semiconductor chips 12 are conceivable. However, in the case of non-uniform current paths, they can be made closer to each other depending on the arrangement positions of the conductive members.

(Tenth embodiment)
FIG. 25 is a cross-sectional view illustrating the semiconductor device of this embodiment and corresponding to a cross section taken along line NN ′ of FIG.
As shown in FIG. 25, the semiconductor device 100 b of this embodiment further includes insulating layers 162 and 164. The insulating layer 162 is provided between the cooling plate 152 of the cooler 150 and the first main surface 117 a of the first conductor 110. The insulating layer 164 is provided between the cooling plate 154 and the first main surface 119 a of the second conductor 116. The semiconductor device 100b further includes a collector extraction electrode 31 and an emitter extraction electrode 30. The collector extraction electrode 31 and the emitter extraction electrode 30 are extraction electrodes for the collector electrode 12b and the emitter electrode 12c described in the semiconductor device 1 and the like of the first embodiment. Therefore, although a detailed description is omitted, in the present embodiment, the first conductor 110 and the second conductor 116 are electrically insulated by the insulating layers 162 and 164, respectively. Therefore, the collector extraction electrode 31 and the emitter extraction electrode 30 is required for connection with an external circuit.

  The insulating layers 162 and 164 are provided for electrical insulation between the first conductor 110 and the cooling plate 152 and electrical insulation between the second conductor 116 and the cooling plate 154, respectively. The insulating layers 162 and 164 are so-called insulating sheets, and are made of, for example, a resin. When the insulating layers 162 and 164 have a low elastic modulus, the stress due to thermal expansion of the first conductor 110 and the second conductor 116 is absorbed while the cooling plates 152 and 154 are fixed when the cooler 150 is installed. be able to.

The operation and effect of the semiconductor device 100b of this embodiment will be described.
In the semiconductor device 100b of this embodiment, the cooler 150, the first conductor 110, and the second conductor 116 are electrically insulated from each other, so that the cooler 150 can be set to zero potential. Therefore, for example, a conductive liquid such as ethylene glycol can be used as the refrigerant of the cooler 150. When the first conductor 110 and the second conductor 116 and the cooler 150 are not insulated and the cooling plates 152 and 154 have potentials, pure water or the like is used as a non-conductive refrigerant. A rate management device or the like is required, and the system tends to increase in size. In the semiconductor device 100b of this embodiment, the refrigerant can be used regardless of whether it is conductive or not, so that the structure of the cooler 150 can be simplified and the system can be downsized.

  In the case where an elastic rubber-like material or the like is used as the insulating layers 162 and 164, stress due to thermal expansion of the first conductor 110 and the second conductor 116 can be absorbed, and the more reliable semiconductor device 100b can be obtained. Can be realized.

  According to the embodiment described above, it is possible to realize a semiconductor device capable of high current output with high safety.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

  1-1c Semiconductor device, 10 1st conductor, 10a flat plate, 10b post part, 10c flange, 10d insertion hole, 10f convex part, 10g surface, 12 semiconductor chip, 12a semiconductor substrate, 12b collector electrode, 12c emitter electrode, 12d gate Electrode, 13 Gate conductor, 14 Conductive bonding material, 16 Second conductor, 16a Flat plate, 16b Post part, 16c Flange, 16d Insertion hole, 16e Notch part, 16f Convex part, 16g surface, 17a First main surface, 17b First 2 main surfaces, 18 conductive bonding material, 19a first main surface, 19b second main surface, 20 resin member, 20a first resin member, 20b second resin member, 22 gate wiring substrate, 22a substrate, 22b wiring, 22c Opening, 22d connection pad, 22f connection pad, 24 case, 26 injection hole, 27-29 Terminal extraction hole, 30 emitter extraction electrode, 31 collector extraction electrode, 32 gate extraction electrode, 34 insertion hole, 36 mounting screw, 37 female screw, 52 gate wiring substrate, 52a substrate, 52b wiring, 52d connection pad, 52f connection pad, 54 Solder, 56 cover, 58 injection hole, 70 semiconductor device, 72 semiconductor element, 74, 76 conductive bonding material, 78 case, 80 first conductor, 80a flat plate, 80b post portion, 84 conductive bonding material, 86 second conductor , 86a flat plate, 86b post portion, 88 conductive bonding material, 100, 100b semiconductor device, 110 first conductor, 110a flat plate, 110b post portion, 116 second conductor, 116a flat plate, 116b post portion, 117a, 119a first main Surface, 120, 122 elastic member, 130, 134 conductive member, 132,136 Short-circuit plate, 150 cooler, 152,154 Cooling plate, 162,164 Insulating layer

Claims (13)

A first conductor;
A semiconductor chip having a first electrode on one side and a second electrode on the other side;
A conductive first bonding material provided between the first conductor and the first electrode;
A second conductor having a first portion having a first surface, and a second portion having a second surface which is provided between the first portion and the semiconductor chip and has an area smaller than the area of the first surface; ,
A conductive second bonding material provided between the second electrode and the second surface;
A resin member provided so as to cover at least a peripheral portion of the semiconductor chip;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the second portion is a columnar body extending in a first direction orthogonal to the second surface, and the first surface is parallel to the second surface.   The semiconductor device according to claim 2, wherein the resin member is provided so as to cover a side surface of the second portion. The semiconductor chip further has a control electrode on the other surface,
The semiconductor device according to claim 1, further comprising a substrate that is provided between the second conductor and the control electrode and includes a wiring connected to the control electrode. A case member surrounding the first conductor and the second conductor;
The semiconductor device according to claim 1, wherein the resin member is filled in a portion surrounded by the first conductor, the second conductor, and the case member.   The resin member is provided so as to cover at least a peripheral portion of the semiconductor chip and a periphery of the first resin member, and has a greater compressive strength than the first resin member. The semiconductor device according to claim 1, further comprising: a second resin member having   The semiconductor device according to claim 6, further comprising a holding member between the first resin member and the second resin member. A first conductor;
A plurality of semiconductor chips each having a first electrode on one side and a second electrode on the other side;
A conductive first bonding material provided between the first conductor and each first electrode;
A first portion each having a first surface; and a plurality of second portions each having a second surface provided between the first portion and the plurality of semiconductor chips and having an area smaller than the area of the first surface; A second conductor having
A conductive second bonding material provided between the second electrode and the second surface;
A resin member provided to cover at least the peripheral edge of each of the plurality of semiconductor chips;
A semiconductor device comprising: A first conductor;
A semiconductor chip having a first electrode on one side and a second electrode on the other side; a conductive first bonding material provided between the first conductor and the first electrode; A second conductor having a first portion having one surface, and a second portion having a second surface which is provided between the first portion and the semiconductor chip and has an area smaller than the area of the first surface; A plurality of semiconductor elements comprising: a conductive second bonding material provided between the second electrode and the second surface; and a resin member provided so as to cover at least a peripheral portion of the semiconductor chip; ,
A conductive third bonding material for connecting the first conductors of each of the plurality of semiconductor elements;
A conductive fourth bonding material connecting the second conductors of each of the plurality of semiconductor elements;
A semiconductor device comprising: A first conductor;
A second conductor;
A first elastic member provided between the first conductor and the second conductor;
A third portion having a first portion having a first surface, and a second portion having a second surface provided between the first portion and the first conductor and having an area smaller than the area of the first surface. Conductors,
A fourth portion having a third portion having a third surface, and a fourth portion having a fourth surface provided between the third portion and the second conductor and having an area smaller than the area of the third surface. Conductors,
A second elastic member provided between the first part and the third part;
A first end electrically connected to the first conductor between the first conductor and the third conductor;
A second end electrically connected to the second conductor between the second conductor and the fourth conductor;
A first conductive member including a fifth portion having elasticity between the first end and the second end;
A third end electrically connected to the first portion between the first conductor and the first portion;
A fourth end electrically connected to the third portion between the second conductor and the third portion;
A second conductive member including a sixth portion having elasticity between the third end and the fourth end;
A junction between the first conductor and the second conductor, having a first electrode on one surface and a second electrode on the other surface, the junction between the first electrode and the first conductor A first semiconductor chip connected to the first conductor by a material and connected to the second portion by a bonding material between the second electrode and the second portion;
A junction between the third conductor and the second conductor, provided between the second conductor and the fourth portion, having a third electrode on one side and a fourth electrode on the other side. A second semiconductor chip connected to the second conductor by a material and connected to the fourth portion by a bonding material between the fourth electrode and the fourth portion;
A resin member covering at least a peripheral portion of the first semiconductor chip and the second semiconductor chip;
A semiconductor device comprising:   11. The second conductive member is configured such that the third end portion surrounds the second portion and is connected to the first portion, and the sixth portion surrounds the second portion. The semiconductor device described.   The second conductive member has a third end connected to the first part between the second part and the third part, and a fourth end connected to the fourth part and the first part. 11. The semiconductor device according to claim 10, wherein the semiconductor device is connected to the third portion in between, and the sixth portion is provided starting from a connection position between the third end portion and the first portion. A first insulating layer provided on the first main surface and the second main surface;
A second insulating layer provided on a surface opposite to the first semiconductor chip of the first conductor and on a surface opposite to the second semiconductor chip of the second conductor; ,
Further comprising
The first conductor has a first terminal extending in a first direction;
The semiconductor device according to claim 10, wherein the third conductor has a second terminal extending in the second direction.

Images