JP2017092055A - Structure of flash memory and operation method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a finer cell size in a NOR flash memory.SOLUTION: A MOS memory cell transistor is formed by providing: an U-shaped groove to a semiconductor substrate, a gate insulation film of a triple-layered insulation film of which the second layer is a charge accumulation layer in the groove, a gate electrode onto them, and a source and drain diffusion layer to both ends of the groove. An upper surface of the gate electrode to which the U-shaped groove is embedded is existed at lower than the upper surface of the source and drain diffusion layer, and an insulation film is laminated to the gate electrode. At a direction perpendicularly crossed with the U-shaped groove, an element separation trench groove is formed, a thickness insulation film is embedded, the U-shaped groove corresponding to the source and drain and the separation trench groove are arranged in a matrix direction, and a memory array cell is constructed. The gate electrode in the U-shaped groove is connected between the adjacent memory cells separated by the trench groove, and becomes a word line. The charge accumulation layer is, for example, a silicon nitride film. In such a case, it becomes SONOS type nonvolatile memory cell.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a structure of a flash memory, which is an electrically rewritable nonvolatile semiconductor memory device, and a method for reading, writing and erasing the flash memory.

  At present, various NOR flash memories have been proposed and put into practical use. As shown in FIG. 29, a floating gate type and a SONOS type have been put to practical use as a main flash memory storage element (Non-patent Document 1). Further, as a structure of the flash memory, a 1-transistor, 1.5-transistor, 2-transistor, and 3-transistor shapes are put into practical use. Each has advantages and disadvantages, but focusing on the cell size, the 1.5-transistor, 2-transistor, and 3-transistor configurations have the disadvantage of increasing the cell size as the number of transistors increases compared to one transistor. The 1.5 transistor shape has a large cost increase due to the complexity of the structure. Although the floating gate type with one transistor is widely used as a batch erase NOR type flash memory, it is difficult to miniaturize the memory cell in this structure as well.

  FIG. 30 shows a sectional view of a conventional SONOS one-transistor NOR type flash memory, and FIG. 31 shows a circuit of the memory cell array (Non-patent Document 2). A memory cell 30 shown in FIG. 30 is a MOS transistor having a charge storage layer. A gate insulating film 33 and a gate electrode 32 (hereinafter referred to as a control gate) made of a three-layer insulating film are formed on a P-type silicon substrate 31. The regions formed sequentially are defined as channels, and a thick insulating film 36 is formed on both sides of the gate insulating film 33 with an N-type diffusion layer formed on the substrate 31 to form a source 34 and a drain 35. The gate insulating film Reference numeral 33 denotes a three-layered silicon oxide film 33-1, silicon nitride film 33-2, and silicon oxide film 33-3 from the substrate side, and the silicon nitride film 33-2 is a charge storage layer.

FIG. 31 shows a memory cell array 40 in which the memory cells 30 of FIG. 30 are arranged in a matrix. In the matrix arrangement of the memory cell array, the memory cell array 40 includes a word line 37 having the control gates 32 commonly connected in the row direction, and a source line 39 and a bit line 38 having the sources 34 or drains 35 commonly connected in the column direction. Is controlled. The source line 39 and the bit line 38 are formed of a diffusion layer.

When hot-electron injection is performed for writing into the memory cell 30, a high voltage of 4V or higher is applied to the drain 35, a positive potential close to 0V to 0V is applied to the source 34, and a selected control gate 31 has a voltage close to 10V. Give high voltage. As a result, electrons having high energy are generated in the vicinity of the drain 35, and a part thereof is injected into the silicon nitride film 33-2 of the charge storage layer. Here, in the memory cell array 40, the word line 37-1, the bit line 38-1, and the source line 39-2 are selected, and the word line 37-1 is 10V, the bit line 38-1 is 4V, and the source line 39-2. 0V is applied to the non-selected word lines 37-2 and 37-3, and the non-selected memory cell MC01 is written with the non-selected bit line and the source line floating and the non-selected memory cell MC01 is written. In MC02 and MC03, the non-selected word line is 0V, and the memory transistor is in an off state, but 4V is applied between the bit line and the source line. That is, the control gate 32 is 0V and the voltage between the drain 35 and the source 34 is 4V. However, if the channel length L of the memory cell transistor 30 is shortened, punch-through occurs between the drain 35 and the source 34, and current flows regardless of non-selection. In order to prevent this, the channel length L could not be shortened. Also, the drain of each memory cell is doped with a high concentration of N-type impurities and diffused by a thermal process after doping, and it is difficult to reduce the area of the drain portion. Therefore, there is a limit to the area reduction of the memory cell. As described above, the one-transistor structure is a simple and inexpensive structure, but punch-through between the drain and the source becomes a problem, and there is a limit to the area reduction of the memory cell.

Hideto Hidaka. “Evolution of Embedded Flash Memory Technology for MCU”, in IEEE ICICDT 2011, Tech. Dig. E. Maayan, et al, “A 512Mb NROM Flash data storage memory with 8MB / s data rate”, IEEE ISSCC, Tech. Dig., Pp. 76-77, 2002.

  As described above, in the prior art, it is difficult to manufacture an inexpensive flash memory capable of reducing the cell size. It is an object of the present invention to provide a NOR flash memory that solves this problem.

In the flash memory according to the present invention, a U-shaped groove is provided in a part on a semiconductor substrate, an insulating film in which three layers of insulating films are stacked is provided in the groove, and an intermediate insulating film is a silicon nitride film. . A material having a low electrical resistance is provided on the insulating film to form a gate electrode. A semiconductor region having a conductivity type opposite to that of the semiconductor substrate is provided at both ends of the groove to serve as a source and a drain. A MOS transistor is formed by the above-described source and drain and the insulating film and gate electrode on the U-shaped groove therebetween. The upper portion of the gate electrode is below the upper surfaces of the plurality of source and drain diffusion layers, and an insulating film is stacked on the gate electrode. A trench groove is formed in the semiconductor substrate for element isolation at the other ends of the U-shaped groove, and a thick insulating film is embedded in the groove, and the trench groove becomes a line having the same groove width. Yes. Further, another U-shaped groove and source / drain diffusion layers are formed across the trench, and the above-described MOS transistor is electrically insulated from the source and drain. The gate electrode is connected between the adjacent MOS transistors separated by the trench and serves as a shared gate material. In this structure, the plurality of MOS transistors change in threshold value when electric charges are injected into or removed from the silicon nitride film, and become non-volatile memory cells.
Further, different impurity distributions can be made on the side surface and the lower portion of the U-shaped groove, and different threshold values can be set on the side surface and the lower portion of the U-shaped MOS transistor.

  According to the present invention, the distance between the source diffusion layer and the drain diffusion layer is determined independently of the channel length of the memory cell transistor, and the channel length under the control gate is U-shaped. Since the length can be increased and the short channel effect can be reduced, the distance between the source diffusion layer and the drain diffusion layer can be reduced, so that the memory cell area can be reduced. In addition, since the distance between the connection electrode and the gate electrode for applying a potential to the source and drain can be reduced, the area of the source diffusion layer and the drain diffusion layer can be reduced, and the cell area can also be reduced. It becomes.

1 is a bird's-eye view showing a basic structure of a flash memory cell array according to the present invention, which is used in the first to seventh embodiments. The top view corresponding to FIG. FIG. 3 is a plan view showing a flash memory cell array according to the first and second embodiments of the present invention. FIG. 3 is a circuit diagram of a flash memory cell array according to the first and second embodiments. FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 3. B-B 'sectional view of FIG. C-C 'sectional view of FIG. FIG. 4 is a cross-sectional view taken along the line D-D ′ in FIG. 3. FIG. 6 is a plan view showing a flash memory cell array according to third, fourth, and fifth embodiments. The circuit diagram of the flash memory cell array of 3rd, 4th, 5th embodiment. FIG. 10 is a sectional view taken along line A-A ′ in FIG. 9. B-B 'sectional view of FIG. FIG. 10 is a sectional view taken along the line C-C 'in FIG. D-D 'sectional view of FIG. FIG. 9 is a plan view showing flash memory cell arrays of sixth and seventh embodiments. FIG. 10 is a circuit diagram of a flash memory cell array according to sixth and seventh embodiments. A-A 'sectional view of FIG. B-B 'sectional view of FIG. FIG. 15 is a cross-sectional view taken along the line C-C 'in FIG. D-D 'sectional view of FIG. 9 shows a well structure of a flash memory according to first to seventh embodiments. Circuit diagram corresponding to Table 1 Circuit diagram corresponding to Table 2 Circuit diagram corresponding to Table 3 Circuit diagram corresponding to Table 4 Circuit diagram corresponding to Table 5 Circuit diagram corresponding to Table 6 Circuit diagram corresponding to Table 7 The figure which shows the kind of memory cell of a prior art example Sectional view of a conventional memory cell Circuit diagram of conventional example corresponding to FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. In the following, a one-transistor flash memory is described as an example, but the present invention is not limited thereto.

FIG. 1 is a bird's-eye view showing the structure of the memory cell array of the first embodiment. FIG. 2 shows a plan view thereof. An element isolation trench 5 and a buried insulating film (not shown) are formed in the P well 2, and then a word line 3 is formed by embedding an electrode material after forming a U-shaped groove and a gate insulating film 4, and a source and An N-type diffusion layer is formed in the drain region 1. This N-type diffusion layer 1 becomes the source or drain of each memory cell. Each word line 3 is positioned below the N-type diffusion layer 1 and formed in a linear shape. The element isolation trench 5 is provided in a linear shape so as to be orthogonal to the word line 3. The lower end of the element isolation trench 5 is located below the word line 3 and the upper end is located above the word line to separate adjacent source or drain diffusion layers. At the location where the element isolation region 5 and the word line 3 intersect, the word line 3 extends in a straight line so as to penetrate the element isolation groove 5. A gate insulating film 4 covers the lower and side surfaces of the word line 3. The gate insulating film 4 is composed of, for example, three insulating films, and the second insulating film 4-2 stores positive or negative charges as a charge storage layer of the memory cell. In FIG. 2, a region surrounded by a square broken line is a region corresponding to one memory cell.

One N-type diffusion layer 1 is shared by adjacent memory cells, and two independent N-type diffusion layers are provided in each memory cell with the word line 3 interposed therebetween. A contact portion 7 to the bit line 6 or a contact portion 9 to the source line 8 is provided on the N-type diffusion layer 1, but is located above the word line 3, and the upper portion of the word line is covered with an insulating film. Therefore, even if the position of the contact portion 7 or 9 is slightly shifted and protrudes from the diffusion layer 1, there is no electrical contact with the word line, and the distance between the word line and these contact portions is increased. There is no need to make room, and the cell area can be reduced. In each memory cell, the word line 3 serves as a control gate. Since this gate has a U-shaped shape, the execution channel length of the control gate becomes long, and the punch-through phenomenon due to the short channel is suppressed. Thereby, the control gate width (corresponding to the distance between the source and the drain) can be reduced.

FIG. 21 shows the structure of a silicon substrate including a cell array and a peripheral circuit portion. The peripheral circuit portion is formed on a P-type silicon substrate 19. In the cell array region, a cell portion N well 20 is provided on a P-type silicon substrate 19, and a cell portion P well 2 is provided therein. The memory cell is formed on the cell portion P well 2. The potential of the P-type silicon substrate surface 19 is fixed by applying 0 V to the P-type silicon substrate contact P-type diffusion layer 24. The cell part N well potential 25 is applied via the cell part N well part contact N type diffusion layer 22, and the cell part P well potential 26 is provided via the cell part P well part contact P type diffusion layer 23.

  FIG. 3 is a plan view including bit line and source line wiring. A portion surrounded by a broken line is an area of one memory cell. The bit line 6 and the source line 8 are metal wirings that run perpendicular to each other and are located above the N-type diffusion layer 1, and the metal wiring of the bit line 6 is located above the metal wiring of the source line 8. The bit line contact 7 electrically connects one N type diffusion layer 1 in each memory cell and the bit line 6 which is a metal wiring. The source line contact 9 electrically connects the other N type diffusion layer 1 in each memory cell and the source line 8 which is a metal wiring. The word line 3 runs in parallel with the source line 8 and is orthogonal to the bit line. The element isolation region 5 runs in parallel with the bit line 6.

  FIG. 4 shows a circuit diagram of the memory cell array corresponding to FIG. A region surrounded by a broken line is one memory cell region. A plurality of memory cells are arranged to form a memory cell array. The word line 3 serves as a control gate in one memory cell transistor. A plurality of word lines 3 run in parallel in the memory cell array, and a gate insulating film 4 is provided under the word lines 3. The gate insulating film 4 is a multilayer insulating film, for example, is formed of a three-layer insulating film, and the second insulating film 4-2 can store positive or negative charges as a charge storage layer of the memory cell. The drain portion of the diffusion layer 1 of the memory cell transistor is connected to the bit line 6, and the source portion is connected to the source line 8. Each drain portion and source portion is assigned with every other diffusion layer 1, and each bit line 6 is a drain portion diffusion layer 1 arranged in the horizontal direction and connected in common by a contact 7. Further, all the wirings in which the diffusion layers 1 of the source parts arranged in the direction are commonly connected by the contacts 9 are connected.

FIG. 5 shows a cross-sectional view taken along the line A-A 'of FIG. An element isolation region 5 is provided on the P well 2 in the memory cell region. FIG. 5 is a cross-sectional view taken along a plane orthogonal to a plurality of element isolation regions 5 running in parallel. The gate insulating film 4 and the word line 3 run horizontally on the element isolation trench 5, and the insulating film 10 is laid on the word line 3. Furthermore, a wiring interlayer insulating film 11 is formed thereon. A plurality of bit lines 6 are formed on the wiring interlayer insulating film 11. The second insulating film 4-2 in the gate insulating film 4 is a charge storage layer. FIG. 5 is also a cross-sectional view taken along a plane perpendicular to the plurality of bit lines 6 running in parallel.

FIG. 6 shows a cross-sectional view taken along the line B-B 'of FIG. At the position B-B ′, the word line is not visible, and one source line contact 9 is arranged in each N type diffusion layer 1 and connected to the source line 8. FIG. 7 shows a cross-sectional view taken along the line C-C 'of FIG. Since the C-C ′ section is a section along the center of the bit line 6, the sections of the diffusion layer 1 and the U-shaped word line 3 appear alternately. The P well 2 in the memory cell region is etched into a U shape, and a gate insulating film 4 is first deposited in the U shape groove, and then the word line electrode 3 is embedded. An insulating film 10 is laid on the word line 3. Bit line contacts 7 are arranged in every other N type diffusion layer 1 and connected to the bit line 6. FIG. 8 is a sectional view taken along the line D-D 'in FIG. Since the D-D 'cross section is a cross section along the center of the element isolation trench 5, the U-shaped gate insulating film 4 and the word line 3 are periodically arranged in the element isolation insulating film 12. Further, after the U-shaped etching of the P well 2 in the memory cell region or the deposition of any one of the gate insulating films 4, impurity implantation at a vertical or constant angle is performed from above to form the side surface of the U-shaped groove. It is possible to have different impurity distributions in the lower part.

Table 1 shows the potential relationship between the write, erase, and read operation modes. A circuit diagram corresponding to Table 1 is shown in FIG. The case where the word line-1 and the bit line-1 are selected, that is, the case where the memory cell MC11 is selected is shown. The system of Table 1 is called channel hot electron write FN tunnel erase, and the circuit of FIG. 22 is called a common source line system. In Table 1, the combination of the source line voltage VSL> 0V and the bit line-2 voltage 0V is prohibited because of the current flowing during writing and reading.

First, in writing, the memory cell MC11 at the intersection of the word line-1 and the bit line-1 in FIG. 22 is selectively injected into the charge storage layer 4-2 and written, and the other memory cells MC12, MC21 and MC22 are written. In the charge storage layer, electrons are not injected and are not written. A predetermined positive voltage VBL (program) for writing is applied to the bit line-1, and it is set to 0V or floating state (floating) so as not to write to the bit line-2, and writing to the word line-1 is performed. A predetermined positive voltage VWL (program) is applied, 0 V is applied to the word line -2 so that writing is not performed, and 0 V or a predetermined positive voltage VSL (program) is applied to the source line 8, and the N-type well of the memory cell portion 20 and P well 2 are set to 0V. Here, there is normally a voltage relationship of VWL >> VBL >> VSL, and VWL is approximately 10V, and VBL is 3.5V or more. In the selected memory cell MC11, the memory cell transistor is turned on, and electrons flowing from the source 8 become high energy in the vicinity of the drain with a certain probability because of the predetermined high voltage VWL, exceeding the band barrier of the gate insulating film. It is injected into the charge storage layer 4-2. Therefore, the threshold value of the memory cell MC11 changes in the positive direction (that is, written). In the memory cell MC21 at the intersection of the word line-1 and the bit line-2, the memory cell transistor is turned on. However, since there is no potential difference between the bit line-2 and the source line 8, no current flows and electrons are charged. There is no injection into the storage layer 4-2. In the memory cells MC12 and MC22 connected to the word line-2, since the memory cell transistor is in the OFF state, no current flows, and similarly, no electrons are injected into the charge storage layer 4-2. Therefore, the threshold values of these three non-selected memory cells are not changed by writing.

Erasing is performed at once for all four memory cells in FIG. Fowler-Nordheim tunnel phenomenon (hereinafter referred to as FN tunnel) is applied by applying a voltage of approximately 15V or more (P well side is positive) between the control gate and P well of all memory cell transistors in the batch erase area. Then, electrons injected by writing are extracted from the charge storage layer 4-2 into the P well. Therefore, in FIG. 22, 0V or a predetermined negative voltage VWL (erase) is applied to word line-1 and word line-2, and a predetermined positive voltage Verase is applied to memory cell N well 20 and P well 2. . The bit line-1, the bit line-2, and the source line 8 are applied with a positive voltage Verase or are in a floating state. Even if the bit line and the source line are in a floating state, a current flows from the memory cell portion P well 2 to the drain and source through the PN junction, and automatically becomes substantially the same potential as the P well. As a result, electrons escape from the charge storage layer 4-2 of each of the memory cells MC11 to MC22 to the memory cell portion P well, and the threshold value changes in the negative direction (that is, is erased).

Next, in FIG. 22, when the selected memory cell MC11, that is, the memory cell at the intersection of the word line-1 and the bit line-1, is read, a predetermined positive voltage VBL (read) is applied to the bit line-1. 2 is 0V or in a floating state, a predetermined positive voltage Vread is applied to the word line-1, 0V is applied to the word line-2, 0V to a predetermined positive voltage VSL (read) is applied to the source line 8, and the memory cell section. 0V is applied to the N well 20 and the P well 2. Normally, VBL (read)> VSL (read) is used. Here, if the threshold value of the selected memory cell MC11 is lower than the voltage Vread of the word line-1, a current flows from the bit line-1 to the source line 8, and if the threshold value is higher than Vread, no current flows. Then, a sense amplifier connected to the bit line -1 is detected through a column switch selected by the column decoder to determine whether or not a current flows through the bit line, and a determination of "0" or "1" is made. Since the bit line-2 is not selected, the column switch is turned off and the bit line-2 is not connected to the sense amplifier, and data is not detected.

The memory cell array structure and circuit of the second embodiment are the same as those shown in FIGS. 1 to 8 and 21 shown in the first embodiment. Table 2 shows the potential relationship between the write, erase, and read operation modes. A circuit diagram corresponding to Table 2 is shown in FIG. 23, which is not different from the circuit FIG. 22 of the first embodiment. The write operation and read are also the same as those shown in Table 1. In the second embodiment, erasing is performed using a Band to Band tunnel phenomenon (hereinafter referred to as a BtoB tunnel) instead of an FN tunnel. Place control gates of all memory cell transistors in the region to be erased collectively in a channel cutoff voltage condition with respect to the P-well, and apply a positive voltage higher than causing a BtoB tunnel to the drain or source, thereby making the vicinity of the drain or source Hot electrons and hot holes are generated at, and the holes neutralize the electrons in the charge storage layer.

In Table 2 and FIG. 23, erasing is performed all at once in the four memory cells of FIG. A predetermined positive voltage Verase is applied to the bit line-1 and the bit line-2, 0V or a predetermined negative voltage 1 is applied to the word line-1 and the word line-2, and a positive voltage Verase is applied to the source line 8. The memory cell P well 2 is applied with 0 V or a predetermined negative voltage 2. As a result, a BtoB tunnel is generated in the vicinity of the drains of all the memory cells MC11 to MC22, and hot holes are injected into the charge storage layer 4-2. As a result, the threshold value of the memory cell is lowered (that is, erased). The memory cell N well can be set to 0 V regardless of the operation mode. When the memory cell portion P well 2 is set to 0 V, it is not necessary to provide a double well structure of the memory cell portion N well 20 and the P well 2, and the cell array portion may be simply provided on the P-type silicon substrate 19. I can do it.

The basic structure of the memory cell array of Embodiment 3 is the same as that of Embodiment 1, FIG. 2, FIG. 21 and FIG. FIG. 9 shows a plan view including the metal wiring layer of the bit line. A portion surrounded by a broken line is an area of one memory cell. Unlike the first and second embodiments, the source line 8 is not provided. Instead, two types of bit lines, the first bit line 14 and the second bit line 15, are provided, which run in parallel. The drain diffusion layer 1 in FIG. 1 is connected to the first bit line 14, and the source diffusion layer 1 is connected to the second bit line 15. A memory cell array circuit diagram corresponding to FIG. 10 is shown. Similar to FIG. 4, a region surrounded by a broken line is one memory cell region, and a gate insulating film 4 is provided under each word line, that is, a control gate of the memory cell transistor. 9 and 10, the charge storage layer is included in the gate insulating film in the same manner as in the first embodiment. In this embodiment, the second layer of the three-layer gate insulating film 4 is the charge storage layer 4-2. And

FIG. 11 is a cross-sectional view taken along the line A-A 'of FIG. The difference from FIG. 5 in the first embodiment is that the uppermost bit line is a pair of the first bit line 14 and the second bit line 15. Since one wiring layer of the source line is no longer necessary, the interlayer insulating film 11 is thinner by one layer. FIG. 12 shows a cross-sectional view taken along line B-B 'of FIG. The difference from FIG. 6 of the first embodiment is that the source line 8 is changed to the second bit line 15 and the second bit line 15 runs in the same direction on the same metal wiring layer as the first bit line 14. The metal wiring layer of the source line is removed. The first bit line 14 is connected to each memory drain portion diffusion layer 1 by a first bit line contact 16, and the second bit line is connected to each memory source portion N-type diffusion layer 1 by a second bit line contact 17. The

FIG. 13 is a cross-sectional view taken along the line C-C 'of FIG. The difference from FIG. 7 of the first embodiment is that the source line 8 is eliminated, the bit line becomes the first bit line 14, and the insulating film 11 is thinner by one layer. At this position, the first bit line 14 can be seen and the second bit line 15 cannot be seen. FIG. 14 is a sectional view taken along the line D-D 'of FIG. The difference from FIG. 8 of the first embodiment is that the source line 8 is eliminated.

Table 3 shows the potential relationship during writing, erasing and reading. A circuit diagram corresponding to Table 3 is shown in FIG. A case where the word line-1, the first bit line-1, and the second bit line-1 are selected, that is, the memory cell MC11 is selected is shown. The method in Table 3 is channel hot electron writing FN tunnel erasure as in the first embodiment. However, the circuit in FIG. 24 is not a common source line method, but the source portion of each memory cell along the bit line is a bit. The second bit line is connected in the same manner as the line.

First, in writing, the selected memory cell MC11 shown in FIG. 24 is selectively injected with electrons into the charge storage layer 4-2 and written, and the other memory cells MC12, MC21 and MC22 are written without being injected with electrons. I can't. The first bit line-1 has a predetermined positive voltage VABL (program), the second bit line-1 has a predetermined positive voltage VBBL (program) lower than VABL (program), and the word line-1 has a predetermined positive voltage VWL. (program), 0 V is applied to the word line-2, the first bit line-2 and the second bit line-2 are set to 0V or in a floating state, and the memory cell N well 20 and the P well 2 are set to 0V. Thus, only the memory cell MC11 at the intersection of the word line-1 and the first bit line-1 can be selectively written. In the memory cell MC11, the memory cell transistor is turned on, and electrons flowing from the source (second bit line-1) become high energy near the drain with a certain probability and are injected into the charge storage layer 4-2. Therefore, the threshold value of the memory cell changes in the positive direction (that is, is written). Even in the memory cell MC21 at the intersection of the word line-1 and the first bit line-2, the memory cell transistor is turned on, but since there is no potential difference between the first bit line-2 and the second bit line-2, Is not injected into the charge storage layer 4-2. In the memory cells MC12 and MC22 connected to the word line-2, since the memory cell transistor is in the OFF state, electrons are not injected into the charge storage layer 4-1, and the threshold values of these non-selected memory cells are not changed by writing.

Here, the above includes the case where the write data is “write”, including the third table, and if the data is “not write”, a voltage under a condition that does not write is applied to the selected memory cell MC11. . In this case, there is a method of setting the voltage VABL (program) of the first bit line-1 to VBBL (program), or setting both the voltages of the first bit line-1 and the second bit line-1 to 0V. is there.

Erasing is similarly performed at once, and the operation is the same as in the first embodiment. All the first bit lines and second bit lines in the region to be collectively erased are applied with a predetermined positive voltage Verase or set in a floating state, and all word lines are set to 0 V or a predetermined negative voltage with the memory cell N well 20. Verase is applied to P-well 2. In each memory cell, the positive potential Verase of the memory cell part P well 2 and the 0 V or negative voltage of the word line are sufficient for the voltage between the charge storage layer 4-2 and the memory cell part P well to cause an FN tunnel. Then, electrons escape from the charge storage layer 4-2 to the memory cell P well 2, and the threshold value changes in the negative direction (that is, is erased). As in the first embodiment, when the first bit line and the second bit line are in a floating state, the potential automatically becomes the same as the potential of the memory cell P well 2.

Next, when reading the selected memory cell MC11, a predetermined positive voltage VABL (read) is applied to the first bit line-1, and a predetermined positive voltage VBBL (read) is applied to the second bit line-1 which is lower than the first bit line-1. ), A predetermined positive voltage Vread is applied to the word line-1 and 0V is applied to the word line-2. The first bit line-2 and the second bit line-2 are set to 0V or in a floating state, and the memory cell N well 20 and the P well 2 are set to 0V. In the selected memory cell MC11, current flows from the first bit line-1 to the second bit line-1 if the threshold is lower than Vread, and no current flows if the threshold is higher than Vread. Then, the two states are detected by the sense amplifier connected to the first bit line-1 as in the first embodiment, and “0” and “1” are determined.

The memory cell array structure and circuit of the fourth embodiment are the same as those in FIGS. 9 to 14 and 21 shown in the third embodiment. Table 4 shows the potential relationship between the write, erase, and read operation modes. FIG. 25 shows a circuit diagram corresponding to Table 4, which is the same as the circuit FIG. 24 of the third embodiment. The write operation and read are also the same as those shown in Table 3. In the fourth embodiment, unlike the third embodiment, the erasure is performed not by using the FN tunnel but by using the BtoB tunnel as in the second embodiment.

In Table 4 and FIG. 25, a predetermined positive voltage Verase is applied to all the first bit lines in the region to be erased at once, Verase is applied to the second bit line or in a floating state, and all the word lines are 0V or a predetermined negative voltage 1 is applied, and 0V or a predetermined negative voltage 2 is applied to the memory cell P well 2. As described above, as in the second embodiment, holes are injected into the charge storage layer 4-2, thereby lowering the threshold value of the memory cell. The case where the memory cell portion P well 2 is set to 0 V is the same as in the second embodiment.

The memory cell array structure and circuit of the fifth embodiment are the same as those in FIGS. 9 to 14 and 21 shown in the third embodiment. Table 5 shows the potential relationship between the write, erase, and read operation modes. A circuit diagram corresponding to Table 5 is shown in FIG. 26, which is the same as the circuit FIG. 24 of the third embodiment. The erase operation and reading are the same as those shown in Table 3. In the fifth embodiment, unlike the third embodiment, writing is performed using FN tunnels instead of channel hot electrons. In the first or third embodiment, the FN tunnel is used for erasing, but in the fifth embodiment, both writing and erasing are performed by the FN tunnel.

In Table 5 and FIG. 26, the selected memory cell is also MC11. For writing, 0 V or a predetermined negative voltage VNNP is applied to the first bit line-1 and the second bit line-1, the first bit line-2 and the second bit line-2 are set to a predetermined positive voltage, and the word line-1 is set to The selected memory cell MC11 can be written by setting a predetermined positive potential VWL (program), the word line -2 to 0V or another negative voltage 1, and the memory cell portion P well 2 to 0V or the negative voltage VNNP. Here, the first bit line-1, the second bit line-1, and the memory cell portion P-well 2 are at a negative voltage VNNP, the word line -1 is at a positive voltage VWL (program), and the voltage difference causes an FN tunnel. If the voltage is sufficient (for example, 10 V), contrary to erasure, electrons are injected from the P well 2 into the charge storage layer 4-2, and the threshold value of the memory cell MC11 changes in the positive direction. When not writing to the selected memory cell MC11, although not shown in Table 5, a predetermined positive voltage is applied as in the first bit line-2 so as not to cause an FN tunnel. In the half-selected memory cell MC21 in which the word line-1 is selected, a predetermined positive voltage is applied to the first bit line-2 so that the gate oxide film 4 has a low electric field that does not cause FN tunneling, thereby generating electrons. Is not injected into the charge storage layer 4-2, so the threshold value does not change. Similarly, the memory cells MC12 and MC22 connected to the word line-2 do not cause FN tunneling because the word line-2 is at a low voltage. There is no combination of the negative voltage of the first bit line-1 and the second bit line-1 and 0V of the memory cell P well. This is because the PN junction becomes a forward bias condition. The memory cell N well is set to 0 V or a positive voltage. This is because, when the memory cell portion P-well has a negative voltage, the PN junction similarly becomes a forward bias condition.

The basic structure of the memory cell array of Embodiment 6 is the same as that of Embodiment 1, FIG. 2, FIG. 21 and FIG. FIG. 15 shows a plan view including the metal wiring layer of the bit line. A portion surrounded by a broken line is an area of two memory cells. Unlike the first to fifth embodiments, this is a repetitive unit in the memory cell array. The difference from the third to fifth embodiments is that the second bit line 15 is shared by two rows of memory cells of two adjacent word lines. That is, two first bit lines 14 and one second bit line 15 are arranged in parallel for two adjacent rows of memory cells. The drain diffusion layer 1 in FIG. 1 is connected to the first bit line 14 and the source diffusion layer 1 is connected to the second bit line 15 in the same way. Although the line is the same metal wiring layer as the second bit line, in the sixth embodiment, the first bit line 14 is the second bit line 15 as in the bit lines 6 and the source lines 8 of the first and second embodiments. It becomes a two-layer structure using the metal wiring layer on one layer. This is because the wiring portion connecting the source diffusion layer 1 of the second bit lines of the upper and lower memory cells in two rows is positioned below the first bit line 14. A circuit diagram corresponding to FIG. 16 is shown.

FIG. 17 is a sectional view taken along the line A-A 'of FIG. The third embodiment is different from FIG. 11 in that the metal wiring layer has two layers, the second bit line 15 is disposed in the lower layer, the first bit line 14 is disposed in the upper layer, and two second bit lines are disposed. One arrangement is provided for the first bit line. FIG. 18 is a cross-sectional view taken along the line B-B ′ of FIG. A difference from FIG. 12 of the third embodiment is that, similarly to FIG. 17, the second bit line 15 is arranged in the lower layer of the two metal wiring layers and the first bit line 14 is arranged in the upper layer. The second bit line of the memory cell is connected.

19 is a cross-sectional view taken along the line C-C 'of FIG. 15, and FIG. 19 is a cross-sectional view taken along the line D-D' of FIG. The difference from FIG. 13 and FIG. 14 of the third embodiment is that the thickness of the interlayer insulating film 11 is increased because the metal wiring layer has two layers.

Table 6 shows the potential relationship at the time of writing, erasing, and reading in the sixth embodiment. A circuit diagram corresponding to Table 6 is shown in FIG. This example also shows a case where the memory cell MC11 is selected. The method of Table 6 is channel hot electron write FN tunnel erase as in the third embodiment, and the write, erase, and read operations are the same. The only difference from the third table of the third embodiment is that the term of the second bit line-2 is eliminated. Since the voltage relationship between the first bit line-1 and the second bit line is the same, the memory cells MC11 and MC12 are not changed. However, in the first bit line-2, selection of 0V as the voltage at the time of writing and reading Only when the second bit line voltage VBBL is set to 0V. When the word line 1 is at the positive voltage VWL (program) or Vread, if the memory cell MC21 is in the erased state, a current flows from the second bit line voltage VBBL to the voltage 0V of the first bit line-2. Under this condition, even if a positive voltage VBBL is applied to the second bit line, the voltage on the first bit line-2 only rises from 0V to VBBL, so the voltage VBBL must be sufficiently lower than the write / read voltage VABL. For example, there is no problem as in the first embodiment.

The memory cell array structure and circuit of the seventh embodiment are the same as those in FIGS. 15 to 20 and 21 shown in the sixth embodiment. Table 7 shows the potential relationship between the write, erase, and read operation modes. FIG. 28 shows a circuit diagram corresponding to Table 7, which is the same as the circuit FIG. 27 of the sixth embodiment. Further, the writing, erasing and reading of the seventh embodiment are performed by using channel hot electron writing BtoB tunnel erasing as in the fourth embodiment.

In Table 7, writing and reading are the same as in Table 6 of Embodiment 6, but only erasing is different. On the other hand, the difference from the fourth table of the fourth embodiment is that the second bit line-2 is eliminated, but the second bit line-1 and the second bit line-2 are set at exactly the same voltage during erasing. Erasing in the seventh embodiment can be performed in the same manner as in the fourth embodiment. Therefore, writing, erasing, and reading can be performed as in the fourth and sixth embodiments.

In the above embodiment, the gate insulating film 4 has been described by taking a three-layer insulating film as an example. However, the present invention is not limited to this. For example, a thin silicon oxide film can be used as the first insulating film. A multilayer insulating film in which a silicon nitride film or an alumina film is laminated, a silicon nitride film, a hafnium oxide film, an alumina film, or a laminated film thereof is used as a second charge storage layer, and a third layer In addition to the silicon oxide film, an alumina film, a silicon oxynitride film, or a laminated film thereof can be used as the insulating film. Furthermore, other high dielectric constant or low dielectric constant insulating films can be used. Further, a structure called nanocrystal in which fine particles such as silicon, gold, or platinum are dispersed in an insulating film can be used as the charge storage layer.

  In the NOR type flash memory, the memory cell area can be reduced with a simple structure, thereby providing a low cost flash memory.

DESCRIPTION OF SYMBOLS 1 N type diffused layer 2 P well 3 of memory cell part 3 Word line 4 Multilayer insulating film 4-1 First insulating film 4-2 Second insulating film, charge storage layer 4-3 Third insulating film 5 Element isolation region 6 Bit line 7 Bit line contact 8 Source line 9 Source line contact 10 Insulating film on word line 11 Inter-wiring insulating film 12 Element isolation insulating film 13 Element isolation insulating film lower end 14 First bit line 15 Second bit line 16 1st bit line contact 17 2nd bit line contact 18 2nd bit line short circuit line 19 P type silicon substrate 20 Memory cell part N well 22 Memory cell part N well part contact N type diffusion layer 23 Memory cell part P well part Contact P-type diffusion layer 24 P-type silicon substrate Contact P-type diffusion layer 25 Memory cell portion N-well potential 26 Memory cell portion P-well potential

Claims (8)

A charge storage layer and a control gate are stacked on a P-type silicon substrate, or an N-well is provided on a P-type silicon substrate, a P-well is further provided thereon, and a charge storage layer and a control gate are stacked on the P-well. In a nonvolatile semiconductor memory device configured by arranging memory cells that perform data rewriting by transferring charges between the charge storage layer and the substrate, the charge storage layer and the control gate are embedded in a groove portion of the silicon substrate, and The substrate serving as the source and drain of the memory cell and the upper end of the anti-conductive diffusion layer are located above the upper end of the control gate, and an insulating film is provided between the upper surface of the control gate and the upper surfaces of the source and drain. Non-volatile memory. The bit line or source line is connected to the source or drain of each memory cell, but the distance seen from the upper surface of the contact region to the bit line or source line of the source and drain and the control gate is 0.5 micrometer or less, 2. The nonvolatile semiconductor memory according to claim 1, wherein the contact region and the control gate region overlap each other. A bit line and a source line orthogonal to the bit line are in the memory cell array, the bit line is electrically connected to the drain of each memory cell via a contact portion, and the source line is connected to the source and contact portion of each memory cell. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is electrically connected. There are two parallel bit line pairs in the memory cell array, the first bit line is electrically connected to the drain of each memory cell via the contact portion, and the second bit line is the source of each memory cell. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is electrically connected to each other through a contact portion. There are two parallel bit line pairs in the memory cell array, the first bit line is electrically connected to the drain of each memory cell via the contact portion, and the second bit line is connected to each memory cell. The second bit line is electrically connected to a source portion of an adjacent memory cell connected to a different first bit line, and is electrically connected to the source via a contact portion. The nonvolatile semiconductor memory according to claim 1 or 2. 6. The nonvolatile semiconductor memory according to claim 1, wherein a silicon nitride film, a silicon film, a metal oxide film, silicon fine particles, and metal fine particles are used as the charge storage layer.
Examples of the metal oxide film include a hafnium oxide film, an aluminum oxide film, and a tantalum oxide film. By setting the control gate of the memory cell to a high potential, electrons are injected from the source and drain or the silicon substrate to the charge storage layer, or a predetermined potential difference is provided between the source and drain of the memory cell, and the control gate is set to a higher potential than the source. 7. The nonvolatile semiconductor memory according to claim 1, wherein high energy electrons in the vicinity of the drain are injected into the charge storage layer. The charge storage layer is formed by extracting electrons from the charge storage layer to the silicon substrate by setting the potential of the silicon substrate of the memory cell higher than that of the control gate, or by setting the potential of the source or drain of the memory cell to be higher than that of the control gate. 8. The nonvolatile semiconductor memory according to claim 1, wherein erasing is performed by extracting electrons from the source to the drain.