JP2017084148A - Control apparatus, control method, and control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actuate an appropriate physical CPU core in a multiprocessor system.SOLUTION: A monitoring device 100 includes: a storage unit which stores information on physical positions of a plurality of processing apparatuses in an information processing system 1, and management information indicating whether the processing apparatuses are running or not; and a control unit which determines one or more first processing apparatuses to be actuated, from among the processing apparatuses, on the basis of the physical position information of the processing apparatuses stored in the storage unit, and executes updating the management information stored in the storage unit, in accordance with a result of determination, and actuating one or more first processing apparatuses.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a control technique for a multiprocessor system.

  A multiprocessor system in which a function of CoD (Capacity On Demand) is implemented can flexibly change the amount of physical CPU (Central Processing Unit) resources provided to a user according to the situation. For example, when the physical CPU resource allocated to the domain processing executed on the multiprocessor system is insufficient and the processing performance of the domain is reduced, the number of physical CPU cores allocated to the domain processing is increased according to the user request. Improve the processing performance. In this example, CoD is used when a physical resource is allocated to a domain. However, this is a CoD in a virtual environment where a physical resource is allocated to a virtual domain (hereinafter simply referred to as a virtual machine). May be. Rather, in recent years, CoD in a virtual environment in which physical resources are allocated to virtual machines has become widespread.

  For example, in a multiprocessor system in which a CoD function is implemented in a virtual environment, when a number of physical CPU cores determined by a CoD contract are allocated to a user's virtual machine, Will reduce the performance of the virtual machine. This is because contention for the L (Level) 1 cache and the L2 cache in the physical CPU occurs depending on the arrangement of the physical CPU cores.

  Further, depending on the arrangement of the operating physical CPU core, a locally hot place may occur. When the CPU temperature reaches an unacceptable temperature, not only does the physical CPU fail to operate normally, but it also causes the physical CPU to fail, so it is not preferable that a high-temperature location occurs in the multiprocessor system. .

  Although there is a conventional technique related to a multiprocessor system, there is no technique that can appropriately select a physical CPU core to be operated with respect to the above problems.

JP 2013-37458 A JP 2012-43254 A

  Accordingly, an object of the present invention, in one aspect, is to provide a technique for operating an appropriate physical CPU core in a multiprocessor system.

  A control device according to the present invention includes a storage unit that stores information on a physical position of each of a plurality of processing devices in an information processing system, and management information indicating whether or not the processing device is operating, and a storage unit Based on the stored physical position information of each of the plurality of processing devices, one or more first processing devices to be operated are determined from among the plurality of processing devices, and stored in the storage unit according to the determination result. And a control unit that executes updating of the management information and processing for operating one or more first processing devices.

  In one aspect, an appropriate physical CPU core can be operated in a multiprocessor system.

FIG. 1 is a diagram illustrating an example of a multiprocessor system. FIG. 2 is a diagram for explaining the power mode. FIG. 3 is a diagram illustrating an example of an arrangement of performance modes. FIG. 4 is a diagram illustrating an example of the arrangement of the balance mode. FIG. 5 is a diagram illustrating an example of the arrangement of the power saving mode. FIG. 6 is a diagram illustrating a configuration of the information processing system according to the first embodiment. FIG. 7 is a diagram illustrating an example of a hardware configuration of the CPU. FIG. 8 is a diagram for explaining identification of the physical position of the core. FIG. 9 is a hardware configuration diagram of the monitoring device. FIG. 10 is a diagram illustrating an example of data stored in the core position data storage unit. FIG. 11 is a diagram illustrating an example of data stored in the LCU position data storage unit. FIG. 12 is a diagram illustrating an example of data stored in the first management data storage unit. FIG. 13 is a diagram illustrating an example of data stored in the second management data storage unit. FIG. 14 is a diagram showing a main processing flow. FIG. 15 is a diagram showing a processing flow of license allocation processing. FIG. 16 is a diagram illustrating a processing flow of the first centralized allocation processing. FIG. 17 is a diagram illustrating an example of data stored in the first management data storage unit. FIG. 18 is a diagram illustrating an example of data stored in the first management data storage unit. FIG. 19 is a diagram illustrating a processing flow of the first distributed allocation processing. FIG. 20 is a diagram illustrating an example of data stored in the first management data storage unit. FIG. 21 is a diagram illustrating a processing flow of the second centralized allocation processing. FIG. 22 is a diagram illustrating an example of data stored in the core position data storage unit. FIG. 23 is a diagram illustrating an example of data stored in the core position data storage unit. FIG. 24 is a diagram illustrating a processing flow of the second distributed allocation processing. FIG. 25 is a diagram illustrating a processing flow of power-on processing. FIG. 26 is a diagram illustrating an example of data stored in the LCU position data storage unit. FIG. 27 is a diagram illustrating an example of data stored in the LCU position data storage unit. FIG. 28 is a diagram illustrating the relationship between the power supply mode, performance, and power saving. FIG. 29 is a diagram illustrating an overview of an information processing system according to the second embodiment. FIG. 30 is a diagram illustrating a specific configuration of hardware. FIG. 31 is a functional block diagram of the control unit and the system control unit. FIG. 32 is a hardware configuration diagram of the master monitoring device. FIG. 33 is a hardware configuration diagram of a monitoring device that is not the master. FIG. 34 is a functional block diagram of the virtualization software. FIG. 35 is a diagram illustrating an example of first management data stored in the management data storage unit. FIG. 36 is a diagram illustrating an example of second management data stored in the management data storage unit. FIG. 37 is a diagram illustrating a processing flow of processing executed by the control unit. FIG. 38 is a diagram for explaining the temperatures T0 to T3. FIG. 39 is a diagram illustrating a processing flow of processing executed by the control unit. FIG. 40 is a diagram illustrating a processing flow of processing executed by the system control unit. FIG. 41 is a diagram illustrating a processing flow of determination processing according to the second embodiment. FIG. 42 is a diagram illustrating an example of first management data stored in the management data storage unit. FIG. 43 is a diagram for explaining core switching. FIG. 44 is a diagram for explaining the update of mapping data. FIG. 45 is a diagram illustrating a processing flow of determination processing according to the third embodiment. FIG. 46 is a diagram illustrating a process flow of the determination process in the fourth embodiment.

[Embodiment 1]
The outline of the first embodiment will be described with reference to FIGS. 1 to 5.

  FIG. 1 shows an information processing system having CPUs 1p to 4p. Each of the CPUs 1p to 4p is mounted on a socket. Each of the CPUs 1p to 4p has a plurality of LCUs (Local Cache Units) each having a plurality of physical CPU cores (hereinafter simply referred to as cores) and one L1 cache, and one L2 cache. In the example of FIG. 1, the CPU 1p includes LCUs 11l to 14l, the CPU 2p includes LCUs 21l to 24l, the CPU 3p includes LCUs 31l to 34l, and the CPU 4p includes LCUs 41l to 44l. Each of the CPUs 1p to 4p is connected to a memory. A plurality of cores included in the same LCU access the L1 cache included in the LCU. A plurality of cores included in the same CPU access an L2 cache included in the CPU. In the first embodiment, power is turned on and off in units of LCUs.

  In FIG. 1, a numbered core is a core to which a license is assigned, and a core to which a license is assigned operates. That is, cores 1 to 8 operate on CPU 1p, cores 13 to 20 operate on CPU 2p, cores 25 to 30 operate on CPU 3p, and CPU 4p operates on CPU 4p. Cores No. 37 through No. 42 operate. In the first to fourth embodiments, an operating core means a core that is turned on and assigned a license, and is simply a turned on core (or turned on). Does not mean that the core is not assigned a license).

  As described above, the arrangement of operating cores affects performance and the like. Therefore, in the first embodiment, the arrangement of operating cores can be switched according to the power supply mode designated by the user or the administrator. Specifically, as shown in FIG. 2, the performance mode, the balance mode, and the power saving mode can be specified. In the performance mode, the arrangement is performed so that the CPUs including the operating cores are distributed and the LCUs including the operating cores are distributed. In the balance mode, the arrangement is performed such that the CPUs including the operating cores are distributed and the operating cores are collected in a specific LCU. In the power saving mode, the arrangement is performed such that the operating cores are collected by a specific CPU and the operating cores are collected by a specific LCU.

  FIG. 3 shows an example of the arrangement of performance modes. As shown in FIG. 3, in the performance mode, the operating cores are distributed to the CPUs 1p to 4p, and the operating cores are distributed to a plurality of LCUs in each CPU. This makes it difficult for contention to occur in the L2 cache of each CPU, and makes it difficult for contention to occur in the L1 cache of each LCU. Therefore, the performance of the system realized using the CPUs 1p to 4p can be improved.

  FIG. 4 shows an example of the arrangement of the balance mode. As shown in FIG. 4, in the balance mode, the operating cores are distributed to the CPUs 1p to 4p, and the operating cores are collected in a specific LCU in each CPU. This makes it difficult for competition to occur in the L2 cache of each CPU, and reduces the number of LCUs to be powered on, thereby suppressing power consumption.

  FIG. 5 shows an example of the arrangement of the power saving mode. As shown in FIG. 5, in the power saving mode, the operating cores are collected by a specific CPU, and the operating cores are collected by a specific LCU in each CPU. As a result, the number of LCUs to be powered on can be reduced and power consumption can be further suppressed. Compared with FIG. 4, the number of LCUs to be powered on is not reduced, but the number of LCUs to be powered on is reduced depending on the number of operating cores.

  Hereinafter, the first embodiment will be described more specifically. Here, an example will be described in which a function for optimizing the physical arrangement of the cores to be operated in one casing based on performance or power consumption is provided, but the present invention is not limited to this. For example, you may apply to implementation in a virtual environment by using virtual mapping data processing together.

  FIG. 6 shows the configuration of the information processing system 1 according to the first embodiment. The information processing system 1 includes, for example, a monitoring device 100 that is a service processor and monitors and controls the hardware 12, and the hardware 12. The hardware 12 includes a motherboard 13, and the motherboard 13 includes CPUs 1 p to 4 p and a memory 14. In FIG. 6, the number of CPUs is 4, but the number is not limited. Further, in order to make the drawing easy to see, the connection between the CPUs 1p to 4p and the memory 14 is omitted.

  The virtualization software 11 is expanded in the memory 14 and executed by the CPUs 1p to 4p. An OS (Operating System) 10 program is also loaded in the memory 14 and executed by the CPUs 1p to 4p. On the OS 10, an application program of a virtual machine realized by the virtualization software 11 is executed, but the description is omitted for the sake of simplicity of the drawing.

  FIG. 7 shows an example of the hardware configuration of the CPU 1p. The CPU 1p, which is a multi-core processor, includes a plurality of LCUs 11l to 14l each including a plurality of cores and an L1 cache, an L2 cache 1c, and a memory access controller 1mc. The LCUs 11l to 14l are connected to the L2 cache 1c, and the L2 cache 1c is connected to the memory access controller 1mc. In FIG. 7, the number of cores is 3 and the number of LCUs is 4, but the number is not limited. Although the CPU 1p is described as an example here, the hardware configuration of the CPUs 2p to 4p is the same as the hardware configuration of the CPU 1p.

  The specification of the physical position of the core will be described with reference to FIG. In order to make the figure easy to see, the L2 cache 1c and the memory access controller 1mc of the CPU 1p are omitted. In the first embodiment, the physical position of the core is determined by the number 1 of the socket (1 = 1 in the example of FIG. 8) to which the CPU including the core is attached and the number m of the LCU (in FIG. 8). In the example, m is a natural number that satisfies 1 ≦ m ≦ 4) and a number n that represents the position of the core in the LCU (in the example of FIG. 8, n is a natural number that satisfies 1 ≦ n ≦ 3). Identified. For example, in FIG. 8, the physical position of the core whose ID (IDentifier) is “c-08” is represented by three-dimensional coordinates (1, m, n) = (1, 3, 2). Hereinafter, the ID of the core is represented as C-ID.

  Returning to the description of FIG. 6, the monitoring apparatus 100 includes a license management unit 101, a second management data storage unit 102, a power mode management unit 103, a first management data storage unit 104, an allocation determination unit 105, a core position. A data storage unit 106, a power-on management unit 107, an LCU position data storage unit 108, and a power supply control unit 109 are included.

  The license management unit 101 receives an input instruction for the number of contract licenses (that is, the number of cores to be operated), and notifies the allocation determination unit 105 of the number of contract licenses. In addition, the license management unit 101 updates the data stored in the second management data storage unit 102 in accordance with the license assignment determined by the assignment determination unit 105.

  The power mode management unit 103 receives an instruction to input a power mode and notifies the allocation determination unit 105 of the power mode.

  The allocation determination unit 105 executes processing based on the data stored in the core position data storage unit 106, updates the data stored in the core position data storage unit 106 based on the processing result, and includes a first management data storage unit The data stored in 104 is updated based on the processing result.

  The power-on management unit 107 executes processing based on the data stored in the core position data storage unit 106, and updates the data stored in the LCU position data storage unit 108 based on the processing result.

  The power control unit 109 performs power on / off of the LCU according to the data stored in the LCU position data storage unit 108.

  FIG. 9 shows a hardware configuration diagram of the monitoring apparatus 100. The monitoring device 100 includes a CPU 111, a RAM (Random Access Memory) 112, a ROM (Read Only Memory) 113, and a bus 115. The CPU 111, RAM 112, and ROM 113 are connected via the bus 115. The ROM 113 stores system control firmware 114. The system control firmware 114 is read into the RAM 112 by the CPU 111 and executed by the CPU 111. The license management unit 101, the power mode management unit 103, the allocation determination unit 105, the power-on management unit 107, and the power control unit 109 illustrated in FIG. 6 are realized by the CPU 111 executing the system control firmware 114. The second management data storage unit 102, the first management data storage unit 104, the core position data storage unit 106, and the LCU position data storage unit 108 are provided in the RAM 112, for example.

  FIG. 10 shows an example of data stored in the core position data storage unit 106. In the example of FIG. 10, a C-ID, a socket number 1, an LCU number m, a core number n, and a license assignment flag are stored. A CPU whose license allocation flag is “ON” operates, and a CPU whose license allocation flag is “OFF” does not operate.

  FIG. 11 shows an example of data stored in the LCU position data storage unit 108. In the example of FIG. 11, the LCU-ID that is the ID of the LCU, the socket number 1, the LCU number m, and the power-on flag are stored. The LCU whose power-on flag is “ON” is powered on, and the LCU whose power-on flag is “OFF” is not powered on.

  FIG. 12 shows an example of data stored in the first management data storage unit 104. In the example of FIG. 12, the socket number of the socket to which the CPU is attached and the number of assigned licenses are stored. In the example of FIG. 12, four cores operate in a socket with a socket number of 2.

  FIG. 13 shows an example of data stored in the second management data storage unit 102. In the example of FIG. 13, the serial number and the C-ID of the core to which the license is assigned are stored.

  Next, processing executed by the monitoring apparatus 100 will be described with reference to FIGS. It is assumed that no power is turned on for any core at the start of this process.

  First, the license management unit 101 of the monitoring apparatus 100 accepts an input instruction for the number of contract licenses by an administrator of the information processing system 1, for example (FIG. 14: Step S1). The license management unit 101 notifies the allocation determination unit 105 of the number of contract licenses.

  The power mode manager 103 accepts a power mode selection instruction (step S3). The power mode manager 103 notifies the allocation determination unit 105 of the power mode.

  Then, the assignment determining unit 105 executes a license assignment process (step S5). The license allocation process will be described with reference to FIGS.

  First, the assignment determining unit 105 determines whether the power mode is “power saving” (FIG. 15: step S21). When the power mode is “power saving” (step S21: Yes route), the allocation determining unit 105 executes a first centralized allocation process (step S23). The first centralized allocation process will be described with reference to FIGS. 16 to 18.

  First, the assignment determination unit 105 sets the number of licenses assigned to each CPU stored in the first management data storage unit 104 to 0 (FIG. 16: step S41). By the processing in step S41, data as shown in FIG. 17 is stored in the first management data storage unit 104, for example.

  The allocation determining unit 105 reads out the number K of cores per CPU stored in advance from the RAM 112 (step S43). In the present embodiment, it is assumed that each CPU has the same number of cores.

  The allocation determining unit 105 sets the variable l representing the socket number as 1 = 1, and sets the variable count representing the number of unallocated licenses as count = the number of contract licenses (step S45). The number of contract licenses is the number of contract licenses notified from the license management unit 101.

  The allocation determining unit 105 determines whether count-K ≧ 0 is satisfied (step S47). When count-K ≧ 0 is satisfied (step S47: Yes route), the assignment determining unit 105 sets the number of licenses assigned to the CPU attached to the socket having the socket number l to K (step S49). Specifically, the assignment determination unit 105 sets the number of licenses corresponding to the socket number l stored in the first management data storage unit 104 to K.

  The allocation determining unit 105 increments l by 1 (step S51), and sets count to count = count-K (step S53). Then, the process returns to step S47.

  On the other hand, if count-K ≧ 0 is not satisfied (step S47: No route), the assignment determining unit 105 sets the number of licenses assigned to the CPU attached to the socket having the socket number l to “count” (step S55). ). Specifically, the assignment determining unit 105 sets the number of licenses corresponding to the socket number l stored in the first management data storage unit 104 to “count”. Then, the process returns to the original process.

  By executing the processing as described above, it is possible to realize an arrangement in which operating cores are collected by a specific CPU. For example, when K = 12, and the initial value of count is 20, the first management data storage unit 104 stores data as shown in FIG.

  Returning to the description of FIG. 15, when the power mode is not “power saving” (step S21: No route), the allocation determining unit 105 executes a first distributed allocation process (step S25). The first distributed allocation process will be described with reference to FIGS. 19 and 20.

  First, the assignment determining unit 105 sets the number of licenses assigned to each CPU stored in the first management data storage unit 104 to 0 (FIG. 19: step S61). As a result of the processing in step S61, the first management data storage unit 104 stores data as shown in FIG.

  The allocation determining unit 105 sets a variable count indicating the number of unallocated licenses as count = the number of contract licenses (step S63). The number of contract licenses is the number of contract licenses notified from the license management unit 101.

  The allocation determining unit 105 reads out the number L of sockets of the information processing system 1 stored in advance from the RAM 112 (step S65).

  The allocation determining unit 105 calculates the quotient A and the remainder B when the count is divided by L (step S67).

  The allocation determination unit 105 sets the number of licenses allocated to each CPU stored in the first management data storage unit 104 to A (step S69).

  The allocation determining unit 105 sets the variable l representing the socket number as 1 = 1 (step S71).

  The allocation determining unit 105 determines whether B-1 ≧ 0 is satisfied (step S73). When B-1 ≧ 0 is satisfied (step S73: Yes route), the assignment determining unit 105 increments the number of licenses assigned to the CPU attached to the socket having the socket number l by 1 (step S75). Specifically, the assignment determination unit 105 increments the number of licenses corresponding to the socket number l stored in the first management data storage unit 104 by one.

  The allocation determining unit 105 sets B as B = B-1 (step S77) and 1 as l = l + 1 (step S79). Then, the process returns to step S73.

  On the other hand, if B-1 ≧ 0 is not satisfied (step S73: No route), the process returns to the original process of the call.

  By executing the processing as described above, it is possible to realize an arrangement in which operating cores are distributed among the CPUs 1p to 4p. For example, when L = 4 and the initial value of count is 20, the first management data storage unit 104 stores data as shown in FIG.

  Returning to the description of FIG. 15, the assignment determining unit 105 reads the number of licenses assigned to the CPU attached to each socket from the first management data storage unit 104 (step S <b> 27).

  The allocation determining unit 105 determines whether the power mode is “performance” (step S29). When the power mode is not “performance” (step S29: No route), the allocation determining unit 105 executes the second centralized allocation process (step S31). The second centralized allocation process will be described with reference to FIGS.

  First, the assignment determining unit 105 identifies one unprocessed CPU among the CPUs in the information processing system 1, and sets the socket number l to the socket number of the socket to which the CPU is attached (FIG. 21: Step S81). ). Hereinafter, the CPU identified in step S81 is referred to as a “processing target CPU”.

  The allocation determination unit 105 reads the number of licenses num allocated to the processing target CPU from the first management data storage unit 104 (step S83).

  The assignment determination unit 105 sets the license assignment flag of each core of the processing target CPU stored in the core position data storage unit 106 to “OFF” (step S85).

  The allocation determining unit 105 sets the LCU number m as m = 1 and the core number n as n = 1 (step S87).

  The allocation determining unit 105 determines whether num> 0 is satisfied (step S89). When num> 0 is satisfied (step S89: Yes route), the assignment determining unit 105 sets the license assignment flag of the core whose physical position is (l, m, n) stored in the core position data storage unit 106. “ON” is set (step S91).

  The allocation determining unit 105 sets num as num = num−1 (step S93).

  The allocation determining unit 105 determines whether n <the number of cores N per LCU is satisfied (step S95). If n <the number N of cores per LCU is established (step S95: Yes route), the assignment determining unit 105 sets n to n = n + 1 (step S97), and returns to the process of step S89.

  On the other hand, when n <the number of cores N per LCU does not hold (step S95: No route), the assignment determining unit 105 sets n to n = 1 (step S99).

  The allocation determining unit 105 sets m as m = m + 1 (step S101). Then, the process returns to step S89.

  On the other hand, when num> 0 is not satisfied (step S89: No route), the assignment determination unit 105 determines whether there is an unprocessed CPU in the information processing system 1 (step S103). When there is an unprocessed CPU (step S103: Yes route), the process returns to step S81. If there is no unprocessed CPU (step S103: No route), the process returns to the caller process.

  By executing the processing as described above, it is possible to realize an arrangement in which operating cores are collected in a specific LCU. For example, when data as shown in FIG. 22 is initially stored in the core position data storage unit 106, when the second centralized allocation process is executed, for example, data as shown in FIG. Stored.

  Returning to the description of FIG. 15, when the power mode is “performance” (step S29: Yes route), the allocation determining unit 105 executes the second distributed allocation process (step S33). The second distributed allocation process will be described with reference to FIG.

  First, the assignment determination unit 105 identifies one unprocessed CPU among the CPUs in the information processing system 1, and sets the socket number l to the socket number of the socket to which the CPU is attached (FIG. 24: Step S111). ). Hereinafter, the CPU identified in step S111 is referred to as a “processing target CPU”.

  The allocation determining unit 105 reads the number of licenses num allocated to the processing target CPU from the first management data storage unit 104 (step S113).

  The assignment determining unit 105 sets the license assignment flag of each core of the processing target CPU stored in the core position data storage unit 106 to “OFF” (step S115).

  The allocation determining unit 105 sets the LCU number m as m = 1 and the core number n as n = 1 (step S117).

  The allocation determining unit 105 determines whether num> 0 is satisfied (step S119). When num> 0 is satisfied (step S119: Yes route), the assignment determination unit 105 displays the license assignment flag of the core whose physical position is (l, m, n) stored in the core position data storage unit 106. “ON” is set (step S121).

  The allocation determining unit 105 sets num as num = num−1 (step S123).

  The allocation determining unit 105 determines whether m <the number of LCUs M per socket is satisfied (step S125). If m <the number M of LCUs per socket is satisfied (step S125: Yes route), the allocation determining unit 105 sets m to m = m + 1 (step S127), and returns to the process of step S119.

  On the other hand, if m <the number M of LCUs per socket does not hold (step S125: No route), the allocation determination unit 105 sets m to m = 1 (step S129).

  The allocation determining unit 105 sets n as n = n + 1 (step S131). Then, the process returns to step S119.

  On the other hand, when num> 0 is not satisfied (step S119: No route), the assignment determining unit 105 determines whether there is an unprocessed CPU in the information processing system 1 (step S133). When there is an unprocessed CPU (step S133: Yes route), the process returns to step S111. If there is no unprocessed CPU (step S133: No route), the process returns to the caller process.

  By executing the processing as described above, it is possible to realize an arrangement in which operating cores are distributed over a large number of LCUs.

  Returning to the description of FIG. 15, the assignment determination unit 105 notifies the license management unit 101 of the C-ID of the core whose license assignment flag stored in the core position data storage unit 106 is “ON”. Then, the license management unit 101 updates the C-ID stored in the second management data storage unit 102 with the C-ID notified from the assignment determination unit 105 (step S35). Then, the process returns to the calling process.

  Returning to the description of FIG. 14, the monitoring apparatus 100 accepts a power-on instruction from the administrator of the information processing system 1 (step S7), and the monitoring apparatus 100 starts a power control program (step S9). The power supply control unit 109 starts operating by starting the power supply control program.

  The power control unit 109 executes a power on process (step S11). Then, the process ends. The power-on process will be described with reference to FIGS.

  First, the power-on management unit 107 sets the power-on flag of each LCU stored in the LCU position data storage unit 108 to “OFF” (FIG. 25: step S141). Through the processing in step S141, data as shown in FIG. 26 is stored in the LCU position data storage unit 108, for example.

  The power-on management unit 107 sets a variable p_id representing the number of processed cores as p_id = 1 (step S143).

  The power-on management unit 107 specifies the license assignment flag of the core whose C-ID is c_ (p_id) from the core position data storage unit 106 (step S145).

  The power-on management unit 107 determines whether or not the license assignment flag specified in step S145 is “ON” (step S147). When the license allocation flag is not “ON” (step S147: No route), the process proceeds to step S153.

  On the other hand, when the license assignment flag is “ON” (step S147: Yes route), the power-on management unit 107 receives the socket number l of the core whose C-ID is c_ (p_id) from the core position data storage unit 106. And the LCU number m is specified (step S149).

  The power-on management unit 107 sets the power-on flag of the LCU having the socket number l and the LCU number m to “ON” (step S151). By the processing in step S151, for example, as shown in FIG. 27, only the power-on flag of the LCU to be powered on is set to “ON”.

  The power-on management unit 107 sets p_id as p_id = p_id + 1 (step S153).

  The power-on management unit 107 determines whether p_id ≦ L * M * N is satisfied (step S155). When p_id ≦ L * M * N is satisfied (step S155: Yes route), the process returns to step S145.

  On the other hand, when p_id ≦ L * M * N is not satisfied (step S155: No route), the power supply control unit 109 specifies and specifies the LCU whose power-on flag in the LCU position data storage unit 108 is “ON”. The LCU is powered on (step S157). Then, the process returns to the calling process.

  If the processing as described above is executed, the power can be turned on only to the LCU that should be turned on. FIG. 28 shows the relationship between the power supply mode, performance, and power saving. When the power mode is “performance”, the performance is high, but the effect of power saving is small. When the power mode is “power saving”, the performance is low but the power saving effect is great. When the power supply mode is “balance”, the performance and power saving effects are moderate.

[Embodiment 2]
Next, a second embodiment will be described. According to the second embodiment, temperature unevenness in the multiprocessor system can be eliminated by switching the operating core. In the second to fourth embodiments, there is shown an example of providing a function for optimizing the physical arrangement of cores operated between cases from the viewpoint of temperature unevenness, and virtual mapping data is shown. It is applied to the virtual environment by using processing together.

  FIG. 29 shows an overview of the information processing system 2 according to the second embodiment. The information processing system 2 includes hardware 23 including a plurality of connected casings, and can operate as a single server. That is, the information processing system 2 is a system constructed by a building block method. The virtualization software 22 operates on the hardware 23, and the OS 21 operates on the virtualization software 22. Each of the plurality of cases includes a monitoring device that is a service processor, for example, and a control unit is executed on each monitoring device. One of the plurality of monitoring devices is a master monitoring device (in this embodiment, the monitoring device 0m), and the system control unit 200 is further executed on the master monitoring device. In the example of FIG. 29, the casing 0b executes the control unit 0f, the casing 1b executes the control unit 1f, and the casing 2b executes the control unit 2f.

  FIG. 30 shows a more specific configuration of the hardware 23. The housing 0b includes CPUs 00p to 02p, an intake air temperature sensor 50s for measuring the temperature of air taken into the housing 0b by the cooling fan (hereinafter referred to as intake air temperature), and a monitoring device 0m. The CPU 00p has a CPU temperature sensor 00s that measures the temperature of the CPU 00p, the CPU 01p has a CPU temperature sensor 01s that measures the temperature of the CPU 01p, and the CPU 02p has a CPU temperature sensor 02s that measures the temperature of the CPU 02p. Each CPU is a multi-core processor having (p + 1) (p is a natural number) cores. However, the number of cores included in each CPU may be different. Since the configurations of the housing 1b and the housing 2b are basically the same as the configuration of the housing 0b, description thereof is omitted here.

  Each CPU can communicate with another CPU through a dedicated high-speed interface. Each monitoring device can communicate with other monitoring devices through a dedicated interface.

  FIG. 31 shows functional blocks of the control unit 0f and functional blocks of the system control unit 200. The control unit 0f includes a temperature abnormality processing unit 301, a power supply control unit 302, a switching unit 303, a temperature monitoring unit 304, and a fan control unit 305. The processing executed by the control units 1f and 2f is basically the same as the processing executed by the control unit 0f, and thus description thereof is omitted here. The system control unit 200 includes an OS interface unit 201, a CPU selection unit 202, a management data storage unit 203, and a temperature data processing unit 204.

  The temperature monitoring unit 304 notifies the temperature data processing unit 204 of the temperature data acquired from the CPU temperature sensor of each CPU in the housing 0b and the temperature data acquired from the intake air temperature sensor 50s in the housing 0b. In addition, the temperature monitoring unit 304 notifies the temperature abnormality processing unit 301, the switching unit 303, and the fan control unit 305 according to the CPU temperature of each CPU in the housing 0b. In response to the notification from the temperature monitoring unit 304, the temperature abnormality processing unit 301 instructs the power source control unit 302 to control (for example, disconnect) the power of the CPU in which the temperature abnormality has occurred, and control the OS 21 (for example, shutdown). To the OS interface unit 201. The switching unit 303 outputs a core switching request to the CPU selection unit 202 in response to the notification from the temperature monitoring unit 304. The fan control unit 305 controls the rotation speed of the cooling fan in the housing 0b in response to the notification from the temperature monitoring unit 304. In response to the switching request received from the switching unit 303, the CPU selection unit 202 executes processing based on the data stored in the management data storage unit 203, and outputs a core switching instruction generated based on the processing result to the virtualization software 22 to output. The temperature data processing unit 204 updates the data stored in the management data storage unit 203 based on the temperature data received from the temperature monitoring unit 304.

  FIG. 32 shows a hardware configuration diagram of the monitoring device 0m as a master. The monitoring device 0m includes a CPU 251, a RAM 252, a ROM 253, and a bus 255. The CPU 251, RAM 252 and ROM 253 are connected via a bus 255. The ROM 253 stores system control firmware 2541 and control firmware 2542. The system control firmware 2541 and the control firmware 2542 are read into the RAM 252 by the CPU 251 and executed by the CPU 251. The OS interface unit 201, the CPU selection unit 202, and the temperature data processing unit 204 illustrated in FIG. 31 are realized by the CPU 251 executing the system control firmware 2541. The management data storage unit 203 is provided in the RAM 252, for example. The temperature abnormality processing unit 301, the power supply control unit 302, the switching unit 303, the temperature monitoring unit 304, and the fan control unit 305 illustrated in FIG. 31 are realized by the CPU 251 executing the control firmware 2542.

  FIG. 33 shows a hardware configuration diagram of a monitoring device that is not the master. The monitoring devices 1m and 2m that are not masters include a CPU 261, a RAM 262, a ROM 263, and a bus 265. The CPU 261, RAM 262, and ROM 263 are connected via a bus 265. The ROM 263 stores the control firmware 264. The control firmware 264 is read into the RAM 262 by the CPU 261 and executed by the CPU 261. The temperature abnormality processing unit 301, the power supply control unit 302, the switching unit 303, the temperature monitoring unit 304, and the fan control unit 305 of the monitoring device that is not the master are realized by the CPU 261 executing the control firmware 264.

  FIG. 34 shows a functional block diagram of the virtualization software 22. The virtualization software 22 includes a CPU management unit 401 and a mapping data storage unit 402. The CPU management unit 401 updates the data stored in the mapping data storage unit 402 based on the core switching instruction received from the CPU selection unit 202.

  FIG. 35 shows an example of first management data stored in the management data storage unit 203. In the example of FIG. 35, the case identification information, the CPU identification information, the CPU temperature and its rank, the intake air temperature and its rank, the number of unused cores, the total number of cores and their rank, The distance between the body and its rank, a numerical value indicating the total rank, and an overall rank determined based on the numerical value indicating the total rank are stored. The distance between the cases is the distance between the case containing the processing target CPU and each of the other cases. Since the lower the CPU temperature and the intake air temperature are, the more effective the temperature unevenness is. The higher the number of unused cores, the lower the temperature rise, and the higher the ranking. The longer the distance between the casings, the more effective the elimination of temperature unevenness, and the higher the ranking.

  FIG. 36 shows an example of second management data stored in the management data storage unit 203. In the example of FIG. 36, the CPU identification information, the number for identifying the core, and whether the core is operating (ie, the core is powered on and used for program execution (ie, the license is And an operation flag indicating whether or not assigned) is stored. The second management data is updated by the CPU selection unit 202 when the core is switched.

  Next, processing performed in the information processing system 2 will be described with reference to FIGS. First, the processing executed by the control unit (here, the control unit 0f) will be described with reference to FIGS. However, the processing executed by the control units 1f and 2f is the same as the processing executed by the control unit 0f.

  First, the temperature monitoring unit 304 reads the intake air temperature from the intake air temperature sensor 50s, and notifies the read intake air temperature to the temperature data processing unit 204 (FIG. 37: step S161).

  The temperature monitoring unit 304 identifies one unprocessed CPU among the CPUs in the housing 0b (step S163). Hereinafter, the CPU specified in step S163 is referred to as a processing target CPU.

  The temperature monitoring unit 304 reads the CPU temperature of the processing target CPU from the CPU temperature sensor of the processing target CPU, and notifies the temperature data processing unit 204 of the read CPU temperature (step S165).

  The temperature monitoring unit 304 determines whether the CPU temperature of the processing target CPU is equal to or higher than T3 (step S167).

  When the CPU temperature of the processing target CPU is equal to or higher than T3 (step S167: Yes route), the temperature monitoring unit 304 notifies the temperature abnormality processing unit 301 that the CPU temperature is equal to or higher than T3. In response to this, the temperature abnormality processing unit 301 outputs a shutdown request for the OS 21 to the OS interface unit 201 in the system control unit 200 (step S169). In response to this, the OS interface unit 201 executes shutdown of the OS 21. Further, the temperature abnormality processing unit 301 may instruct the power supply control unit 302 to control the power supply of the processing target CPU (for example, cut off), and cause the power supply control unit 302 to execute the power supply cutting of the processing target CPU. Then, the process proceeds to step S183 in FIG.

  On the other hand, when the temperature of the processing target CPU is not equal to or higher than T3 (step S167: No route), the temperature monitoring unit 304 determines whether the CPU temperature of the processing target CPU is equal to or higher than T2 (step S171).

  When the CPU temperature of the processing target CPU is equal to or higher than T2 (step S171: Yes route), the temperature monitoring unit 304 outputs a core switching request to the CPU selection unit 202 in the system control unit 200 (step S173). The core switching request includes the identification information of the processing target CPU. Processing executed by the system control unit 200 will be described later. Then, the process proceeds to step S183 in FIG.

  On the other hand, when the CPU temperature of the processing target CPU is not equal to or higher than T2 (step S171: No route), the temperature monitoring unit 304 determines whether the CPU temperature of the processing target CPU is equal to or higher than T1 (step S175).

  When the CPU temperature of the processing target CPU is equal to or higher than T1 (step S175: Yes route), the temperature monitoring unit 304 notifies the fan control unit 305 that the CPU temperature of the processing target CPU is equal to or higher than T1. In response to this, the fan control unit 305 increases the rotation speed of the cooling fan mounted on the housing 0b (step S177). For example, a rotation speed designated in advance is set as the rotation speed to be set when the CPU temperature is equal to or higher than T1. Then, the processing shifts to the processing in step S183 in FIG.

  On the other hand, when the CPU temperature of the processing target CPU is not equal to or higher than T1 (step S175: No route), the temperature monitoring unit 304 determines whether the CPU temperature of the processing target CPU is equal to or lower than T0 (step S179).

  When the CPU temperature of the processing target CPU is equal to or lower than T0 (step S179: Yes route), the temperature monitoring unit 304 notifies the fan control unit 305 that the CPU temperature of the processing target CPU is equal to or lower than T0. In response to this, the fan control unit 305 cancels the increase in the rotation speed of the cooling fan mounted on the housing 0b (step S181). When the rotation speed of the cooling fan is not increased, the current rotation speed is maintained. Then, the processing shifts to the processing in step S183 in FIG.

  On the other hand, when the CPU temperature of the processing target CPU is not equal to or lower than T0 (step S179: No route), the process proceeds to the process of step S183 in FIG.

  The relationship between T0 to T3 will be described with reference to FIG. In the second embodiment, the relationship T0 <T1 <T2 <T3 is established. By such T0 to T3, it is possible to implement measures against temperature rise step by step.

  39, the temperature monitoring unit 304 determines whether there is an unprocessed CPU among the CPUs in the information processing system 2 (step S183). If there is an unprocessed CPU (step S183: Yes route), the process returns to the process of step S163 in FIG.

  On the other hand, if there is no unprocessed CPU (step S183: No route), it is determined whether a processing end instruction has been received from the administrator of the information processing system 2 (step S185). When the process termination instruction has not been received (step S185: No route), the process returns to the process of step S161 in FIG. When the process end instruction is accepted (step S185: Yes route), the process ends.

  By executing the processing as described above, an appropriate response can be flexibly implemented according to the CPU temperature.

  Next, processing executed by the system control unit 200 will be described with reference to FIGS. 40 to 44. Also in this embodiment, it is assumed that cores having a predetermined number of contract licenses are operated in the information processing system 2.

  First, the temperature data processing unit 204 in the system control unit 200 receives notification of temperature data from the temperature monitoring unit 304 in the control units 0f to 2f, and updates the first management data stored in the management data storage unit 203 (FIG. 40: Step S191). In step S191, the number of unused cores of each CPU may be calculated based on the second management data, and the first management data may also be updated.

  The CPU selection unit 202 determines whether a core switching request has been received from the switching unit 303 in the control units 0f to 2f (step S193). When a core switching request has not been received from the switching unit 303 (step S193: No route), the process proceeds to step S203. On the other hand, when a core switching request is received from the switching unit 303 (step S193: Yes route), the CPU selection unit 202 executes a determination process (step S195). The determination process will be described with reference to FIGS.

  First, the CPU selection unit 202 ranks “CPU temperature” in the first management data (FIG. 41: step S211), and updates the first management data. In step S211, ranking is performed such that the lower the CPU temperature, the higher the ranking.

  The CPU selection unit 202 ranks the “intake air temperature” in the first management data (step S213), and updates the first management data. In step S213, ranking is performed such that the lower the intake air temperature, the higher the ranking.

  The CPU selection unit 202 ranks the “number of unused cores” in the first management data (step S215), and updates the first management data. In step S215, the ranking is such that the higher the number of unused cores, the higher the ranking.

  The CPU selection unit 202 calculates the distance between the casings of the casing including the CPU specified by the CPU identification information included in the core switching request and the other casings. Then, the CPU selection unit 202 ranks “inter-casing distance” in the first management data (step S217), and updates the first management data. In step S217, ranking is performed such that the ranking increases as the distance between the casings increases.

  The CPU selection unit 202 calculates the sum of the CPU temperature rank, the intake air temperature rank, the number of unused cores, and the inter-chassis distance rank (step S219), and updates the first management data.

  The CPU selection unit 202 determines the overall ranking according to the sum calculated in step S219 (step S221), and updates the first management data.

  The CPU selection unit 202 sets the variable a representing the order as a = 1 (step S223), and identifies the CPU having the overall rank a (step S225).

  The CPU selection unit 202 determines whether the CPU identified in step S225 has an unused core (step S227). Whether or not it has an unused core is determined by information stored in the column of the number of unused cores in the first management data. When the CPU identified in step S225 does not have an unused core (step S227: No route), the CPU selection unit 202 sets a as a = a + 1 (step S229), and returns to the process of step S225. Thus, for example, in the example of FIG. 42, the CPU 31p with the overall ranking of 1 is first identified, then the CPU 20p, CPU 21p and CPU 30p with the overall ranking of 2 are identified, and so on. Specified from the CPU.

  On the other hand, when the CPU identified in step S225 has an unused core (step S227: Yes route), the CPU selection unit 202 selects one unused core from the unused cores of the CPU identified in step S225. Identify. Then, information indicating that the identified unused core is a core to be newly operated is generated (step S231) and stored in the RAM 252. Then, the process returns to the calling process.

  Returning to the description of FIG. 40, the CPU selection unit 202 sets one core in the CPU whose CPU temperature has reached T2 (that is, the CPU specified by the identification information included in the core switching request) to be invalid (step). S197). Specifically, the CPU selection unit 202 sets the operation flag of one core set to invalid in the second management data stored in the management data storage unit 203 to OFF.

  The CPU selection unit 202 effectively sets one core to be newly operated (that is, the core specified by the information generated in step S231) (step S199). Specifically, the CPU selection unit 202 sets the operation flag of one core that is set valid in the second management data stored in the management data storage unit 203 to ON.

  The core switching will be described with reference to FIG. In the example of FIG. 43, the intake temperature of the casing 0b installed at the highest position in the vertical direction is the highest, and the intake temperature of the casing 3b installed at the lowest position in the vertical direction is the lowest. ing. The bold core is an active core (ie, the active core).

  In this example, it is assumed that the temperature of the CPU 00p is equal to or higher than T2. In such a case, based on the processing described above, one core in the CPU 00p stops operating and one core in another CPU is operated. In the example of FIG. 43, one core of the CPU 31p in the housing 3b having the lowest intake air temperature starts a new operation. Thus, it is possible to enhance the temperature resistance of the information processing system 2 while ensuring that the CPU of the contract license number operates.

  The CPU selection unit 202 instructs the CPU management unit 401 in the virtualization software 22 to update the mapping data. In response to this, the CPU management unit 401 updates the mapping data stored in the mapping data storage unit 402 (step S201).

  The update of mapping data is demonstrated using FIG. In updating the mapping data, the association between the virtual CPU number and the physical CPU number is changed. Normally, a virtual machine executed on the OS 21 uses a core based on a virtual CPU number, but actually, the virtual CPU number is converted into a physical CPU number in the virtualization software 22, and the core is used based on the physical CPU number. . In step S201, the 7th core is newly used by switching the core, and the physical number “# 3” in the mapping data is rewritten to “# 7” by the CPU management unit 401 accordingly. It is done. In this way, it is possible to change the arrangement of operating cores without changing the virtual CPU number. That is, it is not necessary to modify the OS 21.

  The CPU selection unit 202 determines whether an instruction to end the process by the administrator of the information processing system 2 has been received (step S203). When the process termination instruction has not been received (step S203: No route), the process returns to step S191. When an instruction to end the process is received (step S203: Yes route), the process ends.

  By executing the processing as described above, it is possible to prevent the temperature from becoming locally high, so that the occurrence of temperature unevenness can be suppressed and the stable operation of the system can be maintained. Further, if the temperature tolerance can be enhanced by changing the arrangement of the operating CPUs, it may not be necessary to increase the rotation speed of the cooling fan, which leads to a reduction in power consumption.

  In addition, according to the above processing, it is considered that the number of cores that are in an advantageous position for cooling increases and the number of cores that are in an unfavorable position for cooling gradually decreases.

[Embodiment 3]
Next, a third embodiment will be described.

  The determination process of the third embodiment is different from the determination process of the second embodiment in that at least the CPU temperature and the calculated inter-chassis distance are ranked, and the other points are the third. The second embodiment and the second embodiment are the same. Below, the determination process of 3rd Embodiment is demonstrated.

  First, the CPU selection unit 202 ranks “CPU temperature” in the first management data (FIG. 45: step S241), and updates the first management data. In step S241, ranking is performed such that the lower the CPU temperature, the higher the ranking.

  The CPU selection unit 202 calculates the distance between the casings of the casing including the CPU specified by the CPU identification information included in the core switching request and the other casings. Then, the CPU selection unit 202 ranks “distance between cases” in the first management data (step S243), and updates the first management data. In step S243, ranking is performed such that the ranking increases as the distance between the casings increases.

  The CPU selection unit 202 calculates the sum of the CPU temperature order and the inter-case distance order (step S245), and updates the first management data.

  The CPU selection unit 202 determines the overall ranking according to the sum calculated in step S245 (step S247), and updates the first management data.

  The CPU selection unit 202 sets the variable a representing the ranking as a = 1 (step S249), and identifies the CPU having the overall ranking a (step S251).

  The CPU selection unit 202 determines whether the CPU identified in step S251 has an unused core (step S253). Whether or not it has an unused core is determined by information stored in the column of the number of unused cores in the first management data. When the CPU specified in step S251 does not have an unused core (step S253: No route), the CPU selection unit 202 sets a as a = a + 1 (step S255), and returns to the process of step S251.

  On the other hand, when the CPU identified in step S251 has an unused core (step S253: Yes route), the CPU selection unit 202 selects one unused core from the unused cores of the CPU identified in step S251. Identify. Then, information indicating that the identified unused core is a core to be newly operated is generated (step S257) and stored in the RAM 252. Then, the process returns to the calling process.

  By executing the processing as described above, it is possible to prevent the temperature from becoming locally high, so that the occurrence of temperature unevenness can be suppressed and the stable operation of the system can be maintained. Further, if the temperature tolerance can be enhanced by changing the arrangement of the operating CPUs, it may not be necessary to increase the rotation speed of the cooling fan, which leads to a reduction in power consumption. For example, in the case where there is almost no difference in the intake air temperature between the cases, or the case where the number of cores used in the CPU has a small effect on the rise in the CPU temperature, the third embodiment is It is valid.

[Embodiment 4]
Next, a fourth embodiment will be described.

  The determination process of the fourth embodiment is different from the determination process of the second and third embodiments in that at least the intake air temperature and the number of unused cores are ranked, and the other points are the fourth. The second embodiment and the third and third embodiments are the same. Hereinafter, a determination process according to the fourth embodiment will be described.

  The CPU selection unit 202 ranks the “intake air temperature” in the first management data (FIG. 46: step S261), and updates the first management data. In step S261, ranking is performed such that the lower the intake air temperature, the higher the ranking.

  The CPU selection unit 202 ranks the “number of unused cores” in the first management data (step S263), and updates the first management data. In step S263, ranking is performed such that the higher the number of unused cores, the higher the ranking.

  The CPU selection unit 202 calculates the sum of the ranking of the intake air temperature and the ranking of the number of unused cores (step S265), and updates the first management data.

  The CPU selection unit 202 determines the overall ranking according to the sum calculated in step S265 (step S267), and updates the first management data.

  The CPU selection unit 202 sets the variable a representing the order as a = 1 (step S269), and identifies the CPU having the overall rank a (step S271).

  The CPU selection unit 202 selects the CPU specified by the identification information included in the switching request between the housing including the CPU specified in step S271 and the core, and the CPU specified in step S271 has an unused core. It is determined whether the condition that the distance between the housings including the housing is larger than 0 is satisfied (step S273).

  When the condition is not satisfied (step S273: No route), the CPU selection unit 202 sets a as a = a + 1 (step S275), and returns to the process of step S271.

  On the other hand, when the condition is satisfied (step S273: Yes route), the CPU selection unit 202 specifies one unused core from the unused cores of the CPU specified in step S271. Then, information indicating that the identified unused core is a core to be newly operated is generated (step S277) and stored in the RAM 252. Then, the process returns to the calling process.

  By executing the processing as described above, it is possible to prevent the temperature from becoming locally high, so that the occurrence of temperature unevenness can be suppressed and the stable operation of the system can be maintained. Further, if the temperature tolerance can be enhanced by changing the arrangement of the operating CPUs, it may not be necessary to increase the rotation speed of the cooling fan, which leads to a reduction in power consumption. For example, the fourth embodiment is effective particularly when the intake air temperature and the number of cores used in the CPU have a large effect on the CPU temperature.

  Although one embodiment of the present invention has been described above, the present invention is not limited to this. For example, the functional block configurations of the monitoring device 100, the control units 0f to 2f, the system control unit 200, and the virtualization software 22 described above may not match the actual program module configuration.

  In addition, the configuration of each data storage unit described above is an example, and the above configuration is not necessarily required. Further, in the processing flow, the processing order can be changed if the processing result does not change. Further, it may be executed in parallel.

  Further, in steps S219, S247, and S267, the sum of the ranks may be obtained after weighting the ranks. As a result, the order of items to be prioritized is easily reflected in the overall order.

  The embodiment of the present invention described above is summarized as follows.

  The control device (also referred to as a monitoring device) according to the first aspect of the present embodiment includes (A) information on the physical position of each of the plurality of processing devices in the information processing system and whether or not the processing device is operating. And (B) one or a plurality of processing devices to be operated from among the plurality of processing devices based on the information on the physical positions of the plurality of processing devices stored in the storage unit. And a control unit that executes updating of management information stored in the storage unit and processing for operating one or a plurality of first processing devices according to the determination result.

  This makes it possible to operate an appropriate processor in the multiprocessor system.

  The information processing system has a plurality of central processing units, and each of the plurality of central processing units has one or a plurality of groups each having one or a plurality of processing units using the same primary cache. However, the processing devices belonging to one or more groups included in the same central processing unit use the same secondary cache, the power supply of the information processing system is controlled in units of groups, and the physical position information is processed Information on the position of the central processing unit including the device and information on the position of the group to which the processing device belongs may be included. If a large number of processing devices do not operate in the same group, it is possible to suppress the occurrence of contention for the primary cache, thereby preventing a decrease in performance. Further, if a large number of processing devices are not operated in the same central processing unit, it is possible to suppress the occurrence of contention for the secondary cache, thereby preventing a decrease in performance. On the other hand, if a large number of processing devices operate in the same group, the number of groups to be powered on can be reduced, so that power consumption can be suppressed. Therefore, if the process as described above is executed, the power consumption and the performance can be appropriately controlled according to the physical position of the processing apparatus to be operated.

  In addition, the control unit described above includes (b1) one or more first processing devices so that one or more first processing devices are distributed to a plurality of central processing devices and one or more processing devices are distributed to a plurality of groups. A plurality of first processing devices may be determined. As a result, it is possible to suppress the occurrence of contention for the secondary cache and to suppress the occurrence of contention for the primary cache. That is, the information processing system can be operated with emphasis on performance.

  In addition, the control unit described above includes (b2) one or a plurality of first processing devices so that one or a plurality of first processing devices are distributed to a plurality of central processing devices and one or a plurality of processing devices are collected in a specific group. The first processing apparatus may be determined. As a result, it is possible to suppress the occurrence of contention for the secondary cache and to suppress power consumption. That is, the information processing system can be operated with an emphasis on the balance between performance and power saving.

  In addition, the control unit described above may include (b3) one or a plurality of first processing devices so that one or more first processing devices are collected in a specific central processing device and one or more processing devices are collected in a specific group. The first processing apparatus may be determined. As a result, the information processing system can be operated with emphasis on power saving.

  Moreover, the process for operating the 1 or several 1st processing apparatus mentioned above may also include the process which powers on a 1 or several 1st processing apparatus. For example, it becomes possible to operate at an optimum physical position from the time of starting the information processing system.

  The information processing system may include a plurality of central processing units, and each of the plurality of processing units may be included in any of the plurality of central processing units. And the control part mentioned above detects that the temperature of the specific processing apparatus exceeded the threshold among (b4) operating processing apparatuses, and the distance between each processing apparatus and the specific processing apparatus, Based on the temperature of the central processing unit including each processing unit, one first processing unit may be determined from among the plurality of processing units. In order to prevent the occurrence of a locally hot place and to lower the temperature of the information processing system as a whole, a processing device that is distant from a specific processing device and a processing device included in a central processing device having a low temperature operate. Is preferred. Thus, as described above, it is possible to suppress the occurrence of temperature unevenness and the high temperature of the information processing system.

  The information processing system may include a plurality of central processing units, and each of the plurality of processing units may be included in any of the plurality of central processing units. And the control part mentioned above detects that the temperature of the specific processing apparatus exceeded the threshold among (b5) operating processing apparatuses, and the distance between each processing apparatus and the specific processing apparatus, Even if one first processing device is determined from a plurality of processing devices based on the intake air temperature of the space including each processing device and the number of processing devices not operating in the central processing device including each processing device. Good. In the sense of preventing the occurrence of a locally hot place and reducing the temperature of the information processing system as a whole, a processing device away from a specific processing device, a processing device included in a low-temperature space, and a non-operating process It is preferable that the processing apparatus included in the central processing apparatus having many apparatuses operates. Thus, as described above, it is possible to suppress the occurrence of temperature unevenness and the high temperature of the information processing system.

  Further, the control unit described above may determine (b6) one first processing device from among the plurality of processing devices based on the temperature of the central processing device including each processing device. Thereby, temperature control can be performed more flexibly.

  In addition, the process for operating one or more first processing devices is stored in a data storage unit that stores virtual identification information of the processing device and physical identification information of the processing device in association with each other. A process of rewriting physical identification information of a specific processing apparatus with identification information of one first processing apparatus may be included. For example, during operation of the information processing system, the processor to be operated can be appropriately switched depending on the situation.

  The control method according to the second aspect of the present embodiment includes (C) information on each physical position of a plurality of processing devices in the information processing system, and management information indicating whether or not the processing devices are operating. Determining one or a plurality of first processing devices to be operated from among the plurality of processing devices based on the information on the physical positions of the plurality of processing devices stored in the storage unit storing (D) In accordance with the result, the management information stored in the storage unit is updated, and processing for operating one or more first processing devices is included.

  A program for causing the processor to perform the processing according to the above method can be created, and the program can be a computer-readable storage medium such as a flexible disk, a CD-ROM, a magneto-optical disk, a semiconductor memory, a hard disk, or the like. It is stored in a storage device. The intermediate processing result is temporarily stored in a storage device such as a main memory.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Appendix 1)
A storage unit that stores information on the physical position of each of the plurality of processing devices in the information processing system and management information indicating whether the processing device is operating;
Based on the information on the physical position of each of the plurality of processing devices stored in the storage unit, one or more first processing devices to be operated are determined from the plurality of processing devices, and according to the determination result A control unit that executes updating of the management information stored in the storage unit and processing for operating the one or more first processing devices;
Control device.

(Appendix 2)
The information processing system has a plurality of central processing units,
Each of the plurality of central processing units has one or more groups each having one or more processing units using the same primary cache;
Processing devices belonging to one or more groups included in the same central processing unit use the same secondary cache,
The power source of the information processing system is controlled in groups,
The information on the physical position includes information on a position of a central processing unit including the processing device and information on a position of a group to which the processing device belongs.
The control device according to appendix 1.

(Appendix 3)
The controller is
The one or more first processing devices are determined such that the one or more first processing devices are distributed to the plurality of central processing devices and the one or more processing devices are distributed to the plurality of groups. To
The control device according to attachment 2.

(Appendix 4)
The controller is
Determining the one or more first processing devices such that the one or more first processing devices are distributed to the plurality of central processing devices and the one or more processing devices are collected in a particular group;
The control device according to attachment 2.

(Appendix 5)
The controller is
Determining the one or more first processing devices such that the one or more first processing devices are collected in a specific central processing device and the one or more processing devices are collected in a specific group;
The control device according to attachment 2.

(Appendix 6)
The processing for operating the one or more first processing devices includes:
Including a process of turning on power to the one or more first processing devices,
The control device according to any one of appendices 1 to 5.

(Appendix 7)
The information processing system has a plurality of central processing units,
Each of the plurality of processing devices is included in any of the plurality of central processing devices,
The controller is
It is detected that the temperature of a specific processing device has exceeded a threshold value among the operating processing devices, the distance between each processing device and the specific processing device, the temperature of the central processing device including each processing device, And determining one first processing device from among the plurality of processing devices,
The control device according to appendix 1.

(Appendix 8)
The information processing system has a plurality of central processing units,
Each of the plurality of processing devices is included in any of the plurality of central processing devices,
The controller is
It is detected that the temperature of a specific processing device out of the operating processing devices exceeds a threshold, the distance between each processing device and the specific processing device, the intake air temperature of the space including each processing device, Determining one first processing device from the plurality of processing devices based on the number of processing devices not operating in the central processing unit including each processing device;
The control device according to appendix 1.

(Appendix 9)
The controller is
Further determining the first first processing device from the plurality of processing devices based on a temperature of a central processing device including each processing device;
The control device according to appendix 8.

(Appendix 10)
The processing for operating the one or more first processing devices includes:
The physical identification information of the specific processing device stored in the data storage unit that stores the virtual identification information of the processing device and the physical identification information of the processing device in association with each other is the first first information. Including processing to rewrite the identification information of one processing device,
The control device according to any one of appendices 7 to 9.

(Appendix 11)
Processor
Each of the plurality of processing devices stored in a storage unit that stores information on the physical position of each of the plurality of processing devices in the information processing system and management information indicating whether or not the processing device is operating. Determining one or a plurality of first processing devices to be operated from among the plurality of processing devices based on the physical position information;
According to the result of the determination, the management information stored in the storage unit is updated, and the process for operating the one or more first processing devices is executed.
A control method for executing processing.

(Appendix 12)
To the processor,
Each of the plurality of processing devices stored in a storage unit that stores information on the physical position of each of the plurality of processing devices in the information processing system and management information indicating whether or not the processing device is operating. Determining one or a plurality of first processing devices to be operated from among the plurality of processing devices based on the physical position information;
According to the result of the determination, the management information stored in the storage unit is updated, and the process for operating the one or more first processing devices is executed.
A control program that executes processing.

1 Information processing system 10 OS
11 virtualization software 12 hardware 13 motherboard 14 memory 1p, 2p, 3p, 4p CPU 100 monitoring device 11l, 12l, 13l, 14l, 21l, 22l, 23l, 24l, 31l, 32l, 33l, 34l, 41l, 42l , 43l, 44l LCU
1c L2 cache 1mc memory access controller 101 license management unit 102 second management data storage unit 103 power supply mode management unit 104 first management data storage unit 105 allocation determination unit 106 core position data storage unit 107 power-on management unit 108 LCU position data storage Unit 109 Power control unit 111 CPU
112 RAM 113 ROM
114 System control firmware 115 Bus 2 Information processing system 21 OS
22 Virtualization software 23 Hardware 0b, 1b, 2b Case 0f, 1f, 2f Control unit 200 System control unit 0m, 1m, 2m Monitoring device 00s, 01s, 02s, 10s, 11s, 12s, 20s, 21s, 22s CPU temperature sensor 50s, 51s, 52s Intake air temperature sensor 251, 261 CPU
252,262 RAM 253,263 ROM
2541 System control firmware 2542, 264 Control firmware 255, 265 Bus 201 OS interface unit 202 CPU selection unit 203 Management data storage unit 204 Temperature data processing unit 301 Temperature abnormality processing unit 302 Power supply control unit 303 Switching unit 304 Temperature monitoring unit 305 Fan control unit 401 CPU management unit 402 Mapping data storage unit

Claims (12)

A storage unit that stores information on the physical position of each of the plurality of processing devices in the information processing system and management information indicating whether the processing device is operating;
Based on the information on the physical position of each of the plurality of processing devices stored in the storage unit, one or more first processing devices to be operated are determined from the plurality of processing devices, and according to the determination result A control unit that executes updating of the management information stored in the storage unit and processing for operating the one or more first processing devices;
Control device. The information processing system has a plurality of central processing units,
Each of the plurality of central processing units has one or more groups each having one or more processing units using the same primary cache;
Processing devices belonging to one or more groups included in the same central processing unit use the same secondary cache,
The power source of the information processing system is controlled in groups,
The information on the physical position includes information on a position of a central processing unit including the processing device and information on a position of a group to which the processing device belongs.
The control device according to claim 1. The controller is
The one or more first processing devices are determined such that the one or more first processing devices are distributed to the plurality of central processing devices and the one or more processing devices are distributed to the plurality of groups. To
The control device according to claim 2. The controller is
Determining the one or more first processing devices such that the one or more first processing devices are distributed to the plurality of central processing devices and the one or more processing devices are collected in a particular group;
The control device according to claim 2. The controller is
Determining the one or more first processing devices such that the one or more first processing devices are collected in a specific central processing device and the one or more processing devices are collected in a specific group;
The control device according to claim 2. The processing for operating the one or more first processing devices includes:
Including a process of turning on power to the one or more first processing devices,
The control device according to any one of claims 1 to 5. The information processing system has a plurality of central processing units,
Each of the plurality of processing devices is included in any of the plurality of central processing devices,
The controller is
It is detected that the temperature of a specific processing device has exceeded a threshold value among the operating processing devices, the distance between each processing device and the specific processing device, the temperature of the central processing device including each processing device, And determining one first processing device from among the plurality of processing devices,
The control device according to claim 1. The information processing system has a plurality of central processing units,
Each of the plurality of processing devices is included in any of the plurality of central processing devices,
The controller is
It is detected that the temperature of a specific processing device out of the operating processing devices exceeds a threshold, the distance between each processing device and the specific processing device, the intake air temperature of the space including each processing device, Determining one first processing device from the plurality of processing devices based on the number of processing devices not operating in the central processing unit including each processing device;
The control device according to claim 1. The controller is
Further determining the first first processing device from the plurality of processing devices based on a temperature of a central processing device including each processing device;
The control device according to claim 8. The processing for operating the one or more first processing devices includes:
The physical identification information of the specific processing device stored in the data storage unit that stores the virtual identification information of the processing device and the physical identification information of the processing device in association with each other is the first first information. Including processing to rewrite the identification information of one processing device,
The control device according to any one of claims 7 to 9. Processor
Each of the plurality of processing devices stored in a storage unit that stores information on the physical position of each of the plurality of processing devices in the information processing system and management information indicating whether or not the processing device is operating. Determining one or a plurality of first processing devices to be operated from among the plurality of processing devices based on the physical position information;
According to the result of the determination, the management information stored in the storage unit is updated, and the process for operating the one or more first processing devices is executed.
A control method for executing processing. To the processor,
Each of the plurality of processing devices stored in a storage unit that stores information on the physical position of each of the plurality of processing devices in the information processing system and management information indicating whether or not the processing device is operating. Determining one or a plurality of first processing devices to be operated from among the plurality of processing devices based on the physical position information;
According to the result of the determination, the management information stored in the storage unit is updated, and the process for operating the one or more first processing devices is executed.
A control program that executes processing.

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