JP2017076916A - Pixel inspection device, image processing apparatus, pixel inspection method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pixel inspection device that appropriately and quickly detects defective pixels irrespective of a processing mode.SOLUTION: A pixel inspection part 10 inspects when an input pixel is a defective pixel in a two-pixel parallel processing mode or a two-line parallel processing mode. The pixel inspection part 10 switches appropriately, according to the processing mode, reading addresses of a table Teo for an odd-number-th defect on an even-numbered line, a table Too for an odd-number-th defect on an odd-numbered line, a table Tee for an even-number-th defect on an even-numbered line, and a table Toe for an even-number-th defect on an odd-numbered line, and information on read defective coordinates, and inputs information on the coordinates Ta and Tb of the defective pixel to defect determination parts 16e and 16o. The defect determination parts determines a defect by comparing counter values: an X counter and a Y counter of the input pixel with the information on the coordinates of the defective pixel.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a pixel inspection device, an image processing device, a pixel inspection method, and a program, and more specifically, a pixel inspection device that inspects whether each pixel of input image data is a defective pixel, an image processing device, The present invention relates to a pixel inspection method and a program.

  An imaging sensor, for example, a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), or the like generally has a defective pixel. Conventionally, an image of a defective pixel is converted into an effective pixel that is a surrounding non-defective pixel. Correction is performed using.

  In order to perform a defective pixel detection process for determining whether or not the read pixel is a defective pixel and a correction process using pixels around the defective pixel, a defective pixel table in which defective pixels are registered in advance has been used.

  In this defective pixel table, defective pixels are registered for all the pixels of the image sensor, but the image sensor has a plurality of reading modes (for example, horizontal inversion / vertical inversion / thinning / cutout). It is necessary to correspond to each reading mode.

  In other words, when the reading method of the image sensor changes from the normal reading method, the pixel reading order changes from the case of reading all data of the image sensor from left to right and from top to bottom, and the coordinates registered in the defective pixel table are changed. Information and input pixels do not match.

  Therefore, conventionally, a method having a plurality of defective pixel tables, a method of converting the addresses of the defective pixel tables according to the reading order, and the like are used according to the reading mode provided.

  For example, conventionally, when input pixel data corresponds to a defective pixel, a defect correction calculation unit that corrects the pixel data, m memories that cyclically distribute and record all position information of the defective pixel, and the input A pixel position management unit that manages position information of m pixels including pixels corresponding to the pixel data; and the m pieces of position information and m pieces of the position information that are distributed and recorded in the m memories. The position information comparison unit that compares the position information of the defective pixels and outputs a match signal corresponding to the number when the position information matches, and only the match signal corresponding to the valid pixel among the match signals. A pixel defect correction apparatus including a match signal output control unit that outputs to the defect correction calculation unit and an address management unit that manages the read addresses of the m memories corresponding to the number of the match signals is proposed. Are (see Patent Document 1).

  That is, in this prior art, defective pixel information is managed separately in a plurality of memories in order to search for defective pixels at high speed without increasing the memory capacity.

  However, the prior art described in the above publication has a problem that defective pixel search corresponding to various reading modes cannot be performed at high speed.

  That is, in recent years, in order to improve the processing speed, two-pixel parallel processing for processing two pixels in parallel and two-line parallel processing for processing two lines in parallel may be performed. Are not considered for 2-pixel parallel processing and 2-line parallel processing. Therefore, in the technology described in the conventional publication, the defective pixel detection process and the defective pixel correction process cannot be performed with respect to the two-pixel parallel process and the two-line parallel process, and there is a need for improvement.

  In view of the above, an object of the present invention is to detect defective pixels appropriately and at high speed even when the detection processing modes of defective pixels are different.

  In order to achieve the above object, the pixel inspection apparatus according to claim 1, wherein a predetermined number of pixels in a main scanning direction is one line, and pixels of image data having a predetermined number of lines are sub-scanned perpendicular to the main scanning direction. This is a pixel inspection apparatus that uses the head pixel in the main scanning direction of the head line in the direction as a reference pixel, is input as an input pixel continuously from the reference pixel, and detects whether the input pixel is a defective pixel or not. The even-numbered odd-numbered defect pixel coordinates in which the even-numbered odd-numbered defective pixel coordinates of the even-numbered lines are registered, and the odd-numbered odd-numbered lines in which the odd-numbered defective pixel coordinates of the odd-numbered lines are registered. An eye defect table, an even line even-numbered defect pixel coordinate in which the even-numbered defective pixel coordinates of even-numbered lines are registered, and an even-numbered defective pixel coordinate in the main-scanning direction of odd-numbered lines are registered. The odd-numbered line even-numbered defect table, and the defective pixel coordinates read from the odd-numbered line odd-numbered defect table or the even-numbered line even-numbered defect table based on the respective read addresses and the odd-numbered line even number Even-numbered defective pixel coordinate switching means for switching the defective pixel coordinates read from the individual defect table according to the defective pixel detection processing mode and the even-numbered table switching signal and outputting them as even-numbered defective pixel coordinates. And reading from the defective pixel coordinates read from the odd line odd number defect table or the even line even number defect table and the even line odd number defect table based on the respective read addresses. The defective pixel coordinates that have been detected correspond to the defective pixel detection processing mode and the odd-side table switching signal. Odd-numbered defective pixel coordinate switching means for switching and outputting as odd-numbered defective pixel coordinates, coordinate detection means for detecting coordinates of the input pixel in the main scanning direction and the sub-scanning direction, and detection detected by the coordinate detection means An even pixel defect determining means for comparing coordinates and the even-numbered defective pixel coordinates to determine whether or not the input pixel of the detected coordinates is a defective pixel; and the detected coordinates detected by the coordinate detecting means and the odd number Odd pixel defect determining means for comparing the defective pixel coordinates of the detected coordinates to determine whether the input pixel of the detected coordinates is a defective pixel, the determination result of the even pixel defect determining means and the detected coordinates The even-side table switching unit that outputs the even-side table switching signal to the even-side defective pixel coordinate switching unit, the determination result of the odd-numbered pixel defect determining unit, and the odd-number according to the detected coordinates. An odd-numbered table switching unit that outputs a number-side table switching signal to the odd-numbered defective pixel coordinate switching unit, and a read address to each table based on the determination results of the even-numbered pixel defect determining unit and the odd-numbered pixel defect determining unit. And an address control means for outputting.

  According to the present invention, defective pixels can be detected appropriately and at high speed even when the detection processing modes for defective pixels are different.

1 is a main part configuration diagram of an image processing apparatus to which an embodiment of the present invention is applied. The figure which shows the relationship between an input pixel order and a defective pixel. The figure which shows an example of the table for four defects. Explanatory drawing of a processing mode. The functional block diagram of a pixel test | inspection part. Without showing an example of a conventional general defect table. Explanatory drawing of 2 pixel parallel processing. The timing diagram of each signal in 2 pixel parallel processing. Explanatory drawing of 2 line parallel processing. The timing diagram of each signal in 2 line parallel processing.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 10 are diagrams illustrating an embodiment of a pixel inspection device, an image processing device, a pixel inspection method, and a program according to the present invention. FIG. 1 illustrates a pixel inspection device, an image processing device, and a pixel inspection according to the present invention. It is a principal part block diagram of the image processing apparatus 1 provided with the pixel test | inspection part to which one Example of a method and a program is applied.

  In FIG. 1, an image processing apparatus 1 includes a pixel inspection unit 10, an image sensor (not shown) (CCD, CMOS, etc.) and the like. The pixel inspection unit 10 includes a counter unit 11, a defective pixel coordinate information storage unit 12, a defective pixel table setting unit 13, a defective pixel table sorting unit 14, selectors Sa1 and Sb1, an even-numbered odd-numbered defect table Teo, and an odd-numbered line. Odd defect table Too, even line even defect table Tee, odd line even defect table Toe, selectors Sa0 and Sb0, selectors Sa2 and Sb2, table switching units 15e and 15o, defect determination unit 16e, 16o, address control units 17e and 17o, defective pixel correction units 18e and 18o, and the like.

  The counter unit 11 counts pixel positions in the X direction and Y direction of pixel data input from the imaging sensor (not shown), and outputs count values (X counter, Y counter) to the defect determination units 16e and 16o.

  That is, the counter unit 11, from the image sensor, as shown by a broken line arrow in FIG. 2, if the upper left in FIG. 2 is the origin (X = 0, Y = 0), the pixels from left to right and top to bottom Is entered. That is, the image processing apparatus 1 sequentially inputs pixels of image data from the imaging sensor to the counter unit 11 in the main scanning direction and the sub-scanning direction with the origin pixel as a reference pixel. 2, the areas indicated by the squares are pixels, and the pixels from “A” to “H” shown in black on the white are defective pixels. , Y = 0), the defective pixel “A” is (X = 3, Y = 2), and the defective pixel “H” is (X = 20, Y = 3). As for the defective pixel, the defective pixel position (X coordinate, Y coordinate) is specified in the inspection at the time of shipment of the image processing apparatus 1.

  The defective pixel coordinate information storage unit 12 uses non-volatile memory such as NVRAM (Non Volatile RAM), SSD (Solid State Drive), etc., and the defective pixel coordinate information of the image sensor is stored at the time of shipment of the image processing apparatus 1. Is done. The defective pixel coordinate information storage unit 12 does not need to store the defective pixel coordinate information in the formats of four defect tables Teo, Too, Tee, and Toe, which will be described later. It is only necessary that the position information of the defective pixel is stored in order.

  The defective pixel table setting unit 13 reads out defective pixel coordinate information stored in the defective pixel coordinate information storage unit 12. The defective pixel table setting unit 13 determines the defect tables Teo, Too, Tee, and Toe to which the defective pixel coordinate information is set, table setting information indicating the determined defect tables Teo, Too, Tee, and Toe and the defects. Pixel coordinate information is passed to the defective pixel table distribution unit 14.

  The defective pixel table setting unit 13 determines the setting destination to the defect tables Teo and Tee for even lines when the Y coordinate of the defective pixel coordinates is even, and to the defect tables Too and Toe for odd lines when the Y coordinate is odd. . Further, the defective pixel table setting unit 13 sets the setting destination to the even-numbered defect tables Tee and Toe when the defect is an even-numbered defect, and to the odd-numbered defect tables Teo and Too when the defect is an odd-numbered defect. decide.

  The defective pixel table allocating unit 14 transfers the defective pixel coordinate information passed from the defective pixel table setting unit 13 to the four defect tables Teo, Too, Tee, and Toe based on the table setting information of the defective pixel coordinate information. Sort and register.

  The defective pixel table setting unit 13 and the defective pixel table allocating unit 14 may have a hardware configuration or a software configuration executed by a CPU (Central Processing Unit) (not shown).

  When the defective pixel table setting unit 13 and the defective pixel table allocating unit 14 are configured by hardware, the defect table Teo is not conscious of the four defect tables Teo, Too, Tee, and Toe in terms of software. , Too, Tee, Toe address is mapped to the address space where the defective pixel coordinate information is mapped, the hardware performs the distribution, the four defect tables Teo, Too, Tee, which exist internally Set to Toe.

  When the defective pixel table setting unit 13 and the defective pixel table allocating unit 14 are realized by software, the four defect tables Teo, Too, Tee, and Toe exist in four as the register address space. The defective pixel coordinate information is written in a register at the corresponding address.

  The even-numbered odd-numbered defect table Teo is a table in which the coordinate information of the even-numbered and odd-numbered defective pixels is registered, and is managed with an address as shown in FIG. Is done. Note that the even-numbered odd-numbered defect table Teo need not have an address that matches the address of the register space recognized by the software.

  The even-numbered even-numbered defect table Tee is a table in which the coordinate information of the even-numbered and even-numbered defective pixels is registered, and is managed with an address as shown in FIG. Is done. Note that the even-numbered even-numbered defect table Tee does not need to match the address of the register space recognized by the software.

  The odd-numbered odd-numbered defect table Too is a table in which coordinate information of the odd-numbered defective pixels existing in the odd-numbered lines is registered, and is managed by an address as shown in FIG. The Note that the odd-numbered odd-numbered defect table Too does not have to match the address of the register space recognized by the software.

  The odd-numbered even-numbered defect table Toe is a table in which the coordinate information of the even-numbered and even-numbered defective pixels is registered, and is managed by an address as shown in FIG. Is done. The address of the odd-numbered even-numbered defect table Toe need not match the address of the register space recognized by the software.

  In FIG. 3, the meanings of “even” and “odd” of the odd-numbered defective pixel and the even-numbered defective pixel are the even-numbered and odd-numbered pixels counted from the coordinates in ascending order of the even-numbered lines and odd-numbered lines, respectively. And has nothing to do with the coordinate values (X = *, Y = *) itself. Also, the number of defective pixels starts from the first, and 2, 4, 6, 8... Is an even number, 1, 3, 5, 7. Coordinates and counts are represented by the beginning of 0, and 0, 2, 4, 6... Are even numbers, 1, 3, 5, 7.

  The defective pixels A, B, C and D shown in FIG. 2 are even-numbered defective pixels. A is the first defective pixel, B is the second defective pixel, C is the third defective pixel, and D is the defective pixel. This is the fourth defective pixel. The defective pixels E, F, G, and H are odd-numbered defective pixels, where E is the first defective pixel, F is the second defective pixel, G is the third defective pixel, and H is the fourth defective pixel. It becomes a defective pixel.

  The defect tables Teo, Too, Tee, and Toe may include not only defective pixel coordinate information but also other information, for example, a defective pixel correction method. The information other than the defective pixel coordinate information is, for example, information indicating which pixel of the peripheral pixels is used for processing when the defective pixel is corrected.

  The selector Sa0 receives a processing mode signal Sm indicating the reading mode (processing mode) of the image sensor, and based on the processing mode signal Sm, the even-numbered even-numbered defect table Tee and the odd-numbered odd-numbered odd numbered table Too. Make a selection. The selector Sao outputs the table information of the selected even-numbered even-numbered defect table Tee or odd-numbered odd-numbered odd numbered table Too as Ta1 and outputs it to the selector Sa2. When the processing mode signal Sm is “1”, it indicates that the processing mode is the two-pixel parallel processing mode, and when it is “0”, it indicates that the processing mode is the two-line parallel processing mode. The processing mode (reading mode) does not change during the processing of one frame of image data, and is the same processing mode.

  Here, when the processing mode which is the reading mode detects a defective pixel, the detection processing mode is set, and hereinafter also referred to as a processing mode as appropriate. The two-pixel parallel processing mode is a processing mode in which two pixels that are continuous in the main scanning direction on the same line (arrangement of pixels in the main scanning direction) are processed in parallel as shown in FIG. The two-line parallel processing mode is a processing mode in which two pixels at the same position are processed in parallel in the main scanning direction of two consecutive lines as shown in FIG.

  The selector Sao selects the even-numbered even-numbered defect table Tee when the processing mode signal Sm is “1” (two-pixel parallel processing), and when the processing mode signal Sm is “0” (two-line parallel processing). ), The odd-numbered odd-numbered defect table Too is selected. The selector Sao outputs information on the selected table to the selector Sb1 as table information Ta1.

  Similarly to the selector Sao, the selector Sb0 receives the processing mode signal Sm, and selects the even line odd number defect table Tee and the odd line odd number defect table Too based on the processing mode signal Sm. The selector Sbo selects the odd-numbered odd-numbered defect table Too when the processing mode signal Sm is “1” (two-pixel parallel processing), and when the processing mode signal Sm is “0” (two-line parallel processing). ), The even line even-numbered defect table Tee is selected. The selector Sbo outputs the table information of the selected even-numbered even-numbered defect table Tee or odd-numbered odd-numbered odd numbered table Too as table information Tb1 to the selector Sb2.

  The selector Sa1 receives the processing mode signal Sm, receives the address A1 from the address controller 17e, and receives the address B1 from the address controller 17o. The selector Sa1 selects the address A1 when the processing mode signal Sm is “1”, and selects the address B1 when the processing mode signal Sm is “0”. The selector Sa1 outputs the selected address A1 or address B1 to the odd-numbered odd-numbered defect table Too.

  The selector Sb1 receives the processing mode signal Sm, the address A1 from the address controller 17e, and the address B1 from the address controller 17o. The selector Sb1 selects the address B1 when the processing mode signal Sm is “1”, and selects the address A1 when the processing mode signal Sm is “0”. The selector Sb1 outputs the selected address A1 or address B1 to the even-numbered even-numbered defect table Tee.

  The selector Sa2 receives table information Ta1 from the selector Sa0 and table information Ta0 from the even-numbered odd-numbered defect table Teo, and further receives a table switching control signal Ste from the table switching unit 15e. The selector Sa2 selects one of the table information Ta1 and the table information Ta0 based on the table switching control signal Ste, and outputs the table information Ta to the defect determination unit 16e.

  The selector Sb2 receives table information Tb1 from the selector Sb0 and table information Tb0 from the odd-numbered even-numbered defect table Toe, and further receives a table switching control signal Sto from the table switching unit 15o. The selector Sb2 selects one of the table information Tb1 and the table information Tb0 based on the table switching control signal Sto, and outputs the table information Tb to the defect determination unit 16o.

  The defect determination unit 16e receives the table information Ta from the selector Sa2 and the table information Tb2 from the selector Sb2, and further receives an X counter and a Y counter from the counter unit 11. The defect determination unit 16e determines whether or not the even-numbered pixel in the parallel processing is a defective pixel. That is, the defect determination unit 16e compares the even-numbered defective pixel coordinate information of the two table information of the table information Ta and the table information Tb with the values of the X counter and the Y counter. When the even-numbered defective pixel coordinate of the table information Ta matches the value of the X counter / Y counter, the defect determining unit 16e asserts defective pixel matching information HIT_AE to the address control unit 7e. Further, when the even-numbered defective pixel coordinates of the table information Tb and the value of the X counter / Y counter match, the defect determining unit 16e asserts defective pixel matching information HIT_BE to the address control unit 17o.

  Further, since the table information Ta and the table information Tb are coordinate information of defective pixels having different coordinates, the defective pixel matching information HIT_AE and the defective pixel matching information HIT_BE are not asserted at the same time. Then, the defect determination unit 16e generates a defective pixel determination result signal SE under the OR condition of the defective pixel matching information HIT_AE and the defective pixel matching information HIT_BE, and outputs the defective pixel determination result signal SE to the defective pixel correction unit 18e.

  Similarly to the defect determination unit 16e, the defect determination unit 16o receives the table information Ta from the selector Sa2 and the table information Tb2 from the selector Sb2, and further receives an X counter and a Y counter from the counter unit 11. The defect determination unit 16o determines whether or not the odd-numbered pixel in the parallel processing is a defective pixel. In other words, the defect determination unit 16o compares the odd-numbered defective pixel coordinate information of the two pieces of table information, the table information Ta and the table information Tb, with the values of the X counter and the Y counter. When the odd-numbered defective pixel coordinate of the table information Ta matches the value of the X counter / Y counter, the defect determining unit 16o asserts defective pixel matching information HIT_AO to the address control unit 17e. Further, when the odd-numbered defective pixel coordinates of the table information Tb and the value of the X counter / Y counter match, the defect determination unit 16o outputs defective pixel matching information HIT_BO to the address control unit 17o.

  Further, the defect determination unit 16o generates a defective pixel determination result signal SO under the OR condition of the defective pixel matching information HIT_AO and the defective pixel matching information HIT_BO, and outputs it to the defective pixel correction unit 18o.

  The address control unit 17e receives the defective pixel match information HIT_AE, HIT_AO and the table switching control signal Ste from the defect determination unit 16e and the defect determination unit 16o. The address control unit 17e controls the read addresses A1 and A0 of the odd-numbered defect tables Teo and Too based on the defective pixel match information HIT_AE and HIT_AO and the table switching control signal Ste.

  The address control is a different process depending on the processing mode. That is, the address control unit 17e increments the address A0 when the table information Ta0 is selected under the OR condition of the defective pixel matching information HIT_AE and HIT_AO, and when the table information Ta1 is selected, the address A1 is incremented.

  The address control unit 17e holds an address when processing an unselected line, and resumes incrementing from the held address when selected again. The address control unit 17e clears the address after completing the processing of one frame and returns it to “0”. The address control unit 17e does not assert the defective pixel match information HIT_AE and the defective pixel match information HIT_AO at the same time because the defect determination unit 16e and the defect determination unit 16o perform determination on pixels having different coordinates.

  The address control unit 17o receives the defective pixel match information HIT_BE and HIT_BO and the table switching control signal Sto from the defect determination unit 16e and the defect determination unit 16o. The address control unit 17o controls the read addresses B1 and B0 of the even-numbered defect tables Toe and Tee based on the defective pixel match information HIT_BE and HIT_BO and the table switching control signal Sto.

  The address control unit 17o increments the address B0 when the table information Tb0 is selected under the OR condition of the defective pixel match information HIT_BE and HIT_BO, and the address B1 is selected when the table information Tb1 is selected. Increment.

  The address control unit 17o holds an address when processing an unselected line, and restarts incrementing from the held address when the line is selected again. The address control unit 17o clears the address after completing the processing of one frame and returns it to “0”. In the address control unit 17o, since the defect determination unit 16e and the defect determination unit 16o perform determination on pixels having different coordinates, the defective pixel match information HIT_BE and the defective pixel match information HIT_BO are not asserted at the same time.

  The defective pixel correction unit 18e receives the even-numbered data of the pre-correction pixel and the defective pixel determination result signal SE from the defect determination unit 16e, and corrects the defective pixel of the even-numbered pixel in parallel processing. If the input even-numbered pre-correction pixel is a non-defective pixel, the defective pixel correction unit 18e performs no processing on the pixel, and performs a defective pixel correction if the pixel is a defective pixel. The even-side corrected pixel is output. The defective pixel correction unit 18e corrects the defective pixel by a known defective pixel correction method, and this defective pixel correction method is not limited as long as it is a method for performing appropriate correction. The method can be used.

  The defective pixel correction unit 18o receives the odd-numbered data of the uncorrected pixel and the defective pixel determination result signal SO from the defect determination unit 16o, and corrects the defective pixel of the odd-numbered pixel in the parallel processing. The defective pixel correction unit 18o does not perform any processing for the input odd-numbered pre-correction pixel if it is a non-defective pixel, and performs defective pixel correction if it is a defective pixel. The odd-side corrected pixels are output. The defective pixel correction unit 18o corrects defective pixels by a known defective pixel correction method, and this defective pixel correction method is not limited as long as it is an appropriate correction method. The method can be used.

  The table switching unit 15e receives the defective pixel determination result signal SE from the defect determination unit 16e and the Y counter from the counter unit 11, outputs a table switching control signal Ste to the selector Sa2, and switches the selector Sa2. In the two-pixel parallel processing mode, the table switching unit 15e switches the selector Sa2 alternately for each line between the even line and the odd line based on the Y counter. In the two-line parallel processing mode, the table switching unit 15e switches the selector Sa2 alternately for each defective pixel detection based on the defective pixel determination result signal SE.

  The table switching unit 15o receives the defective pixel determination result signal SO from the defect determination unit 16o and the Y counter from the counter unit 11, outputs the table switching control signal Sto to the selector Sb2, and switches the selector Sb2. In the two-pixel parallel processing mode, the table switching unit 15o switches the selector Sb2 alternately for each line between the even line and the odd line based on the Y counter. In the two-line parallel processing mode, the table switching unit 15o switches the selector Sa2 alternately for each defective pixel detection based on the defective pixel determination result signal SO.

  The image processing apparatus 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), and a DVD. The pixel inspection method of the present invention recorded on a computer-readable recording medium such as (Digital Versatile Disk), USB (Universal Serial Bus) memory, SD (Secure Digital) card, MO (Magneto-Optical Disc) is executed. A pixel inspection unit that executes a pixel inspection method for detecting a defective pixel appropriately and at high speed even when a defective pixel detection processing mode described later is different by loading the program to be read into a ROM or a hard disk (not shown) 10 is built as an image processing apparatus. A program for executing the pixel inspection method is a computer-executable program described in a legacy programming language such as an assembler, C, C ++, C #, Java (registered trademark), an object-oriented programming language, or the like. Can be stored and distributed.

  In the pixel inspection unit 10, a functional block as shown in FIG. 5 is constructed by introducing the program. That is, the pixel inspection unit 10 introduces the above program, and as shown in FIG. 5, the even line odd number defect table 21eo, the odd line odd number defect table 21oo, the even line even number defect. Table 21ee, odd-numbered even-numbered defect table 21oe, even-numbered defective pixel coordinate switching unit 22e, odd-numbered defective pixel coordinate switching unit 22o, coordinate detecting unit 23, even-numbered pixel defect determining unit 24e, odd-numbered pixel defect determining unit 24o The even-side table switching unit 25e, the odd-side table switching unit 25o, the address control unit 26 including the address input switching unit 26a, the coordinate registration unit 27, and the correction unit 28 are constructed.

  The even-numbered odd-numbered defect table 21eo is constructed by the even-numbered odd-numbered defect table Teo, and is a table in which odd-numbered defective pixel coordinates of the even-numbered lines are registered. Therefore, the even-numbered odd-numbered defect table 21eo functions as an even-numbered odd-numbered defect table 21eo.

  The odd-numbered odd-numbered defect table 21oo is constructed by the odd-numbered odd-numbered defect table Too, and is a table in which odd-numbered defective pixel coordinates of the odd-numbered lines are registered. Therefore, the odd line odd number defect table 21oo functions as an odd line odd number defect table.

  The even-numbered line even-numbered defect table 21ee is a table that is constructed from the even-numbered line even-numbered defect table Tee and registers even-numbered defective pixel coordinates of the even-numbered lines in the main scanning direction. Therefore, the even line even-numbered defect table 21ee functions as an even-numbered line even-numbered defect table.

  The odd-numbered even-numbered defect table 21oe is constructed by the odd-numbered even-numbered defect table Toe, and is a table in which even-numbered defective pixel coordinates of the odd-numbered lines are registered. Therefore, the odd-numbered line even-numbered defect table 21oe functions as an odd-numbered line even-numbered defect table.

  The even-numbered defective pixel coordinate switching unit 22e is constructed by the selector Sa0 and the selector Sa2. The even-numbered defective pixel coordinate switching unit 22e has defective pixel coordinate information which is defective pixel coordinates read from the odd-numbered line odd-numbered defect table 21oo or the even-numbered line even-numbered defect table 21ee based on the respective read addresses. Switching between the table Ta1 and the defective pixel coordinate information table Ta0 that is the defective pixel coordinates read from the odd-numbered even-numbered defect table 21oe according to the processing mode and the table switching control signal Ste that is the even-side table switching signal Are output as table information Ta which are even-numbered defective pixel coordinates. Therefore, the even-numbered defective pixel coordinate switching unit 22e functions as even-numbered defective pixel coordinate switching means.

  The odd-numbered defective pixel coordinate switching unit 22o is constructed by the selector Sb0 and the selector Sb2. The odd-numbered defective pixel coordinate switching unit 22o has defective pixel coordinate information which is defective pixel coordinates read from the odd-numbered line odd-numbered defect table 21oo or the even-numbered line even-numbered defect table 21ee based on the respective read addresses. Switching between the table Tb1 and the defective pixel coordinate information table Tb0 that is the defective pixel coordinates read from the even-numbered odd-numbered defect table 21eo according to the processing mode and the table switching control signal Sto that is the odd-side table switching signal And output as table information Tb which is odd-numbered defective pixel coordinates. Therefore, the odd-numbered defective pixel coordinate switching unit 22o functions as odd-numbered defective pixel coordinate switching means.

  The coordinate detection unit 23 is constructed by the counter unit 11 and detects coordinates (X counter, Y counter) of the input pixel in the main scanning direction and the sub scanning direction. Therefore, the coordinate detection unit 23 functions as a coordinate detection unit.

  The even pixel defect determination unit 24e is constructed by the defect determination unit 16e, and compares the detection coordinates detected by the coordinate detection unit 23 with the even-side defect pixel coordinates (table information Ta) from the even-side defect pixel coordinate switching unit 22e. Thus, it is determined whether or not the input pixel of the detected coordinate is a defective pixel. Therefore, the even pixel defect determination unit 24e functions as an even pixel defect determination unit.

  The odd pixel defect determination unit 24o is constructed by the defect determination unit 16o, and compares the detection coordinates detected by the coordinate detection unit 23 with the odd defect pixel coordinates (table information Tb) from the odd defect pixel coordinate switching unit 22o. Thus, it is determined whether or not the input pixel of the detected coordinate is a defective pixel. Therefore, the odd pixel defect determination unit 24o functions as an odd pixel defect determination unit.

  The even-side table switching unit 25e is constructed by the table switching unit 15e, and switches the even-side table switching signal (table switching control signal Ste) according to the determination result of the even-numbered pixel defect determining unit 24e and the detected coordinates. To 22e. Therefore, the even-side table switching unit 25e functions as an even-side table switching unit.

  The odd-side table switching unit 25o is constructed by the table switching unit 15o, and the odd-side table switching signal (table switching control signal Sto) corresponding to the determination result of the odd-numbered pixel defect determining unit 24o and the detected coordinates is switched to the odd-side defective pixel coordinates. To the unit 22o. Therefore, the odd-side table switching unit 25o functions as an odd-side table switching unit.

  The address control unit 26 includes an address input switching unit 26a constructed by the address control units 17e and 17o and constructed by the selectors Sa1 and Sb1. The address control unit 26 outputs a read address to each table 21eo, 21oo, 21ee, 21oe based on the determination results of the even pixel defect determination unit 24e and the odd pixel defect determination unit 24o. Therefore, the address control unit 26 functions as an address control unit. The address input switching unit 26a switches the read address input destination between the odd-numbered line odd-numbered defect table 21oo and the even-numbered line even-numbered defect table 21ee according to the detection processing mode. In this case, the address control unit 26 directly outputs the read addresses for the even-numbered odd-numbered defect table 21eo and the odd-numbered even-numbered defect table 21oe.

  The coordinate registration unit 27 includes a defective pixel coordinate information storage unit 12, a defective pixel table setting unit 13, and a defective pixel table distribution unit 14. The coordinate registration unit 27 sets the coordinates of the defective pixels to the even line odd number defect table 21eo, the odd line odd number defect table 21oo, the even line even number defect table 21ee, and the odd line even number defect table. Sort and register to 21 oe. Therefore, the coordinate registration unit 27 functions as a coordinate registration unit.

  The correcting unit 28 is constructed by the defective pixel correcting unit 18e and the defective pixel correcting unit 18o, and corrects the defective pixel determined by the even pixel defect determining unit 24e and the odd pixel defect determining unit 24o as a defective pixel. Therefore, the correction unit 28 functions as a correction unit.

  Next, the operation of this embodiment will be described. In the image processing apparatus 1 according to the present embodiment, the pixel inspection unit 10 detects a defective pixel appropriately and at high speed even when the defective pixel detection processing mode is different.

  In general, as shown in FIG. 4 as an image, an imaging sensor has a defective pixel, and an image processing apparatus that processes image data from the imaging sensor has an input pixel from the imaging sensor as a defective pixel. It is necessary to detect whether or not.

  A general image processing apparatus outputs pixels from the image sensor to the main scanning direction from the reference pixel in the main scanning direction of the first line in FIG. 4 to the main scanning direction and to the line from the upper line. Is done.

  A typical image processing apparatus that processes read image data has conventionally been provided with a defect table as shown in FIG. 6, and the defect table has the coordinates of defective pixel position information in accordance with the input order of the image data. Defective pixel coordinate information is registered in order. The defect table is addressed from the beginning of the defect table. For example, as shown in FIG. 6, if there are N addresses from address 0 to N-1, up to N defects. Pixels can be registered and detected. FIG. 6 shows a state in which the coordinate information of the defective pixel is registered at the address corresponding to the defective pixel in FIG.

  The image processing apparatus reads the coordinate information at address 0 in the defect table (A (X = 3, Y = 2) in FIG. 6) and counts the X direction counter and the Y direction counter that are counted every time image data is input. The value is compared with the coordinate information. When the values of the X counter and the Y direction counter match the XY coordinates of the defect table, the image processing apparatus determines that the input pixel is a defective pixel. When the image processing apparatus determines that the pixel is defective, the address of the defect table is incremented by one, and the coordinate information of the next address in the defect table (B (X = 12, Y = 2 in FIG. 6)) is obtained. Reading and performing the same process repeatedly.

  However, since the above processing is performed pixel by pixel, in order to improve the processing speed, it is necessary to process a plurality of pixels, for example, two pixels each.

  For example, the processing speed can be improved by performing the two-pixel parallel processing shown in FIG. In this case, it is necessary to read out coordinate information for two pixels from the defect table in consideration of the case where defective pixels are continuously arranged in the two-pixel main scanning direction. In addition, the image processing apparatus may perform not only two-pixel parallel processing but also the two-line parallel processing shown in FIG. 4 for the convenience of image processing and an image sensor. It is necessary to consider that there are two defective pixels. However, in the conventional defect table, addresses are assigned in the main scanning direction, and in the case of two-line parallel processing, a defect table for two-line parallel processing is prepared, or address conversion for two-line processing is performed. It is necessary to read out the defective pixel from the defect table. Further, when the two-pixel parallel processing and the two-line parallel processing are performed by switching, the image processing apparatus needs to perform the above processing for each processing mode, and the processing efficiency is poor.

  Therefore, the image processing apparatus 1 of the present invention includes the pixel inspection unit 10 as shown in FIG. 1 and detects a defective pixel appropriately and at high speed even when the detection processing mode of the defective pixel is different.

  That is, when the processing mode is two-pixel parallel processing, the pixel inspection unit 10 performs an operation process as illustrated in FIGS. 7 and 8 to detect a defective pixel appropriately and at high speed.

  In the two-pixel parallel processing mode, the pixel inspection unit 10 includes an even-numbered line even-numbered defect table Tee and an even-numbered line odd-numbered defect table Teo during even-numbered line processing, as indicated by thick arrows in FIG. Two tables are read and defective pixel correction processing is performed. In addition, during the odd line processing, the pixel inspection unit 10 reads out two tables, the odd line even number defect table Toe and the odd line odd number defect table Too, and performs defective pixel correction processing.

  That is, in the two-pixel parallel processing mode, the pixel inspection unit 10 has the processing mode “1” as shown in FIG. 7, and the selectors Sa0, Sa1, Sb0, and Sb1 are fixed during the period of one frame. . The pixel inspection unit 10 provides the selector Sa2 with the defective pixel coordinate information of the even-numbered odd-numbered defect table Teo as the table information Ta0, and the defective pixel coordinate information of the odd-numbered odd-numbered defect table Too as the table information Ta1. Is entered. In addition, the pixel inspection unit 10 supplies the selector Sb2 with the defective pixel coordinate information of the odd-numbered even-numbered defect table Toe as the table information Tb0 and the defective pixel of the even-numbered even-numbered defect table Tee as the table information Tb1. Coordinate information is input.

  In the two-pixel parallel processing mode, the pixel inspection unit 10 switches the outputs of the selectors Sa2 and Sb2 for each line by the table switching control signals Ste and Sto. Therefore, the selector Sa2 switches and outputs the defective pixel coordinate information tables Tao and Ta1 of the odd-numbered defect tables Teo and Too for each line as the table information Ta. Similarly, the selector Sb2 switches and outputs the defective pixel coordinate information tables Tb0 and Tb1 of the even-numbered defect tables Tee and Toe for each line as the table information Tb.

  The defect determination units 16e and 16o detect defective pixels with reference to both the even-numbered table information Ta and the odd-numbered table information Tb.

  That is, the pixel inspection unit 10 detects a defective pixel at the operation timing shown in FIG. 8 in the two-pixel parallel processing mode.

  The selector Sa2 switches the defective pixel coordinate information tables Tao and Ta1 for each line by the table switching control signal Ste from the table switching unit 15e, and outputs the table information Ta. The selector Sb2 switches the defective pixel coordinate information tables Tb0 and Tb1 for each line by the table switching control signal Sto from the table switching unit 15o, and outputs it as table information Tb. In FIG. 8, in the defective pixel coordinate information tables Ta0, Ta1, Tb0, and Tb1, the hatched period is a non-selection period, and the non-hatched period is a selection period.

  In FIG. 8, the pixel inspection unit 10 has a defect determination unit 16e because the odd-numbered data of the second line (even line) matches the table information Ta (defective pixel A (X = 3, Y = 2)) at T1. However, the defective pixel match information HIT_AO is asserted. When the defective pixel matching information HIT_AO is asserted, the address control unit 17e increments the address A0 and reads the table information Ta of the new defective pixel C (X = 18, Y = 2) in the next cycle.

  Since the pixel inspection unit 10 matches the table data Tb (defective pixel B (X = 12, Y = 2)) with the even-numbered data of the second line (even number line) at T2, the defect determination unit 16e The match information HIT_BE is asserted. When the defective pixel matching information HIT_BE is asserted, the address control unit 17o increments the address B1, and reads the table information Tb of the new defective pixel D (X = 19, Y = 2) in the next cycle.

  In T3, since the even-numbered data of the second line (even number line) matches the table information Ta at T3, the defect determining unit 16e asserts the defective pixel matching information HIT_AE. When the defective pixel matching information HIT_AE is asserted, the address control unit 17e increments the address A0, and a new defective pixel (X = *, Y = *) is read in the next cycle. In addition, since the odd-numbered data of the second line (even number line) matches the table information Tb at T3, the defect determination unit 16o asserts the defective pixel match information HIT_BO. When the defective pixel match information HIT_BO is asserted, the address control unit 17o increments the address B1, and the table information Tb of the new defective pixel (X = *, Y = *) is read in the next cycle.

  In T4, since the even-numbered data of the third line (odd line) matches the table information Ta at T4, the defect determination unit 16e asserts the defective pixel match information HIT_AE. When the defective pixel matching information HIT_AE is asserted, the address control unit 17e increments the address A1, and the table information Ta of the new defective pixel (X = 12, Y = 3) is read in the next cycle.

  The pixel inspection unit 10 asserts the defective pixel matching information HIT_BO because the odd-numbered data of the third line (odd line) matches the table information Tb at T5. When the defective pixel match information HIT_BO is asserted, the address control unit 17o increments the address B0, and the table information Tb of the new defective pixel (X = 20, Y = 3) is read in the next cycle.

  In T6, since the even-numbered data of the third line (odd line) matches the table information Ta at T6, the defect determination unit 16e asserts the defective pixel match information HIT_AE. When the defective pixel matching information HIT_AE is asserted, the address control unit 17e increments the address A1, and the table information Tb of the new defective pixel (X = *, Y = *) is read in the next cycle.

  In T7, since the even-numbered data of the third line (odd line) matches the table information Tb at T7, the defect determination unit 16e asserts the defective pixel match information HIT_BE. When the defective pixel matching information HIT_BE is asserted, the address control unit 17o increments the address B0, and a table Ta of new defective pixels (X = *, Y = *) is read in the next cycle.

  When the pixel inspection unit 10 sequentially repeats the above-described operation process and processes up to the final pixel of the final line, the detection process ends.

  Further, when the processing mode is 2-line parallel processing, the pixel inspection unit 10 performs operation processing as illustrated in FIGS. 9 and 10 to detect defective pixels appropriately and at high speed.

  In the two-line parallel processing mode, the pixel inspection unit 10 has the processing mode “0” and the selectors Sa0, Sa1, Sb0, and Sb1 are fixed during the period of one frame, as indicated by a thick arrow in FIG. The The pixel inspection unit 10 provides the selector Sa2 with the defective pixel coordinate information of the even-numbered odd-numbered defect table Teo as the table information Ta0 and the defective pixel coordinate information of the even-numbered even-numbered defect table Tee as the table information Ta1. Is entered. Further, the pixel inspection unit 10 supplies the selector Sb2 with the defective pixel coordinate information of the odd-numbered even-numbered defect table Toe as the table information Tb0 and the defective pixel of the odd-numbered odd-numbered defect table Too as the table information Tb1. Coordinate information is input.

  In the two-line parallel processing mode, the pixel inspection unit 10 switches the outputs of the selectors Sa2 and Sb2 every time a defective pixel is detected by the table switching control signals Ste and Sto. Accordingly, the selector Sa2 switches and outputs the defective pixel coordinate information tables Tao and Ta1 of the even line defect tables Teo and Tee as the table information Ta every time defective pixel detection is performed. Similarly, the selector Sb2 switches and outputs the defective pixel coordinate information tables Tb0 and Tb1 of the odd line defect tables Tee and Too for each defective pixel detection as the table information Tb.

  The defect determination units 16e and 16o detect defective pixels with reference to both table information Ta that is defect information of even lines and table information Tb that is defect information of odd lines.

  That is, the pixel inspection unit 10 detects defective pixels at the operation timing shown in FIG. 10 in the two-line parallel processing mode.

  The selector Sa2 switches the defective pixel coordinate information tables Tao and Ta1 for each defective pixel detection by the table switching control signal Ste from the table switching unit 15e, and outputs it as table information Ta. The selector Sb2 switches the defective pixel coordinate information tables Tb0 and Tb1 for each defective pixel detection by the table switching control signal Sto from the table switching unit 15o, and outputs the table information Tb. In FIG. 10, in the defective pixel coordinate information tables Ta0, Ta1, Tb0, and Tb1, a hatched period is a non-selection period, and a non-hatched period is a selection period.

  In FIG. 10, since the pixel inspection unit 10 matches the table information Tb of the defective pixel E (X = 2, Y = 3) at T1, the defect determination unit 16o asserts the defective pixel matching information HIT_BO at T1. To do. When the defective pixel matching information HIT_BO is asserted, the address control unit 17o increments the address B1 because the table switching control signal Sto is “1”. Further, the table switching unit 15o switches the table switching control signal Sto from “1” to “0” because the defect is detected in the odd-numbered data.

  In the pixel inspection unit 10, since the even-numbered data matches the table information Ta at T2, the defect determination unit 16e asserts the defective pixel matching information HIT_AE. When the defective pixel matching information HIT_AE is asserted, the address control unit 17e increments the address A0 because the table switching control signal Ste is “0”. Further, the table switching unit 15e switches the table switching control signal Ste from “0” to “1” because a defect is detected in the even-numbered data.

  In the pixel inspection unit 10, since the even-numbered data matches the table information Tb at T3, the defect determination unit 16o asserts the defective pixel match information HIT_BO. When the defective pixel matching information HIT_BO is asserted, the address control unit 17o increments the address B0 because the table switching control signal Sto is “0”. The table switching unit 15o switches the table switching control signal Sto from “0” to “1” because a defect is detected in the odd-numbered data.

  In the pixel inspection unit 10, since the even-numbered data matches the table information Ta at T4, the defect determination unit 16e asserts the defective pixel matching information HIT_AE. When the defective pixel matching information HIT_AE is asserted, the address control unit 17e increments the address A1 because the table switching control signal Ste is “1”. Further, the table switching unit 15e switches the table switching control signal Ste from “1” to “0” because the defect is detected in the even data. In addition, since the pixel inspection unit 10 matches the odd-numbered data with the table information Tb at T4, the defect determination unit 16o asserts the defective pixel matching information HIT_BO. When the defective pixel matching information HIT_BO is asserted, the address control unit 17o increments the address B1 because the table switching control signal Sto is “1”. Further, the table switching unit 15o switches the table switching control signal Sto from “1” to “0” because the defect is detected in the odd-numbered data.

  In the pixel inspection unit 10, since the even-numbered data matches the table information Ta at T5, the defect determination unit 16e asserts the defective pixel matching information HIT_AE. When the defective pixel matching information HIT_AE is asserted, the address control unit 17e increments the address A0 because the table switching control signal Ste is “0”. Further, the table switching unit 15e switches the table switching control signal Ste from “0” to “1” because a defect is detected in the even-numbered data.

  In the pixel inspection unit 10, since the even-numbered data matches the table information Ta at T6, the defect determination unit 16e asserts the defective pixel match information HIT_AE. When the defective pixel matching information HIT_AE is asserted, the address control unit 17e increments the address A1 because the table switching control signal Ste is “1”. The table switching unit 15e switches the table switching control signal Ste from “1” to “0” because a defect is detected in the even-numbered data.

  In the pixel inspection unit 10, since the odd-numbered data matches the table information Tb at T7, the defect determination unit 16o asserts the defective pixel matching information HIT_BO. When the defective pixel matching information HIT_BO is asserted, the address control unit 17o increments the address B0 because the table switching control signal Sto is “0”. The table switching unit 15o switches the table switching control signal Sto from “0” to “1” because a defect is detected in the odd-numbered data.

  As described above, when the processing mode is the two-pixel parallel processing mode, the pixel inspecting unit 10 according to the present exemplary embodiment has an even-numbered even-numbered defect table Tee and an even-numbered odd-numbered defective pixel table during even-numbered line processing. Two tables of Teo are read to detect defective pixels. In addition, during the odd line processing, the pixel inspection unit 10 reads out two tables of the odd line even number defect table Toe and the odd line odd number defect table Too, and performs defective pixel detection.

  Furthermore, when the processing mode is the two-line parallel processing mode, the pixel inspection unit 10 reads two tables of the even-numbered even-numbered defect table Tee and the even-numbered odd-numbered defect table Teo at the time of even-numbered line processing. To detect defective pixels. In addition, during the odd line processing, the pixel inspection unit 10 reads out two tables of the odd line even number defect table Toe and the odd line odd number defect table Too, and performs defective pixel detection.

  Therefore, the pixel inspection unit 10 can appropriately and quickly perform the defect pixel detection processing mode without rewriting the defect pixel coordinate information to the defect tables Teo, Too, Tee, and Toe depending on the processing mode. Detection of defective pixels can be performed.

  Further, the pixel inspection unit 10 uses the defective pixel table setting unit 13 and the defective pixel table distribution unit 14 to convert defective pixel coordinates stored in the defective pixel coordinate information storage unit 12 at the time of shipment of the image processing apparatus 1. The table Teo, Too, Tee, and Toe are distributed and registered.

  Therefore, the coordinate information of the defective pixel can be automatically distributed and registered in the defect tables Teo, Too, Tee, and Toe, and the processing performance can be improved.

  Further, in the pixel inspection unit 10, the defective pixel correction unit 18e and the defective pixel correction unit 18o are based on the defective pixel determination result signal SE and the defective pixel determination result signal SO that are the determination results of the defect determination unit 16e and the defect determination unit 16o. Thus, the input pixel which is a defective pixel is corrected. An appropriate correction method can be used as the correction method for the defective pixel.

  Therefore, it is possible to improve image quality by correcting defective pixels detected appropriately and at high speed.

  As described above, the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment is configured so that pixels of image data having a predetermined number of lines with a predetermined number of pixels as one line in the main scanning direction are orthogonal to the main scanning direction. A pixel inspection device that detects whether or not the input pixel is a defective pixel, and is input as an input pixel continuously from the reference pixel with the first pixel in the main scanning direction of the head line in the scanning direction as a reference pixel. The even-numbered odd-numbered defect pixel table 21eo (Teo) in which the even-numbered odd-numbered defective pixel coordinates of the even-numbered lines are registered, and the odd-numbered number of defective pixel coordinates of the odd-numbered lines in the main-scanning direction are registered. Odd-numbered odd-numbered defect table 21oo (Too), even-numbered even-numbered defect table 21ee (Tee) in which even-numbered even-numbered defective pixel coordinates of the even-numbered line are registered, The odd-numbered even-numbered defect table 21oe (Toe) in which the even-numbered defective pixel coordinates of several lines in the main scanning direction are registered, and the odd-numbered odd-numbered defect table 21oo based on the respective read addresses The defective pixel detection process mode and table of the defective pixel coordinates read from the even line even number defect table 21ee and the defective pixel coordinates read from the odd line even number defect table 21oe. An even-side defective pixel coordinate switching unit (even-side defective pixel coordinate switching means) 22e that switches according to the even-side table switching signal as the switching control signal Ste and outputs the even-side defective pixel coordinates as the table information Ta, respectively. Based on the read address, the odd number line odd number defect table 21oo or the even number The defective pixel detection processing mode and table switching between the defective pixel coordinates read from the in-even-numbered defect table 21ee and the defective pixel coordinates read from the even-numbered odd-numbered defect table 21eo An odd-side defective pixel coordinate switching unit (odd-side defective pixel coordinate switching means) 22o that switches according to an odd-side table switching signal as the control signal Sto and outputs the odd-side defective pixel coordinates as the table information Tb, and the input pixel A coordinate detection unit (coordinate detection means) 23 for detecting coordinates in the main scanning direction and the sub-scanning direction, and the detected coordinates detected by the coordinate detection unit 23 and the even-numbered defective pixel coordinates are compared and detected. Even pixel defect determining unit (even pixel defect determining means) 2 which is a defect determining unit 16e for determining whether or not the input pixel of the coordinates is a defective pixel. 4e is a defect determination unit 16o that compares the detected coordinates detected by the coordinate detection unit 23 with the odd-numbered defective pixel coordinates to determine whether or not the input pixel of the detected coordinates is a defective pixel. A pixel defect determination unit (odd pixel defect determination unit) 24o and the determination result of the even pixel defect determination unit 24e and the even-side table switching signal corresponding to the detected coordinates are output to the even-numbered defective pixel coordinate switching unit 22e. An even-side table switching unit (even-side table switching means) 25e, which is a table switching unit 15e, and the odd-side defective pixel coordinates corresponding to the determination result of the odd-numbered pixel defect determination 24o and the odd-numbered table switching signal according to the detected coordinates. An odd-numbered table switching unit (odd-side table switching means) 25o that is a table switching unit 15o to be output to the switching unit 22o, and the even-numbered pixel defect determination unit 24e; An address control unit (address control means) 26 which is an address control unit 17e, 17o that outputs a read address to each of the tables 21eo, 21oo, 21ee, 21oe based on the determination result of the odd pixel defect determination unit 24o. ing.

  Therefore, the pixel inspection unit 10 can appropriately and quickly perform the defect pixel detection processing mode without rewriting the defect pixel coordinate information to the defect tables Teo, Too, Tee, and Toe depending on the processing mode. Detection of defective pixels can be performed.

  In addition, the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment is configured so that pixels of image data having a predetermined number of lines with a predetermined number of pixels as one line in the main scanning direction are orthogonal to the main scanning direction. Executed by a pixel inspection apparatus that performs detection processing as to whether or not the input pixel is a defective pixel, with the first pixel in the main scanning direction of the first line as a reference pixel, as input pixels continuously input from the reference pixel An even line odd-numbered defect table registration processing step for registering even-numbered odd-numbered defective pixel coordinates of even-numbered lines in the even-numbered line odd-numbered defect table 21eo (Teo), Odd-numbered odd-numbered defect table registration step for registering odd-numbered defective pixel coordinates in the main scanning direction of the line in the odd-numbered odd-numbered odd-numbered defect table 21oo (Too); Even-numbered line even-numbered defect pixel coordinates are registered in the even-numbered line even-numbered defect table 21ee (Tee), and even-numbered line even-numbered defect table registration processing step, Odd line even-numbered defect table registration processing step for registering the defective pixel coordinates of the eyes in the odd-numbered even-numbered defect table 21 oe (Toe), and the odd-numbered odd-numbered defect table based on the respective read addresses 21oo or the defective pixel coordinates read from the even-numbered even-numbered defect table 21ee and the defective pixel coordinates read from the odd-numbered even-numbered defect table 21oe are used to detect the defective pixels. Switch according to the even-side table switching signal as the mode and table switching control signal Ste The even-numbered defective pixel coordinate switching process step which is output as the even-numbered defective pixel coordinates as the table information Ta, and the odd-numbered odd-numbered defect table 21oo or the even-numbered even-numbered defect table based on the respective read addresses The defective pixel coordinates read from 21ee and the defective pixel coordinates read from the even-numbered odd-numbered defect table 21eo are set to the odd-numbered side as the defective pixel detection processing mode and the table switching control signal Sto. Odd-numbered defective pixel coordinate switching processing step for switching according to a table switching signal and outputting as odd-numbered defective pixel coordinates; coordinate detection processing step for detecting coordinates of the input pixel in the main scanning direction and the sub-scanning direction; Detection coordinates detected in the coordinate detection processing step and the even-side defect pixel coordinates The even pixel defect determination processing step for determining whether or not the input pixel of the detected coordinate is a defective pixel, and the detected coordinate detected in the coordinate detection processing step and the odd-numbered defective pixel coordinate In comparison, the odd-numbered pixel defect determination processing step for determining whether or not the input pixel of the detected coordinate is a defective pixel, the determination result in the even-numbered pixel defect determination processing step, and the even-numbered side according to the detected coordinate An even-side table switching processing step for outputting a table switching signal to the even-numbered defective pixel coordinate switching processing step; a determination result in the odd-numbered pixel defect determining processing step; and the odd-side table switching signal according to the detected coordinates. Odd side table switching processing step for output to odd side defective pixel coordinate switching processing step, the even pixel defect determining processing step, and the odd pixel missing step An address control processing step of outputting a read address to the respective tables based on the judging result of the judging process step, performing a pixel inspection method having.

  Therefore, the pixel inspection unit 10 can appropriately and quickly perform the defect pixel detection processing mode without rewriting the defect pixel coordinate information to the defect tables Teo, Too, Tee, and Toe depending on the processing mode. Detection of defective pixels can be performed.

  Further, the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment is configured so that pixels of image data having a predetermined number of lines with a predetermined number of pixels as one line in the main scanning direction are orthogonal to the main scanning direction. Mounted in a pixel inspection apparatus that detects whether or not the input pixel is a defective pixel and is input as an input pixel continuously from the reference pixel, with the first pixel in the main scanning direction of the first line as a reference pixel An even-numbered line odd-numbered defect table registration process for registering an even-numbered number of odd-numbered defective pixel coordinates in an even-numbered line odd-numbered defect table 21eo (Teo) in a control processor; Odd line odd-numbered defect table registration processing for registering odd-numbered defective pixel coordinates of odd-numbered lines in the odd-numbered odd-numbered defect table 21oo (Too). The even-numbered even-numbered defect table registration process for registering the even-numbered defective pixel coordinates of the even-numbered lines in the even-numbered even-numbered defect table 21ee (Tee) and the even-numbered odd-numbered lines in the main scanning direction. Odd line even-numbered defect table registration processing for registering eye defective pixel coordinates in the odd-numbered line even-numbered defect table 21oe (Toe), and the odd-numbered odd-numbered defect table 21oo based on the respective read addresses. Alternatively, the defective pixel coordinates read from the even-numbered even-numbered defect table 21ee and the defective pixel coordinates read from the odd-numbered even-numbered defect table 21oe are used as the defective pixel detection processing mode. The table information T is switched according to the even-side table switching signal as the table switching control signal Ste. The even-numbered defective pixel coordinate switching process for outputting the even-numbered defective pixel coordinates and the odd-numbered line odd-numbered defect table 21oo or the even-numbered line even-numbered defect table 21ee based on the respective read addresses. The defective pixel coordinates and the defective pixel coordinates read from the even-numbered odd-numbered defect table 21eo are used as an odd-side table switching signal as the defective pixel detection processing mode and the table switching control signal Sto. Detected by the odd-numbered defective pixel coordinate switching process for switching according to the odd-numbered defective pixel coordinates, the coordinate detection process for detecting the coordinates of the input pixel in the main scanning direction and the sub-scanning direction, and the coordinate detection process. The detected coordinates and the even-numbered defective pixel coordinates are compared, and the input pixel of the detected coordinates is a defective pixel. Whether or not the input pixel of the detected coordinate is a defective pixel by comparing the detected coordinate detected by the even-numbered pixel defect determining process and the detected coordinate detected by the coordinate detecting process with the odd-numbered defective pixel coordinate Odd-numbered pixel defect determination processing for determining whether or not, even-numbered table switching for outputting the even-numbered table switching signal according to the determination result in the even-numbered pixel defect determination processing and the detected coordinates to the even-numbered defective pixel coordinate switching processing Odd number table switching processing for outputting the odd number side table switching signal to the odd number side defective pixel coordinate switching processing, and the even number pixel defect determination. And a program for executing an address control process for outputting a read address to each table based on a determination result in the odd pixel defect determination process.

  Therefore, the pixel inspection unit 10 can appropriately and quickly perform the defect pixel detection processing mode without rewriting the defect pixel coordinate information to the defect tables Teo, Too, Tee, and Toe depending on the processing mode. Detection of defective pixels can be performed.

  In addition, the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment includes the even-numbered odd-numbered defect table 21eo (Teo), the odd-numbered odd-numbered defect table 21oo (Too), and the even-numbered even-numbered line. The eye defect table 21ee (Tee) and the odd-numbered even-numbered defect table 21oe (Toe) are stored in each storage unit or one storage unit.

  Therefore, defective pixel coordinate information can be quickly read out from the defect tables 21eo, 21oo, 21ee, and 21oe to perform defective pixel detection processing. As a result, even when the defective pixel detection processing mode is different, the defective pixel can be detected more appropriately and at high speed.

  Further, in the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment, the address control unit 26 includes an address input switching unit (address input switching unit) 26a, and the even-numbered odd-numbered defect table 21eo and the The odd-numbered even-numbered defect table 21 oe directly outputs the read address, and the address input switching unit 26 a determines the input destination of the read address according to the detection processing mode. The defect table 21oo and the even-numbered even-numbered defect table 21ee are switched to each other.

  Accordingly, the defective pixel coordinate information is read from each defect table 21eo, 21oo, 21ee, 21oe by switching the read address of each defect table 21eo, 21oo, 21ee, 21oe promptly and appropriately, and a defective pixel detection process is performed. be able to. As a result, even when the defective pixel detection processing mode is different, the defective pixel can be detected more appropriately and at high speed.

  In the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment, the processing mode is the same as the two-line parallel processing mode in which two pixels at the same position in the main scanning direction of two consecutive lines are processed in parallel. And a two-pixel parallel processing mode in which two pixels that are continuous in the main scanning direction in a line are processed in parallel.

  Therefore, even when the processing mode is switched between the two-pixel parallel processing mode and the two-line parallel processing mode, the processing mode does not rewrite defective pixel coordinate information to the defect tables Teo, Too, Tee, and Toe. In addition, defective pixels can be detected at high speed.

  Furthermore, in the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment, the even-numbered table switching unit 25e and the odd-numbered table switching unit 25o have the even number when the processing mode is the two-pixel parallel processing mode. The even-side table switching signal and the odd-side table switching signal for switching the side defective pixel coordinates and the odd-side defective pixel coordinates are switched in line units.

  Therefore, in the two-pixel parallel processing mode, the defect table Teo, Too, Tee, and Toe can be switched in units of lines to read out defective pixel coordinates, and defective pixels can be detected appropriately and at high speed.

  Further, the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment uses the even-numbered line odd-numbered defect table 21eo (Teo) and the odd-numbered line odd-numbered defect table 21oo (Too) as the coordinates of the defective pixels. ), And a coordinate registration unit (coordinate registration means) 27 for sorting and registering the even-numbered even-numbered defect table 21ee (Tee) and the odd-numbered even-numbered defect table 21oe (Toe).

  Accordingly, the defective pixel coordinate information can be automatically registered by being quickly and accurately distributed to each of the defect tables Teo, Too, Tee, and Toe. As a result, processing optimization and processing speed can be improved.

  Further, the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment corrects a defective pixel (correction unit) that corrects the defective pixel determined by the even pixel defect determination unit 24e and the odd pixel defect determination unit 24o as a defective pixel. ) 28 is further provided.

  Therefore, the input defective pixel can be corrected appropriately and promptly, and the image quality of the processed image can be improved.

  In addition, the pixel inspection unit 10 of the image processing apparatus 1 according to the present embodiment includes the even-numbered odd-numbered defect table 21eo (Teo), the odd-numbered odd-numbered defect table 21oo (Too), and the even-numbered even-numbered line. The eye defect table 21ee (Tee) and the odd-numbered even-numbered defect table 21oe (Toe) also store information on the correction method by the correction unit 28.

  Therefore, the correction according to the correction method intended by the user and the state of the defective pixel can be performed, and the usability can be improved and the image quality of the processed image can be improved.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 10 Pixel inspection part 11 Counter part 12 Defective pixel coordinate information storage part 13 Defective pixel table setting part 14 Defective pixel table distribution part Sa1, Sb1 Selector Teo Even line odd number odd number table Too odd number odd number Defect table Tee Even line even number defect table Toe Odd line even number defect table Sa0, Sb0 selector Sa2, Sb2 selector 15e, 15o Table switching unit 16e, 16o Defect determining unit 17e, 17o Address control unit 18e, 18o Defective pixel correction unit 21eo Even line odd number defect table 21oo Odd line odd number defect table 21ee Even line even number defect table 21oe Odd line even number defect table 22e Even number side defective pixel coordinate switching section 2o Odd-side defective pixel coordinate switching unit 23 Coordinate detection unit 24e Even-numbered pixel defect determination unit 24o Odd-numbered pixel defect determination unit 25e Even-side table switching unit 25o Odd-side table switching unit 26 Address control unit 26a Address input switching unit 27 Coordinate registration unit 28 Correction unit

Japanese Patent No. 4582768

Claims (11)

A pixel of image data having a predetermined number of lines with a predetermined number of pixels in the main scanning direction as one line is determined by using the first pixel in the main scanning direction of the first line in the sub-scanning direction orthogonal to the main scanning direction as the reference pixel A pixel inspection device that is continuously input from a pixel as an input pixel and performs a detection process as to whether or not the input pixel is a defective pixel,
An even-numbered odd-numbered defect table in which odd-numbered defective pixel coordinates of even-numbered lines are registered;
An odd-numbered odd-numbered defect table in which odd-numbered defective pixel coordinates of odd-numbered lines are registered;
Even-numbered line even-numbered defect table in which even-numbered defective pixel coordinates of even-numbered lines in the main scanning direction are registered;
An odd-numbered even-numbered defect table in which even-numbered defective pixel coordinates of odd-numbered lines are registered;
Based on the respective read addresses, the defective pixel coordinates read from the odd-numbered line odd-numbered defect table or the even-numbered line even-numbered defect table and the odd-numbered line even-numbered defect table were read out. The defective pixel coordinate switching means for switching the defective pixel coordinate according to the detection processing mode of the defective pixel and the even-side table switching signal and outputting as the even-side defective pixel coordinate;
The defect pixel coordinates read from the odd line odd number defect table or the even line even number defect table and the even line odd number defect table are read based on the respective read addresses. Odd side defective pixel coordinate switching means for switching the defective pixel coordinates according to the defective pixel detection processing mode and the odd side table switching signal to output as odd side defective pixel coordinates;
Coordinate detection means for detecting coordinates of the input pixel in the main scanning direction and the sub-scanning direction;
Even pixel defect determining means for comparing the detected coordinates detected by the coordinate detecting means with the even-numbered defective pixel coordinates to determine whether the input pixel of the detected coordinates is a defective pixel;
An odd pixel defect determining means for comparing the detected coordinates detected by the coordinate detecting means with the odd-numbered defective pixel coordinates and determining whether or not the input pixel of the detected coordinates is a defective pixel;
An even-side table switching unit that outputs the even-side table switching signal according to the determination result of the even-numbered pixel defect determining unit and the detected coordinates to the even-side defective pixel coordinate switching unit;
Odd-numbered table switching means for outputting the odd-numbered side table switching signal corresponding to the determination result of the odd-numbered pixel defect determining means and the detected coordinates to the odd-numbered defective pixel coordinate switching means;
Address control means for outputting a read address to each table based on the determination results of the even pixel defect determination means and the odd pixel defect determination means;
A pixel inspection apparatus comprising: The even line odd number defect table, the odd line odd number defect table, the even line even number defect table, and the odd line even number defect table are:
2. The pixel inspection apparatus according to claim 1, wherein the pixel inspection apparatus is stored in each storage unit or one storage unit. The address control means includes
With address input switching means,
For the even line odd number defect table and the odd line even number defect table, the read address is directly output,
The address input switching means is
2. The input destination of the read address is switched between the odd-numbered line odd-numbered defect table and the even-numbered line even-numbered defect table according to the detection processing mode. Item 3. The pixel inspection device according to Item 2. The processing mode is:
Two-line parallel processing mode for processing two pixels at the same position in the main scanning direction on two consecutive lines in parallel, and two-pixel parallel processing mode for processing two pixels on the same line in the main scanning direction in parallel The pixel inspection apparatus according to claim 1, wherein: The even-numbered table switching means and the odd-numbered table switching means are
When the processing mode is the two-pixel parallel processing mode, the even-side table switching signal and the odd-side table switching signal for switching the even-side defective pixel coordinates and the odd-side defective pixel coordinates are switched in line units. 5. The pixel inspection apparatus according to claim 4, wherein The pixel inspection device includes:
The coordinates of the defective pixels are distributed and registered in the even-numbered line odd-numbered defect table, the odd-numbered line odd-numbered defect table, the even-numbered line even-numbered defect table, and the odd-numbered line even-numbered defect table. Coordinate registration means to
The pixel inspection apparatus according to claim 1, further comprising: The pixel inspection device includes:
Correction means for correcting defective pixels determined by the even pixel defect determination means and the odd pixel defect determination means as defective pixels,
The pixel inspection apparatus according to claim 1, further comprising: The even line odd number defect table, the odd line odd number defect table, the even line even number defect table, and the odd line even number defect table are:
The pixel inspection apparatus according to claim 7, wherein information on a correction method by the correction unit is also stored. An image processing apparatus that performs image processing based on image data output by an imaging unit and includes a pixel inspection unit that inspects defective pixels of the image data,
An image processing apparatus comprising the pixel inspection device according to claim 1 as the pixel inspection unit. A pixel of image data having a predetermined number of lines with a predetermined number of pixels in the main scanning direction as one line is determined by using the first pixel in the main scanning direction of the first line in the sub-scanning direction orthogonal to the main scanning direction as the reference pixel A pixel inspection method that is executed by a pixel inspection device that is continuously input from a pixel as an input pixel and performs a detection process as to whether or not the input pixel is a defective pixel,
Even-numbered odd-numbered defect pixel registration for registering even-numbered odd-numbered defective pixel coordinates in the even-numbered line odd-numbered defect table in the main scanning direction;
Odd-numbered odd-numbered defect pixel coordinates for registering odd-numbered defective pixel coordinates in the main scanning direction of odd-numbered lines to the odd-numbered odd-numbered defect table;
Even-numbered line even-numbered defect table registration processing step for registering even-numbered even-numbered defective pixel coordinates in the even-numbered line even-numbered defect table;
Odd line even-numbered defect table registration processing step for registering even-numbered defective pixel coordinates of odd-numbered lines in the odd-numbered even-numbered defect table;
Based on the respective read addresses, the defective pixel coordinates read from the odd-numbered line odd-numbered defect table or the even-numbered line even-numbered defect table and the odd-numbered line even-numbered defect table were read out. The defective pixel coordinate switching processing step for switching the defective pixel coordinates according to the defective pixel detection processing mode and the even number side table switching signal to output as the even number side defective pixel coordinates;
The defect pixel coordinates read from the odd line odd number defect table or the even line even number defect table and the even line odd number defect table are read based on the respective read addresses. Odd-side defective pixel coordinate switching processing step for switching the defective pixel coordinates according to the defective pixel detection processing mode and the odd-side table switching signal and outputting them as odd-side defective pixel coordinates;
A coordinate detection processing step of detecting coordinates in the main scanning direction and the sub-scanning direction of the input pixel;
An even-numbered pixel defect determination processing step for comparing the detected coordinates detected in the coordinate detection processing step with the even-numbered side defective pixel coordinates to determine whether the input pixel of the detected coordinates is a defective pixel;
Comparing the detected coordinates detected in the coordinate detection processing step with the odd-numbered defective pixel coordinates and determining whether or not the input pixel of the detected coordinates is a defective pixel; and
An even-side table switching processing step for outputting the even-side table switching signal corresponding to the determination result in the even-numbered pixel defect determination processing step and the detected coordinates to the even-numbered side defective pixel coordinate switching processing step;
An odd-side table switching processing step of outputting the determination result in the odd-numbered pixel defect determination processing step and the odd-numbered table switching signal corresponding to the detected coordinates to the odd-numbered defective pixel coordinate switching processing step;
An address control processing step for outputting a read address to each table based on determination results in the even pixel defect determination processing step and the odd pixel defect determination processing step;
A pixel inspection method characterized by comprising: A pixel of image data having a predetermined number of lines with a predetermined number of pixels in the main scanning direction as one line is determined by using the first pixel in the main scanning direction of the first line in the sub-scanning direction orthogonal to the main scanning direction as the reference pixel A program installed in a pixel inspection apparatus that is continuously input from a pixel as an input pixel and performs a detection process as to whether or not the input pixel is a defective pixel,
To the control processor,
Even-numbered odd-numbered defect table registration processing for registering odd-numbered defective pixel coordinates of even-numbered lines in an even-numbered odd-numbered defect table;
Odd line odd-numbered defect table registration processing for registering odd-numbered defective pixel coordinates of odd-numbered lines in an odd-numbered odd-numbered defect table,
Even-numbered line even-numbered defect table registration processing for registering even-numbered line even-numbered defective pixel coordinates in the even-numbered line even-numbered defect table;
Odd-numbered even-numbered defect table registration processing for registering even-numbered defective pixel coordinates of odd-numbered lines in an odd-numbered even-numbered defect table;
Based on the respective read addresses, the defective pixel coordinates read from the odd-numbered line odd-numbered defect table or the even-numbered line even-numbered defect table and the odd-numbered line even-numbered defect table were read out. The defective pixel coordinate switching process for switching the defective pixel coordinate according to the detection process mode of the defective pixel and the even-side table switching signal and outputting as the even-side defective pixel coordinate;
The defect pixel coordinates read from the odd line odd number defect table or the even line even number defect table and the even line odd number defect table are read based on the respective read addresses. The defective pixel coordinates are switched according to the defective pixel detection processing mode and the odd-side table switching signal and output as odd-side defective pixel coordinates and output as odd-side defective pixel coordinates,
A coordinate detection process for detecting coordinates in the main scanning direction and the sub-scanning direction of the input pixels;
An even pixel defect determination process that compares the detected coordinates detected in the coordinate detection process with the even-numbered defective pixel coordinates and determines whether the input pixel of the detected coordinates is a defective pixel;
An odd pixel defect determination process that compares the detected coordinates detected in the coordinate detection process with the odd-numbered defective pixel coordinates and determines whether the input pixel of the detected coordinates is a defective pixel;
An even-side table switching process of outputting the even-side table switching signal corresponding to the determination result in the even-numbered pixel defect determination process and the detected coordinates to the even-side defective pixel coordinate switching process;
An odd-side table switching process for outputting the determination result in the odd-numbered pixel defect determination process and the odd-side table switching signal according to the detected coordinates to the odd-numbered defective pixel coordinate switching process;
An address control process for outputting a read address to each table based on determination results in the even pixel defect determination process and the odd pixel defect determination process;
A program characterized by having executed.

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