JP2017069352A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2017069352A
JP2017069352A JP2015192319A JP2015192319A JP2017069352A JP 2017069352 A JP2017069352 A JP 2017069352A JP 2015192319 A JP2015192319 A JP 2015192319A JP 2015192319 A JP2015192319 A JP 2015192319A JP 2017069352 A JP2017069352 A JP 2017069352A
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Prior art keywords
lead terminal
lead
heat
semiconductor chip
heat sink
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JP2015192319A
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Japanese (ja)
Inventor
博之 荻野
Hiroyuki Ogino
博之 荻野
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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Priority to JP2015192319A priority Critical patent/JP2017069352A/en
Priority to CN201620122033.8U priority patent/CN205564736U/en
Publication of JP2017069352A publication Critical patent/JP2017069352A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves improved resin adhesion and improved heat dissipation property and high reliability.SOLUTION: A semiconductor device of the present embodiment comprises: a first heat sink and a second heat sink; first lead terminals, a second lead terminal, third lead terminals and a fourth lead terminal; a first semiconductor chip mounted on a principal surface of the first heat sink and a second semiconductor chip mounted on a principal surface of the second heat sink; and a mold material which covers the heat sinks, the lead terminals and the semiconductor chips, in which the first lead terminals and the second lead terminals, and the third lead terminals and the fourth lead terminals are led out from a pair of lateral faces of the mold material in opposite directions, respectively. The fourth lead terminal is coupled to the second heat sink, and the fourth lead terminal has a plurality of through holes piercing the fourth lead terminal in a thickness direction on the second heat sink side, and a position between the through holes is wire bonded.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置に関し、特にパワー半導体チップとコントロール半導体チップがリードフレーム上に搭載され、モールド材で樹脂封止された半導体装置に関する。
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a power semiconductor chip and a control semiconductor chip are mounted on a lead frame and sealed with a molding material.

大電流のスイッチングや整流を行うパワー半導体チップ（整流用ダイオード、パワーＭＯＳＦＥＴ、ＩＧＢＴ等）は、動作中での発熱量が大きい。このため、パワー半導体チップを樹脂封止材中に内蔵した半導体装置では、高い放熱効率が要求されている。
A power semiconductor chip (such as a rectifier diode, a power MOSFET, or an IGBT) that performs switching and rectification of a large current generates a large amount of heat during operation. For this reason, in a semiconductor device in which a power semiconductor chip is built in a resin sealing material, high heat dissipation efficiency is required.

例えば、特許文献１には、パワー半導体モジュールにおいて、放熱板とリード端子とから構成されるリードフレームが使用され、この放熱板の上にパワー半導体チップが搭載される。また、樹脂から成るモールド材で樹脂封止され、パッケージ化した構造が開示されている。
For example, Patent Document 1 uses a lead frame including a heat sink and lead terminals in a power semiconductor module, and a power semiconductor chip is mounted on the heat sink. Further, a package structure in which a resin is sealed with a molding material made of resin and packaged is disclosed.

リードフレームは、熱伝導率の高い銅等で形成されている。また、リードフレームの一部を構成するリード端子がモールド材から突出した形態とされる。パワー半導体チップの電極は、電気信号の入出力端子を構成する各リードにボンディングワイヤ等を用いて接続される。パワー半導体チップは、外部から各リードに印加された電圧によって動作する。この構成のパワー半導体モジュールは、プリント基板中に形成されたスルーホールに各リードが挿入されてはんだ付けされることによって使用される。
The lead frame is made of copper having a high thermal conductivity. Further, the lead terminals constituting a part of the lead frame are projected from the mold material. The electrodes of the power semiconductor chip are connected to the respective leads constituting the input / output terminals for electrical signals using bonding wires or the like. The power semiconductor chip operates by a voltage applied to each lead from the outside. The power semiconductor module having this configuration is used by inserting each lead into a through hole formed in a printed circuit board and soldering.

特許４９８５８０９号公報Japanese Patent No. 4985809

一般的に、モールド材を構成するモールド材の熱伝導率は、リードフレームと比較すると高くはない。このため、放熱効率を高めるためには、パワー半導体チップからの発熱を、リードフレームを介して外部に放出することが重要となる。
Generally, the thermal conductivity of the molding material constituting the molding material is not high compared to the lead frame. For this reason, in order to improve the heat dissipation efficiency, it is important to release the heat generated from the power semiconductor chip to the outside through the lead frame.

しかしながら、従来技術は、放熱板の延伸部からも放熱する観点はよいが、大電流のスイッチングや整流を行うパワー半導体チップの動作中での発熱量が大きいため、熱応力でリードフレームとモールド材（封止樹脂）が剥離し、ワイヤボンディングが剥がれるという課題がある。
However, the conventional technology has a good point of view of heat dissipation from the extended part of the heat sink, but the heat generated during operation of the power semiconductor chip that performs switching and rectification of a large current is large. There is a problem that (sealing resin) is peeled off and wire bonding is peeled off.

従って、本発明は、上述した課題を解決するためになされたものであり、樹脂密着性とワイヤボンディング性を向上させた高信頼性の半導体装置を提供することを目的とする。
Accordingly, the present invention has been made to solve the above-described problems, and an object thereof is to provide a highly reliable semiconductor device with improved resin adhesion and wire bonding properties.


上述の課題を解決するために、本発明は、以下に掲げる構成とした。
本発明の半導体装置は、第１の放熱板と第２の放熱板と、第１の側面の側に配置された第１のリード端子と第２のリード端子と、第２の側面の側に配置された第３のリード端子と第２の側面の側において第３のリード端子よりも第２の放熱板に近い側に配置された第４のリード端子と、第１の放熱板の主面に搭載された第１の半導体チップと第２の放熱板の主面に搭載された第２の半導体チップと、それらを被覆するモールド材とを備え、第１のリード端子及び第２のリード端子と、第３のリード端子及び第４のリード端子とが、それぞれモールド材における１対の側面からそれぞれ反対方向に導出された構成であって、第４リード端子は第２の放熱板に連結され、第４のリード端子の第２の放熱板側において、第４のリード端子の厚さ方向に向かって貫通する小径の貫通孔を複数備え、小径の貫通孔の間にワイヤボンディングしていることを特徴とする。
In order to solve the above-described problems, the present invention has the following configurations.
The semiconductor device according to the present invention includes a first heat radiating plate, a second heat radiating plate, a first lead terminal disposed on the first side surface side, a second lead terminal, and a second side surface side. The fourth lead terminal disposed on the side closer to the second heat sink than the third lead terminal on the side of the third lead terminal disposed on the second side and the main surface of the first heat sink A first semiconductor chip mounted on the first semiconductor chip, a second semiconductor chip mounted on the main surface of the second heat radiation plate, and a molding material covering them, a first lead terminal and a second lead terminal And the third lead terminal and the fourth lead terminal are respectively led out in opposite directions from a pair of side surfaces of the molding material, and the fourth lead terminal is connected to the second heat radiating plate. The thickness direction of the fourth lead terminal on the second heat sink side of the fourth lead terminal A plurality of small-diameter through hole toward the through, characterized in that in wire bonding between the small-diameter through-hole.

本発明は、以上のように構成されているので、樹脂密着性とワイヤボンディング性が向上した高信頼性の半導体装置を提供することができる。
Since the present invention is configured as described above, a highly reliable semiconductor device having improved resin adhesion and wire bonding can be provided.

本発明の実施例１に係る半導体装置の内観構造を示す平面図である。It is a top view which shows the interior structure of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の外観構造を示す平面図及び側面図である。It is the top view and side view which show the external appearance structure of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置のリードフレーム構造を示す平面図である。It is a top view which shows the lead frame structure of the semiconductor device which concerns on Example 1 of this invention.

以下、本発明を実施するための形態について、図を参照して詳細に説明する。ただし、本発明は以下の記載に何ら限定されるものではない。
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description.

本発明の実施例１に係る半導体装置１を説明する。図１は、半導体装置１の内観構造を示す平面図である。図２は、半導体装置１の外観構造を示す平面図及び側面図である。図３は、半導体装置１のリードフレーム構造を示す平面図である。
A semiconductor device 1 according to Example 1 of the invention will be described. FIG. 1 is a plan view showing the interior structure of the semiconductor device 1. FIG. 2 is a plan view and a side view showing the external structure of the semiconductor device 1. FIG. 3 is a plan view showing a lead frame structure of the semiconductor device 1.

図１に示すように、半導体装置１は、リードフレーム２と半導体チップ３１、３２とワイヤ４とモールド材５で構成されている。
As shown in FIG. 1, the semiconductor device 1 includes a lead frame 2, semiconductor chips 31 and 32, wires 4 and a molding material 5.

ここでは、パワー半導体チップと制御用ＩＣチップが、リードフレーム のそれぞれ独立した放熱板上に搭載され、複数のリード端子と組み合わせた形態となった組立体である。これがモールド材で樹脂封止された形態の半導体装置となる。
In this example, the power semiconductor chip and the control IC chip are mounted on independent heat sinks of the lead frame and combined with a plurality of lead terminals. This is a semiconductor device in the form of resin sealing with a molding material.

図２に示すように、半導体装置１は、モールド材５から導出されたリード端子にリードフォーミングが施され、各リード端子はその先端部がプリント基板上のスルーホールに挿入され、プリント基板にはんだ付けによって固定されるＤＩＰ型パッケージである。
As shown in FIG. 2, in the semiconductor device 1, lead forming is performed on the lead terminals derived from the molding material 5, and the lead terminals of the lead terminals are inserted into through holes on the printed circuit board, and soldered to the printed circuit board. It is a DIP type package fixed by attaching.

図３に示すように、リードフレーム２は、放熱板とリード端子からなっている。放熱板は、第１の放熱板２１と、第１の放熱板２１と互いに離間して配置された第２の放熱板２２からなっている。第１の放熱板２１の一部が第２の放熱板２２側へ延伸している。これにより面積が大きく放熱が良好である。
As shown in FIG. 3, the lead frame 2 includes a heat sink and lead terminals. The heat radiating plate includes a first heat radiating plate 21 and a second heat radiating plate 22 that is disposed away from the first heat radiating plate 21. A part of the first heat radiating plate 21 extends toward the second heat radiating plate 22. As a result, the area is large and the heat dissipation is good.

リード端子は、第１の放熱板２１における第１の側面(一方の側面：図１中では右側面）に沿って第１のリード端子２３が配置されている。また、第１の放熱板２１における第１の側面の反対側に位置する第２の側面（他方の側面：図１中では左側面）の側に、第２のリード端子２４と第２の放熱板２２に近い側に第３のリード端子２５と第４のリード端子２６が互いに並行して配置される。
The first lead terminal 23 is disposed along the first side surface (one side surface: the right side surface in FIG. 1) of the first heat radiation plate 21. Further, the second lead terminal 24 and the second heat radiation are disposed on the second side surface (the other side surface: the left side surface in FIG. 1) located on the opposite side of the first side surface of the first heat radiating plate 21. The third lead terminal 25 and the fourth lead terminal 26 are arranged in parallel to each other on the side close to the plate 22.

ここで用いられるリード端子は、その機能上区分される。第１の放熱板２１は、第１のリード端子２３の配列方向において、前記第１のリード端子２３の端部と連結され、第１のリード端子２３の第１の放熱板２１側において、第１のリード端子２３の厚さ方向に向かって貫通する貫通孔２７を備えている。また、第２のリード端子２４、第３のリード端子２５も同様に貫通孔２７を備えている。第４のリード端子２６は、第２の放熱板２２と連結され、ここは、貫通孔２８を複数備えている。
The lead terminals used here are classified according to their functions. The first heat radiating plate 21 is connected to the end portion of the first lead terminal 23 in the arrangement direction of the first lead terminals 23, and on the first heat radiating plate 21 side of the first lead terminal 23, One lead terminal 23 is provided with a through hole 27 penetrating in the thickness direction. Similarly, the second lead terminal 24 and the third lead terminal 25 are also provided with a through hole 27. The fourth lead terminal 26 is connected to the second heat radiating plate 22, and includes a plurality of through holes 28.

第１の放熱板２１の主面には第１の半導体チップ３１が搭載され、第２の放熱板２２の主面には第２の半導体チップ３２が搭載される。
A first semiconductor chip 31 is mounted on the main surface of the first heat sink 21, and a second semiconductor chip 32 is mounted on the main surface of the second heat sink 22.

例えば、第１の半導体チップ３１はパワー半導体チップであり、第２の半導体チップ３２の制御用ＩＣチップである。第１の半導体チップ３１のパワー半導体チップは、第２の半導体チップ３２の制御用ＩＣチップと比較して大きな発熱が生じるので、パワー半導体チップの発した熱が伝達して制御用ＩＣチップの温度が上昇し性能が劣化しないよう放熱板が２つに分割されている。かつ、その放熱効果を高くするために、第１の放熱板２１の一部が第２の放熱板２２側へ延伸して、面積が大きくなっている。
For example, the first semiconductor chip 31 is a power semiconductor chip, and is a control IC chip for the second semiconductor chip 32. Since the power semiconductor chip of the first semiconductor chip 31 generates a large amount of heat as compared with the control IC chip of the second semiconductor chip 32, the heat generated by the power semiconductor chip is transmitted to the temperature of the control IC chip. The heat sink is divided into two parts so that the temperature does not deteriorate and the performance is not deteriorated. And in order to make the heat dissipation effect high, a part of 1st heat sink 21 is extended to the 2nd heat sink 22 side, and the area is large.

第１の放熱板２１及び第２の放熱板２２は、所望の機械的強度と放熱効果が得られる厚さの銅又は銅合金、鉄または鉄合金、アルミニウムまたはアルミニウム合金等で構成される。また、第１の放熱板２１及び第２の放熱板２２を、各リード端子２３〜２６よりも厚くすることも可能である。具体的には第１の放熱板３１及び第２の放熱板３２は０．２５ｍｍから１．０ｍｍ、リード端子２３〜２６は０．２５ｍｍから０．７５ｍｍで構成されることが好ましい。銅又は銅合金、鉄または鉄合金、アルミニウムまたはアルミニウム合金等は、モールド材を構成するエポキシ樹脂等と比べて充分に高い熱伝導率をもつため、パワー半導体チップ３１が動作時に発する熱は、放熱板を介し、さらに連結されたリード端子から放熱させることができる。
The first heat radiating plate 21 and the second heat radiating plate 22 are made of copper or a copper alloy, iron or an iron alloy, aluminum or an aluminum alloy having a thickness that can obtain a desired mechanical strength and a heat radiating effect. Moreover, it is also possible to make the 1st heat sink 21 and the 2nd heat sink 22 thicker than each lead terminal 23-26. Specifically, the first heat radiating plate 31 and the second heat radiating plate 32 are preferably configured from 0.25 mm to 1.0 mm, and the lead terminals 23 to 26 are configured from 0.25 mm to 0.75 mm. Since copper or copper alloy, iron or iron alloy, aluminum or aluminum alloy, etc. have sufficiently high thermal conductivity compared to epoxy resin or the like constituting the molding material, heat generated by the power semiconductor chip 31 during operation is radiated. Heat can be dissipated from the connected lead terminals via the plate.

ここで、第１の半導体チップ３１は、パワー半導体チップであり、整流用ダイオード、パワーＭＯＳＦＥＴ、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等、高電圧が印加され、大電流が流されてスイッチング動作をおこなう半導体素子である。第１の半導体チップ３１の一方の主面は導電性接着材（図示せず）を介して第１の放熱板２１に電気的機械的に接続されている。例えば、ドレイン電極であり、第１のリード端子２３に電気的に接続されている。 他方の主面には、複数のボンディングパッド（図示せず）が設けられている。
Here, the first semiconductor chip 31 is a power semiconductor chip, such as a rectifier diode, a power MOSFET, and an IGBT (Insulated Gate Bipolar Transistor), which is applied with a high voltage and a large current flows to perform a switching operation. It is an element. One main surface of the first semiconductor chip 31 is electrically and mechanically connected to the first heat sink 21 via a conductive adhesive (not shown). For example, it is a drain electrode and is electrically connected to the first lead terminal 23. A plurality of bonding pads (not shown) are provided on the other main surface.

第２の半導体チップ３２は、パワー半導体チップの制御を行う制御用ＩＣチップである。他方の主面には、第１の半導体チップ３１と同様に複数のボンディングパッド（図示せず）が設けられている。
The second semiconductor chip 32 is a control IC chip that controls the power semiconductor chip. Similar to the first semiconductor chip 31, a plurality of bonding pads (not shown) are provided on the other main surface.

第１の半導体チップ３１、第２の半導体チップ３２への電気的接続は、これらの上面に形成されたボンディングパッドと各リード端子にボンディングワイヤ４を接続することによって行われる。接続箇所は機能によって選択することができる。
Electrical connection to the first semiconductor chip 31 and the second semiconductor chip 32 is performed by connecting bonding wires 4 to the bonding pads formed on the upper surfaces of these and the lead terminals. The connection location can be selected depending on the function.

例えば、パワー半導体チップ（３１）のソース電極と第３のリード端子２５との間、パワー半導体チップ（３１）のゲート電極と制御用ＩＣチップ（３２）のボンディングバッドとの間がボンディングワイヤ４を用いて電気的に接続されている。また、制御用ＩＣチップ（３２）のボンディングバッドと第３のリード端子２５の間もボンディングワイヤ４を用いて電気的に接続されている。
For example, the bonding wire 4 is connected between the source electrode of the power semiconductor chip (31) and the third lead terminal 25, and between the gate electrode of the power semiconductor chip (31) and the bonding pad of the control IC chip (32). Electrically connected. The bonding pad of the control IC chip (32) and the third lead terminal 25 are also electrically connected using the bonding wire 4.

さらに、制御用ＩＣチップ（３２）のボンディングバッドと第４のリード端子２６との間もボンディングワイヤ４を用いて電気的に接続されている。ここでは、第４のリード端子２６は、第２の放熱板２２と連結され、連結部強度の関係から、孔径の小さい貫通孔２８を複数備えている。この孔間にワイヤボンディングしている。
Further, the bonding pad of the control IC chip (32) and the fourth lead terminal 26 are also electrically connected using the bonding wire 4. Here, the 4th lead terminal 26 is connected with the 2nd heat sink 22, and is provided with two or more through-holes 28 with a small hole diameter from the relationship of connection part intensity | strength. Wire bonding is performed between the holes.

製造方法としては、リードフレーム上に半導体チップを搭載し、必要箇所をワイヤボンディングで配線し、樹脂成形後、個片に切断するものである。これは通常、半導体装置において知られる製造方法で可能である。
As a manufacturing method, a semiconductor chip is mounted on a lead frame, necessary portions are wired by wire bonding, and after resin molding, cut into individual pieces. This is usually possible with manufacturing methods known in semiconductor devices.

効果としては、第１の放熱板２１は、第１のリード端子２３の配列方向において、延伸部を設け前記第１のリード端子２３の端部と連結されている。これにより、第１の半導体チップ３１（パワー半導体チップ）から発する熱の放熱は、第１の放熱板２１とリード端子２３を介して外部に効率よく放出することができる。
As an effect, the first heat radiating plate 21 is connected to the end portion of the first lead terminal 23 by providing an extending portion in the arrangement direction of the first lead terminals 23. Thereby, the heat radiated from the first semiconductor chip 31 (power semiconductor chip) can be efficiently discharged to the outside through the first heat radiating plate 21 and the lead terminals 23.

また、第１のリード端子２３の第１の放熱板２１側において、第１のリード端子２３の厚さ方向に向かって貫通する貫通孔２７を備えている。これにより、第１の半導体チップ３１（パワー半導体チップ）から発する熱の温度上昇で、リードフレーム２（放熱板２１、リード端子２３）とモールド材５とが膨張差を生じても、樹脂剥離の発生を防止することができる。
Further, the first lead terminal 23 is provided with a through hole 27 penetrating in the thickness direction of the first lead terminal 23 on the first heat dissipation plate 21 side. Thereby, even if the lead frame 2 (the heat radiation plate 21 and the lead terminal 23) and the molding material 5 cause a difference in expansion due to the temperature rise of the heat generated from the first semiconductor chip 31 (power semiconductor chip), the resin is peeled off. Occurrence can be prevented.

このため、パワー半導体チップ３１からの過渡的な放熱等を第１の放熱板２１によって良好に吸収しても、モールド材５との膨張差による剥離を生じることがなく、発熱を外部に良好に放出することができる。また、第１の放熱板２１に連結された第１のリード端子２３は、モールド材の外部に延伸しており、パワー半導体チップ３１からの発熱を外部に導出する機能を有する。
For this reason, even if transient heat dissipation from the power semiconductor chip 31 is satisfactorily absorbed by the first heat dissipation plate 21, exfoliation due to a difference in expansion from the mold material 5 does not occur, and heat generation is excellent outside. Can be released. The first lead terminal 23 connected to the first heat radiating plate 21 extends to the outside of the molding material, and has a function of deriving heat generated from the power semiconductor chip 31 to the outside.

また、樹脂密着性の強固な部位である貫通孔２７、２８を備え、貫通孔２８近傍（孔間）にワイヤボンディングを接続しているので、ワイヤボンディング剥離の発生を防止することができる。よって、ワイヤボンディング性を向上させた高信頼性の半導体装置とすることができる。
Moreover, since the through-holes 27 and 28 which are strong resin adhesive portions are provided and the wire bonding is connected in the vicinity of the through-holes 28 (between the holes), the occurrence of peeling of the wire bonding can be prevented. Thus, a highly reliable semiconductor device with improved wire bonding can be obtained.

上述のように、本発明を実施するための形態を記載したが、この開示から当業者には様々な代替実施の形態、実施例が可能であることが明らかになるはずである。
As described above, the mode for carrying out the present invention has been described. From this disclosure, it should be apparent to those skilled in the art that various alternative embodiments and examples are possible.

図２の構成では、リード端子の構成を左右対称とし、右側面において４本のリード端子を設けたが、半導体装置の機能により、左右で異なる本数のリード端子を設けた非対称の構成とすることもできる。
In the configuration of FIG. 2, the configuration of the lead terminals is bilaterally symmetric and four lead terminals are provided on the right side. However, depending on the function of the semiconductor device, an asymmetric configuration in which different numbers of lead terminals are provided on the left and right sides is used. You can also.

また、各放熱板にパワー半導体チップ、制御用ＩＣチップをそれぞれ搭載するとしたが、これら以外のチップも同時に各放熱板に搭載することができる。この場合には、動作時の発熱量の大きなチップを第１の放熱板に、発熱量の小さなチップを第２の放熱板に搭載することが好ましい。
In addition, although the power semiconductor chip and the control IC chip are mounted on each heat sink, other chips can be mounted on each heat sink at the same time. In this case, it is preferable to mount a chip having a large heat generation amount during operation on the first heat radiating plate and a chip having a small heat generation amount on the second heat radiating plate.

また、放熱板の厚さは、リード端子の厚さより厚くてもよい。これにより放熱性を向上させることができる。また、厚くした部位をモールド材の裏面に放熱板が露出した形態とすることもできる。この場合、裏面の放熱板自身もプリント基板にはんだ付けされて使用されることもある。
Moreover, the thickness of the heat sink may be thicker than the thickness of the lead terminal. Thereby, heat dissipation can be improved. Further, the thickened portion may be in a form in which the heat sink is exposed on the back surface of the mold material. In this case, the heat sink on the back surface itself may be used by being soldered to the printed circuit board.

また、貫通孔の形状は丸に限らず、四角であってもよく、複数備えてもよい。面積や製造容易な形状に対応することができる。リード端子をモールド材が貫通するような形状であれば、同様の効果を奏する。
The shape of the through hole is not limited to a circle, and may be a square or a plurality of through holes. It can correspond to an area or a shape that is easy to manufacture. The same effect can be obtained if the shape allows the molding material to penetrate the lead terminal.

また、制御用ＩＣチップ中には、その温度を測定する温度センサを形成してもよい。温度センサは、パワー半導体チップの温度を電気的に感知し、制御回路に出力し、異常時はパワー半導体チップの動作を制御するように機能する。これにより、半導体装置１の過熱による誤動作を防止できる。
A temperature sensor for measuring the temperature may be formed in the control IC chip. The temperature sensor electrically senses the temperature of the power semiconductor chip, outputs it to the control circuit, and functions to control the operation of the power semiconductor chip when there is an abnormality. Thereby, malfunction due to overheating of the semiconductor device 1 can be prevented.

１、半導体装置
２、リードフレーム
２１、第１の放熱板
２２、第２の放熱板
２３、第１のリード端子
２４、第２のリード端子
２５、第３のリード端子
２６、第４のリード端子
２７、２８、貫通孔
３１、第１の半導体チップ
３２、第２の半導体チップ
４、ボンディングワイヤ
５、モールド材 DESCRIPTION OF SYMBOLS 1, Semiconductor device 2, Lead frame 21, 1st heat sink 22, 2nd heat sink 23, 1st lead terminal 24, 2nd lead terminal 25, 3rd lead terminal 26, 4th lead terminal 27, 28, through-hole 31, first semiconductor chip 32, second semiconductor chip 4, bonding wire 5, molding material

Claims (3)

第１の放熱板と、前記第１の放熱板と離間して配置された第２の放熱板と、前記第１の放熱板における第１の側面の側に配置された複数の第１のリード端子と、前記第２の放熱板における第１の側面の側に配置された複数の第２のリード端子と、前記第１の放熱板における前記第１の側面の反対側に位置する第２の側面の側に配置された第３のリード端子と、前記第２の側面の側において前記第３のリード端子よりも前記第２の放熱板に近い側に配置された第４のリード端子と、前記第１の放熱板の主面に搭載された第１の半導体チップと、前記第２の放熱板の主面に搭載された第２の半導体チップと、前記第１の放熱板、前記第２の放熱板、前記第１のリード端子の一部、前記第２のリード端子の一部、前記第３のリード端子の一部、前記第４のリード端子の一部、前記第１の半導体チップ、及び前記第２の半導体チップを被覆するモールド材を備え、前記第１のリード端子及び前記第２のリード端子と、前記第３のリード端子及び前記第４のリード端子とが、それぞれ前記モールド材における１対の側面からそれぞれ反対方向に導出された半導体装置であって、前記第４のリード端子は前記第２の放熱板に連結され、前記第４のリード端子の前記第２の放熱板側において、前記第４のリード端子の厚さ方向に向かって貫通する小径の貫通孔を複数備え、前記小径の貫通孔の間にワイヤボンディングしていることを特徴とする半導体装置。
A first heat dissipating plate, a second heat dissipating plate disposed away from the first heat dissipating plate, and a plurality of first leads disposed on a first side surface of the first heat dissipating plate. A terminal, a plurality of second lead terminals disposed on the first side surface of the second heat radiating plate, and a second position located on the opposite side of the first side surface of the first heat radiating plate. A third lead terminal disposed on the side surface side, and a fourth lead terminal disposed on the second side surface side closer to the second heat dissipation plate than the third lead terminal; A first semiconductor chip mounted on a main surface of the first heat dissipation plate; a second semiconductor chip mounted on a main surface of the second heat dissipation plate; the first heat dissipation plate; A heat sink, a part of the first lead terminal, a part of the second lead terminal, a part of the third lead terminal, 4, including a molding material covering a part of the lead terminals, the first semiconductor chip, and the second semiconductor chip, the first lead terminal, the second lead terminal, and the third lead The terminal and the fourth lead terminal are each a semiconductor device led out in opposite directions from a pair of side surfaces of the molding material, and the fourth lead terminal is connected to the second heat sink. A plurality of small-diameter through holes penetrating in the thickness direction of the fourth lead terminal on the second heat dissipation plate side of the fourth lead terminal, and wire bonding between the small-diameter through holes A semiconductor device characterized by that.
前記第１の半導体チップは、裏面側に一方の主電極、上面側に他方の主電極をそれぞれ有し、前記一方の主電極は前記第１の放熱板と電気的に接続されたパワー半導体チップであり、前記複数の第１のリード端子は、前記第１の放熱板に連結されて前記一方の主電極の取り出し電極とされ、前記第２の半導体チップは制御用ＩＣチップであることを特徴とする請求項１に記載の半導体装置。
The first semiconductor chip has one main electrode on the back surface side and the other main electrode on the upper surface side, and the one main electrode is electrically connected to the first heat radiating plate. The plurality of first lead terminals are connected to the first heat radiation plate to serve as extraction electrodes of the one main electrode, and the second semiconductor chip is a control IC chip. The semiconductor device according to claim 1.
前記第１の放熱板は、前記第１のリード端子、前記第２のリード端子、前記第３のリード端子、及び前記第４のリード端子より厚く形成されていることを特徴とする請求項１又は２に記載の半導体装置。   2. The first heat radiating plate is formed thicker than the first lead terminal, the second lead terminal, the third lead terminal, and the fourth lead terminal. Or the semiconductor device of 2.
JP2015192319A 2015-09-29 2015-09-29 Semiconductor device Pending JP2017069352A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113661567A (en) * 2019-03-11 2021-11-16 株式会社电装 Semiconductor device with a plurality of semiconductor chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113661567A (en) * 2019-03-11 2021-11-16 株式会社电装 Semiconductor device with a plurality of semiconductor chips
CN113661567B (en) * 2019-03-11 2024-01-05 株式会社电装 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

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