JP2017063356A - Frequency multiplier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a function capable of compensating the fluctuation in the frequency of a reference frequency signal by regulating a number of multiplication even if the reference frequency signal frequency fluctuates owing to manufacturing variations or temperature fluctuations.SOLUTION: A frequency multiplier circuit comprises: a subtracter 13; a loop filter 52; a digital-to-analog converter (DAC) 75; a voltage control type oscillator (VCO) 76; a counter 77; and a register 54. The subtracter subtracts, from a multiplication number 10, an output value of the register which uses a reference frequency signal as a clock, and inputs a result of the subtraction to the loop filter. The digital-to-analog converter converts a digital output of the loop filter into an analog value. The analog value is input to the voltage control type oscillator. The counter counts up the number of waves of an oscillation output signal of the voltage control type oscillator. The output of the counter is reset to "0" by the register. The number of waves of the output of the voltage control type oscillator in one cycle of the reference frequency signal is counted. The average of values thus counted is made to match with the multiplication number.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a frequency multiplication circuit capable of multiplying a reference frequency signal not only by an integer but also by a real number having a numerical value of a decimal point or less.

  Chapter 15 Section 5 of “Design and application of analog CMOS integrated circuit” describes a general frequency multiplier. FIG. 1 shows a general phase-locked (PLL) type frequency multiplier. The circuit comprises a phase comparator 13, a charge pump 14, a low-pass filter 15, an n divider 17, and a voltage controlled oscillator (VCO) 16. For these components, the reference frequency signal and the output of the n divider are input to the phase comparison, and the phase comparator compares the difference between the rising edges of the waveform of the reference frequency signal and the output signal of the n divider for the phase comparison. A pulse having a difference length is generated. This pulse waveform is input to the charge pump, converted into a current by the charge pump, charges and discharges the capacitance in the filter, and smoothes the filter output voltage. This smoothed voltage is input to the control voltage input terminal of the VCO, and an oscillation waveform having a frequency corresponding to the control voltage is output as a VCO output. Further, this oscillation waveform is input to the n divider, and the 1 / n frequency of the VCO oscillation waveform becomes the frequency divider output, which is input to the phase comparator.

  FIG. 2 shows a timing chart of output signals of the respective constituent circuits of the circuit of FIG. The VCO output is divided by an n divider to obtain a rectangular wave with a frequency of 1 / n. FIG. 2 shows an example of n = 4. A difference (phase difference) between the rise time of the frequency divider output and the reference frequency signal waveform is detected by a phase detector, and a pulse waveform in which only the difference in the rise time is high is generated by the charge pump. This pulse waveform is smoothed by a low-pass filter to obtain a VCO control voltage. The circuit in FIG. 1 is a negative feedback control circuit, and is controlled so that the difference between the rise time of the waveform of the divider output and the reference frequency signal becomes zero. Since the rising edges of the waveform of the frequency divider output and the reference frequency signal match, the period of the waveform of the frequency divider output and the reference frequency signal matches, and the frequency of the frequency divider output and the reference frequency signal match. For this reason, the frequency of the VCO output, which is the input of the frequency divider, is multiplied by n times the reference frequency signal. However, this circuit can only multiply the frequency by the frequency division number of the frequency divider. Further, since the frequency divider operates at the rising or falling edge of the input waveform, it can operate only in the time of one cycle of the VCO output, and therefore the frequency dividing number n can be realized only as an integer.

  On the other hand, a fractional frequency division PLL frequency multiplier that can multiply not only integers but also numbers less than a decimal point is "Frequency-divided PLL in a variable frequency divider using a ΔΣ modulator." Proposed by ECT-15-032 etc. on March 5, 2015. Figure 3 shows this circuit. In this circuit, the n frequency dividing circuit of the above-mentioned PLL type frequency multiplying circuit is a variable frequency divider 32 that can vary the n frequency dividing and the n + 1 frequency dividing by the control signal 31. For example, when n is set to 5, dividing by 5 is performed 4 times, then dividing by 6 is performed once, and by repeating this, dividing by 5.2 can be realized on average. As a result, real numbers including decimal numbers can be multiplied by the frequency multiplication circuit shown in FIG. However, if one period of the reference frequency signal is Tref, one period of the VCO output in the period of 5 division is Tref / 5, and one period of the VCO output in the period of 6 division is Tref / 6. Since one ideal period of VCO divided by 5.2 is Tref / 5.2, the rise time of each VCO output waveform of the fractional frequency division PLL frequency multiplier is the rise time of each ideal VCO output waveform. In contrast, a phase error occurs.

  Figure 4 shows the VCO output of the fractional frequency division PLL frequency multiplier when the frequency of the reference frequency signal is 80 kHz, n = 12, and n and n + 1 are 1: 1 and the frequency division is 12.5. It is a spectrum figure of a simulation result. The frequency of the VCO output is 1 MHz, which is 12.5 times the frequency of the reference frequency signal 80 kHz, but the frequency of 80 kHz of the reference frequency signal is multiplied by 0.5, which is the fractional part of the multiplication factor, every 40 kHz. The phase noise called is generated. In addition, when the multiplication number is a small value such as 12.01, the 12 frequency division is performed 99 times and the 13 frequency division is performed once, so that the fractional spurious occurs at 800 Hz under the same conditions as in FIG. Thus, the frequency difference between the multiplied frequency of the VCO output and the fractional spurious becomes small, and the cutoff frequency of the low-pass filter 15 needs to be sufficiently reduced in order to suppress this fractional spurious. In this case, it is necessary to increase the element values of the constituent elements of the filter. In the case of IC, the filter cannot be on-chip, and in order to sufficiently suppress spurious generated every 800 Hz, the filter time constant must be increased. In other words, there is a disadvantage that the phase synchronization time becomes long.

  The present invention requires that the element value of the constituent elements of the filter be increased when the fractional number of the conventional fractional frequency division PLL type frequency multiplication circuit is a small value. In the case of an IC, the filter cannot be on-chip. This solves the drawback that the time of phase synchronization becomes longer due to the increase of the time constant. Further, even if the frequency of the reference frequency signal fluctuates due to manufacturing variations or temperature fluctuations, a function capable of compensating for these fluctuations by adjusting the multiplication number is provided.

  In the conventional frequency multiplication circuit, frequency division was performed using a frequency divider and a phase synchronization function inserted in the feedback loop of the PLL, but the present invention uses the principle of a nose shaping D / A converter or a ΔΣ modulator. Frequency multiplication is performed by synchronizing.

FIG. 5 is a configuration example of a ΔΣ D / A converter which is an example of a noise shaping DAC which is the basis of the present invention. The input signal 50 is a digital signal of about 16 bits to 24 bits, and the subtracter 55 subtracts the register output from the input signal and inputs it to the loop filter. In a delta-sigma modulator, the loop filter generally has a discrete integral characteristic 1 / (1-z ^-1 ) characteristic of the nth power. The loop filter output is a signal having the same number of bits as the input signal. The output of this loop filter is input to a quantizer, and a digital value of about 16 bits to 24 bits or more is converted into a low bit signal 57 of about 1 bit to 4 bits. The low bit signal is input to the low bit DAC and input to the register. The register latches and outputs the input by the sampling clock. At this time, if the input signal 50 is X, the low bit signal 57 of Y is Y, and the rounding error (quantization noise) when quantizing is Q, Y is expressed by the following z function.

Y = X + (1−z ^-1 ) n ・ Q (1)
(1−z ⁻¹ ) n is an n-th order differential characteristic, and the attenuation becomes larger in the low frequency region. Since Q is quantization noise and has a uniform amount of power in all frequency regions, Y has a characteristic that the quantization noise becomes smaller in the low frequency region as shown in FIG. From this, it can be seen that when the input signal is low frequency or direct current, the signal obtained by removing high frequency quantization noise from the low bit signal matches the input signal.

  FIG. 7 shows a conceptual configuration of the present invention. The quantizer of the ΔΣ D / A converter shown in FIG. 5 is replaced with a DAC 75, a VCO 76, and a counter 77. The input signal is a multiplication number and is a binary number expressed in a fixed point, and the multiplication output signal is a VCO output. Here, the loop filter output is converted to an analog value by the DAC and becomes a VCO frequency control signal. A signal having a frequency corresponding to the voltage value of the frequency control signal is output from the VCO. The counter counts the wave number of the VCO output signal within one sampling period and outputs an integer number of counts. Here, the number of bits of the DAC input is a large number of bits of about 10 bits to 16 bits, and the counter output becomes an integer value near the multiplication number, so the number of bits is small. This is exactly the same operation as the quantizer described in FIG. Therefore, in this configuration circuit, the average value of the counter output is equal to the input multiplication number.

  DAC output voltage value Vcont, VCO center oscillation frequency Fcent, VCO gain Gfv, reference frequency signal frequency Fsamp, multiplication factor FDW, VCO output frequency Fvco, counter output value Ncount, generated by counter reset If the truncation error is Q, the following formula is established.

Fvco = Fcent + Vcont ・ Gfv (2)
Ncount + Q = Fvco / Fsamp (3)
Since the output value of the subtracter 83 is controlled to 0 by the action of the negative feedback loop of this circuit,
FDW = Ncount (4)
It becomes. from now on,
Fvco = FDW ・ Fsamp + Q ・ Fsamp (5)
It becomes. Since the error Q is random noise, the long-term average is 0,
Fvco = FDW ・ Fsamp (6)
It becomes. For Vcont
Vcont = (FDW ・ Fsamp−Fcent) / Gfv (7)
Is obtained.
From this, the VCO output becomes the frequency multiplied by the frequency multiplication factor of the reference frequency signal, and the VCO control voltage (Vcont) is the VCO oscillation frequency multiplied by the frequency multiplication factor of the reference frequency signal from the center oscillation frequency. It can be seen that the voltage value is shifted to the frequency. In this case, since the multiplication number can be about 16 bits to 24 bits, it is possible to set a multiplication number of about 5 digits after the decimal point. When a reference frequency signal is used as the sampling signal, a frequency multiplication circuit capable of multiplying the reference frequency signal by a multiplication number having a numerical value after the decimal point can be obtained.

  In the prior art, the phase of the reference frequency signal and the signal obtained by dividing the VCO output are synchronized and multiplied by the frequency. In the present invention, the frequency of the VCO output during one period of the reference frequency signal is adjusted by matching the frequency. Multiplication is performed, and the basic principle of multiplication is different from that of the prior art. For this reason, when the multiplication number is set to a real number including a value after the decimal point, the conventional technique generates a fractional spurious because it is realized by variable division of n division and n + 1 division. There is an advantage that no fractional spurious is generated in principle. In addition, in the prior art, the operation for phase comparison and synchronization is performed at the timing when the rising edges of the reference frequency signal and the signal obtained by dividing the VCO output match, but if the multiplication number includes a value after the decimal point, The operation for phase comparison and synchronization can be performed only at the timing of every k times the wavelength of the reference frequency signal by obtaining k such that k times becomes an integer. For this reason, depending on the set value of the multiplication number, k becomes a very large value, and phase synchronization becomes difficult. On the other hand, in the present invention, the frequency of the reference frequency signal and the signal obtained by dividing the VCO output coincide with each other so that the average value of the wave number of the VCO output during one period is made the same as the multiplication number by the noise shaping operation. It is possible to shorten the time required to do this, and in principle, the multiplication number can be any real number.

Conventional PLL frequency multiplier. The timing chart of the output waveform of each circuit of a PLL type frequency multiplier circuit. Fraction frequency division PLL type frequency multiplier. Spectrum of output waveform of fractional frequency division PLL type frequency multiplier. Configuration example of a ΔΣ D / A converter. The spectrum of the output signal of the ΔΣ D / A converter. The conceptual circuit diagram of the frequency multiplication circuit of this invention. The embodiment of claim 1. The embodiment of claim 2. The first embodiment of claim 3. The second embodiment of claim 3. The embodiment of claim 4. An example of a DC detection circuit. The first embodiment of claim 5. The twelfth embodiment of claim 5. The embodiment of claim 6.

FIG. 8 shows an embodiment of claim 1 of the present invention. The frequency multiplication circuit receives a multiplication number 80 that is a constant and a reference frequency signal 81 that is a reference signal, and a multiplication output signal 82 of the frequency multiplication circuit is a VCO 86 output. The output of the register 88 that operates using the reference frequency signal 81 as a latch clock from the multiplication number 80 is subtracted by the subtracter 83 and input to the loop filter. The loop filter is a digital filter or an integrator having a gain having an nth-order low-pass filter characteristic having a discrete integral characteristic 1 / (1-z ⁻¹ ) characteristic or gain. The digital output of this loop filter is converted into a voltage value or current value by a DAC (D / A converter), and this voltage value or current value is input to the control input of the VCO to control the oscillation frequency of the VCO. Further, the VCO output is input to the counter 87, and the wave number of the VCO output is counted. The counter output is input to the register 88 and latched at the rising or falling timing of the reference frequency signal 81, and the contents of the counter are reset to 0 at the same timing. Even if the DAC and VCO are replaced with digital value controlled oscillators (DCO), an equivalent circuit is obtained. Since this circuit is the same as the circuit shown in FIG. 7, the operation is the same as that described above if the DAC, VCO, and counter are handled as one block and handled as a quantizer.

  FIG. 9 shows an embodiment of claim 2 of the present invention. By reducing the noise of the control voltage input to the control input of the VCO by inserting the digital filter 90 at the DAC input and the analog filter 91 at the DAC output, the phase noise and jitter of the VCO output are reduced. It is. In this example, both a digital filter and an analog filter are inserted, but only one of them may be used. Either of them can achieve the effect of noise reduction.

FIG. 10 shows an embodiment of claim 3 of the present invention. A constant multiplication number 80 and a reference frequency signal 81 are input, and a VCO output is a multiplication output signal 82. The output of the multiplier 105 is subtracted from the constant 3 by the subtracter 83 and input to the loop filter. Constant 3 is 0, but other values are possible. The loop filter is a digital filter having an nth-order low-pass filter characteristic having a discrete integral characteristic 1 / (1-z ⁻¹ ) characteristic or gain. The constant 1 is added to the digital output of this loop filter by the adder 102, the addition result is converted to a voltage value or current value by a DAC (D / A converter), and this voltage value or current value is input to the control input of the VCO. The VCO oscillation frequency is controlled. Further, the VCO output is input to the counter 87, and the wave number of the VCO output is counted. The counter output is input to the register 88 and latched at the rising or falling timing of the reference frequency signal 81, and the counter contents are reset to 0 at the same timing. The multiplication number 80 is subtracted from the register output by the subtractor 104, and the output of the subtractor 104 is multiplied by the constant 2 by the multiplier 105 to be used as the subtraction input of the subtractor 83. Even if the DAC and VCO are replaced with digital value controlled oscillators (DCO), an equivalent circuit is obtained.

When constant 1 is C1, the following formula is obtained from the above formula (7).
Vcont + C1 = (FDW ・ Fsamp−Fcent) / Gfv (8)
If the value is set such that C1 = (FDW · Fsamp−Fcent) / Gfv, the average value of Vcont can be set to zero. Also,
FDW = Fvco / Fsamp
Therefore, from equation (3)
Ncount−FDW = Ncount−Fvco / Fsamp = -Q (9)
The result of subtracting the multiplication number from the register output multiplied by the constant 2 = C2 is
-Q / C2. Here, if C2 is a constant smaller than 1, the truncation error generated by resetting the counter among the values fed back to the subtracter 83 can be reduced, and the phase noise generated at the VCO output can be reduced.

  FIG. 11 shows an embodiment of claim 4 of the present invention. A second DAC 115 is provided, and the constant 1 is converted into an analog value by the second DAC and added by the adder 113 of the first DAC output and the analog value, and the addition result is used as the control voltage of the VCO. In both the first and second embodiments of the present invention, filters can be inserted before and after the DAC as in the second embodiment.

  FIG. 12 shows an embodiment of claim 4 of the present invention. This is a circuit obtained by adding a DC detection circuit 121 to the embodiment of claim 3 in FIG. The DC detection circuit is a circuit that detects the DC value of the output of the loop filter 84, adds a value such that the output of the loop filter 84 becomes 0, and inputs it to the DAC. FIG. 13 shows an example of a DC detection circuit that realizes this operation. The DC value of the loop filter output is extracted by a low-pass filter, this DC value is integrated by an integrator composed of an adder 133 and a register 132, and this integrated value is output. In the circuit of FIG. 12, this integrator output is negatively fed back via the VCO and counter, so the absolute value of the loop filter output is controlled to be small, and the integral value changes when the DC value of the loop filter output becomes zero. Disappear. As a result, the DC value of the loop filter output can be made zero.

FIG. 14 shows a first embodiment of claim 5 of the present invention. When the coefficient 141 is a1, the characteristic (transfer function) of the loop filter is the discrete integral characteristic 1 / (1-a1 · z ⁻¹ ), and the characteristic of the ΔΣ modulator is given. When the input is a small DC value near 0, the ΔΣ modulator causes an oscillation phenomenon called limit cycle oscillation and does not operate normally. At this time, if the coefficient 141 is set to a value larger than 1, limit cycle oscillation is suppressed and the circuit operates normally.

FIG. 15 shows a second embodiment of the fifth aspect of the present invention. A loop filter with two stages of discrete integrators connected in series is used as [1 / (1-a1 · z ^-1 )] ² and has the characteristics of a second-order ΔΣ modulator. The loop is stabilized by negatively feeding back the multiplier output to the first stage output. Even in this embodiment, when the input is a small DC value near 0, an oscillation phenomenon called limit cycle oscillation occurs and normal operation is not performed. At this time, if either the coefficient 141 or the coefficient 147 is set to a value larger than 1, limit cycle oscillation is suppressed and the circuit operates normally.

  FIG. 16 shows an embodiment of claim 6 of the present invention. Although claim 6 can be applied to all of claims 1 to 5, FIG. 16 is an example applied to FIG. 8 which is an embodiment of claim 1. The output of DAC 58 is input to filter 161, the output of filter 161 is input to the control input of VCO 162, and the output of VCO 162 is used as the output of the frequency multiplier circuit. At this time, the VCO 162 has the same characteristics as the VCO 86 and the filter has a low-pass filter characteristic with a low cut-off frequency. Noise can be removed and low phase noise characteristics can be obtained as the output of the frequency multiplier.

11: Reference frequency signal, 12: Multiplication output signal, 13: Phase detector, 14: Charge pump, 15: Low-pass filter, 16: Voltage controlled oscillator, 17: n divider,
31: Frequency division control signal, 32: n / n + 1 variable frequency divider,
50: Input signal, 51: Sampling clock, 52: Loop filter, 53: Quantizer, 54: Register, 56: Low bit DAC, 57: Low bit signal, 58: Analog output, 59: ΔΣ modulator,
75: DAC, 76: VCO, 77: Counter,
80: Multiplier, 81: Reference frequency signal, 82: Multiplier output signal, 83: Subtractor, 84: Loop filter, 85: DAC, 86: VCO, 87: Counter, 88: Register,
90: Digital filter, 91: Analog filter,
101: constant 1, 102: constant 2, 103: adder, 104: subtractor, 105: multiplier, 106: constant 3,
113: Adder, 115: DAC,
121: DC detection circuit,
130: Input, 131: Output, 132: Register, 133: Adder, 134: Low-pass filter, 135: Integrator
141: Coefficient 1, 142: Register, 143: Adder
144: subtractor, 145: register, 146: adder, 147: coefficient 2
161: Filter, 162: VCO

Claims (6)

A frequency multiplier circuit that outputs an output signal with a frequency obtained by multiplying the frequency of the reference frequency signal by an arbitrary real number. Subtracter, loop filter, digital analog converter (DAC), voltage controlled oscillator (VCO), counter, register With
The subtracter subtracts the output value of the register using a reference frequency signal as a clock from a multiplication number which is an arbitrary real number, inputs the subtraction value to the loop filter, and converts the digital output of the loop filter to the digital-to-analog conversion The analog value is converted by an analog-to-digital converter (DAC), and the analog value is input to the voltage-controlled oscillator (VCO). The oscillation output of the voltage-controlled oscillator (VCO) is used as an output signal. As an input, the wave number of the output signal is counted, the output of the counter is used as an input of the register, the output of the counter is reset to “0” by the reference frequency signal, and one cycle of the reference frequency signal is obtained. The frequency of the voltage controlled oscillator (VCO) output during the period is counted, and the average of the number of counts coincides with the multiplication number. Circuit. The frequency multiplier circuit according to claim 1, wherein
A frequency multiplying circuit having either or both of a digital filter and an analog filter on the input side of the digital-analog converter (DAC). The frequency multiplier circuit according to claim 1, wherein
A function of adding a first constant to an input value of the digital-analog converter (DAC), a function of subtracting a multiplication number from an output value of the register, Frequency multiplication circuit having a function of multiplying a value obtained by subtracting the multiplication number from the output value of the second constant by a second constant. The frequency multiplication circuit according to claim 3,
A frequency having a function of taking the output of the loop filter as an input, outputting a fourth constant such that an average value of the output of the loop filter is “0”, and adding it to the input value of the digital analog converter (DAC) Multiplier circuit. In the frequency multiplication circuit as described in any one of Claim 1 to 4,
When one or more integrators are included in the loop filter, a frequency multiplication circuit that prevents limit cycle oscillation by setting an integration coefficient of one or more of the integrators therein to a coefficient larger than one. In the frequency multiplication circuit as described in any one of Claim 1 to 5,
The filter and the voltage controlled oscillator (VCO) are added, the output of the digital-analog converter (DAC) is input to the added filter, and the output of the added filter is added to the voltage controlled oscillator (VCO) ), And the output of the added voltage controlled oscillator (VCO) is the output of the frequency multiplier.

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