JP2017063174A - Semiconductor device and power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an ON-resistance while suppressing reduction in withstanding voltage.SOLUTION: A semiconductor device 100 comprises a substrate 110, a first semiconductor layer 120, a second semiconductor layer 130, a third semiconductor layer 140, a trench 152, and an insulating film 160 that covers a surface of the trench. A carrier concentration of the first semiconductor layer forms a peak in a thickness direction orthogonal to a surface direction. A high-concentration carrier region 123 where the carrier concentration is at its peak, on the first semiconductor layer, extends in the surface direction at a position apart from the trench toward the substrate side.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a power conversion device.

  A vertical transistor having a trench gate structure in which a gate electrode is formed in a trench (groove) is known as a semiconductor device (semiconductor device, semiconductor element). Patent Document 1 discloses that a vertical transistor is provided with a current distribution layer at a depth where a trench exists between a drift layer and a channel layer for the purpose of reducing on-resistance. This current spreading layer has the same conductive characteristics as the drift layer and a higher carrier concentration than the drift layer.

JP 2009-194065 A

  According to the present inventor, in the technique of Patent Document 1, a depletion layer formed at a pn junction interface between a drift layer (n-type) and a channel layer (p-type) spreads in the current dispersion layer, thereby As a result, the on-resistance cannot be sufficiently reduced because the current distribution in the circuit is inhibited. Further, in the technique of Patent Document 1, for the purpose of suppressing the influence of the depletion layer, when the carrier concentration of the current dispersion layer is made higher, or when the thickness of the current dispersion layer is made thicker, Since the electric field tends to concentrate on the corners of the trench, there is a problem that the breakdown voltage decreases. Therefore, there has been a demand for a technique capable of reducing the on-resistance while suppressing a decrease in breakdown voltage in a vertical transistor having a trench gate structure.

  The present invention solves at least a part of the problems described above and can be realized as the following forms.

(1) One embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate extending in a plane direction; a first semiconductor layer located above the substrate and having one of n-type and p-type characteristics; and located on the first semiconductor layer. A second semiconductor layer having the other characteristic different from the one characteristic among n-type and p-type; and a third semiconductor layer located on the second semiconductor layer and having the one characteristic A trench penetrating from the third semiconductor layer to the first semiconductor layer and penetrating into the first semiconductor layer; and an insulating film covering a surface of the trench; The carrier concentration forms a peak in the thickness direction orthogonal to the plane direction, and the high concentration carrier region in which the carrier concentration reaches a peak in the first semiconductor layer is located at a position away from the trench toward the substrate side. Spread in the surface direction. According to this aspect, since the high concentration carrier region exists at a position away from the trench in the first semiconductor layer toward the substrate, it is formed at the pn junction interface between the first semiconductor layer and the second semiconductor layer. The influence of the depletion layer on the high concentration carrier region can be reduced. As a result, the current flowing into the first semiconductor layer via the channel formed in the second semiconductor layer is sufficiently supplied in the plane direction in the high concentration carrier region away from the trench in the first semiconductor layer toward the substrate. Can be dispersed. As a result, the on-resistance can be reduced while suppressing a decrease in breakdown voltage.

(2) In the semiconductor device described above, the carrier concentration in the high concentration carrier region may be 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less. According to this embodiment, a sufficient breakdown voltage can be ensured while sufficiently dispersing the current in the surface direction.

(3) In the semiconductor device described above, the high-concentration carrier region may be present at a position closer to the second semiconductor layer than the substrate. According to this embodiment, the current flowing into the first semiconductor layer via the channel can be effectively dispersed.

(4) In the semiconductor device described above, the thickness of the high concentration carrier region may be 10 nm or more and 10 μm or less. According to this embodiment, a sufficient breakdown voltage can be ensured while sufficiently dispersing the current in the surface direction.

(5) In the semiconductor device described above, the first semiconductor layer further includes a first region located on the substrate side from the high concentration carrier region; and a second semiconductor layer side located from the high concentration carrier region. The carrier concentration in the first region is equal to the carrier concentration in the second region. According to this embodiment, a sufficient breakdown voltage can be secured.

(6) In the semiconductor device described above, a plurality of cells having the same shape have a structure regularly arranged in the plane direction, and the distance from the second semiconductor layer to the high concentration carrier region is the cell Or less than half the cell pitch. According to this embodiment, the current can be sufficiently dispersed in the surface direction.

(7) In the semiconductor device described above, the first semiconductor layer may be mainly made of a compound semiconductor. According to this embodiment, in a semiconductor device using a compound semiconductor, the on-resistance can be reduced while suppressing a decrease in breakdown voltage.

(8) In the semiconductor device described above, the first semiconductor layer may be mainly made of gallium nitride (GaN). According to this aspect, in the semiconductor device using gallium nitride (GaN), the on-resistance can be reduced while suppressing a decrease in breakdown voltage.

(9) The semiconductor device described above further includes a third region having the other characteristic between the second semiconductor layer and the high-concentration carrier region, and the third direction has the third property in the plane direction. The region may be located away from the trench. According to this embodiment, the concentration of the electric field in the vicinity of the outer periphery of the bottom surface of the trench can be alleviated, so that a reduction in breakdown voltage can be more effectively suppressed.

(10) In the semiconductor device described above, the third region may be located away from the high-concentration carrier region in the thickness direction. According to this embodiment, the on-resistance can be more effectively reduced.

  The present invention can be realized in various forms other than the semiconductor device. For example, a power conversion device including the semiconductor device of the above form, a manufacturing method of manufacturing the semiconductor device of the above form, and a manufacturing apparatus for implementing the manufacturing method Can be realized.

  According to the present invention, since the high-concentration carrier region exists at a position away from the trench in the first semiconductor layer toward the substrate side, it is formed at the pn junction interface between the first semiconductor layer and the second semiconductor layer. The influence of the depletion layer on the high concentration carrier region can be reduced. As a result, the current flowing into the first semiconductor layer via the channel formed in the second semiconductor layer is sufficiently supplied in the plane direction in the high concentration carrier region away from the trench in the first semiconductor layer toward the substrate. Can be dispersed. As a result, the on-resistance can be reduced while suppressing a decrease in breakdown voltage.

It is sectional drawing which shows the structure of a semiconductor device typically. It is an expanded sectional view of a semiconductor device. It is an expanded sectional view of the semiconductor device in a 2nd embodiment. It is explanatory drawing which shows the structure of a power converter device. It is an expanded sectional view of the semiconductor device in a 5th embodiment. It is an expanded sectional view of the semiconductor device in a 6th embodiment.

A. First Embodiment FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device 100. FIG. 2 is an enlarged cross-sectional view of the semiconductor device 100.

  FIG. 1 shows XYZ axes orthogonal to each other. Of the XYZ axes in FIG. 1, the X axis is an axis from the left side to the right side in FIG. The + X-axis direction is a direction toward the right side of the paper, and the -X-axis direction is a direction toward the left side of the paper. Of the XYZ axes in FIG. 1, the Y axis is an axis that extends from the front side of the paper in FIG. The + Y-axis direction is a direction toward the back of the sheet, and the -Y-axis direction is a direction toward the front of the sheet. Of the XYZ axes in FIG. 1, the Z axis is an axis that extends from the bottom of FIG. 1 to the top of the page. The + Z-axis direction is a direction toward the paper surface, and the -Z-axis direction is a direction toward the paper surface. The XYZ axes in FIG. 1 correspond to the XYZ axes in the other drawings.

  The semiconductor device 100 is a vertical transistor having a trench gate structure. In the present embodiment, the semiconductor device 100 is a vertical trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In the present embodiment, the semiconductor device 100 is used for power control and is also called a power device. In the present embodiment, the semiconductor device 100 is a GaN-based semiconductor device formed using gallium nitride (GaN), which is one of compound semiconductors.

  The semiconductor device 100 has a structure in which a plurality of cells CL having the same shape are regularly arranged in a plane direction (at least one of the X-axis direction and the Y-axis direction). In the present embodiment, the semiconductor device 100 has a structure in which a plurality of cells CL having a regular hexagon when viewed from the + Z-axis direction are regularly arranged in the X-axis direction and the Y-axis direction. In another embodiment, the semiconductor device 100 may have a structure in which a plurality of cells CL that form a rectangle extending linearly in the Y-axis direction are regularly arranged in the X-axis direction. May have a structure in which a plurality of cells CL forming other different polygons (for example, squares) are regularly arranged in the X-axis direction and the Y-axis direction.

  The semiconductor device 100 includes a substrate 110, an n-type semiconductor layer 120, a p-type semiconductor layer 130, and an n-type semiconductor layer 140. The semiconductor device 100 includes a trench 152 and a recess 156 as a structure formed in each semiconductor layer. The semiconductor device 100 further includes an insulating film 160, a gate electrode 172 that is a control electrode, a source electrode 174 that is a first electrode, a p body electrode 176 that is a second electrode, and a third electrode. A drain electrode 178. Note that the n-type semiconductor layer 120 is also referred to as a first semiconductor layer, the p-type semiconductor layer 130 is also referred to as a second semiconductor layer, and the n-type semiconductor layer 140 is also referred to as a third semiconductor layer.

The substrate 110 of the semiconductor device 100 is a semiconductor having a plate shape extending in the plane direction (X-axis direction and Y-axis direction). In the present embodiment, the substrate 110 is mainly made of gallium nitride (GaN). In the description of the present specification, “mainly composed of gallium nitride (GaN)” means that 90% or more of gallium nitride (GaN) is contained in a molar fraction. In the present embodiment, the substrate 110 is an n-type semiconductor having n-type characteristics. In the present embodiment, the substrate 110 contains silicon (Si) as a donor element. In this embodiment, the average value of the silicon (Si) concentration contained in the substrate 110 is about 1.0 × 10 ¹⁸ cm ⁻³ . The thickness of the substrate 110 (the length in the Z-axis direction) is preferably 100 μm or more and 500 μm or less, and is about 300 μm in this embodiment.

  The n-type semiconductor layer 120 of the semiconductor device 100 is a semiconductor having n-type characteristics. The n-type semiconductor layer 120 is located above the substrate 110. In the present embodiment, the n-type semiconductor layer 120 is located on the + Z axis direction side of the substrate 110. In the present embodiment, the n-type semiconductor layer 120 extends in the plane direction (X-axis direction and Y-axis direction). In the present embodiment, the n-type semiconductor layer 120 is mainly made of gallium nitride (GaN). In the present embodiment, the n-type semiconductor layer 120 contains silicon (Si) as a donor element. The carrier concentration of the n-type semiconductor layer 120 forms a peak in the thickness direction (Z-axis direction). The n-type semiconductor layer 120 includes a low concentration carrier region 121, a high concentration carrier region 123, and a low concentration carrier region 125. Note that the low concentration carrier region 121 is also referred to as a first region, and the low concentration carrier region 125 is also referred to as a second region.

The low-concentration carrier region 121 of the n-type semiconductor layer 120 is a first region located closer to the substrate 110 than the high-concentration carrier region 123 among the regions constituting the n-type semiconductor layer 120. The carrier concentration in the low concentration carrier region 121 is lower than the carrier concentration in the high concentration carrier region 123. In the present embodiment, the carrier concentration of the low concentration carrier region 121 is substantially constant in the Z-axis direction except for the vicinity of the boundary with the high concentration carrier region 123. In other embodiments, the carrier concentration in the low concentration carrier region 121 may be increased or decreased with a small width compared to the difference in carrier concentration between the low concentration carrier region 121 and the high concentration carrier region 123. In this embodiment, the average value of the silicon (Si) concentration contained in the low concentration carrier region 121 is about 1.0 × 10 ¹⁶ cm ⁻³ . In the present embodiment, the thickness (length in the Z-axis direction) of the low concentration carrier region 121 is about 10 μm.

The high-concentration carrier region 123 of the n-type semiconductor layer 120 is a region where the carrier concentration has a peak in the n-type semiconductor layer 120 among the regions constituting the n-type semiconductor layer 120. In other words, the carrier concentration of the high concentration carrier region 123 is higher than the carrier concentration of the low concentration carrier regions 121 and 125. In the present embodiment, the carrier concentration of the high concentration carrier region 123 is substantially constant in the Z-axis direction except for the vicinity of the boundary with the low concentration carrier regions 121 and 125. In another embodiment, the carrier concentration of the high concentration carrier region 123 may be increased or decreased with a small width compared to the difference in carrier concentration between the low concentration carrier regions 121 and 125 and the high concentration carrier region 123. The average value of the silicon (Si) concentration contained in the high concentration carrier region 123 is preferably 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less. 2 × 10 ¹⁶ cm ⁻³ . When the carrier concentration in the high concentration carrier region 123 is less than 1.0 × 10 ¹⁶ cm ⁻³ , the current cannot be sufficiently dispersed in the high concentration carrier region 123. When the carrier concentration in the high-concentration carrier region 123 exceeds 1.0 × 10 ¹⁸ cm ^−3, it is impossible to ensure a sufficient breakdown voltage.

  The high-concentration carrier region 123 extends in the plane direction (X-axis direction and Y-axis direction) at a position away from the trench 152 toward the substrate 110 side. In the present embodiment, the low concentration carrier region 121 is present at a position closer to the p-type semiconductor layer 130 than the substrate 110. In the present embodiment, the distance Dh from the p-type semiconductor layer 130 to the high-concentration carrier region 123 is not more than half of the cell pitch CP that is the distance between the reference points of the cell CL.

  The thickness (the length in the Z-axis direction) of the high concentration carrier region 123 is preferably 10 nm or more from the viewpoint of stably forming the high concentration carrier region 123 in the plane direction. The thickness of the high-concentration carrier region 123 is preferably thinner than the low-concentration carrier region 121 from the viewpoint of sufficiently ensuring a breakdown voltage, that is, preferably 10 μm or less. In the present embodiment, the thickness of the high concentration carrier region 123 is about 2.0 μm.

The low-concentration carrier region 125 of the n-type semiconductor layer 120 is a second region located closer to the p-type semiconductor layer 130 than the high-concentration carrier region 123 among the regions constituting the n-type semiconductor layer 120. The carrier concentration in the low concentration carrier region 125 is lower than the carrier concentration in the high concentration carrier region 123. In the present embodiment, the carrier concentration of the low concentration carrier region 125 is substantially constant in the Z-axis direction except for the vicinity of the boundary with the high concentration carrier region 123. In other embodiments, the carrier concentration of the low concentration carrier region 125 may be increased or decreased with a small width compared to the difference in carrier concentration between the low concentration carrier region 125 and the high concentration carrier region 123. In the present embodiment, the carrier concentration of the low concentration carrier region 125 is substantially equal to the carrier concentration of the low concentration carrier region 121. In the present embodiment, the average value of the silicon (Si) concentration contained in the low concentration carrier region 125 is about 1.0 × 10 ¹⁶ cm ⁻³ . In the present embodiment, the thickness (length in the Z-axis direction) of the low concentration carrier region 125 is about 0.5 μm.

  In the present embodiment, the n-type semiconductor layer 120 is formed on the substrate 110 by epitaxial growth using metal organic chemical vapor deposition (MOCVD). In the present embodiment, the low concentration carrier region 121, the high concentration carrier region 123, and the low concentration carrier region 125 are formed by increasing or decreasing the amount of dopant supplied during the growth of the n-type semiconductor layer 120. In another embodiment, the high-concentration carrier region 123 may be formed by ion-implanting a dopant after epitaxially growing the n-type semiconductor layer 120 to a thickness corresponding to the high-concentration carrier region 123. In this case, a low concentration carrier region 125 is formed on the high concentration carrier region 123 by regrowth after ion implantation.

The p-type semiconductor layer 130 of the semiconductor device 100 is a semiconductor having p-type characteristics. The p-type semiconductor layer 130 is located on the n-type semiconductor layer 120. In the present embodiment, the p-type semiconductor layer 130 is located on the + Z-axis direction side of the n-type semiconductor layer 120. In the present embodiment, the p-type semiconductor layer 130 extends in the plane direction (X-axis direction and Y-axis direction). In the present embodiment, the p-type semiconductor layer 130 is mainly made of gallium nitride (GaN). In the present embodiment, the p-type semiconductor layer 130 contains magnesium (Mg) as an acceptor element. In this embodiment, the average value of the magnesium (Mg) concentration contained in the p-type semiconductor layer 130 is about 1.0 × 10 ¹⁸ cm ⁻³ . In the present embodiment, the thickness (length in the Z-axis direction) of the p-type semiconductor layer 130 is about 1.0 μm.

The n-type semiconductor layer 140 of the semiconductor device 100 is a semiconductor having n-type characteristics. The n-type semiconductor layer 140 is located on the p-type semiconductor layer 130. In the present embodiment, the n-type semiconductor layer 140 is located on the + Z-axis direction side of the p-type semiconductor layer 130. In the present embodiment, the n-type semiconductor layer 140 extends in the plane direction (X-axis direction and Y-axis direction). In the present embodiment, the n-type semiconductor layer 140 is mainly made of gallium nitride (GaN). In the present embodiment, the n-type semiconductor layer 140 contains silicon (Si) as a donor element. In this embodiment, the average value of the silicon (Si) concentration contained in the n-type semiconductor layer 140 is about 3.0 × 10 ¹⁸ cm ⁻³ . In the present embodiment, the thickness (length in the Z-axis direction) of the n-type semiconductor layer 140 is about 0.3 μm.

  The trench 152 of the semiconductor device 100 is a trench that penetrates the n-type semiconductor layer 120 from the n-type semiconductor layer 140 through the p-type semiconductor layer 130. In the present embodiment, the trench 152 falls to the low concentration carrier region 125 of the n-type semiconductor layer 120. The trench 152 is separated from the high concentration carrier region 123 of the n-type semiconductor layer 120. In this embodiment, the depth (length in the Z-axis direction) of the trench 152 is 1.5 μm. In the present embodiment, the trench 152 has a structure formed by dry etching for each semiconductor layer.

  The recess 156 of the semiconductor device 100 is a recess that penetrates the n-type semiconductor layer 140 and reaches the p-type semiconductor layer 130. In the present embodiment, the recess 156 has a structure formed by dry etching on each semiconductor layer.

The insulating film 160 of the semiconductor device 100 is a film having electrical insulation. The insulating film 160 covers the surface of the trench 152. In the present embodiment, the insulating film 160 is formed from the inside to the outside of the trench 152. In the present embodiment, the insulating film 160 is mainly made of silicon dioxide (SiO ₂ ).

  The gate electrode 172 of the semiconductor device 100 is an electrode formed inside the trench 152 with the insulating film 160 interposed therebetween. In the present embodiment, the gate electrode 172 is formed not only inside the trench 152 but also outside the trench 152. In the present embodiment, the gate electrode 172 is mainly made of aluminum (Al). When a voltage is applied to the gate electrode 172, an inversion layer is formed in the p-type semiconductor layer 130, and this inversion layer functions as a channel CH, thereby forming a conduction path between the source electrode 174 and the drain electrode 178. Is done.

  The source electrode 174 of the semiconductor device 100 is a first electrode that is in ohmic contact with the n-type semiconductor layer 140. In the present embodiment, the source electrode 174 is formed from above the p body electrode 176 to above the n-type semiconductor layer 140. In the present embodiment, the source electrode 174 is composed of a layer mainly made of titanium (Ti), a layer mainly made of aluminum (Al), and a layer mainly made of palladium (Pd) in this order from the n-type semiconductor layer 140 side. Are laminated electrodes.

  The p body electrode 176 of the semiconductor device 100 is a second electrode that is in ohmic contact with the p-type semiconductor layer 130. In the present embodiment, the p body electrode 176 is formed inside the recess 156. In the present embodiment, the p body electrode 176 is mainly made of palladium (Pd).

  The drain electrode 178 of the semiconductor device 100 is a third electrode that is in ohmic contact with the surface of the substrate 110 on the −Z axis direction side. In the present embodiment, the drain electrode 178 is a stacked electrode in which a layer mainly made of titanium (Ti) and a layer mainly made of aluminum (Al) are stacked in this order from the substrate 110 side.

  According to the first embodiment described above, since the high-concentration carrier region 123 exists in the n-type semiconductor layer 120 at a position away from the trench 152 toward the substrate 110, the n-type semiconductor layer 120, the p-type semiconductor layer 130, The influence of the depletion layer DL formed at the pn junction interface on the high concentration carrier region 123 can be reduced. As a result, the current flowing into the n-type semiconductor layer 120 via the channel CH formed in the p-type semiconductor layer 130 is reflected in the high concentration carrier region 123 away from the trench 152 in the n-type semiconductor layer 120 toward the substrate 110. It is possible to sufficiently disperse in the directions (X-axis direction and Y-axis direction). As a result, the on-resistance can be reduced while suppressing a decrease in breakdown voltage. In the present embodiment, as shown in FIG. 2, the high-concentration carrier region 123 is designed to be separated from the depletion layer DL. In another embodiment, a part of the high concentration carrier region 123 may overlap with the depletion layer DL. That is, it is sufficient that the entire high concentration carrier region 123 does not overlap with the depletion layer DL. In the present embodiment, the depletion layer DL is a depletion layer at zero bias when no voltage is applied to the semiconductor device 100.

In addition, since the carrier concentration in the high concentration carrier region 123 is 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less, current flows in the plane direction (X-axis direction and Y-axis direction). It is possible to sufficiently secure a withstand voltage while sufficiently dispersing.

  Further, the high concentration carrier region 123 may exist at a position closer to the n-type semiconductor layer 140 than the substrate 110. According to this form, the current flowing into the n-type semiconductor layer 120 via the channel CH can be effectively dispersed.

  In addition, since the thickness of the high-concentration carrier region 123 is 10 nm or more and 10 μm or less, a sufficient breakdown voltage can be secured while sufficiently dispersing current in the plane direction (X-axis direction and Y-axis direction).

  In addition, since the carrier concentration in the low concentration carrier region 121 is equal to the carrier concentration in the low concentration carrier region 125, a sufficient breakdown voltage can be secured.

  Further, since the distance Dh from the p-type semiconductor layer 130 to the high-concentration carrier region 123 is not more than half the cell pitch CP, the current can be sufficiently dispersed in the plane direction (X-axis direction and Y-axis direction). . In the semiconductor device 100 of the present embodiment, the high concentration carrier region 123 is separated from the bottom surface of the trench 152 by 0.3 μm, but the distance between the high concentration carrier region 123 and the trench 152 is not limited to this. From the viewpoint of sufficiently dispersing the current in the plane direction (X-axis direction and Y-axis direction), the distance between the high-concentration carrier region 123 and the bottom surface of the trench 152 is preferably 10 nm or more. In other words, the distance between the interface between the n-type semiconductor layer 120 and the p-type semiconductor layer 130 and the high-concentration carrier region 123 is from the interface between the n-type semiconductor layer 120 and the p-type semiconductor layer 130 to the bottom surface of the trench 152. It is preferably larger than the distance by 10 nm or more.

B. Second Embodiment FIG. 3 is an enlarged cross-sectional view of a semiconductor device 100B according to a second embodiment. FIG. 3 shows the XYZ axes as in FIG.

  The semiconductor device 100B of the second embodiment is the same as the semiconductor device 100 of the first embodiment, except that the n-type semiconductor layer 120B is provided instead of the n-type semiconductor layer 120. The n-type semiconductor layer 120B of the semiconductor device 100B is the same as the n-type semiconductor layer 120 of the first embodiment except that the high-concentration carrier region 123B and the low-concentration carrier region 124B are provided instead of the high-concentration carrier region 123. is there. The high-concentration carrier region 123B of the n-type semiconductor layer 120B is the same as the high-concentration carrier region 123 of the first embodiment except that it is partially formed in the plane direction (X-axis direction and Y-axis direction). .

The low concentration carrier region 124B of the n-type semiconductor layer 120B is a region located between the high concentration carrier regions 123B in the plane direction (X-axis direction and Y-axis direction). The low concentration carrier region 124B is located between the low concentration carrier region 121 and the low concentration carrier region 125 in the Z-axis direction. The carrier concentration of the low concentration carrier region 124B is lower than the carrier concentration of the high concentration carrier region 123. In the present embodiment, the carrier concentration of the low concentration carrier region 124 </ b> B is equal to the carrier concentration of the low concentration carrier region 121. In the present embodiment, the average value of the silicon (Si) concentration contained in the low concentration carrier region 124B is about 1.0 × 10 ¹⁶ cm ⁻³ .

  According to the second embodiment described above, the on-resistance can be reduced while suppressing a decrease in breakdown voltage, as in the first embodiment.

C. Third Embodiment A semiconductor device of the third embodiment is the same as the semiconductor device 100 of the first embodiment except that the specifications of the high concentration carrier region 123 are different. The high concentration carrier region 123B of the third embodiment is the same as that of the first embodiment except that the carrier concentration is 5.0 × 10 ¹⁷ cm ⁻³ and the thickness is 0.05 μm. . According to the third embodiment, as in the first embodiment, the on-resistance can be reduced while suppressing a decrease in breakdown voltage. As another modification, for example, (i) a high concentration carrier region having a carrier concentration of 7.0 × 10 ¹⁶ cm ⁻³ and a thickness of 0.5 μm may be employed. A high concentration carrier region having a carrier concentration of 1.1 × 10 ¹⁷ cm ⁻³ and a thickness of 0.5 μm may be employed. Even if such a high-concentration carrier region is employed, the on-resistance can be reduced while suppressing a decrease in breakdown voltage, as in the first embodiment.

D. Fourth Embodiment FIG. 4 is an explanatory diagram showing a configuration of the power conversion device 10. The power converter 10 is a device that converts power supplied from the AC power source E to the load R. The power conversion device 10 includes a control circuit 20, a transistor TR, four diodes D1, a coil L, a diode D2, and a capacitor C as components of a power factor correction circuit that improves the power factor of the AC power source E. Is provided. In the present embodiment, the transistor TR is the same as the semiconductor device 100 of the first embodiment. In other embodiments, the transistor TR may be the same as the semiconductor device 100B of the second embodiment, or may be the same as the semiconductor device of the third embodiment.

  Diodes D1 and D2 of power converter 10 are Schottky barrier diodes. In the power conversion device 10, the four diodes D1 constitute a diode bridge DB that rectifies the AC voltage of the AC power source E. The diode bridge DB has a positive electrode output terminal Tp and a negative electrode output terminal Tn as terminals on the DC side. The coil L is connected to the positive electrode output terminal Tp of the diode bridge DB. The anode side of the diode D2 is connected to the positive electrode output terminal Tp via the coil L. The cathode side of the diode D2 is connected to the negative output terminal Tn via the capacitor C. The load R is connected in parallel with the capacitor C.

  The transistor TR of the power conversion device 10 is an FET (Field-Effect Transistor). The source side of the transistor TR is connected to the negative output terminal Tn. The drain side of the transistor TR is connected to the positive electrode output terminal Tp via the coil L. The gate side of the transistor TR is connected to the control circuit 20. The control circuit 20 of the power conversion device 10 is configured so that the source-drain of the transistor TR is based on the voltage output to the load R and the current in the diode bridge DB so that the power factor of the AC power supply E is improved. Control the current.

  According to the fourth embodiment described above, the device characteristics of the transistor TR can be improved. As a result, the power conversion efficiency by the power conversion device 10 can be improved.

E. Fifth Embodiment FIG. 5 is an enlarged cross-sectional view of a semiconductor device 100C according to a fifth embodiment. FIG. 5 shows the XYZ axes as in FIG.

  The semiconductor device 100C according to the fifth embodiment is provided with a p-type region 127A serving as an electric field relaxation region in a part of the low-concentration carrier region 125 between the p-type semiconductor layer 130 and the high-concentration carrier region 123, This is the same as the semiconductor device 100 of the first embodiment. The p-type region 127A is located away from the trench 152 in the surface direction (X-axis direction and Y-axis direction). Note that the p-type region 127A is also referred to as a third region.

In the present embodiment, the p-type region 127A has a dopant concentration added as an acceptor of about 5.0 × 10 ¹⁹ cm ⁻³ and a thickness of about 0.5 μm. In the present embodiment, the p-type region 127A and the high-concentration carrier region 123 are in contact with each other in the thickness direction (Z-axis direction). As a method of forming the p-type region 127A, for example, magnesium (Mg) as a dopant is ion-implanted from above the low-concentration carrier region 125.

  According to the fifth embodiment, as in the first embodiment, the on-resistance can be reduced while suppressing a decrease in breakdown voltage. In addition, according to the fifth embodiment, by providing the p-type region 127A, it is possible to alleviate the concentration of the electric field near the outer periphery of the bottom surface of the trench 152, and thus it is possible to more effectively suppress the decrease in breakdown voltage.

F. Sixth Embodiment FIG. 6 is an enlarged cross-sectional view of a semiconductor device 100D in a sixth embodiment. FIG. 6 shows the XYZ axes as in FIG.

  The semiconductor device 100D of the sixth embodiment is the same as the semiconductor device 100C of the fifth embodiment except that a p-type region 127B is provided instead of the p-type region 127A. The p-type region 127B of the semiconductor device 100D is located away from the high-concentration carrier region 123 in the thickness direction (Z-axis direction), and the p-type region of the semiconductor device 100C is not in contact with the high-concentration carrier region 123. It is the same as 127A. The bottom surface of the p-type region 127B is preferably on the same plane as the bottom surface of the trench 152 or positioned on the substrate 110 side, that is, on the −Z axis direction side. In the present embodiment, the thickness of the p-type region 127A is about 0.4 μm.

  According to the sixth embodiment, as in the first embodiment, the on-resistance can be reduced while suppressing a decrease in breakdown voltage. In addition, according to the sixth embodiment, by providing the p-type region 127B, it is possible to alleviate the concentration of the electric field near the outer periphery of the bottom surface of the trench 152, and thus it is possible to more effectively suppress a decrease in breakdown voltage.

  Further, the p-type region 127B of the sixth embodiment is located away from the high concentration carrier region 123 in the thickness direction (Z-axis direction). For this reason, the influence which the depletion layer formed in the interface of the low concentration carrier region 125 and the p-type region 127B has on the high concentration carrier region 123 can be reduced. As a result, the current that flows into the n-type semiconductor layer 120 via the channel formed in the p-type semiconductor layer 130 is caused to reach the surface in the high-concentration carrier region 123 away from the trench 152 in the n-type semiconductor layer 120 toward the substrate 110. Since it can be sufficiently dispersed in the directions (X-axis direction and Y-axis direction), the on-resistance can be more effectively reduced.

G. Other Embodiments The present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, among the technical features in the embodiments, examples, and modifications, those corresponding to the technical features in each embodiment described in the summary section of the invention are for solving some or all of the above-described problems. Alternatively, in order to achieve part or all of the above-described effects, replacement and combination can be performed as appropriate. Further, technical features that are not described as essential in the present specification can be appropriately deleted.

  The semiconductor device to which the present invention is applied may be a vertical transistor having a trench gate structure, and is not limited to the vertical trench MOSFET described above, but is, for example, an insulated gate bipolar transistor (IGBT). May be.

In the above-described embodiment, the material of the substrate is not limited to gallium nitride (GaN) described above, and may be any of silicon (Si), sapphire (Al ₂ O ₃ ), silicon carbide (SiC), and the like.

  In the above-described embodiment, the material of each semiconductor layer may be a compound semiconductor, and is not limited to the above-described gallium nitride (GaN), but a group III nitride (for example, aluminum nitride (AlN), indium nitride (InN), etc. ).

  In the above-described embodiment, the donor element contained in the n-type semiconductor layer is not limited to silicon (Si), but may be germanium (Ge), oxygen (O), or the like.

  In the above-described embodiment, the acceptor element included in the p-type semiconductor layer is not limited to magnesium (Mg) but may be zinc (Zn), carbon (C), or the like.

  In the above-described embodiment, the relationship between the n-type and the p-type in the substrate and each semiconductor layer may be switched.

  In the above-described embodiment, the n-type semiconductor layer 120 may have two or more high-concentration carrier regions 123 at different positions in the Z-axis direction.

In the above-described embodiment, the material of the insulating film may be any material having electrical insulation properties, and in addition to silicon dioxide (SiO ₂ ), silicon nitride (SiNx), aluminum oxide (Al ₂ O ₃ ), aluminum nitride ( AlN), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), silicon oxynitride (SiON), aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), etc. There may be. The insulating film may be a single layer or two or more layers.

  In the above-described embodiment, the material of each electrode is not limited to the material of the above-described embodiment, and may be other materials.

DESCRIPTION OF SYMBOLS 10 ... Power converter 20 ... Control circuit 100,100B, 100C, 100D ... Semiconductor device 110 ... Substrate 120,120B ... n-type semiconductor layer 121 ... Low concentration carrier region 123,123B ... High concentration carrier region 124B ... Low concentration carrier region 125... Low-concentration carrier region 127 A, 127 B... P-type region 130... P-type semiconductor layer 140... N-type semiconductor layer 152. Drain electrode

Claims (11)

A semiconductor device,
A substrate spreading in the surface direction,
A first semiconductor layer located above the substrate and having one of n-type and p-type characteristics;
A second semiconductor layer located on the first semiconductor layer and having the other characteristic different from the one of the n-type and p-type,
A third semiconductor layer located on the second semiconductor layer and having the one characteristic;
A trench penetrating from the third semiconductor layer through the second semiconductor layer to the first semiconductor layer;
An insulating film covering the surface of the trench,
The carrier concentration of the first semiconductor layer forms a peak in the thickness direction orthogonal to the plane direction,
The high-concentration carrier region having a peak carrier concentration in the first semiconductor layer extends in the surface direction at a position away from the trench toward the substrate. 2. The semiconductor device according to claim 1, wherein a carrier concentration in the high concentration carrier region is 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less.   The semiconductor device according to claim 1, wherein the high-concentration carrier region is present at a position closer to the second semiconductor layer than the substrate.   4. The semiconductor device according to claim 1, wherein a thickness of the high concentration carrier region is not less than 10 nm and not more than 10 μm. A semiconductor device according to any one of claims 1 to 4, wherein
The first semiconductor layer further includes:
A first region located closer to the substrate than the high concentration carrier region;
A second region located closer to the second semiconductor layer than the high-concentration carrier region,
The semiconductor device, wherein the carrier concentration in the first region is equal to the carrier concentration in the second region. A semiconductor device according to any one of claims 1 to 5,
A plurality of cells having the same shape have a structure regularly arranged in the plane direction,
A semiconductor device, wherein a distance from the second semiconductor layer to the high-concentration carrier region is not more than half of a cell pitch of the cell.   The semiconductor device according to claim 1, wherein the first semiconductor layer is mainly made of a compound semiconductor.   The semiconductor device according to claim 1, wherein the first semiconductor layer is mainly made of gallium nitride (GaN). A semiconductor device according to any one of claims 1 to 5, further comprising:
A third region having the other characteristic is provided between the second semiconductor layer and the high-concentration carrier region;
The semiconductor device, wherein the third region is located away from the trench in the planar direction. The semiconductor device according to claim 9,
The semiconductor device, wherein the third region is located away from the high concentration carrier region in the thickness direction.   A power converter device comprising the semiconductor device according to any one of claims 1 to 10.

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