JP2017062429A - Timing control device for display unit, display unit, and television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately synchronize the operations of circuit boards with a simple configuration.SOLUTION: T-CON boards (12a to 12d) are provided respectively in display areas (5a to 5d) obtained by dividing a display area of a display unit (1) into a plurality of areas and arranging side by side in the drawing direction of a scanning signal line, and an output clock signal CLK and an output synchronization signal VSYNC are sequentially transmitted from the T-CON board (12a) arranged at one end in the drawing direction of the scanning signal line to the T-CON board (12d) arranged at the other end.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a timing control device for a display device, a display device including the timing control device, and a television receiver.

  2. Description of the Related Art Conventionally, in a display device in which a plurality of display areas are driven by control circuits provided on separate circuit boards, a technique for suppressing a reduction in display quality due to a video synchronization shift in each display area has been developed.

  For example, in Patent Document 1, in a display device in which a plurality of display units are arranged adjacent to each other to form one display area, an image correction unit provided for each display unit, and each image correction unit Jitter suppression means for correcting a phase difference between output image signals, and the phase-corrected image signal are combined as an image composite signal of one image displayed by the plurality of display means, and the image composite signal A display device is disclosed that includes combining means for supplying the plurality of display devices to the display device.

Japanese Patent No. 4529443 (released July 21, 2005)

  However, in the technique of Patent Document 1, the clock signal and the synchronization signal are distributed by the image data supply source to each image correction unit and input to each image correction unit, and the image correction units operate independently of each other. It has become.

  For this reason, a phase shift of the clock signal occurs in each image correction means, and the synchronization timing tends to shift, and there is a problem that the display quality deteriorates due to the video synchronization shift in each display area.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a simple configuration for the operation of each circuit board in a timing control apparatus for a display device including a plurality of circuit boards each having a timing controller circuit. It is to synchronize properly.

  A timing control device for a display device according to one aspect of the present invention is a timing control device for a display device including a plurality of circuit boards each having a timing controller circuit that controls operation timing of the display device based on a timing control signal. The circuit board is provided for each divided area obtained by dividing the display area of the display device into a plurality of areas arranged in the extending direction of the scanning signal lines, and the circuit boards are arranged in the extending direction of the scanning signal lines. The timing control signal is sequentially transmitted from the circuit board arranged on one end side in the extending direction of the scanning signal line toward the circuit board arranged on the other end side of the plurality of circuit boards. It is characterized by.

  According to the above configuration, the timing control signal for controlling the operation timing of the display device is sequentially directed from the circuit board arranged on one end side in the extending direction of the scanning signal line toward the circuit board arranged on the other end side. Is transmitted. That is, the timing control signal is sequentially transmitted in the same direction as the transmission direction of the scanning signal transmitted through the scanning signal line. As a result, the delay of the timing control signal associated with the transmission between the circuit boards and the delay of the scanning signal transmitted through the scanning signal lines can be offset, so that the operation of each circuit board can be appropriately synchronized with a simple configuration. Accordingly, it is possible to suppress a decrease in display quality due to a deviation between the timing control signal and the scanning signal.

It is a disassembled perspective view which shows schematic structure of the television receiver which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the structure of the timing control apparatus of the television receiver shown in FIG. It is explanatory drawing which shows the structure of the T-CON circuit with which the timing control apparatus of the television receiver shown in FIG. 1 is equipped. It is explanatory drawing which shows the structure of the synchronizing circuit with which the timing control apparatus of the television receiver shown in FIG. 1 is equipped. It is explanatory drawing which shows the waveform of the output clock signal in each synchronizing circuit with which the timing control apparatus of the television receiver shown in FIG. 1 is equipped, and an output synchronizing signal. It is explanatory drawing which shows the structure of the timing control apparatus of the television receiver which concerns on Embodiment 2 of this invention. It is explanatory drawing which shows the structure of the synchronizing circuit with which the timing control apparatus of the television receiver shown in FIG. 6 is equipped. FIG. 8 is an explanatory diagram illustrating waveforms of an output clock signal and an output synchronization signal in the synchronization circuit illustrated in FIG. 7. It is explanatory drawing which shows the structure of the timing control apparatus of the television receiver which concerns on Embodiment 3 of this invention. FIG. 10 is an explanatory diagram illustrating a configuration of a synchronization circuit provided in the timing control device of the television receiver illustrated in FIG. 9. It is explanatory drawing which shows the structure of the phase correction circuit with which the synchronizing circuit shown in FIG. 9 is equipped. FIG. 10 is an explanatory diagram illustrating waveforms of an output clock signal and an output synchronization signal in the synchronization circuit illustrated in FIG. 9.

Embodiment 1
An embodiment of the present invention will be described.

(1-1. Configuration of Television Receiver 1)
FIG. 1 is an exploded perspective view showing a schematic configuration of a television receiver 1 according to the present embodiment.

  As shown in FIG. 1, a television receiver 1 includes a display device 2, a rear-side cabinet 4 that houses the display device 2, and a frame-shaped front surface that is attached to the front side of the rear-side cabinet that houses the display device 2. A side cabinet 3 is provided.

  The display device 2 displays a video corresponding to a video signal received by a tuner (not shown). In the present embodiment, a liquid crystal display device including a liquid crystal display panel 5, a gate driver 6, and source drivers 7a to 7d is used as the display device 2. In the display device 2, four source drivers 7 a to 7 d are arranged along the long side portion of the rectangular liquid crystal display panel 5, and one gate driver 6 is provided along the short side portion. Yes.

  In the present embodiment, the case where the present invention is applied to a television receiver including the display device 2 and a tuner will be described. However, the application target of the present invention is not limited to this. For example, the present invention can be applied to a monitor for a personal computer, a display device used as a monitor for reproducing video recorded on various recording devices, various recording media, and the like.

  Moreover, although this embodiment demonstrates the case where a liquid crystal display device is used as the display apparatus 2, it is not restricted to this. The display device 2 may be any display device that controls the drive timing of each pixel by sequentially scanning the scanning signal lines. For example, an organic EL display or a plasma display may be used.

(1-2. Configuration of Control System of Television Receiver 1)
FIG. 2 is an explanatory diagram showing the configuration of the control system of the television receiver 1. As shown in this figure, the television receiver 1 includes a video processing board 11, a timing control device 10 having T-CON (timing controller) boards 12a to 12d, a gate driver 6, and source drivers 7a to 7d. It has.

  The gate driver 6 sequentially outputs a scanning signal to each gate bus line (not shown) provided in the liquid crystal display panel 5.

  The source drivers 7a to 7d output a data signal corresponding to video data to each source bus line (not shown) provided in the liquid crystal display panel 5 at a timing synchronized with the scanning of the gate bus line by the gate driver 6. To do. As a result, a potential corresponding to the video data is applied to each pixel on the gate bus line scanned by the gate driver 6 to perform display according to the video data.

  In the present embodiment, as shown in FIG. 2, the display screen of the liquid crystal display panel 5 is extended in the extending direction of the source bus line (hereinafter referred to as the vertical direction) and the extending direction of the gate bus line (hereinafter referred to as the vertical direction). Are divided into four display areas 5a to 5d arranged along the horizontal direction. Specifically, in this embodiment, the liquid crystal display panel 5 having a resolution of 8K4K (about 8000 pixels in the horizontal direction × about 4000 pixels in the vertical direction) is used, and the size of each of the display areas 5a to 5d is about 2000 pixels in the horizontal direction. X It is set to about 4000 pixels in the vertical direction.

  The source driver 7a is connected to the display area 5a, the source driver 7b is connected to the display area 5b, the source driver 7c is connected to the display area 5c, and the source driver 7d is connected to a source bus line (not shown) provided in the display area 5d. The scanning timing of the gate bus lines provided in each of the display areas 5a to 5d is controlled by the common gate driver 6.

  The video processing board 11 is a signal (video data, clock signal CLK, horizontal synchronization signal HSYNC, video for displaying video corresponding to the video data on the television receiver 1 based on video data input from a tuner (not shown). Vertical synchronization signal VSYNC and data enable signal DE) are generated and output to the T-CON circuits 13a and 13b of the T-CON boards 12a to 12d provided in the timing control device 10.

  The T-CON substrate (T-CON master substrate) 12a includes a T-CON circuit (T-CON master circuit) 13a, a T-CON substrate (T-CON slave substrate) 13b, and a synchronization circuit 14a. . The T-CON board (T-CON slave board) 12b includes T-CON boards (T-CON slave boards) 13c and 13d and a synchronization circuit 14b, and the T-CON board (T-CON slave board). 12c includes T-CON boards (T-CON slave boards) 13e and 13f and a synchronization circuit 14c, and a T-CON board (T-CON slave board) 12d is a T-CON board (T-CON slave board). 13g, 13h and a synchronizing circuit 14c.

  The T-CON circuit (T-CON master circuit) 13a generates (i) a gate driver drive signal for driving the gate driver 6 in accordance with a signal input from the video processing board 11 through the signal line 15a. (Ii) a source driver driving signal for driving a part of the source driver 7a and video data corresponding to the format used by the source driver 7a. (Iii) for synchronizing the signal output timing of the T-CON circuits 13b to 13h (the operation timing of the display areas 5a to 5b in the display device 2). An output clock signal (timing control signal) and an output synchronization signal (timing control signal) are generated to generate a T-CON circuit 13b. And output to the synchronizing circuit 14a.

  The T-CON circuit (T-CON slave circuit) 13b is based on the signal input from the video processing board 11 via the signal line 15b, and the video corresponding to the source driver control signal and the format adopted by the source driver 7a. Data is generated and output to the source driver 7b via the signal line 17b at an output timing corresponding to the output clock signal and output synchronization signal input from the T-CON circuit 13a.

  T-CON circuits (T-CON slave circuits) 13c to 13h are used as source driver control signals and source drivers 7b to 7d based on signals input from the video processing board 11 via signal lines 15c to 15h. Video data corresponding to the format is generated and output to the source drivers 7b to 7d corresponding to the T-CON circuits 13c to 13h via the signal lines 17b to 17h. The T-CON circuits 13c to 13h are generated by the T-CON circuit 13a of the T-CON substrate 12a, and are described in the order of the T-CON substrate 12b, the T-CON substrate 12c, and the T-CON substrate 12d. Source driver control signals and video data are output to the source drivers 7b to 7d at an output timing corresponding to the sequentially transferred output clock signal and output synchronization signal.

  The synchronization circuit 14a provided in the T-CON board 12a is provided in the subsequent T-CON board 12b with the output clock signal and the output synchronization signal corresponding to the output synchronization signal input from the T-CON circuit 13a. Output to the synchronization circuit 14b.

  The synchronization circuit 14b provided in the T-CON board 12b outputs an output clock signal and an output synchronization signal corresponding to the output synchronization signal input from the T-CON board 12a, T-CON circuits 13c and 13d, and It outputs to the synchronous circuit 14c with which the T-CON board | substrate 12c is equipped.

  The synchronization circuit 14c provided in the T-CON board 12c outputs an output clock signal and an output synchronization signal corresponding to the output clock signal and the output synchronization signal input from the T-CON board 12b, and the T-CON circuits 13e and 13f, and It outputs to the synchronous circuit 14d with which the T-CON board | substrate 12d is equipped.

  The synchronization circuit 14d provided in the T-CON board 12d outputs an output clock signal and an output synchronization signal corresponding to the output synchronization signal input from the T-CON board 12c to the T-CON circuits 13g and 13h. To do.

(1-3. Configuration of T-CON Circuits 13a to 13h)
FIG. 3 is an explanatory diagram showing the configuration of the T-CON circuits 13a to 13h. As shown in this figure, the T-CON circuits 13a to 13h include a memory 21, a format conversion unit 22, a write control unit 23, a timing control unit 24, a selector 25, a selector 26, and an output synchronization signal correction unit 27. ing.

  The memory 21 is a storage unit that temporarily stores a signal input from the video processing board 11. As the memory 21, for example, a FIFO (first in first out) type 2-port SRAM (static random access memory) can be used.

  The format conversion unit 22 converts the video data read from the memory 21 into video data corresponding to the format used by the source drivers 7a to 7d, and outputs the video data to the source drivers 7a to 7d.

  The writing control unit 23 controls data writing to the memory 21 in accordance with control signals (clock signal CLK, horizontal synchronization signal HSYNC, vertical synchronization signal VSYNC, data enable signal DE) input from the video processing board 11. .

  The timing control unit 24 includes a read control unit 24 a that controls reading of data from the memory 21 based on a control signal input from the video processing board 11. Note that the timing control unit 24 of the T-CON circuit 13a is configured to output an output clock signal and an output for synchronizing the signal output timings of the T-CON circuits 13a to 13h based on a control signal input from the video processing board 11. Generate a synchronization signal.

  The selector 25 and the selector 26 depend on whether the T-CON circuits 13a to 13h are T-CON circuits 13a (T-CON master circuits) or T-CON circuits 13b to 13h (T-CON slave circuits). The connection status is switched.

  Specifically, the selector 25 and the selector 26 provided in the T-CON circuit 13a are switched to the connection state A shown in FIG. As a result, the signal from the video processing board 11 is input to the timing control unit 24 of the T-CON circuit 13a, and the output synchronization signal and output clock signal generated by the timing control unit 24 of the T-CON circuit 13a are T -Output to the T-CON circuit 13b and the synchronization circuit 14a of the CON substrate 12a.

  Further, the selector 25 and the selector 26 of the T-CON circuits 13b to 13h are switched to the connection state B shown in FIG. As a result, the timing control unit 24 of the T-CON circuits 13b to 13h receives the output synchronization signal and the output clock signal from the T-CON circuit 13a or the synchronization circuits 14b to 14d, and is based on the output synchronization signal and the output clock signal. Control is performed.

  In the T-CON circuit 13a, the transmission circuit 28 controls the phase of the output clock signal from the T-CON circuit 13a, and the output synchronization signal correction unit 27 converts the output synchronization signal into an output clock signal output from the timing control unit 24. The rise / fall timing of the output synchronization signal is corrected so as to synchronize. The output clock signal and the output synchronization signal whose phases are controlled by the transmission circuit 28 are output from the T-CON circuit 13a to the T-CON circuit 13b and the synchronization circuit 14a.

  In the present embodiment, the T-CON circuit 13a and the T-CON circuits 13b to 13h have a common circuit configuration, but the present invention is not limited to this, and the circuit configurations of both may be different. For example, the selector 25 and the selector 26 are omitted in the T-CON circuit 13a and the T-CON circuits 13b to 13h, and the input / output of the signals described above is performed in each of the T-CON circuit 13a and the T-CON circuits 13b to 13h. A circuit configuration may be used.

(1-4. Configuration of Synchronous Circuits 14a to 14d)
FIG. 4 is an explanatory diagram showing the configuration of the synchronization circuits 14a to 14d. As shown in this figure, the synchronization circuits 14a to 14d include a differential signal restoration unit 31, a selector 32, a differential signal generation unit 33, and buffers 34 and 35.

  In the present embodiment, as shown in FIG. 2, the output clock signal CLK and the output synchronization signal (vertical synchronization signal VSYNC) are input from the T-CON circuit 13a to the synchronization circuit 14a provided in the T-CON board 12a. Is done. Further, the synchronization circuits 14b to 14d provided in the T-CON substrates 12b to 12d are synchronized with the output clock signal CLK (differential signal) from the synchronization circuits 14a to 14c provided in the preceding T-CON substrates 12a to 12c. Signal.

  The differential signal restoration unit 31 included in the synchronization circuits 14b to 14d of the T-CON substrates 12b to 12d is an output clock signal CLK (input from the synchronization circuits 14a to 14c included in the preceding T-CON substrates 12a to 12c. Differential signal) is converted into an output clock signal of a signal level (for example, a CMOS signal level) corresponding to the operating characteristics of the members provided in the T-CON circuits 13c to 13h and output to the selector 32. The output clock signal CLK from the T-CON circuit 13a is input to the synchronization circuit 14a of the T-CON board 12a, and the output clock signal CLK (differential signal) is input to the differential signal restoration unit 31 of the synchronization circuit 14a. Is not entered.

  The connection state of the selector 32 is switched depending on whether the synchronization circuit provided with the selector 32 is the synchronization circuit 14a or the synchronization circuits 14b to 14d.

  Specifically, the selector 32 provided in the synchronization circuit 14 a outputs the output clock signal CLK from the T-CON circuit 13 a to the T-CON circuit 13 b and the differential signal generation unit 33. The selector 32 provided in the synchronization circuits 14b to 14d uses the output clock signal output from the differential signal restoration unit 31 as the T-CON of the T-CON boards 12b to 12d provided with the synchronization circuits 14b to 14d. The signals are output to the circuits 13c to 13h and the differential signal generation unit 33.

  Note that the differential signal restoring unit 31 and the selector 32 are omitted in the synchronization circuit 14a, and the output clock signal CLK from the T-CON circuit 13a is directly output to the T-CON circuit 13b and the differential signal generating unit 33. Also good. Further, the selector 32 is omitted in the synchronization circuits 14b to 14d, and the output clock signal output from the differential signal restoration unit 31 is used as the T-CON of the T-CON substrates 12b to 12d provided with the synchronization circuits 14b to 14d. You may make it output to the circuits 13c-13h and the differential signal generation part 33. FIG.

  The differential signal generation unit 33 receives the output clock signal output from the selector 32, converts it to a differential signal having a signal level suitable for differential transmission, and is provided in the subsequent T-CON substrates 12b to 12d. 14 is output by differential transmission.

  The buffer 34 of the synchronization circuit 14a receives the output synchronization signal input from the T-CON circuit 13a and outputs it to the T-CON circuit 13b and the buffer 35. The buffers 34 of the synchronization circuits 14b to 14d receive output synchronization signals input from the synchronization circuits 14a to 14c provided in the preceding T-CON substrates 12a to 12d, and receive the T-CON circuit 13c corresponding to the synchronization circuit. ~ 13h and output to buffer 35.

  The buffer 35 receives the output synchronization signal input from the buffer 34 and outputs the output synchronization signal to the synchronization circuits 14b to 14d of the T-CON substrates 12b to 12d in the subsequent stage. Note that the transmission of the output synchronization signal between the T-CON boards may be performed by differential transmission in the same manner as the output clock signal.

  With the above configuration, the output clock signal and the output synchronization signal generated by the T-CON substrate (T-CON master substrate) 12a located on the most upstream side in the transmission direction of the scanning signal transmitted via the gate bus line are And sequentially transmitted to the other T-CON substrates (T-CON slave substrates) 12b to 12d arranged along the extending direction of the gate bus line. In each of the T-CON substrates 12a to 12d, the signal output timing to the source drivers 7a to 7d is controlled based on the output clock signal and the output synchronization signal sequentially transferred along the extending direction of the gate bus line. The

(1-5. Signal waveforms of output synchronization signal and output clock signal)
FIG. 5 is an explanatory diagram showing signal waveforms of the output clock signal CLK and the output synchronization signal (vertical synchronization signal) VSYNC in the synchronization circuits 14a to 14d. Specifically, FIG. 5 shows the following signal waveforms (a) to (r). However, for convenience of explanation, the output synchronization signal VSYNC is considered as a signal of 1 CLK.
(A) an output clock signal CLK input from the T-CON circuit 13a to the synchronization circuit 14a;
(B) an output synchronization signal VSYNC input from the T-CON circuit 13a to the synchronization circuit 14a;
(C) an output clock signal CLK output from the synchronization circuit 14a to the synchronization circuit 14b;
(D) an output synchronization signal VSYNC output from the synchronization circuit 14a to the synchronization circuit 14b;
(E) an output clock signal CLK (including a transmission delay between T-CON boards) input to the synchronization circuit 14b;
(F) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14b;
(G) an output clock signal CLK output from the synchronization circuit 14b to the T-CON circuits 13c and 13d;
(H) an output clock signal CLK output from the synchronization circuit 14b to the synchronization circuit 14c;
(I) an output synchronization signal VSYNC output from the synchronization circuit 14b to the synchronization circuit 14c;
(J) Output clock signal CLK (including transmission delay between T-CON boards) input to the synchronization circuit 14c,
(K) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14c,
(L) Output clock signal CLK output from the synchronization circuit 14c to the T-CON circuits 13e and 13f,
(M) an output clock signal CLK output from the synchronization circuit 14c to the synchronization circuit 14d;
(N) an output synchronization signal VSYNC output from the synchronization circuit 14c to the synchronization circuit 14d;
(O) Output clock signal CLK (including transmission delay between T-CON boards) input to the synchronization circuit 14d,
(P) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14d,
(Q) an output clock signal CLK output from the synchronization circuit 14d to the T-CON circuits 13g and 13h;
(R) An output synchronization signal VSYNC output from the synchronization circuit 14d to the T-CON circuits 13g and 13h.

  As shown in FIG. 5, the output clock signal and the output synchronization signal are gradually delayed as the T-CON boards 12a, 12b, 12c, and 12d are sequentially transferred.

  However, in this embodiment, the T-CON substrates 12a, 12b, 12c, and 12d are arranged side by side along the extending direction of the gate bus line. For this reason, since the distance between each T-CON board | substrate is short, the transmission delay time of an output clock signal and an output synchronizing signal is comparatively short. Since the transmission direction of the output clock signal and the output synchronization signal is the same as the extending direction of the gate bus line, the delay of the scanning signal propagating through the gate bus line and the output clock signal and output synchronization transmitted between the T-CON boards The signal delay is offset. For this reason, it is possible to minimize the deterioration of display quality due to the transmission delay of the output clock signal and the output synchronization signal.

  As a result, the output clock signal CLK of the T-CON substrates 12b to 12d can be synchronized with the output clock signal CLK of the T-CON substrate 12a, and a reduction in display quality due to a synchronization shift can be suppressed. In other words, since the operations between the T-CON substrates can be appropriately synchronized, it is possible to suppress display displacement caused by variations in the display screen update timing in the display regions 5a to 5d and to improve display quality. it can.

  In the case of a conventional display device that performs display control by dividing the display screen into four upper left, lower left, lower right, and upper right divided areas (field-shaped divided areas), each divided area has a timing control. Not only the divided areas adjacent to the transmission direction of the signals (output clock signal and output synchronization signal) but also the adjacent divided areas in the direction orthogonal to the transmission direction of the timing control signal. For this reason, when the timing control signal is sequentially transmitted to each divided region, a divided region in which the transmission delay of the timing control signal between adjacent divided regions becomes large is generated. For example, when the timing control signal is transmitted in the order of upper left → lower left → lower right → upper right, the transmission delay of the timing control signal between the upper left divided region and the upper right divided region increases. For this reason, the display timing shift is easily recognized due to the transmission delay of the timing signal, and the display quality is deteriorated.

  On the other hand, in this embodiment, each divided region is adjacent to the direction parallel to the transmission direction of the timing control signal (upstream side and / or downstream side in the transmission direction of the timing control signal) among the other divided regions. Are in contact with only the divided areas.

  For this reason, since the difference in the transmission delay amount of the timing control signal with respect to the adjacent divided areas can be reduced, it is possible to make the display timing shift caused by the transmission delay of the timing control signal less visible, and the display quality is improved. The decrease can be suppressed.

[Embodiment 2]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above-described embodiment are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 6 is an explanatory diagram showing the configuration of the control system of the television receiver 1 in the present embodiment. The configuration shown in FIG. 2 in the first embodiment is that the timing control device 10 includes (i) synchronization circuits 14e to 14h instead of the synchronization circuits 14a to 14d, and (ii) the T-CON circuit 13a. Are different in that the output clock signal and the output synchronization signal are output to the synchronization circuit 14e without being output to the T-CON circuit 13b.

  FIG. 7 is an explanatory diagram showing the configuration of the synchronization circuits 14e to 14h. As shown in this figure, the synchronization circuits 14e to 14h and the synchronization circuits 14a to 14d shown in FIG. 4 in the first embodiment are different in that a delay circuit 36 is provided instead of the buffer 34.

  The delay circuit 36 includes a shift register 37 including latch circuits 37 a to 37 d and a selector 37.

  In this embodiment, D latch circuits each having a D terminal, an STB terminal, and a Q terminal are used as the latch circuits 37a to 37d. Each of these D latch circuits outputs a high level signal from the Q terminal when (i) the input signal at the STB terminal is at a low level and the input signal at the D terminal is at a high level, and (ii) the STB When the input signal at the terminal is at a low level and the input signal at the D terminal is at a low level, a low level signal is output from the Q terminal, and (iii) When the input signal at the STB terminal is at a high level Holds the signal output from the Q terminal when the input signal is switched to the high level immediately before that until the input signal of the STB terminal is switched to the low level.

  The output clock signal CLK output from the selector 32 is input to the STB terminals of the latch circuits 37a to 37d.

  Further, the D terminal of the latch circuit 37a is connected to the T-CON circuit 13a in the case of the synchronization circuit 14e, and the synchronization circuits 14e to 14g provided in the preceding T-CON substrates 12a to 12c in the case of the synchronization circuits 14f to 14h. The output synchronization signal output from is input. The Q terminal of the latch circuit 37a is connected to the 00 terminal of the selector 37 and the D terminal of the latch circuit 37b.

  The Q terminal of the latch circuit 37b is connected to the 01 terminal of the selector 37 and the D terminal of the latch circuit 37c, and the Q terminal of the latch circuit 37c is connected to the 10 terminal of the selector 38 and the D terminal of the latch circuit 37d. The Q terminal of 37 d is connected to the 11 terminal of the selector 37.

  As a result, in each of the latch circuits 37a to 37d, the output synchronization signal is latched at the falling edge of the output clock signal.

  The selector 38 includes 00 terminal, 01 terminal, 10 terminal, and 11 terminal as input terminals, an output terminal, and a setting input terminal. The selector 37 of the synchronizing circuit 14e receives an input signal for the 00 terminal, the selector 38 of the synchronizing circuit 14e receives an input signal for the 01 terminal, and the selector 38 of the synchronizing circuit 14e receives an input signal for the 10 terminal. The selector 37 of the synchronizing circuit 14e is set to output an input signal for the 11 terminal from the output terminal. The output terminal of the selector 38 is output to each T-CON circuit provided on the same T-CON substrate as the synchronization circuit provided with the selector 38. Therefore, the output clock signal and the output synchronization signal are input to the T-CON circuits 13a to 13h from the synchronization circuits 14e to 14h provided on the same T-CON substrate as the T-CON circuit.

FIG. 8 is an explanatory diagram showing signal waveforms of the output clock signal CLK and the output synchronization signal (vertical synchronization signal) VSYNC in the synchronization circuits 14e to 14h. Specifically, FIG. 8 shows the following signal waveforms (a) to (z). However, for convenience of explanation, the output synchronization signal VSYNC is considered as a signal of 1 CLK.
(A) an output clock signal CLK input from the T-CON circuit 13a to the synchronization circuit 14e;
(B) an output synchronization signal VSYNC input from the T-CON circuit 13a to the synchronization circuit 14e;
(C) an output clock signal CLK output from the synchronization circuit 14e to the T-CON circuits 13a and 13b;
(D) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14e;
(E) an output synchronization signal VSYNC output from the buffer 35 of the synchronization circuit 14e;
(F) an output synchronization signal VSYNC input from the synchronization circuit 14e to the T-CON circuits 13a and 13b;
(G) an output clock signal CLK output from the synchronization circuit 14e to the synchronization circuit 14f;
(H) an output clock signal CLK (including a transmission delay between T-CON boards) input to the synchronization circuit 14f;
(I) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14f.
(J) an output clock signal CLK output from the synchronization circuit 14f to the T-CON circuits 13c and 13d,
(K) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14f,
(L) an output synchronization signal VSYNC output from the buffer 35 of the synchronization circuit 14f,
(M) an output synchronization signal VSYNC input from the synchronization circuit 14f to the T-CON circuits 13c and 13d,
(N) an output clock signal CLK output from the synchronization circuit 14f to the synchronization circuit 14g;
(O) Output clock signal CLK (including transmission delay between T-CON boards) input to the synchronization circuit 14g,
(P) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14g,
(Q) an output clock signal CLK output from the synchronization circuit 14g to the T-CON circuits 13e and 13f,
(R) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14g,
(S) an output synchronization signal VSYNC output from the buffer 35 of the synchronization circuit 14g,
(T) an output synchronization signal VSYNC input from the synchronization circuit 14g to the T-CON circuits 13e and 13f,
(U) an output clock signal CLK output from the synchronization circuit 14g to the synchronization circuit 14h;
(V) an output clock signal CLK (including a transmission delay between T-CON boards) input to the synchronization circuit 14h;
(W) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14h,
(X) an output clock signal CLK output from the synchronization circuit 14h to the T-CON circuits 13g and 13h;
(Y) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14h;
(Z) An output synchronization signal VSYNC input from the synchronization circuit 14h to the T-CON circuits 13g and 13h.

  As described above, in this embodiment, the output synchronization signal sequentially transmitted to the T-CON substrates 12a to 12d is latched by the output clock signal CLK sequentially transmitted to the T-CON substrates 12a to 12d, and each T-CON The output synchronization signal output from the synchronization circuits 14e to 14g of the CON substrates 12a to 12c is delayed by the delay circuit 36 and synchronized with the output synchronization signal output from the synchronization circuit 14g of the T-CON substrate 12d arranged at the final stage. Let

  Thereby, the operation | movement between each T-CON board | substrate can be synchronized more appropriately. That is, in this embodiment, since the transmission of the output clock signal CLK between the T-CON boards is performed by differential transmission, the T-CON circuits 13c to 13h are provided from the differential signals in each T-CON board. Since it is necessary to convert the signal level (for example, CMOS signal level) according to the operation characteristics of the member into the signal and vice versa, the output clock signal and the output synchronization signal are increased as transmission between the T-CON boards is repeated. The phase shift between and increases.

  On the other hand, in the present embodiment, the output synchronization signal is latched by the output clock signal in each T-CON board, and the output clock signal is synchronized by the delay circuit 36 by synchronizing the output synchronization signal of each T-CON board. And the output synchronization signal can be suppressed, and the operations between the T-CON substrates can be more appropriately synchronized.

[Embodiment 3]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above-described embodiment are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 9 is an explanatory diagram showing the configuration of the control system of the television receiver 1 in the present embodiment. As shown in this figure, the control system of the television receiver 1 according to the present embodiment includes synchronization circuits 14i to 14l instead of the synchronization circuits 14e to 14h illustrated in FIGS. 6 and 7 in the second embodiment. ing.

  FIG. 10 is an explanatory diagram illustrating a configuration of the synchronization circuits 14i to 14l provided in the T-CON boards 12a to 12d in the timing control device 10 of the television receiver 1 of the present embodiment. As shown in this figure, the synchronization circuits 14i to 14l include a phase correction circuit 39 on the output side of the selector 32 in addition to the configuration of the synchronization circuits 14e to 14h.

  The phase correction circuit 39 corrects the phase of the output clock signal CLK output from the selector 32, including the transmission delay associated with the transmission between the T-CON boards. In addition, the phase correction circuit 39 includes the output clock signal CLK after phase correction on the same T-CON substrate as the latch circuits 37 a to 37 d of the delay circuit 36, the differential signal generation unit 33, and the phase correction circuit 39. Output to each T-CON circuit.

  FIG. 11 is an explanatory diagram showing the configuration of the phase correction circuit 39. As shown in this figure, the phase correction circuit 39 includes a PLL circuit 41, a shift register 42 including a plurality of latch circuits 42a to 42i (i is an arbitrary integer), and a selector 43. The PLL circuit 41 creates a multiplied wave of the output clock signal CLK input from the selector 32, and outputs it to the latch circuits 42a to 42i. Each of the latch circuits 42 a to 42 i latches the output clock signal CLK input from the selector 32 according to the multiplied wave input from the PLL circuit 41. The output clock signal CLK latched by the latch circuits 42 a to 42 i is input to the selector 43. The selector 43 selects the output clock signal CLK for synchronizing with the phase of the output clock signal CLK output from the T-CON circuit 13a among the output clock signals CLK output from the latch circuits 42a to 42i, and delays the delay circuit. 36, the differential signal generation unit 33, and the selector 43 output to each T-CON circuit provided on the same T-CON substrate.

FIG. 12 is an explanatory diagram showing signal waveforms of the output clock signal CLK and the output synchronization signal (vertical synchronization signal) VSYNC in the synchronization circuits 14i to 14l. Specifically, FIG. 12 shows the following signal waveforms (a) to (D). However, for convenience of explanation, the output synchronization signal VSYNC is considered as a signal of 1 CLK.
(A) an output clock signal CLK input from the T-CON circuit 13a to the synchronization circuit 14i;
(B) an output synchronization signal VSYNC input from the T-CON circuit 13a to the synchronization circuit 14i;
(C) an output clock signal input to the phase correction circuit 39 of the synchronization circuit 14i;
(D) an output clock signal output from the phase correction circuit 39 of the synchronization circuit 14i to the T-CON circuits 13a and 13b and the differential signal generation unit 33;
(E) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14i;
(F) an output synchronization signal VSYNC output from the buffer 35 of the synchronization circuit 14i to the synchronization circuit 14j;
(G) an output synchronization signal VSYNC input from the synchronization circuit 14i to the T-CON circuits 13a and 13b;
(H) an output clock signal CLK output from the synchronization circuit 14i to the synchronization circuit 14j;
(I) an output clock signal CLK (including a transmission delay between T-CON boards) input to the synchronization circuit 14j;
(J) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14j,
(K) an output clock signal CLK input to the phase correction circuit 39 of the synchronization circuit 14j;
(L) The output clock signal CLK output from the phase correction circuit 39 of the synchronization circuit 14j to the T-CON circuits 13c and 13d and the differential signal generation unit 33.
(M) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14j,
(N) an output synchronization signal VSYNC output from the buffer 35 of the synchronization circuit 14j to the synchronization circuit 14k;
(O) an output synchronization signal VSYNC input from the synchronization circuit 14j to the T-CON circuits 13c and 13d,
(P) an output clock signal CLK output from the synchronization circuit 14j to the synchronization circuit 14k;
(Q) An output clock signal CLK (including a transmission delay between T-CON boards) input to the synchronization circuit 14k.
(R) Output synchronization signal VSYNC (including transmission delay between T-CON boards) input to the synchronization circuit 14k.
(S) an output clock signal CLK input to the phase correction circuit 39 of the synchronization circuit 14k;
(T) The output clock signal CLK output from the phase correction circuit 39 of the synchronization circuit 14k to the T-CON circuits 13e and 13f and the differential signal generator 33,
(U) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14k,
(V) an output synchronization signal VSYNC output from the buffer 35 of the synchronization circuit 14k to the synchronization circuit 14l;
(W) an output synchronization signal VSYNC input from the synchronization circuit 14k to the T-CON circuits 13e and 13f,
(X) an output clock signal CLK output from the synchronization circuit 14k to the synchronization circuit 14l;
(Y) an output clock signal CLK (including a transmission delay between T-CON boards) input to the synchronization circuit 14l;
(Z) Output synchronization signal VSYNC (including a transmission delay between T-CON boards) input to the synchronization circuit 14l;
(A) an output clock signal CLK input to the phase correction circuit 39 of the synchronization circuit 14l,
(B) An output clock signal CLK output from the phase correction circuit 39 of the synchronization circuit 14k to the T-CON circuits 13g and 13h.
(C) an output synchronization signal VSYNC output from the latch circuit 37a of the synchronization circuit 14k,
(D) An output synchronization signal VSYNC input from the synchronization circuit 14k to the T-CON circuits 13g and 13h.

  As described above, in this embodiment, in addition to the configuration shown in the second embodiment, the synchronization circuits 14i to 14l of the T-CON substrates 12a to 12d synchronize the phase of the input output clock signal CLK. The phase correction circuit 39 is provided.

  Thereby, since the phase of the output clock signal in each T-CON board | substrate can be synchronized, the operation | movement between each T-CON board | substrate can be synchronized more appropriately. In the present embodiment, the configuration including four T-CON substrates has been described. However, the present invention is not limited to this, and in principle, each T-CON substrate can be connected to any number of T-CON substrates. The phase of the output clock signal can be synchronized.

[Summary]
The timing control device 10 according to the first aspect of the present invention includes a circuit board (T-CON board 12a) including timing controller circuits (T-CON circuits 13a to 13h) that control the operation timing of the display device 2 based on a timing control signal. To 12d), the circuit board (T-CON boards 12a to 12d) includes a plurality of display regions of the display device 2 arranged in the extending direction of the scanning signal lines. Each of the circuit boards (T-CON boards 12a to 12d) is arranged in the extending direction of the scanning signal lines, and is provided for each of the divided areas (display areas 5a to 5d). A circuit board in which a timing control signal is arranged on one end side of the scanning signal line in the extending direction of the plurality of circuit boards (T-CON boards 12a to 12d). It is characterized by being sequentially transmitted towards the circuit board disposed at the other end (T-CON substrate 12d) from (T-CON substrate 12a).

  According to said structure, the timing control signal for controlling the operation timing of the display apparatus 2 is arrange | positioned from the circuit board (T-CON board | substrate 12a) arrange | positioned at the one end side of the extending | stretching direction of a scanning signal line to the other end side. The signals are sequentially transmitted toward the circuit board (T-CON board 12d). That is, the timing control signal is sequentially transmitted in the same direction as the transmission direction of the scanning signal transmitted through the scanning signal line. As a result, the delay of the timing control signal accompanying the transmission between the circuit boards and the delay of the scanning signal transmitted through the scanning signal lines can be offset, so that each circuit board (T-CON boards 12a to 12d) It is possible to appropriately synchronize the operation with a simple configuration, and to suppress the deterioration in display quality due to the deviation between the timing control signal and the scanning signal.

  In the timing control device 10 according to the second aspect of the present invention, in the first aspect, the timing control signal includes the clock signal CLK and the synchronization signal VSYNC, and the circuit board (T-CON boards 12a to 12d). ) Latches the synchronization signal VSYNC based on the clock signal CLK, and the latched synchronization signal VSYNC is disposed on the most downstream side in the transmission direction of the timing control signal (T-CON substrate 12d). Is provided with a delay circuit 36 that outputs at a timing synchronized with the output timing of the synchronization signal VSYNC.

  According to said structure, the output timing of the synchronizing signal from each circuit board (T-CON board | substrates 12a-12d) is sent from the said circuit board (T-CON board | substrate 12d) arrange | positioned most downstream in the transmission direction. Since it is possible to match the output timing of the synchronization signal, it is possible to appropriately suppress the deterioration of display quality due to the synchronization signal shift.

  In the aspect 2, the timing control device 10 according to the aspect 3 of the present invention transmits data from other circuit boards (T-CON boards 12a to 12c) among the plurality of circuit boards (T-CON boards 12a to 12d). The circuit boards (T-CON boards 12b to 12d) that receive the timing control signals to be transmitted have the phases of the clock signals CLK output from the circuit boards (T-CON boards 12b to 12d) determined by the timing control signals. In this configuration, a phase correction circuit 39 that corrects the phase of the clock signal CLK output from the circuit board (T-CON board 12a) arranged on the most upstream side in the transmission direction is provided.

  According to said structure, since the phase of the clock signal output from each circuit board can be synchronized, the fall of the display quality resulting from a synchronization shift can be suppressed more appropriately.

  In the timing control device 10 according to the aspect 4 of the present invention, in any one of the aspects 1 to 3, the timing control signal includes a clock signal CLK and a synchronization signal VSYNC, and the clock signal CLK The circuit board is transmitted by differential transmission between circuit boards (between T-CON boards 12a-12b, between T-CON boards 12b-12c, and between T-CON boards 12c-12d).

  According to said structure, deterioration of the clock signal by the noise accompanying the transmission between circuit boards can be prevented, and each circuit board can be operated correctly.

  The timing control device 10 according to the fifth aspect of the present invention is the timing control device 10 according to any one of the first to fourth aspects, wherein each of the circuit boards (T-CON boards 12a to 12d) includes the timing controller circuit (T-CON circuits 13a to 13h). ).

  According to the above configuration, the delay of the timing control signal transmitted to each timing controller circuit (T-CON circuits 13a to 13h) and the delay of the scanning signal transmitted through the scanning signal line can be offset. In addition, it is possible to suppress a decrease in display quality due to a shift between the timing control signal and the scanning signal with a simple configuration.

  The timing control device according to aspect 6 of the present invention is the timing control device according to any one of the aspects 1 to 5, wherein each of the divided areas (display areas 5a to 5d) is in the transmission direction of the timing control signal among other divided areas. In this configuration, only the divided areas arranged adjacent to each other in the parallel direction are in contact with each other.

  According to said structure, since the difference of the transmission delay amount of the timing control signal between adjacent division areas can be made small, the fall of the display quality by the transmission delay of a timing control signal can be suppressed.

  A display device 2 according to an aspect 7 of the present invention includes the timing control device 10 according to any one of the above aspects 1 to 6.

  According to said structure, the fall of the display quality by the shift | offset | difference of a timing control signal and a scanning signal can be suppressed.

  The television receiver 1 according to the eighth aspect of the present invention is configured to include the display device 2 according to the seventh aspect.

  According to said structure, the fall of the display quality by the shift | offset | difference of a timing control signal and a scanning signal can be suppressed.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

DESCRIPTION OF SYMBOLS 1 Television receiver 2 Display apparatus 5 Liquid crystal display panels 5a-5d Display area (divided area)
6 Gate drivers 7a to 7d Source driver 10 Timing control device 11 Video processing board 12a T-CON board (master T-CON board)
12b-12d T-CON board (slave T-CON board)
13a T-CON circuit (master T-CON circuit)
13b to 13h T-CON circuit (slave T-CON circuit)
14a to 14l Synchronous circuit 31 Differential signal restoration unit 33 Differential signal generation unit 34, 35 Buffer 36 Delay circuit 39 Phase correction circuit CLK Output clock signal (clock signal)
VSYNC output synchronization signal (synchronization signal)

Claims (8)

A timing control device for a display device comprising a plurality of circuit boards having a timing controller circuit for controlling the operation timing of the display device based on a timing control signal,
The circuit board is provided for each divided area obtained by dividing the display area of the display device into a plurality of areas arranged in the extending direction of the scanning signal lines, and the circuit boards are arranged in the extending direction of the scanning signal lines. Has been
The timing control signal is sequentially transmitted from the circuit board arranged on one end side in the extending direction of the scanning signal line toward the circuit board arranged on the other end side of the plurality of circuit boards. Timing control device. The timing control signal includes a clock signal and a synchronization signal,
The circuit board latches the synchronization signal based on the clock signal, and the output timing of the synchronization signal from the circuit board disposed on the most downstream side in the transmission direction of the timing control signal. The timing control device according to claim 1, further comprising a delay circuit that outputs at a timing synchronized with the timing control circuit. Among the plurality of circuit boards, a circuit board that receives the timing control signal transmitted from another circuit board is:
A phase correction circuit for correcting the phase of the clock signal output from the circuit board so as to coincide with the phase of the clock signal output from the circuit board disposed on the most upstream side in the transmission direction of the timing control signal The timing control device according to claim 2, further comprising: The timing control signal includes a clock signal and a synchronization signal,
4. The timing control device according to claim 1, wherein the clock signal is transmitted between the circuit boards by differential transmission. 5.   5. The timing control apparatus according to claim 1, wherein each of the circuit boards includes a plurality of the timing controller circuits. 6.   Each of the divided areas is in contact with only divided areas arranged adjacent to each other in a direction parallel to the transmission direction of the timing control signal among other divided areas. The timing control device according to claim 1.   A display device comprising the timing control device according to claim 1.   A television receiver comprising the display device according to claim 7.

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