JP2017059689A - Imaging element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging element which is high in performance and suitable for miniaturization.SOLUTION: A solid-state imaging device 1 includes a first electrode 115, a second electrode 112, a photoelectric conversion layer 114 which is disposed between the first electrode 115 and the second electrode 112 and is made of an organic film, a charge accumulation layer 113 which is disposed between the photoelectric conversion layer 114 and the second electrode 112 and accumulates charges generated by the photoelectric conversion layer 114, a first element 101 for generating a control signal for resetting the charges accumulated in the charge accumulation layer 113, a second element 102 to which a charge signal indicating the charges accumulated in the charge accumulation layer 113 is input, and pixel signal wires 107, 108, 109, and 111 for connecting the first element 101, the second element 102, and the second electrode 112.SELECTED DRAWING: Figure 5

Description

  Embodiments described herein relate generally to an image sensor.

  As the photoelectric conversion layer provided in the solid-state imaging device, an organic film having high light absorption efficiency is used.

  For example, a photoelectric conversion region made of an organic layer, a first contact for transmitting an electrical signal (charge signal) generated in the photoelectric conversion region, and a first electrode for transmitting a control signal for controlling the timing of reading the charge signal And a solid-state imaging device that includes an insulating layer disposed between the photoelectric conversion region and the first electrode, and the first contact and the first electrode are formed of different members.

US Patent Application Publication No. 2013/0093932

  Along with downsizing of imaging devices, improvement of processing capability, and storage capacity increase, downsizing and high performance of imaging devices are required. In the conventional configuration in which the electrode for transmitting the charge signal and the electrode for transmitting the control signal are formed of different members, it is difficult to reduce the size of the element.

  In view of the above, an object of the following embodiments is to provide an imaging device that is high-performance and suitable for downsizing.

  The imaging device according to the embodiment includes a first electrode, a second electrode, a photoelectric conversion layer made of an organic film, a photoelectric conversion layer, and a second electrode, disposed between the first electrode and the second electrode. A charge storage layer that is disposed between the first electrode and the charge conversion layer and stores a charge generated by the photoelectric conversion layer; a first element that generates a control signal for resetting the charge stored in the charge storage layer; A second element to which a charge signal indicating the electric charge accumulated in the accumulation layer is input, and a pixel signal wiring that connects the first element, the second element, and the second electrode, To do.

FIG. 3 is a diagram illustrating a configuration of a solid-state imaging element according to the first embodiment. The figure which illustrates the manufacturing process of the solid-state image sensing device concerning a 1st embodiment. The figure which illustrates the manufacturing process of the solid-state image sensing device concerning a 1st embodiment. The figure which illustrates the manufacturing process of the solid-state image sensing device concerning a 1st embodiment. The figure which illustrates the manufacturing process of the solid-state image sensing device concerning a 1st embodiment. FIG. 3 is a diagram illustrating a circuit configuration of a pixel according to the first embodiment. The graph which illustrates the relationship between the applied voltage and current density of the organic photoelectric conversion structure concerning 1st Embodiment. The graph which illustrates the energy band figure and voltage application state of the organic photoelectric conversion structure concerning 1st Embodiment. The graph which illustrates the energy band figure and voltage application state of the organic photoelectric conversion structure concerning 1st Embodiment. The graph which illustrates the energy band figure and voltage application state of the organic photoelectric conversion structure concerning 1st Embodiment. The graph which illustrates the energy band figure and voltage application state of the organic photoelectric conversion structure concerning 1st Embodiment. 6 is a graph illustrating the relationship between the incident light amount and the vacuum level shift amount in the solid-state imaging device according to the first embodiment. The graph which illustrates the application state of each bias seen from the electric current and voltage characteristic of the organic photoelectric conversion structure concerning 1st Embodiment. FIG. 3 is a diagram illustrating a circuit configuration of a pixel according to the first embodiment and a bias name of each node. FIG. 3 is a diagram illustrating a timing chart when a charge signal is read out in the solid-state imaging device according to the first embodiment. The figure which illustrates the timing chart at the time of reading an electric charge signal in the solid-state image sensor concerning 2nd Embodiment. The figure which illustrates the composition of the solid-state image sensing device concerning a 3rd embodiment. FIG. 10 is a diagram illustrating a timing chart when a charge signal is read out in the solid-state imaging device according to the third embodiment. The figure which illustrates the composition of the semiconductor chip concerning a 4th embodiment. The figure which illustrates the composition of the personal digital assistant concerning a 5th embodiment. The figure which illustrates the structure of the motor vehicle concerning 6th Embodiment.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of a solid-state imaging device 1 according to the first embodiment. The solid-state imaging device 1 includes a pixel array 11, a vertical shift register 12, a horizontal shift register 13, row selection lines 14A, 14B, and 14C, pulse power supply lines 15A, 15B, and 15C, column selection lines 16A, 16B, and 16C, and a correlated double. Sampling (CDS: Correlated Double Sampling) circuits 17A, 17B, 17C, analog-to-digital converter (ADC) 18A, 18B, 18C, output bus 19, and constant current circuits 20A, 20B, 20C Including.

  The pixel array 11 is an area where a plurality of pixels 21 are arranged in an array. In FIG. 1, a configuration having 3 × 3 pixels is shown for ease of explanation, but the configuration of the pixel array 11 is not limited to this.

  First, one row selection line 14A is selected from the plurality of row selection lines 14A to 14C by the vertical shift register 12. The charge signals of the pixels 21A, 21B, and 21C connected to the selected row selection line 14A are output to the column selection lines 16A to 16C. The charge signal is a signal indicating the amount of electricity generated by photoelectric conversion of incident light. After the noise is removed by the CDS circuits 17A to 17C, the charge signals are converted into 10-bit digital signals by the ADCs 18A to 18C. The converted digital signal is output to the outside of the solid-state imaging device 1 through the output bus 19 for each column selected by the horizontal shift register 13. The constant current sources 20A to 20C perform a source follower operation with an amplifier transistor in each pixel 21. The vertical shift register 12 also selects the pulse power supply lines 15 </ b> A to 15 </ b> C for controlling the operation of reading the charge signal from the pixel 21.

  2-5 is a figure which illustrates the manufacturing process of the solid-state image sensor 1 concerning 1st Embodiment. First, as shown in FIG. 2, a reset transistor 101, an amplifier transistor 102, and an isolation region 103 are formed on a single crystal silicon substrate 100 using a normal LSI (Large Scale Integration) manufacturing process.

  Next, as shown in FIG. 3, a first intermediate layer 104 is formed on the silicon substrate 100. The first intermediate layer 104 is formed by depositing a silicon oxide film to a thickness of about 500 nm by using, for example, a chemical vapor deposition (CVD) method.

  Next, a first contact via 107 connected to the source-side diffusion layer 105 of the reset transistor 101 and a second contact via 108 connected to the gate 106 of the amplifier transistor 102 are formed. The contact vias 107 and 108 are formed by forming an opening in the first intermediate layer 104 using, for example, a photolithography technique and a reactive ion etching (RIE) method, and then using the CVD method. Tungsten is deposited and the surface thereof is planarized by using a chemical mechanical polishing (CMP) method.

  Next, as shown in FIG. 4, a first wiring layer 109 is formed on the first intermediate layer 104. The first wiring layer 109 is formed by, for example, depositing aluminum to a thickness of about 300 nm using a sputtering method and then forming a wiring pattern using a photolithography technique and an RIE method. The first wiring layer 109 is connected to the first contact via 107 and the second contact via 108.

  Next, the second intermediate layer 110 is formed over the first intermediate layer 104 and the first wiring layer 109. The formation of the second intermediate layer 110 is performed by depositing a silicon oxide film to a thickness of about 2000 nm using, for example, a CVD method.

  Next, a through via 111 is formed in the second intermediate layer 110. The through via 111 is formed by, for example, forming an opening in the second intermediate layer 110 using a photolithography technique and an RIE method, depositing tungsten in the opening using a CVD method, and planarizing the surface using a CMP method. This is done by

  The source side diffusion layer 105 of the reset transistor 101, the gate 106 of the amplifier transistor 102, the first contact via 107, the second contact via 108, the first wiring layer 109, and the through via 111 are collectively referred to as a pixel signal wiring. .

  Next, a lower electrode 112 (second electrode) is formed on the upper end portion of the second intermediate layer 110. The lower electrode 112 is formed by forming a groove pattern with a depth of about 300 nm in the second intermediate layer 110 using, for example, a photolithography technique and an RIE method, depositing tungsten on the groove pattern using a CVD method, and performing CMP. This is done by flattening the surface using a method.

  The lower electrode 112 is not limited to tungsten, and ITO, Al, TiN, or the like can also be used.

  Next, the charge storage layer 113 is formed on the lower electrode 112. In this embodiment, the charge storage layer 113 is a tungsten oxide layer. For example, a tungsten natural oxide film having a thickness of about 25 nm can be formed by depositing tungsten and exposing it to the atmosphere for several days. Further, after the tungsten film is formed, the tungsten oxide layer can also be formed by oxygen annealing, oxygen plasma treatment, or sputter film formation in an oxygen and argon atmosphere using a tungsten target.

As the charge storage layer 113, a binary transition metal oxide such as MoO _x , TiO _x , HfO _x , WO _x or the like (X is a natural number), or STO (strontium titanate: SrTiO ₃ ), BTO (barium titanate: BaTiO ₃ ). Perovskite type oxides such as ₃ ) can be used. At this time, since it also has ferroelectricity, it is desirable that the oxygen valence (X) of WO _x is 3. The charge storage layer 113 can also be formed on the lower electrode 112 by using a sputtering method, a vapor deposition method, an atomic layer deposition method, or the like.

  Next, as shown in FIG. 5, a photoelectric conversion layer 114 made of an organic film is formed on the lower electrode 112. The photoelectric conversion layer 114 is formed by forming a co-deposited film of dimethylquinacridone and subphthalocyanine to a thickness of about 200 nm using, for example, a vacuum deposition method.

  Next, the upper electrode 115 (first electrode) is formed over the photoelectric conversion layer 114. The upper electrode 115 is formed by, for example, forming an ITO (Indium Tin Oxide) film to be a transparent electrode with a thickness of about 50 nm using a sputtering method, and etching by RIE using a lithography technique, hydrogen iodide, and argon gas. And patterning the ITO film in a line.

  Next, a protective film 116 is formed on the upper electrode 115. The protective film 116 is formed by forming a silicon nitride film with a thickness of about 400 nm by using, for example, a CVD method.

  The transmittance of the upper electrode 115 and the protective film 116 is preferably 90% or more in the wavelength range of 400 nm to 700 nm.

  The lower electrode 112, the charge storage layer 113, the photoelectric conversion layer 114, the upper electrode 115, and the protective film 116 are referred to as an organic photoelectric conversion structure 117.

  The photoelectric conversion layer 114 can be, for example, a p-type organic semiconductor single layer, an n-type organic semiconductor layer single layer, or a mixed film of a p-type organic semiconductor layer and an n-type organic semiconductor layer. The mixed film may be, for example, a stacked structure of a p-type organic semiconductor layer and an n-type organic semiconductor layer, or a mixed structure in which a p-type organic semiconductor layer and an n-type organic semiconductor layer are mixedly coated or co-deposited.

  As p-type organic semiconductors and n-type organic semiconductors, “amine derivatives”, “quinacridone derivatives”, “naphthalene derivatives”, “anthracene derivatives”, “phenanthrene derivatives”, “tetracene derivatives”, “pyrene derivatives”, “perylene derivatives” , "Fluoranthene derivatives", "phenylene vinylene, fluorene, carbazole, indole, pyrene, pyrrole, picoline, thiophene, acetylene, or diacetylene polymers and derivatives thereof", "dithiol metal complex dyes", "metal phthalocyanine dyes" , “Metal porphyrin dyes”, “ruthenium complex dyes”, “cyanine dyes”, “merocyanine dyes”, “phenylxanthene dyes”, “triphenylmethane dyes”, “rhodocyanine dyes”, “xanthene dyes” "," Macrocyclic Azaa "Len dyes", "Azulene dyes", "Naphthoquinones", "Anthraquinone dyes", "Linear compounds condensed with condensed polycyclic aromatic, aromatic or heterocyclic compounds such as anthracene and pyrene", "Squarylium Quinoline having a croconic methine group and a croconic methine group "," cyanine-like dyes linked by two nitrogen-containing heterocycles such as benzothiazole and benzoxazole, or squarylium group and croconic methine group " Can do. As the n-type organic semiconductor, “fullerene such as C60 and C70 and derivatives thereof” can be used.

  From the viewpoint of photoelectric conversion efficiency, the photoelectric conversion layer 114 is preferably a mixed film of a p-type organic semiconductor and an n-type organic semiconductor. In this case, the p-type organic semiconductor is preferably a derivative or polymer containing amine, quinacridone, thiophene, carbazole, or the like, and the n-type organic semiconductor is preferably a perylene derivative, a naphthalene derivative, a thiophene derivative, or a fullerene derivative.

  FIG. 6 is a diagram illustrating a circuit configuration of the pixel 21A according to the first embodiment. The amplifier transistor 102 (second element) is a transistor to which a charge signal indicating the charge accumulated in the charge accumulation layer 113 is input. The amplifier transistor 102 outputs in accordance with the potential of the pixel signal wiring 118 (the source side diffusion layer 105, the gate 106, the first contact via 107, the second contact via 108, the first wiring layer 109, and the through via 111). Do. Note that an element to which a charge signal is input is not limited to this.

  The reset transistor 101 (first element) is a transistor that generates a control signal for resetting the charge accumulated in the charge accumulation layer 113. The reset transistor 101 serves as a constant current source for supplying a constant current to the organic photoelectric conversion structure 117 (the lower electrode 112, the charge storage layer 113, the photoelectric conversion layer 114, the upper electrode 115, and the protective film 116). The element that generates the control signal is not limited to this.

  A positive and negative voltage is applied from the pulse power source 139 to the upper electrode 115 of the organic photoelectric conversion structure 117. The selection transistor 140 performs sequential readout by switching the output of the signal of the pixel 21A selected by the row selection line 14A. The output from the amplifier transistor 102 is output to the column selection line 16A.

  Hereinafter, the function and effect of the charge storage layer 113 in the organic photoelectric conversion structure 117 will be described with reference to FIGS. FIG. 7 is a graph illustrating the relationship between applied voltage and current density (dependence of current-voltage characteristics on incident light amount) of the organic photoelectric conversion structure 117 according to the first embodiment. The vertical axis in FIG. 7 represents the logarithm of the absolute value of the current value. The point indicated by the arrow 51 (Vrst) and the points indicated by the arrows 52A and 52B (Vsig_1.2 and Vsig_187) indicate that the direction of the current flowing through the organic photoelectric conversion structure 117 is reversed.

  8A to 8D are graphs illustrating an energy band diagram and a voltage application state of the organic photoelectric conversion structure 117. The positive side of the graph of FIG. 7 is the forward bias side (plus voltage (+ Vf) is applied to the W electrode side of FIGS. 8A to 8D), and the negative side is the reverse bias side (to the W electrode side of FIGS. 8A to D). Minus voltage (-Vr) is applied).

  When a voltage sweep is performed from the + Vf side to the −Vr side, the direction of the current is inverted in the + Vf region, but this inverted voltage value (Vrst) is substantially equal to the photovoltaic power of the photoelectric conversion layer 114. As shown in FIGS. 8A and 8B, the interface charge pair due to the injection of dark current charge e (electrons) from the lower electrode (W) 112 to the charge storage layer 113 is released by + Vf application, and the vacuum level shift occurs. This is considered to be because a HOMO (Highest Occupied Molecular Orbital) -LUMO (Lowest Unoccupied Molecular Orbital) energy difference between the p-type and n-type organic semiconductors constituting the photoelectric conversion layer 114 appears. Therefore, when a voltage sweep is performed from the + Vf side to the −Vr side, a constant value unique to the material that does not depend on external conditions such as the amount of incident light appears, and the charge storage layer 113 is reset.

  When a voltage sweep is performed from the −Vf side to the + Vr side, the current direction is reversed in the −Vf region. This is presumably because, as shown in FIG. 8B, an interface charge pair is generated by injection of dark current charges (electrons) from the lower electrode 112 into the charge storage layer 113, and a vacuum level shift occurs. At this time, as shown in FIG. 7, the amount of shift in the vacuum level shows dependency on the amount of incident light. The reason is considered as follows. When the amount of incident light is small (FIG. 8C), the photocharge generated in the photoelectric conversion layer 114 (hole h shown with a square frame) passes through the valence band of the charge storage layer 113 and then reaches the lower electrode (W) 112. It reaches. Therefore, the influence of the vacuum level shift occurs. On the other hand, when the amount of incident light is large (FIG. 8D), the photocharge generated in the photoelectric conversion layer 114 (hole h shown with a square frame) is directly below the valence band of the charge storage layer 113 because it is filled with holes. The electrode (W) 112 is reached. Therefore, the influence of the vacuum level shift is reduced. As the amount of incident light increases, the apparent vacuum level shift amount (Vrst−Vsig) decreases.

  FIG. 9 is a graph illustrating the relationship (incident light amount dependency) between the incident light amount and the vacuum level shift amount (Vrst−Vsig). The vacuum level shift amount ΔV = Vrst−Vsig shows a sufficiently large value for light detection, and shows a dependency that monotonously decreases with respect to the amount of incident light. As shown in FIG. 9, the amount of vacuum level shift is larger when the amount of incident light is smaller than when the amount of incident light is large. Therefore, according to the fixed imaging device 1 including the organic photoelectric conversion structure 117 according to the present embodiment, the dynamic range can be expanded.

The amount of vacuum level shift depends on the amount of charge injected into the charge storage layer 113. Accordingly, the amount of vacuum level shift can be arbitrarily adjusted by changing the ratio of the area of the charge storage layer 113 to the lower electrode 112. Therefore, according to the fixed imaging device 1 including the organic photoelectric conversion structure 117 according to the present embodiment, the gain value can be easily designed. The ratio of the area of the charge storage layer 113 to the lower electrode 112 is preferably about 40%, for example. The area of the charge storage layer 113 can be adjusted by changing the process conditions such as the oxidation time, the O ₂ flow rate, and the plasma conditions in the surface oxidation process, patterning using photolithography and etching, and the like.

  Hereinafter, a method for reading a charge signal from the pixel 21A will be described with reference to FIGS. FIG. 10 is a graph illustrating the application state of each bias as viewed from the current / voltage characteristics of the organic photoelectric conversion structure 117 according to the first embodiment. In this example, the vacuum level shift amount (Vrst−Vsig) when a constant current is applied is read out as a charge signal. FIG. 11 is a diagram illustrating a circuit configuration of the pixel 21A according to the first embodiment and a bias name of each node. FIG. 12 is a diagram illustrating a timing chart when the charge signal is read in the solid-state imaging device 1 according to the first embodiment. In FIG. 12, the bias name written at the left end corresponds to the bias name of each node shown in FIG.

  First, a negative voltage is applied to the upper electrode 115 by the pulse power source 139. As a result, a forward bias is applied to the organic photoelectric conversion structure 117 and the injected charge in the charge storage layer 113 is reset. This reset operation may be performed immediately before the read timing, or may be performed as a so-called electronic shutter a plurality of rows before the read timing as shown in FIG.

  Next, a positive voltage is applied to the upper electrode 115 by the pulse power source 139. As a result, a reverse bias is applied to the organic photoelectric conversion structure 117, charges are injected into the charge storage layer 113, and photoelectric conversion by the photoelectric conversion layer 114 is performed. Here, no accumulation operation is required, and a change in the amount of current at the time of light incidence is read. Reading is possible after charge injection into the charge storage layer 113 is completed and stabilized.

  Next, after the selection transistor 140 is turned on and a charge signal can be output to the column selection line 16A, the gate bias of the reset transistor 101 is set so as to obtain a predetermined constant current. As a result, the potential of the gate node of the amplifier transistor 102 becomes Vsig which is the output value of the charge signal. This output value Vsig is stored in the CDS circuit 17A via the column selection line 16A.

  After that, by applying a negative voltage to the upper electrode 115 again by the pulse power source 139, a forward bias is applied to the organic photoelectric conversion structure 117, and the injected charge in the charge storage layer 113 is reset. At this time, the gate bias of the reset transistor 101 is set so as to obtain a predetermined constant current so that the reset potential Vrst as the gate node potential of the amplifier transistor 102 is output. Then, this output value Vrst is sent to the CDS circuit 17A via the column selection line 16A, so that the vacuum level shift amount Vrst−Vsig is obtained.

  The gate voltage of the amplifier transistor 102 at the time of reset read may be a negative voltage. In this case, a normally-on type transistor may be used as the amplifier transistor 102.

  According to the fixed imaging element 1, the electrode connected to the reset transistor 101 and the electrode connected to the amplifier transistor 102 are configured by a common member (first wiring layer 109, through via 111, and lower electrode 112). Therefore, downsizing becomes easy. Further, since the vacuum level shift amount becomes larger when the incident light amount is smaller than when the incident light amount is large, the dynamic range can be expanded. Further, since the amount of vacuum level shift can be arbitrarily adjusted by changing the ratio of the area of the charge storage layer 113 to the lower electrode 112, the gain value can be easily designed. From the above, according to the above-described embodiment, it is possible to provide an image sensor that has high performance and is suitable for downsizing.

  Hereinafter, other embodiments will be described with reference to the drawings, but the same or similar portions as those of the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.

(Second Embodiment)
FIG. 13 is a diagram illustrating a timing chart when a charge signal is read out in the solid-state imaging device according to the second embodiment.

  In the second embodiment, the charge storage layer 113 is reset based on the pulse voltage output from the pulse power source 139 and the voltage output from the reset transistor 101.

  The Vpulse waveform of the timing chart according to the second embodiment shown in FIG. 13 is different from the timing chart according to the first embodiment shown in FIG. In the second embodiment, the negative bias is not applied to the pulse power source 139 at the time of reset (electronic shutter) and charge readout, and a pulse of +3.3 V is supplied by the reset transistor 101. Thereby, the same effect as 1st Embodiment can be acquired, and a negative power supply can be deleted from a circuit.

(Third embodiment)
FIG. 14 is a diagram illustrating the configuration of the solid-state imaging device 2 according to the third embodiment. FIG. 15 is a diagram illustrating a timing chart when a charge signal is read in the solid-state imaging device 2 according to the third embodiment.

  The solid-state imaging device 2 according to the third embodiment includes a pulse power supply electrode 144 made of one member connected to all the upper electrodes 115 in the pixel array 11. Based on the change in voltage output from the reset transistor 101, the charge storage layer 113 is reset.

  The solid-state imaging device 2 shown in FIG. 14 does not include the pulse power supply lines 15A to 15C of the solid-state imaging device 1 according to the first embodiment shown in FIG. The pulse power supply electrode 144 is included. This eliminates the need for complicated patterning on the photoelectric conversion layer 114.

  The waveforms of Vpulse and Vrst_d in the timing chart according to the third embodiment shown in FIG. 15 are different from those in the timing chart according to the first embodiment shown in FIG.

  In the third embodiment, the pulse power source 139 applies a DC bias of + 1.5V. The reset transistor 101 applies a pulse bias of +3.3 V at reset, and −3.3 V at stabilization and signal readout. As a result, the applied voltage value of the forward voltage at the time of reset is lowered, but the forward current is larger than that in the reverse direction, so that the reset function can be sufficiently achieved.

(Fourth embodiment)
Examples of mounting the solid-state imaging devices 1 and 2 will be shown below. FIG. 16 is a diagram illustrating the configuration of a semiconductor chip 201 according to the fourth embodiment. The semiconductor chip 201 includes a substrate 211 and a semiconductor element 212. The semiconductor element 212 is fixed on the substrate 211.
The semiconductor element 212 includes the solid-state imaging elements 1 and 2 and performs photoelectric conversion processing. Such a semiconductor chip 201 can be used as a part of an imaging device, for example.

(Fifth embodiment)
FIG. 17 is a diagram illustrating the configuration of the mobile terminal 301 according to the fifth embodiment. The portable terminal 301 includes a housing 311 and an imaging device 312. The imaging device 312 of this example is mounted on the back surface of the housing 311 (the surface opposite to the surface on which the display is installed). The imaging device 312 includes the solid-state imaging devices 1 and 2 or the semiconductor chip 201 including the same.

(Sixth embodiment)
FIG. 18 is a diagram illustrating the configuration of an automobile 401 according to the sixth embodiment. The automobile 401 includes a vehicle body 411 and an imaging device 412. The imaging device 412 of this example is mounted behind the vehicle body 411. The imaging device 412 includes the solid-state imaging devices 1 and 2 or the semiconductor chip 201 including the same.

  As mentioned above, although embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 2 Solid-state imaging device 11 Pixel array 12 Vertical shift register 13 Horizontal shift register 14A, 14B, 14C Row selection line 15A, 15B, 15C Pulse power supply line 16A, 16B, 16C Column selection line 17A, 17B, 17C Correlated double sampling (CDS) circuit 18A, 18B, 18C Analog-digital conversion circuit (ADC)
19 Output bus 20A, 20B, 20C Constant current circuit 21, 21A, 21B, 21C Pixel 100 Silicon substrate 101 Reset transistor 102 Amplifier transistor 103 Isolation region 104 First intermediate layer 105 Source side diffusion layer 106 Gate 107 First contact via 108 second contact via 109 first wiring layer 110 second intermediate layer 111 through via 112 lower electrode 113 charge storage layer 114 photoelectric conversion layer 115 upper electrode 116 protective film 117 organic photoelectric conversion structure 118 pixel signal wiring 139 pulse power supply 140 Selection transistor 144 Pulse power supply electrode 201 Semiconductor chip 211 Substrate 212 Semiconductor element 301 Portable terminal 311 Housing 312 and 412 Imaging device 401 Car 411 Car body

Claims (8)

A first electrode;
A second electrode;
A photoelectric conversion layer made of an organic film, disposed between the first electrode and the second electrode;
A charge storage layer that is disposed between the photoelectric conversion layer and the second electrode and stores charges generated by the photoelectric conversion layer;
A first element that generates a control signal for resetting the charge accumulated in the charge accumulation layer;
A second element to which a charge signal indicating the charge accumulated in the charge accumulation layer is input;
A pixel signal wiring connecting the first element, the second element, and the second electrode;
An image pickup device comprising: The organic film is composed of “amine derivative”, “quinacridone derivative”, “naphthalene derivative”, “anthracene derivative”, “phenanthrene derivative”, “tetracene derivative”, “pyrene derivative”, “perylene derivative”, “fluoranthene derivative”, “Polyphenylene vinylene, fluorene, carbazole, indole, pyrene, pyrrole, picoline, thiophene, acetylene, or diacetylene polymer and derivatives thereof”, “dithiol metal complex dyes”, “metal phthalocyanine dyes”, “metal porphyrin dyes” , “Ruthenium complex dyes”, “cyanine dyes”, “merocyanine dyes”, “phenylxanthene dyes”, “triphenylmethane dyes”, “rhodocyanine dyes”, “xanthene dyes”, “macrocyclic azaannulene” Dyes "," azulene " `` Dye '', `` Naphthoquinone '', `` Anthraquinone dye '', `` A chain compound condensed with condensed polycyclic aromatic, aromatic ring or heterocyclic compound such as anthracene, pyrene '', `` Squarylium group and croconic methine group '' “Quinoline having a chain”, “cyanine-like dyes bonded by two nitrogen-containing heterocycles such as benzothiazole and benzoxazole, or squarylium group and croconic methine group”, and “C60 or C70 fullerene and its derivatives ( A substance selected from the group consisting of “when the organic film is an n-type organic semiconductor)”,
The imaging device according to claim 1. The charge storage layer is made of a binary transition metal oxide or a perovskite oxide,
The imaging device according to claim 1. The binary transition metal oxide includes a material selected from the group consisting of MoO _x , TiO _x , HfO _x , and WO _x (X is a natural number).
The imaging device according to claim 3. The perovskite oxide includes a material selected from the group consisting of strontium titanate and barium titanate,
The imaging device according to claim 3. When the applied voltage supplied to the first electrode is swept from the plus side to the minus side, the current value indicating the charge is reversed in the plus side region, and the applied voltage is swept from the minus side to the plus side. The current value is inverted in the negative region,
The imaging device according to claim 1. A pixel array in which a plurality of pixels including the first electrode, the second electrode, the photoelectric conversion layer, and the charge storage layer are arranged;
A pulse power supply for generating a pulse voltage;
A pulse power line for supplying the pulse voltage to the first electrode of each pixel;
Further comprising
The charge accumulated in the charge accumulation layer is reset according to a change in the pulse voltage and a voltage output from the first element.
The imaging device according to claim 1. A pixel array in which a plurality of pixels including the first electrode, the second electrode, the photoelectric conversion layer, and the charge storage layer are arranged;
A pulse power supply for generating a pulse voltage;
A pulse power supply electrode comprising one member for supplying the pulse voltage to the first electrode of each pixel and connecting to all the first electrodes in the pixel array;
Further comprising
The charge accumulated in the charge accumulation layer is reset according to a change in voltage output from the first element.
The imaging device according to claim 1.

Images