JP2017055461A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of small circuit size.SOLUTION: A semiconductor device has a first transistor, a second transistor and a capacitive element. A gate of the second transistor is electrically connected with one of a source and a drain of the first transistor; and one of a pair of electrodes of the capacitive element is electrically connected with the gate of the second transistor; and the other of the pair of electrode of the capacitive element is electrically connected with one of the source and the drain of the second transistor, in which the gate of the second transistor becomes a floating state when the first transistor becomes an off state. A composition where a channel of the first transistor is formed in an oxide semiconductor can be obtained.SELECTED DRAWING: Figure 1

Description

The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, the present invention provides, for example, a semiconductor device, a display device, a light emitting device, a power storage device, a driving method thereof,
Or it is related with those manufacturing methods. In particular, the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor, for example.

Or this invention relates to the programmable logic device which can change the structure of a hardware.

Programmable logic device (Programmable Logic Device)
e (PLD)) is a device that allows the user to change the internal circuit configuration after manufacture.

JP 2003-198361 A

In a PLD or the like, as a circuit configuration capable of selecting a case where electrical connection is made between a node A and a node B via a diode and a case where electrical connection is made via a resistor, FIG.
) Circuit configuration can be used.

A circuit 8100 illustrated in FIG. 11A includes a memory 8108, a transistor 8101, and a transistor 8102n. The transistor 8102n is an n-channel transistor. One of a source and a drain of the transistor 8101 is electrically connected to the node A, and the other of the source and the drain is electrically connected to the node B. Transistor 810
One of the 2n source and drain is electrically connected to the node A, and the other of the source and drain is electrically connected to the node B. A gate of the transistor 8102n is electrically connected to one of a source and a drain of the transistor 8102n. A signal from the memory 8108 is input to the gate of the transistor 8101.

When the transistor 8101 is turned off by a signal from the memory 8108, the circuit 8100 can operate like a diode 8110 as illustrated in FIG. When the transistor 8101 is turned on by a signal from the memory 8108, the circuit 8100 can operate like a resistor 8111 illustrated in FIG. In addition, when the value of resistance is small, as shown in FIG.
112 can be operated.

As described above, the case where the node A and the node B are electrically connected via the diode and the case where the node A and the node B are electrically connected are selected by the circuit configuration in FIG. be able to.

However, in the circuit as shown in FIG. 11A, at least two transistors and
Since a storage means is required, the circuit scale increases.

An object of one embodiment of the present invention is to provide a semiconductor device with a small circuit scale. Another object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed operation.
Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with high quality. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like including a transparent semiconductor layer. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

The semiconductor device of one embodiment of the present invention includes a first transistor, a second transistor, and a capacitor, and the gate of the second transistor is electrically connected to one of the source and the drain of the first transistor. One of the pair of electrodes of the capacitor is electrically connected to the gate of the second transistor, and the other of the pair of electrodes of the capacitor is connected to one of the source and the drain of the second transistor. The semiconductor device is electrically connected and the gate of the second transistor is in a floating state when the first transistor is turned off. Note that the channel of the first transistor can be formed in an oxide semiconductor.

A semiconductor device of one embodiment of the present invention includes a first transistor, a second transistor, and a capacitor, and the first signal or the gate of the second transistor is connected to the gate of the second transistor. The second signal is input, one of the pair of electrodes of the capacitor is electrically connected to the gate of the second transistor, and the other of the pair of electrodes of the capacitor is the source of the second transistor or When electrically connected to one of the drains and the first transistor is turned off, the gate of the second transistor is in a floating state. When the first signal is input, the first transistor functions as a diode. A semiconductor device that functions as a resistor when a signal is input thereto. Note that the channel of the first transistor can be formed in an oxide semiconductor.

The mobility of the second transistor may be higher than the mobility of the first transistor.

The on-current of the second transistor may be larger than the on-current of the first transistor (current flowing between the source and the drain when the transistor is selected to be on).

The off-state current of the second transistor (the current that flows between the source and the drain when the transistor is selected to be off) may be larger than the off-state current of the first transistor.

The oxide semiconductor may include indium, gallium, zinc, and oxygen. The oxide semiconductor may include zinc and oxygen.

The channel of the second transistor may be formed in silicon. The channel of the second transistor may be formed in an oxide semiconductor.

The semiconductor device of one embodiment of the present invention can be used for a programmable logic device.

The semiconductor device of one embodiment of the present invention can be used for a signal processing circuit such as a CPU.

One embodiment of the present invention can provide a semiconductor device with a small circuit scale. Alternatively, according to one embodiment of the present invention, a semiconductor device capable of high-speed operation can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a high-quality semiconductor device or the like can be provided.

1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. The circuit diagram of the conventional semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 9 illustrates an electronic device.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments given below. Note that in describing the structure of the present invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

In this specification, the connection means an electrical connection, and corresponds to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily indicate a directly connected state, and a wiring, a resistor, a diode, a transistor, or the like is provided so that current, voltage, or potential can be supplied or transmitted. The state of being electrically connected via a circuit element is also included in the category.

In the drawings attached to the present specification, the components are classified by function, and the block diagram is shown as an independent block. However, it is difficult to completely separate the actual components for each function. May involve multiple functions.

Note that the source of a transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode that is electrically connected to the semiconductor film. Similarly, a drain of a transistor means a drain region that is part of a semiconductor film functioning as an active layer or a drain electrode that is electrically connected to the semiconductor film. The gate means a gate electrode.

The terms “source” and “drain” of a transistor interchange with each other depending on the channel type of the transistor and the level of potential applied to each terminal. In general, in an n-channel transistor, a terminal to which a low potential is applied is called a source, and a terminal to which a high potential is applied is called a drain. In a p-channel transistor, a terminal to which a low potential is applied is called a drain, and a terminal to which a high potential is applied is called a source. In this specification, for the sake of convenience, the connection relationship between transistors may be described on the assumption that the source and the drain are fixed. However, the names of the source and the drain are actually switched according to the above-described potential relationship. .

(Embodiment 1)
<Configuration of semiconductor device>
FIG. 1A illustrates a circuit 100 included in a semiconductor device. Circuit 100 includes transistor 101
A transistor 102n and a capacitor 103. In this embodiment, an example in which the transistor 102n is an n-channel transistor is described. Note that the transistor 101 may be an n-channel transistor or a p-channel transistor.

The gate of the transistor 102n is electrically connected to one of the source and the drain of the transistor 101. One of the pair of electrodes of the capacitor 103 is electrically connected to the gate of the transistor 102n. The other of the pair of electrodes of the capacitor 103 is the transistor 1
It is electrically connected to one of the source and drain of 02n. One of a source and a drain of the transistor 102n is electrically connected to the node A, and the other of the source and the drain of the transistor 102n is electrically connected to the node B. The other of the source and the drain of the transistor 101 is electrically connected to the node C. The gate of transistor 101 is
Electrically connected to node D.

The channel of the transistor 101 can be formed in an oxide semiconductor. When the transistor 101 is turned off, the gate of the transistor 102n is in a floating state. In other words, when the transistor 101 is turned off, FIG.
The node F in A) is in a floating state.

<Operation of semiconductor device>
Next, operation of the circuit 100 included in the semiconductor device is described.

In the circuit 100 in FIG. 1A, a signal is input from the node C to the node F through the transistor 101 whose on state is selected by a signal input to the node D. The circuit 100 is
A signal input to the node F is electrically connected between the node A and the node B through the diode 110 as shown in FIG. 1B, and a node as shown in FIG. The case where A and the node B are electrically connected via the resistor 111 can be selected. Note that in the case where the value of the resistor 111 is small, it can be considered that the node A and the node B are electrically connected by the conductive wire 112 as illustrated in FIG.

The signal input to the node F is then held at the node F when the transistor 101 is turned off.

Next, an operation for selecting a function of the circuit 100 in accordance with a signal input to the node F will be described in detail.

(Diode function)
An operation of selecting a case where the node A and the node B are electrically connected via the diode 110 as illustrated in FIG.

At this time, the first signal is input to the node F through the transistor 101. After the first signal is input, the transistor 101 is turned off, whereby the first signal can be held at the node F. After the first signal is input to FIG.
A circuit configuration in which is turned off is schematically shown. The potential difference between the electrodes of the capacitor 103 (V _10
3 ) The potential corresponding to the first signal and the potential of the node A when the first signal is input to the node F are adjusted so that the threshold voltage (V _th102n ) of the transistor 102n becomes smaller. . Note that V ₁₀₃ is a potential difference of the node F with respect to the node A.

As shown in FIG. 2A, when the first signal is held at the node F, the potential of the node A (V _A )
Is equal to or lower than the potential (V _B ) of the node B, the gate voltage with respect to the source of the transistor 102n becomes V ₁₀₃ and the transistor 102n is turned off as shown in FIG. Does not flow.

As shown in FIG. 2A, when the first signal is held at the node F, the potential of the node A (V _A )
Is higher than the potential (V _B ) of the node B, and (V _A + V ₁₀₃ −V _B ) is (V _th102
n ) or more, a current (I _n1 ) flows from the node A to the node B as shown in FIG.

When (V _A + V ₁₀₃ −V _B ) is smaller than (V _th102n ), the node A
And no current flows between node B.

Thus, when the first signal is input to the node F, the circuit 100 can function as the diode 110 that allows current to flow only from the node A to the node B as illustrated in FIG. The threshold voltage of the diode 110 (voltage at which current starts to flow) is (V
_th102n− V ₁₀₃ ).

(Resistance or conductor function)
An operation of selecting a case where the node A and the node B are electrically connected via the resistor 111 and the conductive wire 112 as illustrated in FIGS. 1C and 1D will be described.

At this time, the second signal is input to the node F through the transistor 101. After the second signal is input, the transistor 101 is turned off, whereby the second signal can be held at the node F. After the second signal is input to FIG.
A circuit configuration in which is turned off is schematically shown. The potential difference between the electrodes of the capacitor 103 (V _10
3 ) The potential corresponding to the second signal and the potential of the node A when the second signal is input to the node F are adjusted so that the threshold voltage (V _th102n ) of the transistor 102n becomes _{equal to} or higher. Note that V ₁₀₃ is a potential difference of the node F with respect to the node A.

As shown in FIG. 3A, when the second signal is held at the node F, the potential of the node A (V _A )
Is larger than the potential (V _B ) of the node B, as shown in FIG.
02n is turned on, and a current (I _n2 ) flows from the node A to the node B.

As shown in FIG. 3A, when the second signal is held at the node F, the potential of the node A (V _A )
Is less than the potential (V _B ) of the node B, as shown in FIG.
02n is turned on, and a current (I _n3 ) flows from the node B to the node A.

When the potential of the node A (V _A ) is equal to the potential of the node B (V _B ), no current flows.

Therefore, by inputting the second signal to the node F, the circuit 100 can function as the resistor 111 or the conductive wire 112 as illustrated in FIGS. 3D and 3E.

As described above, the circuit 100 in FIG. 1A includes a case where the node A and the node B are electrically connected via a diode and a case where the node 100 is electrically connected via a resistor. You can choose.

Since the circuit 100 illustrated in FIG. 1A can be formed using two transistors and one capacitor, the circuit scale of the semiconductor device using the circuit 100 can be reduced.

Further, the signal input to the node F is held at the node F when the transistor 101 is turned off thereafter. Here, when the channel of the transistor 101 is formed in an oxide semiconductor, the transistor 101 has a characteristic that leakage current (also referred to as off-state current) is extremely small. Therefore, the signal input to the node F can be kept for a long period. That is, once the transistor 101 is turned on and a predetermined signal is input to the node F, the circuit 100 does not have to input the signal frequently, and the circuit 100 does not have a predetermined function (FIG. 1B or FIG. ) And the function shown in FIG. 1D can be maintained. Thus, in a semiconductor device using the circuit 100, power consumption can be reduced.

Note that the speed of signal transmission between the node A and the node B can be improved by making the mobility of the transistor 102n higher than the mobility of the transistor 101. Further, the speed of signal transmission between the node A and the node B can be improved by making the on-state current of the transistor 102n larger than the on-state current of the transistor 101. Thus,
A semiconductor device using the circuit 100 can be operated at high speed.

Note that the channel of the transistor 102n may be formed of silicon. A transistor in which a channel is formed in an oxide semiconductor is used as the transistor 101 and a transistor in which a channel is formed in silicon is used as the transistor 102n, so that a layer in which the transistor 101 is provided and a layer in which the transistor 102n is provided Can be provided in piles. Therefore, the area of the circuit 100 can be reduced, and the semiconductor device using the circuit 100 can be downsized.

This embodiment can be implemented in free combination with any of the other embodiments.

(Embodiment 2)
In this embodiment, an example of a circuit 100 which is different from the structure shown in Embodiment 1 is described.
<Configuration of semiconductor device>
FIG. 4A illustrates a circuit 100 included in the semiconductor device. Circuit 100 includes transistor 101
A transistor 102p and a capacitor 103. In this embodiment, an example in which the transistor 102p is a p-channel transistor is described. Note that the transistor 101 may be an n-channel transistor or a p-channel transistor.

The gate of the transistor 102p is electrically connected to one of the source and the drain of the transistor 101. One of the pair of electrodes of the capacitor 103 is electrically connected to the gate of the transistor 102p. The other of the pair of electrodes of the capacitor 103 is the transistor 1
It is electrically connected to one of the source and drain of 02p. One of a source and a drain of the transistor 102p is electrically connected to the node A, and the other of the source and the drain of the transistor 102p is electrically connected to the node B. The other of the source and the drain of the transistor 101 is electrically connected to the node C. The gate of transistor 101 is
Electrically connected to node D.

The channel of the transistor 101 can be formed in an oxide semiconductor. When the transistor 101 is turned off, the gate of the transistor 102p is in a floating state. In other words, when the transistor 101 is turned off, FIG.
The node F in A) is in a floating state.

<Operation of semiconductor device>
Next, operation of the circuit 100 included in the semiconductor device is described.

In the circuit 100 in FIG. 4A, a signal is input from the node C to the node F through the transistor 101 whose on state is selected by a signal input to the node D. The circuit 100 is
When a signal input to the node F is used to electrically connect the node A and the node B through the diode 120 as illustrated in FIG. 4B, and a node as illustrated in FIG. The case where A and the node B are electrically connected via the resistor 121 can be selected. Note that in the case where the value of the resistor 121 is small, it can be considered that the node A and the node B are electrically connected by the conductive wire 122 as illustrated in FIG.

The signal input to the node F is then held at the node F when the transistor 101 is turned off.

Next, an operation for selecting a function of the circuit 100 in accordance with a signal input to the node F will be described in detail.

(Diode function)
An operation of selecting a case where the node A and the node B are electrically connected via the diode 120 as illustrated in FIG. 4B will be described.

At this time, the first signal is input to the node F through the transistor 101. After the first signal is input, the transistor 101 is turned off, whereby the first signal can be held at the node F. After the first signal is input to FIG.
A circuit configuration in which is turned off is schematically shown. The potential difference between the electrodes of the capacitor 103 (V _10
3 ) The potential corresponding to the first signal and the potential of the node A when the first signal is input to the node F are adjusted so that the threshold voltage (V _th102p ) of the transistor 102p becomes larger. . Note that V ₁₀₃ is a potential difference of the node F with respect to the node A.

As shown in FIG. 5A, when the first signal is held at the node F, the potential of the node A (V _A )
Is equal to or higher than the potential (V _B ) of the node B, the gate voltage with respect to the source of the transistor 102p becomes V ₁₀₃ , and the transistor 102p is turned off as shown in FIG. Does not flow.

As shown in FIG. 5A, when the first signal is held at the node F, the potential of the node A (V _A )
Is smaller than the potential (V _B ) of the node B, and (V _A + V ₁₀₃ −V _B ) is (V _th102
p ) In the following case, a current (I _p1 ) flows from the node B to the node A as shown in FIG.

When (V _A + V ₁₀₃ −V _B ) is larger than (V _th102p ), the node A
And no current flows between node B.

Therefore, when the first signal is input to the node F, the circuit 100 can function as a diode 120 that allows current to flow only from the node B to the node A as illustrated in FIG. The threshold voltage of the diode 120 (voltage at which current starts to flow) is (V
_th102p− V ₁₀₃ ).

(Resistance or conductor function)
An operation of selecting a case where the node A and the node B are electrically connected through the resistor 121 and the conductive wire 122 as illustrated in FIGS. 4C and 4D will be described.

At this time, the second signal is input to the node F through the transistor 101. After the second signal is input, the transistor 101 is turned off, whereby the second signal can be held at the node F. After the second signal is input to FIG.
A circuit configuration in which is turned off is schematically shown. The potential difference between the electrodes of the capacitor 103 (V _10
3 ) The potential corresponding to the second signal and the potential of the node A when the second signal is input to the node F are adjusted so that the threshold voltage (V _th102p ) of the transistor 102p is equal to or lower. Note that V ₁₀₃ is a potential difference of the node F with respect to the node A.

As shown in FIG. 6A, when the second signal is held at the node F, the potential of the node A (V _A )
Is larger than the potential (V _B ) of the node B, as shown in FIG.
02p is turned on, and a current (I _p2 ) flows from the node A to the node B.

As shown in FIG. 6A, when the second signal is held at the node F, the potential of the node A (V _A )
Is less than the potential (V _B ) of the node B, as shown in FIG.
02p is turned on, and a current (I _p3 ) flows from the node B to the node A.

When the potential of the node A (V _A ) is equal to the potential of the node B (V _B ), no current flows.

Therefore, when the second signal is input to the node F, the circuit 100 can function as the resistor 121 or the conductive wire 122 as illustrated in FIGS. 6D and 6E.

As described above, the circuit 100 illustrated in FIG. 4A includes a case where the node A and the node B are electrically connected via the diode and a case where the node 100 is electrically connected via the resistor. You can choose.

Since the circuit 100 illustrated in FIG. 4A can be formed using two transistors and one capacitor, the circuit scale of the semiconductor device using the circuit 100 can be reduced.

Further, the signal input to the node F is held at the node F when the transistor 101 is turned off thereafter. Here, when the channel of the transistor 101 is formed in an oxide semiconductor, the transistor 101 has a characteristic that leakage current (also referred to as off-state current) is extremely small. Therefore, the signal input to the node F can be kept for a long period. In other words, once the transistor 101 is turned on and a predetermined signal is input to the node F, the circuit 100 does not have to input a signal frequently (FIG. 4B or FIG. 4C). ) And the function shown in FIG. 4D) can be maintained. Thus, in a semiconductor device using the circuit 100, power consumption can be reduced.

Note that the speed of signal transmission between the node A and the node B can be improved by making the mobility of the transistor 102p higher than that of the transistor 101. Further, by increasing the on-state current of the transistor 102p more than the on-state current of the transistor 101, the speed of signal transmission between the node A and the node B can be improved. Thus,
A semiconductor device using the circuit 100 can be operated at high speed.

Note that the channel of the transistor 102p may be formed in silicon. A transistor in which a channel is formed in an oxide semiconductor is used as the transistor 101, and a transistor in which a channel is formed in silicon is used as the transistor 102p, so that a layer in which the transistor 101 is provided and a layer in which the transistor 102p is provided Can be provided in piles. Therefore, the area of the circuit 100 can be reduced, and the semiconductor device using the circuit 100 can be downsized.

This embodiment can be implemented in free combination with any of the other embodiments.

(Embodiment 3)
A plurality of the circuits 100 described in Embodiments 1 and 2 can be used in combination.

For example, a plurality of circuits 100 can be connected in series with each other. Here, connecting a plurality of circuits 100 in series means that one of a node A or a node B of one circuit 100 and one of a node A or a node B of another circuit 100 are electrically connected. State. The plurality of circuits 100 are connected in parallel to each other when one of the nodes A and B of one circuit 100 and one of the nodes A and B of another circuit 100 are electrically connected. It is assumed that the other of the node A or the node B and the other of the node A or the node B of another circuit 100 are electrically connected.

Examples of a configuration in which two circuits 100 described in Embodiment 1 or 2 are used and connected in series are illustrated in FIGS. 7A to 7C and FIGS. 8A to 8C.
9A and 9B, one of the two circuits 100 is a circuit 1100 and the other is a circuit 2100.

The configurations and operation methods of the circuit 1100 and the circuit 2100 are the same as the configuration and operation method of the circuit 100 described in Embodiments 1 and 2, and thus description thereof is omitted.

Further, the transistor 1101 included in the circuit 1100 can have a structure similar to that of the transistor 101. The transistor 2101 included in the circuit 2100 can have a structure similar to that of the transistor 101. The capacitor 1103 included in the circuit 1100 is
A structure similar to that of the capacitor 103 can be employed. Capacitance element 21 constituting circuit 2100
03 can have a structure similar to that of the capacitor 103. The transistor 1102n and the transistor 1102p included in the circuit 1100 can have a structure similar to that of the transistor 102n or the transistor 102p. Transistor 210 constituting circuit 2100
2n and the transistor 2102p can have a structure similar to that of the transistor 102n or the transistor 102p.

It is possible to select any of the functions shown in FIGS. 10A to 10I by using two circuits 100 described in Embodiment 1 or 2 and connecting them in series. Become.

This embodiment can be implemented in free combination with any of the other embodiments.

(Embodiment 4)
An oxide semiconductor that can be used as a region where a channel of the transistor 101, the transistor 1101, and the transistor 2101 in Embodiments 1 to 3 is formed is described.

An oxide semiconductor (purified OS) that is highly purified by reducing impurities such as moisture or hydrogen that serves as an electron donor (donor) and reducing oxygen vacancies is provided by i.
Close to the type (intrinsic semiconductor) or i-type. Therefore, a transistor in which a channel is formed in a highly purified oxide semiconductor has extremely low off-state current and high reliability.

Specifically, it can be proved by various experiments that the off-state current of a transistor in which a channel is formed in a highly purified oxide semiconductor is small. For example, the channel width is 1 × 10 ⁶ μ
Even if the device has a channel length of 10 μm and a voltage between the source electrode and the drain electrode (drain voltage) of 1 V to 10 V, the off-current is below the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻ A characteristic of ¹³ A or less can be obtained. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. In addition, off-state current was measured using a circuit in which a capacitor and a transistor were connected and charge flowing into or out of the capacitor was controlled by the transistor. In this measurement, a highly purified oxide semiconductor film was used for a channel formation region of the transistor, and the off-state current of the transistor was measured from the change in charge amount per unit time of the capacitor. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for a channel formation region has an off-state current of
This is significantly smaller than a transistor using crystalline silicon.

Note that unless otherwise specified, off-state current in this specification refers to the gate potential when the drain potential is higher than that of the source and the gate in the n-channel transistor. It means a current that flows between the source and the drain when is less than or equal to zero. Alternatively, the off-state current in this specification refers to a p-channel transistor in which the potential of the gate is 0 or more with respect to the source potential in a state where the drain is at a lower potential than the source and the gate. In addition, it means a current flowing between the source and the drain.

An oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Zirconium (Z
Preferably, r) is included.

Among oxide semiconductors, In—Ga—Zn-based oxides, In—Sn—Zn-based oxides, and the like have excellent electrical characteristics by sputtering or a wet method, unlike silicon carbide, gallium nitride, or gallium oxide. There is an advantage that a transistor can be manufactured and the mass productivity is excellent. Further, unlike silicon carbide, gallium nitride, or gallium oxide, the In—Ga—Zn-based oxide can manufacture a transistor with excellent electrical characteristics over a glass substrate. In addition, it is possible to cope with an increase in the size of the substrate.

In addition, as other stabilizers, lanthanoids such as lanthanum (La), cerium (
Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium ( Any one kind or plural kinds of Tm), ytterbium (Yb), and lutetium (Lu) may be contained.

For example, as an oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, I
n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, S
n-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also referred to as IGZO), In-Al-Zn-based oxide, In-Sn-Zn Oxides,
Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, I
n-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr-Zn-based oxide, In
-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-
Gd—Zn oxide, In—Tb—Zn oxide, In—Dy—Zn oxide, In—H
o-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb
-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-
Hf—Ga—Zn-based oxide, In—Al—Ga—Zn-based oxide, In—Sn—Al—Zn
A series oxide, an In—Sn—Hf—Zn series oxide, or an In—Hf—Al—Zn series oxide can be used.

Note that for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be included. An In—Ga—Zn-based oxide has sufficiently high resistance when no electric field is applied, and can sufficiently reduce off-state current. In addition, the In—Ga—Zn-based oxide has high mobility.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: G
An In—Ga—Zn-based oxide having an atomic ratio of a: Zn = 2: 2: 1 (= 2/5: 2/5: 1/5) or an oxide in the vicinity of the composition can be used. Alternatively, In: Sn: Zn = 1:
1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1 /
6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio of In—Sn—Zn-based oxide and the vicinity of its composition An oxide may be used.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

For example, the oxide semiconductor film may include a non-single crystal. Non-single crystals are, for example, CAAC (C
(Axis Aligned Crystal), polycrystalline, microcrystalline, and amorphous part.
The amorphous part has a higher density of defect states than microcrystals and CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an CAAC-OS (C
Axis Aligned Crystalline Oxide Semiconductor
uctor).

For example, the oxide semiconductor film may include a CAAC-OS. The CAAC-OS is, for example,
c-axis oriented, and the a-axis and / or b-axis are not aligned macroscopically.

The oxide semiconductor film may include microcrystal, for example. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. The microcrystalline oxide semiconductor film includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example.

For example, the oxide semiconductor film may include an amorphous part. Note that an oxide semiconductor having an amorphous part is referred to as an amorphous oxide semiconductor. An amorphous oxide semiconductor film has, for example, disordered atomic arrangement and no crystal component. Alternatively, the amorphous oxide semiconductor film is, for example, completely amorphous and has no crystal part.

Note that the oxide semiconductor film may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film includes an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The mixed film may have a stacked structure of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region, for example.

Note that the oxide semiconductor film may include a single crystal, for example.

The oxide semiconductor film preferably includes a plurality of crystal parts, and the c-axis of the crystal parts is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor film is a CAAC-OS film.

In most cases, a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 100 nm. In addition, a transmission electron microscope (TEM: Transmission El)
In the observation image by Electron Microscope), the boundary between the crystal part and the crystal part included in the CAAC-OS film is not clear. In addition, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, CAAC-O
In the S film, the decrease in electron mobility caused by the grain boundary is suppressed.

The crystal part included in the CAAC-OS film is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is perpendicular to the ab plane. When viewed from the direction, the metal atoms are arranged in a triangular shape or a hexagonal shape, and when viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

The CAAC-OS film is formed using, for example, X-ray diffraction (XRD: X-Ray Diffraction).
) When an apparatus is used for analysis by the out-of-plane method, a peak where 2θ is around 31 ° may appear. The peak at 2θ of around 31 ° indicates that it is oriented in the (009) plane in the case of InGaZnO ₄ crystal. The CAAC-OS film can be formed using, for example, 2θ
May appear in the vicinity of 36 °. The peak when 2θ is around 36 ° is ZnGa ₂ O
A crystal of ₄ indicates that it is oriented in the (222) plane. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

Further, for example, in the case of a CAAC-OS film including an InGaZnO ₄ crystal, when an analysis is performed by an in-plane method in which X-rays are incident from a direction perpendicular to the c-axis using an XRD apparatus, 2θ is close to 56 ° May appear. The peak when 2θ is around 56 ° is InG
The (110) plane of the aZnO ₄ crystal is shown. Here, when 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the surface normal vector as the axis (φ axis), the directions of the a axis and the b axis are aligned. In the case of a crystalline oxide semiconductor, six symmetry peaks appear, but in the case of a CAAC-OS film, a clear peak does not appear.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, CAA
In the formation process of the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film may be higher in the vicinity of the surface. CA
When an impurity is added to the AC-OS film, the crystallinity of the crystal part in the impurity-added region may be lowered.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, the directions may be different from each other. The crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

The CAAC-OS film is formed by a sputtering method using a polycrystalline metal oxide target, for example.

In order to form the CAAC-OS film, the following conditions are preferably applied.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) existing in the treatment chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. By increasing the substrate heating temperature during film formation, when flat sputtered particles reach the substrate, migration occurs on the substrate,
The flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume.

As an example of the target, an In—Ga—Zn-based oxide target is described below.

In-Ga which is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder at a predetermined molar ratio, and after heat treatment, heat treatment is performed at a temperature of 1000 ° C. to 1500 ° C.
—Zn-based oxide target. X, Y, and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: InO _X powder, GaO _Y powder, and ZnO _Z powder.
1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4: 2: 3 or 3: 1: 2. In addition,
What is necessary is just to change suitably the kind of powder, and the mol number ratio to mix with the target to produce.

Note that an alkali metal is an impurity because it is not an element included in an oxide semiconductor. Alkaline earth metal is also an impurity when it is not an element constituting an oxide semiconductor. In particular, Na in the alkali metal diffuses into the insulating film and becomes Na ⁺ when the insulating film in contact with the oxide semiconductor layer is an oxide. In the oxide semiconductor layer, Na breaks or interrupts the bond between the metal and the oxygen included in the oxide semiconductor. As a result, for example, the transistor is deteriorated in electrical characteristics, such as being normally on due to the shift of the threshold voltage in the negative direction, and a decrease in mobility. In addition, the characteristics vary.
Specifically, the measured value of Na concentration by secondary ion mass spectrometry is 5 × 10 ¹⁶ / cm ³ or less, preferably 1 × 10 ¹⁶ / cm ³ or less, more preferably 1 × 10 ¹⁵ / cm ³ or less. Good. Similarly, the measured value of Li concentration is 5 × 10 ¹⁵ / cm ³ or less, preferably 1 × 1.
It may be 0 ¹⁵ / cm ³ or less. Similarly, the measured value of the K concentration is 5 × 10 ¹⁵ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less.

In addition, in the case where a metal oxide containing indium is used, silicon or carbon whose binding energy to oxygen is higher than that of indium may cut the bond between indium and oxygen, thereby forming an oxygen vacancy. Therefore, if silicon or carbon is mixed in the oxide semiconductor layer,
As in the case of an alkali metal or alkaline earth metal, the electrical characteristics of the transistor are likely to deteriorate. Therefore, it is desirable that the concentration of silicon or carbon in the oxide semiconductor layer be low. Specifically, the measured value of C concentration or the measured value of Si concentration by secondary ion mass spectrometry is preferably 1 × 10 ¹⁸ / cm ³ or less. With the above structure, deterioration of electrical characteristics of the transistor can be prevented, and reliability of the semiconductor device can be improved.

Further, depending on the conductive material used for the source electrode and the drain electrode, the metal in the source electrode and the drain electrode might extract oxygen from the oxide semiconductor film. In this case, a region in contact with the source electrode and the drain electrode in the oxide semiconductor layer is n-type due to formation of oxygen vacancies.

Since the n-type region functions as a source region or a drain region, contact resistance between the oxide semiconductor film and the source and drain electrodes can be reduced.
Thus, by forming an n-type region, the mobility and on-state current of the transistor can be increased, whereby high-speed operation of the switch circuit using the transistor can be realized.

Note that extraction of oxygen by a metal in the source electrode and the drain electrode can occur when the source electrode and the drain electrode are formed by a sputtering method or the like, and can also occur by a heat treatment performed after the source electrode and the drain electrode are formed. .

In addition, the n-type region is more easily formed by using a conductive material that is easily bonded to oxygen for the source electrode and the drain electrode. Examples of the conductive material include Al and C.
r, Cu, Ta, Ti, Mo, W, etc. are mentioned.

In addition, the oxide semiconductor layer is not necessarily composed of a single metal oxide film, and may be composed of a plurality of stacked metal oxide films. For example, in the case of a semiconductor film in which first to third metal oxide films are sequentially stacked, the first metal oxide film and the third metal oxide film are the second
At least one of the metal elements constituting the metal oxide film is included in its constituent elements, and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, and.
The oxide film has a vacuum level of 1 eV or more or 0.15 eV or more, 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Furthermore, it is preferable that the second metal oxide film contains at least indium because carrier mobility is increased.

When the transistor has the semiconductor film having the above structure, by applying a voltage to the gate electrode,
When an electric field is applied to the semiconductor film, a channel region is formed in the second metal oxide film having low energy at the lower end of the conduction band in the semiconductor film. That is, since the third metal oxide film is provided between the second metal oxide film and the gate insulating film, the second metal oxide film separated from the gate insulating film has a channel. Regions can be formed.

In addition, since the third metal oxide film includes at least one of the metal elements constituting the second metal oxide film in its constituent elements, the second metal oxide film and the third metal oxide film Interface scattering is unlikely to occur at the interface. Therefore, the movement of carriers at the interface is not easily disturbed,
The field effect mobility of the transistor is increased.

In addition, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, a channel region is also formed in a region near the interface, so that the threshold voltage of the transistor fluctuates. Resulting in. However, since the first metal oxide film includes at least one of the metal elements constituting the second metal oxide film in its constituent elements, the second metal oxide film and the first metal oxide film It is difficult to form interface states at the interface. Thus, with the above structure, variation in electrical characteristics such as threshold voltage of the transistor can be reduced.

In addition, it is preferable to stack a plurality of oxide semiconductor films so that an interface state that inhibits carrier flow is not formed at the interface between the films due to the presence of impurities between the metal oxide films. . If impurities exist between the stacked metal oxide films, the continuity of the energy at the bottom of the conduction band between the metal oxide films is lost, and carriers are trapped or re-entered near the interface. This is because the bonds disappear. By reducing the impurities between the films, a plurality of metal oxide films having at least one metal as a main component together are not simply stacked. A state of having a U-shaped well structure that continuously changes between them).

In order to form a continuous bond, it is necessary to use a multi-chamber type film forming apparatus (sputtering apparatus) provided with a load lock chamber to continuously laminate each film without exposure to the atmosphere. Each chamber in the sputtering apparatus is evacuated (1 × 10 ⁻⁴ Pa to 5 ×) using an adsorption-type evacuation pump such as a cryopump so as to remove as much water as possible from the oxide semiconductor. It is preferable that it is about 10 ⁻⁷ Pa). Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that gas does not flow backward from the exhaust system into the chamber.

In order to obtain a high-purity intrinsic oxide semiconductor, it is important not only to evacuate each chamber to a high vacuum but also to increase the purity of a gas used for sputtering. The dew point of oxygen gas or argon gas used as the gas is −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −
By setting the temperature to be 100 ° C. or lower and increasing the purity of the gas used, moisture and the like can be prevented from being taken into the oxide semiconductor film as much as possible.

For example, the first metal oxide film or the third metal oxide film is formed using aluminum, silicon, titanium, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium more than the second metal oxide film. As long as the oxide film contains a high atomic ratio. Specifically, as the first metal oxide film or the third metal oxide film, the above-described element is 1.5 times or more, preferably 2 times or more than the second metal oxide film, more preferably 3 times or more. An oxide film including an atomic ratio which is twice or more higher is preferably used. The above element is strongly bonded to oxygen and thus has a function of suppressing generation of oxygen vacancies in the oxide film. Therefore, with the above configuration, the first
This metal oxide film or the third metal oxide film can be an oxide film in which oxygen vacancies are less likely to occur than the second metal oxide film.

Specifically, the second metal oxide film and the first metal oxide film or the third metal oxide film are
In the case where both are In-M-Zn-based oxides, the atomic ratio of the first metal oxide film or the third metal oxide film is set to In: M: Zn = x ₁ : y ₁ : z ₁ , second The atomic ratio of the metal oxide film of In
: M: Zn = x ₂ : y ₂ : When z ₂ , the atomic ratio may be set so that y ₁ / x ₁ is larger than y ₂ / x ₂ . Note that the element M is a metal element having a stronger bond strength with oxygen than In, for example, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, or Hf.
Etc. Preferably, the atomic ratio may be set so that y ₁ / x ₁ is 1.5 times or more larger than y ₂ / x ₂ . More preferably, the atomic ratio may be set so that y ₁ / x ₁ is twice or more larger than y ₂ / x ₂ . More preferably, y ₁ /
As x ₁ is greater 3 times or more y _{2 /} x _2, it may be set the atomic ratio. Furthermore, in the second metal oxide film, it is preferable that y ₂ is x ₂ or more because stable electrical characteristics can be imparted to the transistor. However, if y ₂ is equal to or greater than 3 times the x _2, the field-effect mobility of the transistor is reduced, y ₂ is equal to or x _2, smaller than three times x ₂ preferred.

Note that the thicknesses of the first metal oxide film and the third metal oxide film are 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the second metal oxide film is 3n
m to 200 nm, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm.

In the semiconductor film having a three-layer structure, the first metal oxide film to the third metal oxide film can take either amorphous or crystalline forms. However, since the second metal oxide film in which the channel region is formed is crystalline, stable electrical characteristics can be given to the transistor, and thus the second metal oxide film is crystalline. It is preferable.

Note that a channel formation region means a region of a semiconductor film of a transistor that overlaps with a gate electrode and is sandwiched between a source electrode and a drain electrode. The channel region refers to a region where current mainly flows in the channel formation region.

For example, when an In—Ga—Zn-based oxide film formed by a sputtering method is used as the first metal oxide film and the third metal oxide film, the first metal oxide film and the third metal oxide film are used. For the formation of the physical film, a target that is an In—Ga—Zn-based oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]) can be used. The film forming conditions may be, for example, 30 sccm of argon gas and 15 sccm of oxygen gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

In the case where the second metal oxide film is a CAAC-OS film, an In—Ga—Zn-based oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]),
A target including a polycrystalline In—Ga—Zn-based oxide is preferably used. The film forming conditions may be, for example, an argon gas of 30 sccm and an oxygen gas of 15 sccm as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 300 ° C., and a DC power of 0.5 kW.

Note that the transistor may have a structure in which an end portion of the semiconductor film is inclined or a structure in which an end portion of the semiconductor film is rounded.

In the case where a semiconductor film including a plurality of stacked metal oxide films is used for a transistor, regions in contact with the source electrode and the drain electrode may be n-type. With the above structure, the mobility and on-state current of the transistor can be increased and high-speed operation of the semiconductor device can be realized. Further, in the case where a semiconductor film including a plurality of stacked metal oxide films is used for a transistor, the n-type region reaches the second metal oxide film serving as a channel region. It is more preferable in increasing mobility and on-current and realizing further high-speed operation of the semiconductor device.

This embodiment can be implemented in free combination with any of the other embodiments.

(Embodiment 5)
An example of the semiconductor device described in any of Embodiments 1 to 4 will be described. In FIG.
The transistor 101 and the transistor 10 included in the circuit 100 of the semiconductor device illustrated in FIG.
A cross-sectional structure of 2n and the capacitor 103 is shown as an example.

The case where the channel is formed in the oxide semiconductor as the transistor 101 is illustrated.
Then, the case where the transistor 101 and the capacitor 103 are formed over the transistor 102n in which a channel is formed in single crystal silicon is illustrated.

Note that the transistor 102n can use an amorphous, microcrystalline, polycrystalline, or single crystal semiconductor film such as silicon or germanium for the active layer. Alternatively, the transistor 102n may use an oxide semiconductor for the active layer. In the case where all the transistors use an oxide semiconductor for the active layer, the transistor 101 does not need to be stacked over the transistor 102n, and the transistor 101 and the transistor 102n may be formed in the same layer.

In the case where the transistor 102n is formed using thin silicon, amorphous silicon manufactured by a vapor deposition method such as a plasma CVD method or a sputtering method, and a multicrystal which is crystallized by irradiating laser light on the amorphous silicon. Crystalline silicon, single crystal silicon in which a surface layer portion is separated by implanting hydrogen ions or the like into a single crystal silicon wafer, or the like can be used.

The semiconductor substrate 1400 on which the transistor 102n is formed is, for example, a silicon substrate, germanium substrate, silicon germanium substrate, compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP) having n-type or p-type conductivity. Substrate, GaInA
An sP substrate, a ZnSe substrate, or the like can be used. FIG. 12 illustrates the case where a single crystal silicon substrate having n-type conductivity is used.

The transistor 102n is electrically isolated from other transistors by an element isolation insulating film 1401. The element isolation insulating film 1401 is formed by a selective oxidation method (LOC).
An OS (Local Oxidation of Silicon) method or a trench isolation method can be used.

Specifically, the transistor 102n is provided between the semiconductor substrate 1400 and the gate electrode 1404, and the impurity region 1402 and the impurity region 1403 that function as a source region or a drain region, the gate electrode 1404, and the semiconductor substrate 1400. And a gate insulating film 1405. The gate electrode 1404 overlaps with a channel formation region formed between the impurity region 1402 and the impurity region 1403 with the gate insulating film 1405 interposed therebetween.

An insulating film 1409 is provided over the transistor 102n. An opening is formed in the insulating film 1409. In the opening, an impurity region 1402 and an impurity region 14 are formed.
A wiring 1410 and a wiring 1411 that are in contact with each other 03 and a wiring 1412 that is electrically connected to the gate electrode 1404 are formed.

The wiring 1410 is electrically connected to the wiring 1415 formed over the insulating film 1409. The wiring 1411 is electrically connected to the wiring 1416 formed over the insulating film 1409. Are electrically connected to a wiring 1417 formed over the insulating film 1409.

Over the wirings 1415 to 1417, an insulating film 1420 and an insulating film 1440 are stacked in this order. An opening is formed in the insulating film 1420 and the insulating film 1440, and a wiring 1421 electrically connected to the wiring 1417 is formed in the opening.

In FIG. 12, the transistor 101 and the capacitor 103 are formed over the insulating film 1440.

The transistor 101 includes a semiconductor film 1430 including an oxide semiconductor over the insulating film 1440;
The conductive film 1432 and the conductive film 1433 functioning as a source electrode or a drain electrode over the semiconductor film 1430, the gate insulating film 1431 over the semiconductor film 1430, the conductive film 1432, and the conductive film 1433, and the gate insulating film 1431 are positioned. , Conductive film 1432 and conductive film 1433
A gate electrode 1434 which overlaps with the semiconductor film 1430. In addition,
The conductive film 1433 is electrically connected to the wiring 1421.

Further, the conductive film 1435 is provided over the gate insulating film 1431 so as to overlap with the conductive film 1433.
Is provided. The conductive film 1433 and the conductive film 143 have the gate insulating film 1431 interposed therebetween.
The portion where 5 overlaps functions as the capacitor 103.

Note that FIG. 12 illustrates the case where the capacitor 103 is provided over the insulating film 1440 together with the transistor 101; however, the capacitor 103 includes the transistor 102n and
The insulating film 1440 may be provided below.

Then, the insulating film 1441 and the insulating film 1442 are formed over the transistor 101 and the capacitor 103.
Are provided in order. An opening is provided in the insulating film 1441 and the insulating film 1442, and a conductive film 1443 that is in contact with the gate electrode 1434 in the opening is provided over the insulating film 1442.

Note that in FIG. 12, the transistor 101 includes a gate electrode 1434 and a semiconductor film 1430.
At least one gate electrode may be provided, but a pair of gate electrodes existing with the semiconductor film 1430 interposed therebetween may be provided.

In the case where the transistor 101 includes a pair of gate electrodes present with the semiconductor film 1430 interposed therebetween, a signal for controlling a conductive state or a non-conductive state is supplied to one gate electrode, and the other gate The electrode may be in a state where a potential is applied from another. In this case, the same potential may be applied to the pair of electrodes, or a fixed potential such as a ground potential may be applied only to the other gate electrode. By controlling the level of the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

FIG. 12 illustrates the case where the transistor 101 has a single gate structure having one channel formation region corresponding to one gate electrode 1434. However, the transistor 101 may have a multi-gate structure in which a plurality of channel formation regions are included in one active layer by including a plurality of electrically connected gate electrodes.

Further, the semiconductor film 1430 is not necessarily formed of a single oxide semiconductor, and may be formed of a plurality of stacked oxide semiconductors. For example, FIG. 13A illustrates a configuration example of the transistor 1110A in the case where the semiconductor film 1430 is stacked in three layers.

A transistor 1110A illustrated in FIG. 13A includes a semiconductor film 1430 provided over the insulating film 1440, a conductive film 1432 and a conductive film 1433 which are electrically connected to the semiconductor film 1430, and a gate insulating film 1431. And a gate electrode 1434 provided so as to overlap with the semiconductor film 1430 over the gate insulating film 1431.

In the transistor 1110A, the oxide semiconductor layer 830 is used as the semiconductor film 1430.
a to an oxide semiconductor layer 830c are stacked in that order from the insulating film 1440 side.

The oxide semiconductor layer 830a and the oxide semiconductor layer 830c are formed of the oxide semiconductor layer 830.
The constituent element contains at least one of the metal elements constituting b, and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more than the oxide semiconductor layer 830b. And 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV
Hereinafter, the oxide film is close to a vacuum level. Further, the oxide semiconductor layer 830b preferably contains at least indium because carrier mobility is increased.

Note that as illustrated in FIG. 13B, the oxide semiconductor layer 830c may be provided over the conductive films 1432 and 1433 so as to overlap with the gate insulating film 1431.

This embodiment can be implemented in free combination with any of the other embodiments.

(Embodiment 6)
A semiconductor device or a programmable logic device according to one embodiment of the present invention includes a display device,
Personal computer, image reproducing apparatus equipped with a recording medium (typically DVD: Digi)
a device having a display capable of reproducing a recording medium such as a tal Versatile Disc and displaying an image thereof), and a circuit for controlling or protecting a battery such as a secondary battery. In addition, as an electronic device in which the semiconductor device or the programmable logic device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book, a video camera, a digital still camera, and the like camera,
Goggle type display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, etc. Can be mentioned. Specific examples of these electronic devices are shown in FIGS.

FIG. 14A illustrates a portable game machine, which includes a housing 5001, a housing 5002, a display portion 5003,
A display portion 5004, a microphone 5005, a speaker 5006, operation keys 5007, a stylus 5008, and the like are included. Note that although the portable game machine illustrated in FIG. 14A includes the two display portions 5003 and the display portion 5004, the number of display portions included in the portable game device is not limited thereto.

FIG. 14B illustrates a portable information terminal which includes a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, operation keys 5606, and the like. The first display portion 5603 is provided in the first housing 5601 and the second display portion 5604 is provided in the second housing 56.
02. The first housing 5601 and the second housing 5602 are connected to the connection portion 56.
05, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connecting portion 5605. The video on the first display portion 5603 is displayed on the connection portion 5605.
It is good also as a structure switched according to the angle between the 1st housing | casing 5601 and the 2nd housing | casing 5602. Further, a display device to which a function as a position input device is added to at least one of the first display portion 5603 and the second display portion 5604 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device.
Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 14C illustrates a laptop personal computer, which includes a housing 5401 and a display portion 5402.
A keyboard 5403, a pointing device 5404, and the like.

FIG. 14D illustrates an electric refrigerator-freezer, which includes a housing 5301, a refrigerator door 5302, a refrigerator door 5303, and the like.

FIG. 14E illustrates a video camera, which includes a first housing 5801, a second housing 5802, and a display portion 58.
03, an operation key 5804, a lens 5805, a connection portion 5806, and the like. Operation key 580
4 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. is there. The video on the display portion 5803 is displayed on the connection portion 5806.
It is good also as a structure switched according to the angle between the 1st housing | casing 5801 and the 2nd housing | casing 5802.

FIG. 14F shows an ordinary car, which includes a car body 5101, wheels 5102, a dashboard 510.
3, light 5104 and the like.

This embodiment can be implemented in free combination with any of the other embodiments.

100 circuit 101 transistor 102n transistor 102p transistor 103 capacitor 110 diode 111 resistor 112 conductor 120 diode 121 resistor 122 conductor 830a oxide semiconductor layer 830b oxide semiconductor layer 830c oxide semiconductor layer 1100 circuit 1101 transistor 1102n transistor 1102p transistor 1103 capacitor element 1101A Transistor 1400 Semiconductor substrate 1401 Element isolation insulating film 1402 Impurity region 1403 Impurity region 1404 Gate electrode 1405 Gate insulating film 1409 Insulating film 1410 Wiring 1411 Wiring 1412 Wiring 1415 Wiring 1416 Wiring 1417 Wiring 1420 Insulating film 1421 Wiring 1430 Semiconductor film 1431 Gate insulating film 1432 conductive film 1433 conductive film 1434 gate Electrode 1435 Conductive film 1440 Insulating film 1441 Insulating film 1442 Insulating film 1443 Conductive film 2100 Circuit 2101 Transistor 2102n Transistor 2102p Transistor 2103 Capacitance element 5001 Case 5002 Case 5003 Display portion 5004 Display portion 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Body 5102 Wheel 5103 Dashboard 5104 Light 5301 Case 5302 Refrigeration room door 5303 Freezer compartment door 5401 Case 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Case 5602 Case 5603 Display unit 5604 Display unit 5605 Connection unit 5606 Operation key 5801 Housing 5802 Housing 5803 Display portion 5804 Operation key 5805 Lens 5806 Connection portion 100 circuit 8101 transistor 8102n transistor 8108 storage unit 8110 diode 8111 resistance 8112 conductor

Claims (2)

A first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor;
The first transistor has a channel formation region in a first oxide semiconductor layer;
The third transistor has a channel formation region in the second oxide semiconductor layer;
A gate of the second transistor is electrically connected to one of a source or a drain of the first transistor;
A gate of the fourth transistor is electrically connected to one of a source and a drain of the third transistor;
One of the pair of electrodes of the first capacitor is electrically connected to the gate of the second transistor;
One of the pair of electrodes of the second capacitor element is electrically connected to the gate of the fourth transistor;
The other of the pair of electrodes of the first capacitor is electrically connected to one of a source or a drain of the second transistor;
The other of the pair of electrodes of the second capacitor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;
When the first transistor is turned off, the gate of the second transistor is in a floating state,
When the third transistor is turned off, the gate of the fourth transistor is in a floating state,
The first transistor has a first gate electrode and a second gate electrode with a first oxide semiconductor layer interposed therebetween,
The first gate electrode has a function of controlling a threshold voltage of the first transistor;
The second transistor includes a third gate electrode and a fourth gate electrode with a second oxide semiconductor layer interposed therebetween,
The semiconductor device, wherein the third gate electrode has a function of controlling a threshold voltage of the second transistor. A first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor;
The first transistor has a channel formation region in a first oxide semiconductor layer;
The third transistor has a channel formation region in the second oxide semiconductor layer;
A gate of the second transistor is electrically connected to one of a source or a drain of the first transistor;
A gate of the fourth transistor is electrically connected to one of a source and a drain of the third transistor;
One of the pair of electrodes of the first capacitor is electrically connected to the gate of the second transistor;
One of the pair of electrodes of the second capacitor element is electrically connected to the gate of the fourth transistor;
The other of the pair of electrodes of the first capacitor is electrically connected to one of a source or a drain of the second transistor;
The other of the pair of electrodes of the second capacitor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;
When the first transistor is turned off, the gate of the second transistor is in a floating state,
When the third transistor is turned off, the gate of the fourth transistor is in a floating state,
The first transistor has a first gate electrode and a second gate electrode with a first oxide semiconductor layer interposed therebetween,
A signal different from the signal given to the second gate electrode is given to the first gate electrode,
The second transistor includes a third gate electrode and a fourth gate electrode with a second oxide semiconductor layer interposed therebetween,
2. The semiconductor device according to claim 1, wherein a signal different from a signal applied to the fourth gate electrode is applied to the third gate electrode.

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