JP2017055014A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of improving a dicing yield of a semiconductor substrate having a plurality of materials.SOLUTION: A method of manufacturing a semiconductor device according to an embodiment includes the following steps of: selectively etching a nitride semiconductor layer provided on a first face of a substrate having the first face and a second face until the substrate is exposed to form a first nitride semiconductor region, a second nitride semiconductor region, and a third nitride semiconductor region provided between the first nitride semiconductor region and the second nitride semiconductor region; removing the substrate from the second face side to thin the substrate; and cutting the substrate between the first nitride semiconductor region and the second nitride semiconductor region by blade dicing.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  A plurality of semiconductor elements formed on a semiconductor substrate such as a wafer is divided into a plurality of semiconductor chips by dicing along a dicing region provided on the semiconductor substrate. In some cases, the semiconductor substrate is a composite substrate made of different materials such as a GaN-based semiconductor layer / silicon substrate. When dicing a composite substrate, the physical properties of the respective materials are different, so that chipping or cracking of the substrate is likely to occur. Therefore, it is difficult to improve the dicing yield of the semiconductor device.

JP 2012-156250 A

  The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device, which can improve the dicing yield of a semiconductor substrate having a plurality of materials.

  In the semiconductor device manufacturing method of the embodiment, the nitride semiconductor layer provided on the first surface of the substrate having the first surface and the second surface is selectively etched until the substrate is exposed. A first nitride semiconductor region, a second nitride semiconductor region, and a third nitride semiconductor region provided between the first nitride semiconductor region and the second nitride semiconductor region. Forming, removing the substrate from the second surface side, thinning the substrate, and blade dicing the substrate between the first nitride semiconductor region and the second nitride semiconductor region Disconnect.

The schematic diagram which shows the semiconductor device manufactured with the manufacturing method of the semiconductor device of 1st Embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. The top view which shows the pattern after etching the GaN-type semiconductor layer of 1st Embodiment. The top view which shows the pattern after etching the GaN-type semiconductor layer of 1st Embodiment. FIG. 5 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and description of members once described is omitted as appropriate.

  In this specification, “GaN-based semiconductor” is a general term for GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and semiconductors having intermediate compositions thereof.

(First embodiment)
In the method for manufacturing a semiconductor device according to the present embodiment, a nitride semiconductor layer provided on a first surface of a substrate having a first surface and a second surface is selectively etched until the substrate is exposed, Forming a first nitride semiconductor region, a second nitride semiconductor region, and a third nitride semiconductor region between the first nitride semiconductor region and the second nitride semiconductor region; The substrate is removed from the second surface side, the substrate is thinned, and the substrate between the first nitride semiconductor region and the second nitride semiconductor region is cut by blade dicing.

  FIG. 1 is a schematic view showing a semiconductor device manufactured by the method for manufacturing a semiconductor device of this embodiment. 1A is a top view of the semiconductor device, FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB ′ in FIG.

  The semiconductor device is a semiconductor chip 100. The semiconductor chip 100 includes an element region 100a and a dicing region 100b. The element region 100a is surrounded by the dicing region 100b.

  A semiconductor element is formed in the element region 100a. The semiconductor element is, for example, a HEMT (High Electron Mobility Transistor).

  The “dicing region” is a planned region having a predetermined width for dividing a plurality of semiconductor elements formed on a semiconductor substrate into a plurality of semiconductor chips by dicing. In this specification, a dicing region remaining on the semiconductor chip after dicing is also referred to as a “dicing region”.

  The semiconductor chip 100 includes a silicon substrate (substrate) 10, a first GaN-based semiconductor layer (first nitride semiconductor layer) 12a, a second GaN-based semiconductor layer (second nitride semiconductor layer) 12b, . The first GaN-based semiconductor layer 12 a is provided on the first region 10 a of the silicon substrate 10. The second GaN-based semiconductor layer 12 b is provided on the second region 10 b of the silicon substrate 10. The second region 10b surrounds the first region 10a.

  The first region 10a of the silicon substrate 10 and the first GaN-based semiconductor layer 12a are included in the element region 100a. The second region 10b of the silicon substrate 10 and the second GaN-based semiconductor layer 12b are included in the dicing region 100b.

  For example, the first GaN-based semiconductor layer 12a and the second GaN-based semiconductor layer 12b are physically connected. The width (W in FIG. 1A) of the second GaN-based semiconductor layer 12b is, for example, 10 μm or less. The width of the second GaN-based semiconductor layer 12b is the length in a direction parallel to the direction in which the boundary between the element region 100a and the dicing region 100b extends.

  The first GaN-based semiconductor layer 12a and the second GaN-based semiconductor layer 12b have, for example, a stacked structure of a GaN layer and an AlGaN layer. A source electrode 14, a drain electrode 16, and a gate electrode 18 of HEMT are provided on the surface of the first GaN-based semiconductor layer 12a. For example, a protective film (not shown) is provided on the source electrode 14, the drain electrode 16, and the gate electrode 18. The protective film is, for example, a silicon oxide film.

  2 to 11 are schematic views showing the method for manufacturing the semiconductor device of this embodiment.

  First, a semiconductor wafer in which a GaN-based semiconductor layer (nitride semiconductor layer) 12 is provided on a silicon substrate (substrate) 10 is prepared (FIG. 2). The silicon substrate 10 includes a first surface P1 and a second surface P2.

  The film thickness of the silicon substrate 10 is, for example, 1 mm to 2 mm, and the film thickness of the GaN-based semiconductor layer 12 is, for example, 5 μm to 10 μm.

  The GaN-based semiconductor layer 12 is provided on the first surface P1 of the silicon substrate 10. The GaN-based semiconductor layer 12 is formed on the silicon substrate 10 by epitaxial growth. The GaN-based semiconductor layer 12 has a laminated structure of a GaN layer and an AlGaN layer, for example.

  Next, a plurality of semiconductor elements are formed on the GaN-based semiconductor layer 12. The semiconductor element is, for example, a HEMT.

  For example, a HEMT source electrode 14, drain electrode 16, and gate electrode 18 are formed on the surface of the GaN-based semiconductor layer 12 (FIG. 3). For example, a protective film (not shown) is formed on the source electrode 14, the drain electrode 16, and the gate electrode 18. The protective film is, for example, a silicon oxide film.

  Next, the GaN-based semiconductor layer 12 is selectively etched until the silicon substrate 10 is exposed (FIG. 4).

  FIG. 5 is a top view showing a pattern after etching the GaN-based semiconductor layer 12. After etching the GaN-based semiconductor layer 12, a first GaN-based semiconductor region (first nitride semiconductor region) 12c, a second GaN-based semiconductor region (second nitride semiconductor region) 12d, and a third GaN A system semiconductor region (third nitride semiconductor region) 12 e is left on the silicon substrate 10.

  The third GaN-based semiconductor region 12e is provided between the first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d. The first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d are provided in the element region 100a. A region between the first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d is a dicing region 100b. The third GaN-based semiconductor region 12e is provided in the dicing region 100b.

  A semiconductor element pattern is not formed in the dicing region 100b. The dicing region 100b is provided in a lattice shape on the surface side of the GaN-based semiconductor layer 12 so as to divide the element region 100a.

  The first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d correspond to the first GaN-based semiconductor layer 12a of the semiconductor chip 100 (FIG. 1) manufactured by the manufacturing method of the present embodiment. The third GaN-based semiconductor region 12e corresponds to the second GaN-based semiconductor layer 12b of the semiconductor chip 100 (FIG. 1).

  FIG. 6 is an enlarged top view of the third GaN-based semiconductor region 12e. The third GaN-based semiconductor region 12e is provided between the first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d. The third GaN-based semiconductor region 12e is physically connected to the first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d.

  The third GaN-based semiconductor region 12e is a rectangular pattern. The width (W in the drawing) of the third GaN-based semiconductor region 12e is, for example, 10 μm or less. The width of the third GaN-based semiconductor region 12e is desirably 5 μm or less.

  Etching of the GaN-based semiconductor layer 12 is performed by, for example, RIE (Reactive Ion Etching). Etching of the GaN-based semiconductor layer 12 is performed, for example, using a resist (not shown) as a mask. Etching of the GaN-based semiconductor layer 12 can also be performed by other dry etching or wet etching.

  Next, the support member 24 is bonded onto the GaN-based semiconductor layer 12 (FIG. 7). The support member 24 is bonded to the GaN-based semiconductor layer 12 using an adhesive layer 26, for example.

  The support member 24 has a function of reinforcing the semiconductor wafer when the semiconductor wafer is thinned. The support member 24 is, for example, a glass substrate.

  Next, the silicon substrate 10 is removed from the second surface P2 side of the silicon substrate 10 and thinned (FIG. 8). The thickness of the silicon substrate 10 is reduced to, for example, 100 μm or more and 200 μm or less.

  The removal of the silicon substrate 10 is so-called back grinding. For example, the silicon substrate 10 is removed by grinding using a diamond wheel.

  Next, a resin sheet 32 is attached to the second surface P2 side of the silicon substrate 10 (FIG. 9). The resin sheet 32 is, for example, a dicing tape. The resin sheet 32 is fixed to a metal frame for handling, for example.

  Next, the support member 24 is peeled from the wafer (FIG. 10).

  Next, the silicon substrate 10 between the GaN-based semiconductor layers 12 is cut by blade dicing from the first surface P1 side (FIG. 11). The silicon substrate 10 is cut along the dicing region 100b. The silicon substrate 10 between the first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d is cut. At this time, the third GaN-based semiconductor region 12e in the dicing region 100b is also cut at the same time.

  Thereafter, the resin sheet 22 is peeled from the silicon substrate 10 to obtain a plurality of divided semiconductor chips (semiconductor devices) 100.

  Hereinafter, the operation and effect of the method for manufacturing the semiconductor device of this embodiment will be described.

  When dicing a semiconductor wafer, the semiconductor wafer may be a composite substrate composed of a plurality of different materials, such as a GaN-based semiconductor layer / silicon substrate, as in this embodiment. In the dicing of the composite substrate, it is difficult to improve the yield because the physical properties of the respective materials are different.

  For example, GaN-based semiconductors are harder and more brittle than silicon. For this reason, if both materials are cut simultaneously by blade dicing, for example, chipping and cracking of the semiconductor wafer are likely to occur, and the yield decreases.

  In order to suppress chipping and cracking of the semiconductor wafer, for example, there is a method of cutting the silicon substrate after first removing the GaN-based semiconductor layer in the dicing region. However, even with this method, chipping may occur when the silicon substrate is cut.

  In the method for manufacturing a semiconductor device of this embodiment, when the GaN-based semiconductor layer 12 in the dicing region 100b is removed prior to the cutting of the silicon substrate 10, the GaN-based semiconductor layer 12 is partially left in the dicing region 100b. For example, as shown in FIGS. 5 and 6, the GaN-based semiconductor layer 12 is left between the GaN-based semiconductor layers 12 in the element region 100a. This manufacturing method makes it possible to suppress chipping when cutting the silicon substrate.

  By leaving the GaN-based semiconductor layer 12 partially in the dicing region 100b, it is considered that the stress state in the semiconductor wafer changes as compared with the case where all of the GaN-based semiconductor layer 12 in the dicing region 100b is removed. This difference in stress state is thought to lead to suppression of chipping.

  From the viewpoint of facilitating the cutting of the third GaN-based semiconductor region 12e when the silicon substrate 10 is cut, the width of the third GaN-based semiconductor region 12e is preferably 10 μm or less, and is preferably 5 μm or less. Is more desirable.

  In addition, since the semiconductor chip 100 includes the second GaN-based semiconductor layer 12b in a part of the dicing region 100b, chipping when the silicon substrate 10 is cut can be suppressed.

  12 and 13 are top views showing other examples of patterns after etching the GaN-based semiconductor layer 12. 12 and 13 show the pattern of the third GaN-based semiconductor region 12e.

  The third GaN-based semiconductor region 12e is not necessarily limited to the rectangular pattern as shown in FIG. 6, but as shown in FIGS. 12 (a), 12 (b), 12 (c), and 12 (d). The pattern may be a pattern other than a rectangle and connected to the first GaN-based semiconductor region 12c and the second GaN-based semiconductor region 12d.

  Further, the third GaN-based semiconductor region 12e may be a pattern separated into a plurality of regions as shown in FIGS. 13 (a), 13 (b), 13 (c), and 13 (d). I do not care. For example, FIG. 13A shows a major pattern. By adopting the pattern of FIG. 13A, for example, it is possible to measure the amount of misalignment during dicing afterwards.

  As described above, according to the semiconductor device manufacturing method of the present embodiment, it is possible to improve the dicing yield of a substrate having a plurality of materials.

(Second Embodiment)
The manufacturing method of the semiconductor device of this embodiment is the same as that of the first embodiment except that the substrate is cut from the second surface side by blade dicing. Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 14 is a schematic view showing the method for manufacturing the semiconductor device of this embodiment. The process is the same as that of the first embodiment until the silicon substrate 10 is removed from the second surface P2 side of the silicon substrate 10 and thinned.

  Next, as shown in FIG. 14, the silicon substrate 10 between the GaN-based semiconductor layers 12 is cut from the second surface P2 side by blade dicing.

  Thereafter, the support member 24 is peeled from the silicon substrate 10 to obtain a plurality of divided semiconductor chips (semiconductor devices) 100.

  According to the semiconductor device manufacturing method of the present embodiment, the dicing yield of a substrate having a plurality of materials can be improved as in the first embodiment. In addition, the manufacturing method is simplified as compared with the first embodiment.

  In the first and second embodiments, the case where the semiconductor element is a HEMT has been described as an example. However, the semiconductor element is not limited to a HEMT. It is also possible to apply other semiconductor elements such as a vertical MOSFET.

  In the first and second embodiments, the silicon substrate is described as an example of the substrate. However, a substrate other than the silicon substrate, for example, a sapphire substrate, a silicon carbide (SiC) substrate, or the like is applied. Is possible.

  Although several embodiments and examples of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 Silicon substrate (substrate)
10a First region 10b Second region 12 GaN-based semiconductor layer (nitride semiconductor layer)
12a First GaN-based semiconductor layer (first nitride semiconductor layer)
12b Second GaN-based semiconductor layer (second nitride semiconductor layer)
12c First GaN-based semiconductor region (first nitride semiconductor region)
12d Second GaN-based semiconductor region (second nitride semiconductor region)
12e Third GaN-based semiconductor region (third nitride semiconductor region)
24 Support member 100 Semiconductor chip (semiconductor device)

Claims (8)

A nitride semiconductor layer provided on the first surface of the substrate having the first surface and the second surface is selectively etched until the substrate is exposed to form a first nitride semiconductor region, 2 nitride semiconductor regions, and a third nitride semiconductor region provided between the first nitride semiconductor region and the second nitride semiconductor region,
Removing the substrate from the second surface side, thinning the substrate;
A method for manufacturing a semiconductor device, comprising cutting the substrate between the first nitride semiconductor region and the second nitride semiconductor region by blade dicing.   The method for manufacturing a semiconductor device according to claim 1, wherein a support member is bonded onto the nitride semiconductor layer before the substrate is thinned.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is cut from the first surface side by blade dicing.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is cut from the second surface side by blade dicing.   The method for manufacturing a semiconductor device according to claim 1, wherein the third nitride semiconductor region is connected to the first nitride semiconductor region and the second nitride semiconductor region.   The method for manufacturing a semiconductor device according to claim 1, wherein a width of the third nitride semiconductor region is 10 μm or less.   The method for manufacturing a semiconductor device according to claim 1, wherein the nitride semiconductor layer is a GaN-based semiconductor layer.   The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is a silicon substrate.

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