JP2017054174A - Receiving apparatus, receiving method, and transfer apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiving apparatus or the like, which can receive data in a short period or time, even when an error occurs in processing of receiving the data.SOLUTION: A receiving apparatus 404 includes: a receiving controller 401 which receives element data included in object data, to determine whether the received element data includes an error or not; and a memory controller 402 which stores the element data in the order of reception, on a memory, and stores a storage location of the element data including the error when the element data includes the error. In receiving again the element data included in the object data, the memory controller 402 stores the data following the element data and corresponding to the element data including the error, out of the object data received again, in positions following the storage location.SELECTED DRAWING: Figure 20

Description

  The present invention relates to a receiving apparatus that receives data to be transferred.

  In the interface standard related to SATA, for a control system FIS such as an instruction and status, a process for retransmitting a frame in which an error has occurred in response to an error related to FIS is defined. On the other hand, in the interface standard, for data FIS, a process for retransmitting a frame in response to an error response related to FIS is not defined.

  SATA represents an abbreviation for serial AT_Attachment. FIS represents an abbreviation of Frame_Information_Structure (frame information structure).

  According to the interface standard, when an error occurs in the data FIS during data transmission / reception, processing for issuing a command for transmitting / receiving the data FIS, processing for transmitting / receiving the data FIS, and status after the transmission / reception processing are performed. It is necessary to re-execute a series of processes such as an update process. As a result, when an error occurs with respect to the data FIS, it is necessary to repeatedly execute the process executed until the error occurs, so the process executed before the error occurs is useless.

  The interface device disclosed in Patent Literature 1 includes a decoding unit, a holding unit, a CRC unit, an error detection unit, and a data processing unit. CRC represents an abbreviation for Cyclic_Redundancy_Check. The decoding unit decodes the received data and holds the decoded data in the holding unit. The CRC unit detects a CRC error for the decoded data. The error detection unit detects a decoding error with respect to the decoded data. When the decoding error detected by the error detection unit is an error related to data to be processed during the period when synchronization is ensured in the interface, and the CRC unit does not detect a CRC error, the data processing unit The decoded data that is held is processed as valid data.

  The data transfer control device disclosed in Patent Document 2 includes a reception circuit, an error detection circuit, a FIFO circuit, and a control circuit. FIFO represents an abbreviation for First-In_First-Out. The receiving circuit receives transmission data transmitted in a predetermined data unit. The error detection circuit detects an error in the received transmission data. The control circuit controls processing for transferring the transmission data stored in the FIFO circuit to a subsequent apparatus based on an address pointer indicating an area in the FIFO circuit. When the error detection circuit does not detect an error, the data transfer control device receives the next transmission data by incrementing the address pointer by a predetermined data unit. When the error detection circuit detects an error, the data transfer control device transmits an instruction for decrementing the address pointer in the communication destination by a predetermined data unit to the communication destination and receives the next transmission data.

JP 2011-248977 A JP 2008-017250 A

  However, even if Patent Document 1 is used, it is difficult to efficiently execute the transfer process related to the target data when an error occurs in the transfer process related to the target data. This is because, when an error occurs in the transfer process related to the target data, the apparatus re-executes the transfer process.

  Accordingly, a main object of the present invention is to provide a receiving apparatus or the like that can receive data in a short time even when an error occurs in the process of transferring data.

In order to achieve the above object, in one embodiment of the present invention, a receiving device includes:
A receiving controller that receives element data included in target data and determines whether the received element data includes an error; and
A memory controller that stores the element data in a memory in the order in which the element data is received and stores the position where the element data including the error is stored when the reception controller determines that the element data includes the error And
When the memory controller re-receives the element data included in the target data, the memory controller follows the element data corresponding to the element data including the error among the re-received target data. The data to be stored are sequentially stored in the storage area of the memory with the saved position as a reference.

As another aspect of the present invention, the receiving method is:
In an apparatus comprising a reception controller that receives element data included in target data and determines whether the received element data includes an error,
The element data is stored in the memory in the order received, and when the element data includes the error, the position where the element data including the error is stored is stored, and is included in the target data. When the received element data is received again, the subsequent data after the element data corresponding to the element data including the error is stored after the saved position among the re-received target data. .

  According to the transfer device and the like according to the present invention, even when an error occurs in the process of transferring data, the data can be received in a short time.

It is a block diagram which shows the structure which the computer system which concerns on the 1st Embodiment of this invention has. It is a block diagram which shows the structure which a DMA controller has. It is a block diagram which shows the structure which a PRD table has. FIG. 11 is a diagram conceptually illustrating a Count field related to an instruction “Set_Features”. It is a flowchart which shows the flow of a process in the SATA controller which controls the process which transmits FIS via SATA. It is a flowchart which shows the flow of a process in the SATA controller which controls the process which receives FIS via SATA. It is a flowchart which shows the flow (1/2) of the process in a DMA controller. It is a flowchart which shows the flow (2/2) of the process in a DMA controller. It is a block diagram which shows the structure which the computer system concerning the 2nd Embodiment of this invention has. FIG. 11 is a sequence diagram showing a flow of processing in a transfer device according to the second embodiment in the case of a read command. FIG. 5 is a diagram conceptually illustrating an example (1/2) of data transmitted and received by a transfer device. It is a figure which represents notionally an example (2/2) of the data which a transfer apparatus transmits / receives. It is a sequence diagram which shows the flow of a process in the computer system which concerns on 2nd Embodiment. It is a flowchart which shows the flow (1/4) of the process in a DMA controller. It is a flowchart which shows the flow (2/4) of the process in a DMA controller. It is a flowchart which shows the flow (3/4) of the process in a DMA controller. It is a flowchart which shows the flow (4/4) of the process in a DMA controller. It is a block diagram which shows the structure which the transfer apparatus which concerns on the 3rd Embodiment of this invention has. It is a sequence diagram which shows the flow of a process in the transfer apparatus which concerns on 3rd Embodiment. It is a block diagram which shows the structure which the transfer apparatus which concerns on the 4th Embodiment of this invention has. It is a flowchart which shows the flow of a process in the transfer apparatus which concerns on 4th Embodiment.

  Next, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

<First Embodiment>
The configuration of the computer system 101 according to the first embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a block diagram showing the configuration of the computer system 101 according to the first embodiment of the present invention.

  The computer system 101 according to the first embodiment roughly includes a host device 102 and a device 107. The host device 102 includes a memory 103 and a transfer device 104. The device 107 includes a memory 108 and a transfer device 109. The transfer device 104 includes a DMA controller 105 and a SATA controller 106. The transfer device 109 includes a DMA controller 110 and a SATA controller 111. The host apparatus 102 and the device 107 can transmit and receive information (data) via the SATA controller 106, the SATA controller 111, and a communication path through which the SATA controller 106 and the SATA controller 111 can be connected. The communication path is, for example, the SATA interface 112.

  The configuration of the DMA controller 121 (for example, the DMA controller 105 or the DMA controller 110) will be described in more detail with reference to FIG. FIG. 2 is a block diagram showing a configuration of the DMA controller 121. As shown in FIG.

  The DMA controller 121 includes a PRD table pointer register 122, a PRD index register 123, a DMA base address register 124, and a DMA byte count register 125. PRD represents an abbreviation for Physical_Region_Descriptor.

  The PRD table pointer register 122 can store the start address of a storage area in the memory 103 in which a PRD table (FIG. 3, which will be described later) is stored. Hereinafter, the head address of the storage area in which the PRD table is stored is represented as “PRD base address” (or “transfer base address”).

  The PRD index register 123 can store the start address of the storage area in the PRD table that stores information related to the target data being transferred. Note that the PRD index register 123 may be a relative address when the value stored in the PRD table pointer register 122 is used as a reference. In this case, in the PRD table, the start address of the storage area that stores information related to the data being transferred is stored in the PRD table pointer register 122 and the PRD index register 123. Is the sum of Hereinafter, for convenience of explanation, it is assumed that the PRD index register 123 can store the relative address.

  The DMA base address register 124 can store the start address of the storage area that stores the target data to be transferred.

  The DMA byte count register 125 can store the size (size, length) of the target data.

  The DMA controller 121 may further include a transfer count register. The Transfer count register can store, for example, the size (size, length) of data for which transfer processing has been completed for the target data.

  In the following description, for convenience of explanation, it is assumed that the DMA controller 121 has a Transfer count register.

  In each embodiment of the present invention, a specific value can be stored using a register. However, the register is not necessarily a dedicated register for storing the specific value, but a dedicated register using a general-purpose register. A function corresponding to may be realized. Alternatively, the register capable of storing a value may be a partial storage area in the memory 103. Further, it is assumed that the host apparatus 102 and the device 107 each have the register shown in FIG.

  Next, the configuration of the PRD table referred to in the transfer process will be described in more detail with reference to FIG. FIG. 3 is a block diagram showing the configuration of the PRD table.

  The PRD table is an address in which a head address (base address) indicating a storage area in which target data to be transferred is stored and a byte count indicating the size (size, length) of the target data are associated with each other. It is a table capable of storing at least one set.

  The start address is a value indicating a storage area in the memory (the memory 103 or the memory 108) that stores the target data. Hereinafter, the head address of the storage area storing the value to be transferred is represented as “transfer base address” or the like. In the following description, the byte count may be expressed as “transfer size” or the like.

  In other words, when there are a plurality of target data, the PRD table can store a plurality of types of address sets in which the start address related to each target data is associated with the size related to the target data.

  For convenience of explanation, it is assumed that the PRD table includes N address sets (where N is a natural number). Also, the I (where 1 ≦ I ≦ N) th address set is represented as “the I-th address set”. Further, the transfer base address included in the I-th address set is expressed as “I-th transfer base address”, and the transfer size included in the I-th address set is expressed as “I-th transfer size”. The target data that can be stored in the storage area represented by the I-th address set is represented as “first target data”.

  Next, an instruction “Set_Features” transmitted and received by the SATA controller 106 according to the first embodiment will be described with reference to FIG. FIG. 4 is a diagram conceptually showing a Count field related to the instruction “Set_Features”. That is, the instruction “Set_Features” has a vendor-specific subcommand in the Feature field and has detailed command information in the Count field.

  The command “Set_Features” is, for example, a command for setting the function of the device device to be valid or invalid. For example, the information to be notified to the device 107 is information described in the Feature field and the Count field. The instruction “Set_Features” is realized through a sub-instruction unique to a vendor such as a transfer apparatus, for example. The instruction “Set_Features” includes a Feature field. Furthermore, Set_Features includes a Count field. The Count field can store information (for example, data amount and data size) related to transfer processing between the host apparatus 102 and the device 107 in the normal command.

  The Count field according to the present embodiment will be described in detail. The upper 4 bits (“bits [7: 4]” in FIG. 4) of the value stored in the Count field represent, for example, the number of times the process is repeated with respect to a retransmission process described later. The lower 4 bits of the value (“bit [3: 0]” in FIG. 4) represent, for example, a value related to the instruction content indicating the instruction content.

  When the number of repetitions is 0, for example, the retransmission process is in an invalid state regardless of the value related to the instruction content. When the number of repetitions is 1 or more, for example, it indicates that the retransmission process is in an effective state. Furthermore, when the number of repetitions is a value of 1 or more, this value represents, for example, a threshold value for determining whether or not the retransmission process is abnormally terminated. In other words, when the number of repetitions is a value of 1 or more, when a retransmission process is requested more than the number of repetitions, the apparatus described later abnormally ends with respect to the retransmission process.

  In the Count field illustrated in FIG. 4, “3” is stored in the upper 4 bits (“bit [7: 4]” in FIG. 4), and the lower 4 bits (“bit [3: 0]” in FIG. 4). ) Stores “0”. “3” stored in the upper 4 bits indicates that the retransmission process is set to the valid state, and that the retransmission process is abnormally terminated when the number of repetitions related to the retransmission process is three or more. Also, “0” stored in the lower 4 bits represents a retransmission process executed due to R_ERR (p) transmission.

  Next, a process for controlling the process in which the SATA controller 106 according to the first embodiment transmits and receives the FIS will be described with reference to FIGS. 5 and 6. FIG. 5 is a flowchart showing a process flow in the SATA controller 106 that controls the process of transmitting the FIS via the SATA. FIG. 6 is a flowchart showing a process flow in the SATA controller 106 that controls the process of receiving the FIS via the SATA.

  For convenience of explanation, it is assumed that the SATA controller 106 in the host apparatus 102 receives, for example, an instruction representing a write process in which the host apparatus 102 outputs data to the device 107 (hereinafter referred to as “write instruction”) from an external apparatus or the like. Furthermore, in the processing according to the write command, data that is the target that the host apparatus 102 transmits to the device 107 is represented as “target data”. Further, an instruction representing a process in which the device 107 outputs data to the host apparatus 102 is represented as a “read instruction”.

  First, the SATA controller 106 in the host apparatus 102 receives the write command transmitted from the external apparatus, and starts processing to transmit the FIS related to the target data to the SATA controller 111 in the device 107 in accordance with the received write command (step). S101). When the process is started, the SATA controller 106 in the host apparatus 102 creates a Feature field based on the received write command, and transmits a command “Set_Features” including the created Feature field to the SATA controller 111 in the device 107. . With this processing, the SATA controller 106 in the host apparatus 102 notifies the SATA controller 111 in the device 107 of the status related to the host apparatus 102. Thereafter, the SATA controller 106 in the host apparatus 102 transmits the received command (in this case, a write command) to the SATA controller 111 in the device 107.

  Further, in the processing shown in step S101, the SATA controller 106 in the host apparatus 102 creates instruction parameter information based on the received instruction, and then executes control to activate the DMA controller 105 in the host apparatus 102. For example, the command parameter information based on the command includes the type of processing, the size of the target data, the location information storing the target data, and the like. The command parameter information relating to the instruction according to the command does not necessarily include all the items described above.

  The DMA controller 105 in the host apparatus 102 starts up and executes processing based on the command parameter information created by the SATA controller 106 in the host apparatus 102 in response to executing the control that the SATA controller 106 in the host apparatus 102 starts up. . The processing in the DMA controller 105 will be described later with reference to FIGS.

  On the other hand, the SATA controller 111 in the device 107 receives the command “Set_Features” and the write command transmitted by the SATA controller 106 in the host device 102. That is, in this example, the SATA controller 111 in the device 107 starts a process of receiving target data (step S121). For example, the SATA controller 111 in the device 107 recognizes that the host apparatus 102 is a device that can perform retransmission processing based on the Feature field included in the received command “Set_Features”, and performs retransmission processing based on the Count field. Enable or disable. Further, the SATA controller 111 in the device 107 starts processing according to the received write command.

  In the processing shown in step S121, the SATA controller 111 in the device 107 creates command parameter information based on the write command, and then executes control to activate the DMA controller 110 in the device 107. For example, the instruction parameter information based on the instruction includes the type of processing, the size of the target data, the position information storing the target data, and the like. The DMA controller 110 in the device 107 starts up and executes processing based on the command parameter information created by the SATA controller 111 in the device 107 in accordance with the control that the SATA controller 111 in the device 107 starts up. The DMA controller 110 will be described later with reference to FIGS.

  Next, the SATA controller 106 in the host apparatus 102 transmits data FIS related to the target data to the SATA controller 111 in the device 107 (step S102). In this case, the SATA controller 106 in the host device 102 further detects data relating to the target data (or FIS) (for example, data calculated according to CRC, hereinafter referred to as “CRC data”). Send. That is, an error occurring in the FIS related to the target data can be detected by the process of referring to the CRC data. CRC represents an abbreviation for Cyclic_Redundancy_Check. In the present embodiment, description regarding CRC is omitted.

  In response to this, the SATA controller 111 in the device 107 receives the data FIS transmitted from the SATA controller 106 in the host apparatus 102 (step S122). Further, the SATA controller 111 in the device 107 receives the CRC data, and determines whether or not the received data FIS includes an error based on the received CRC data (step S123). In other words, the SATA controller 111 in the device 107 determines whether an error has occurred for each element data constituting the target data based on the received CRC data.

  The SATA controller 111 in the device 107, when the received data FIS does not contain an error (NO in step S123), a response signal indicating that the data FIS has been received normally (hereinafter referred to as “normal response signal”). ). The SATA controller 111 in the device 107 transmits the created normal response signal to the SATA controller 106 in the host apparatus 102 (step S127).

  If NO in step S123, the SATA controller 111 in the device 107 transmits a normal response signal to the DMA controller 110 in the device 107.

  When the received data FIS includes an error (YES in step S123), the SATA controller 111 in the device 107 selects a response signal to be transmitted according to a certain criterion (step S124), and transmits the selected response signal. . A certain criterion is, for example, a condition indicating whether or not the number of times an error has occurred is equal to or less than a predetermined number. The predetermined number of times is stored, for example, in the Count field in the instruction “Set_Features” shown in FIG. When the SATA controller 111 in the device 107 determines that the certain criterion is satisfied (YES in step S124), the SATA controller 111 selects a response signal (hereinafter referred to as “request response signal”) indicating a request to retransmit the target data. The selected request response signal is transmitted to the SATA controller 106 in the host apparatus 102 (step S125). In the process shown in step S125, the SATA controller 111 in the device 107 outputs a retransmission notification signal for executing a retransmission process on the data FIS in which an error has occurred to the DMA controller 110 in the device 107. The DMA controller 110 in the device 107 receives the retransmission notification signal output from the SATA controller 111 in the device 107 (step S156 in FIG. 8, which will be described later). When the SATA controller 111 in the device 107 determines that the certain determination criterion is not satisfied (NO in step S124), a response signal indicating that the target data has not been correctly received (hereinafter referred to as "abnormal response signal"). Select). The SATA controller 111 in the device 107 outputs the selected abnormality response signal to the DMA controller 110 in the device 107 in the process shown in step S126. The DMA controller 110 in the device 107 inputs the abnormality notification signal output from the SATA controller 111 in the device 107 (step S156 in FIG. 8, which will be described later).

  In other words, the SATA controller 111 in the device 107 outputs a retransmission notification signal to the DMA controller 110 in the device 107 in the case of YES in step S124, and an abnormality notification in the case of NO in step S124. Output a signal. For example, regarding the data FIS causing the error, the SATA controller 111 in the device 107 selects an abnormal response signal when the number of errors is larger than a predetermined number, and the number of errors is a predetermined number. If it is less than the number of times, a request response signal is selected.

  The SATA controller 106 in the host apparatus 102 receives the response signal (normal response signal, abnormal response signal, or request response signal) transmitted by the SATA controller 111 in the device 107 (step S103), and transmits the data FIS. The process ends (step S104). Note that the SATA controller 106 in the host device 102 may execute a process of waiting for a response signal within a period from when the target data is transmitted (step S102) until the response signal is received (step S103).

  Thereafter, the SATA controller 106 in the host apparatus 102 transmits the received response signal to the DMA controller 105 in the host apparatus 102.

  Processing for transmitting such a response signal will be described in detail. The SATA controller 106 in the host device 102 determines whether or not the received response signal is a normal response signal (step S105). When the received response signal is a normal response signal (YES in step S105), the SATA controller 106 in the host device 102 sends a notification signal indicating that no error has occurred to the DMA controller 105 in the host device 102. Output. Hereinafter, for convenience of explanation, a notification signal indicating that no error has occurred is referred to as a “normal notification signal”. Thereafter, the SATA controller 106 in the host apparatus 102 normally ends the processing relating to the data FIS (step S109). The DMA controller 105 in the host apparatus 102 inputs the normal notification signal output from the SATA controller 106 in the host apparatus 102 (step S156 in FIG. 8, which will be described later).

  If the received response signal is not a normal response signal (NO in step S105), the SATA controller 106 in the host device 102 determines whether the received response signal is a request response signal (step S106). When the response signal is the request response signal (YES in step S106), the SATA controller 106 in the host apparatus 102 sends a retransmission notification signal for retransmitting the data FIS in which an error has occurred to the DMA controller 105 in the host apparatus 102. Output. Thereafter, the SATA controller 106 in the host apparatus 102 sets the command parameter information related to the process for retransmitting the target data, and then ends the retransmission (step S107). The DMA controller 105 in the host apparatus 102 inputs the retransmission notification signal output from the SATA controller 106 in the host apparatus 102 (step S156 in FIG. 8, which will be described later).

  When the response signal is not the request response signal (NO in step S106), the SATA controller 106 in the host apparatus 102 outputs an abnormality notification signal indicating that the abnormal termination has been performed to the DMA controller 105 in the host apparatus 102. . Thereafter, the SATA controller 106 in the host apparatus 102 abnormally ends the transfer process related to the data FIS (step S108). Since an abnormal response signal is transmitted when the error related to the data FIS is larger than the predetermined number of times, the transfer process related to the data FIS has failed even though the transfer process related to the data FIS is repeatedly executed. Represents that. The DMA controller 105 in the host apparatus 102 inputs the abnormality notification signal output from the SATA controller 106 in the host apparatus 102 (step S156 in FIG. 8, which will be described later).

  Next, processing in the DMA controller 105 will be described with reference to FIG. FIG. 7 is a flowchart showing a process flow (1/2) in the DMA controller 105. DMA represents an abbreviation for Direct_Memory_Access.

  The DMA controller 105 in the host apparatus 102 starts processing in response to executing control that is activated by the SATA controller 106 in the host apparatus 102. Similarly, the DMA controller 110 in the device 107 starts processing in response to executing control that is activated by the SATA controller 111 in the device 107.

The DMA controller 105 in the host apparatus 102 reads, for example, the instruction parameter information created by the SATA controller 106 in the host apparatus 102 in step S101. Based on the read instruction parameter information, all the target data, that is, N pieces of data are stored in the memory 103. A storage area capable of storing the target data is secured, and a PRD table indicating the area is prepared (step S131).
The DMA controller 105 in the host apparatus 102 stores the head address of the prepared PRD table (that is, “PRD base address”) in the PRD table pointer register (step S132). The DMA controller 105 in the host device 102 secures a memory area for temporarily storing data to be transferred in the transfer process according to the instruction FIS (step S133). The DMA controller 105 in the host apparatus 102 stores the number (for example, 1) of the target data to start processing in the PRD index register (step S134).

  By the processing shown in steps S131 to S134, the DMA controller 105 in the host apparatus 102 performs preparations related to processing for transferring all target data, that is, N target data. By the processing shown in step S134, the DMA controller 105 in the host apparatus 102 prepares for transmitting the first target data included in the N target data.

  Similarly, the DMA controller 110 in the device 107 reads the instruction parameter information created by the SATA controller 111 in the device 107 in step S121, and based on the read instruction parameter information, the same processing as in steps S131 to S134 is performed. Execute the process.

  The DMA controller 105 calculates an address indicating a storage area in which an address related to the first target data is stored (step S135). More specifically, the process shown in step S135 will be described. First, the DMA controller 105 in the host apparatus 102 reads the PRD base address stored in the PRD table pointer register and the value stored in the PRD index register, and reads the read PRD base address and the read value. Calculate the sum. The PRD table pointer register stores a head address indicating a storage area in which the PRD table is stored. The PRD index register stores a value indicating the first target data being processed among the N target data included in the PRD table.

  The DMA controller 105 in the host apparatus 102 reads an address set (that is, a part of the PRD table) related to the first target data from the storage area indicated by the calculated head address (step S136). The DMA controller 105 in the host apparatus 102 stores the transfer base address included in the read address set in the DMA base address register (step S137). The DMA controller 105 in the host apparatus 102 stores the byte count value (that is, “transfer size”) included in the read address set in the DMA byte count register (step S138). By the processing shown in steps S137 and S138, the DMA controller 105 in the host apparatus 102 stores the transfer base address related to the first target data in the DMA base address register, and stores the size related to the first target data in the DMA byte count register. .

  Similarly, the DMA controller 110 in the device 107 executes processing similar to the processing shown in steps S135 to S138 in the device 107.

  The DMA controller 105 in the host device 102 determines whether or not the retransmission process is valid from the instruction parameter information read in step S131. Further, the DMA controller 105 in the host apparatus 102 determines whether or not the notification signal input in step S156 is a retransmission notification signal (step S139). For example, the DMA controller 105 can implement the processing shown in step S139 by referring to the storage area in which the notification signal is stored. When the retransmission processing is valid and the notification signal is a retransmission notification signal (YES in step S139), the DMA controller 105 in the host apparatus 102 stores the data stored in the Transfer count register and the FIS offset register. Is stored (step S140). By this processing, the DMA controller 105 in the host apparatus 102 stores, for example, in the Transfer count register that can store the FIS number that is being transferred, in the storage area that can store the FIS number that starts resending in response to the retransmission request. Stores the stored value. That is, by this processing, the DMA controller 105 in the host apparatus 102 starts processing for transferring the first target data from the FIS number.

  For convenience of explanation, it is assumed that the size of one entry in the PRD table is the same as the size of the FIS in the above-described processing. The same applies to the embodiments described below. However, the size of one entry in the PRD table and the size of the FIS are not necessarily the same.

  If the type of processing is not retransmission processing or the notification signal is not a retransmission notification signal (NO in step S139), the DMA controller 105 in the host apparatus 102 stores 1 in the Transfer count register (step S141). The Transfer count register stores how much data is transferred in one entry of the PRD. For example, the DMA controller 105 in the host apparatus 102 starts a process of transferring the first target data from the first FIS.

  Similarly, the DMA controller 105 in the device 107 executes the same processing as the processing shown in steps S131 to S141 in the device 107.

  Next, processing in the DMA controller 105 subsequent to step S140 (or step S141) will be described with reference to FIG. FIG. 8 is a flowchart showing a process flow (2/2) in the DMA controller 105.

  The DMA controller 105 in the host apparatus 102 stores the value stored in the PRD index register in the FIS index register (step S152). Further, the DMA controller 105 in the host apparatus 102 stores the value (for example, 1) stored in the Transfer count register in the FIS offset register (Step S153). Even if an error occurs in the FIS by the processing shown in steps S152 and S153, for example, the transfer device 104 can reprocess the FIS in which the error has occurred by referring to the FIS index register or the like. it can.

  The DMA controller 105 in the host device 102 reads the value stored in the DMA base address register and the value stored in the Transfer count register, and calculates a value obtained by adding the two read values. The value calculated by the DMA controller 105 in the host apparatus 102 represents a DMA address representing a storage area in which data transferred by the DMA controller 105 with respect to target data is stored.

  The DMA controller 105 in the host apparatus 102 reads data having a size corresponding to the size of the data FIS from the storage area indicated by the calculated DMA address, and outputs the read data to the SATA controller 106 in the host apparatus 102. To do.

  The SATA controller 106 in the host apparatus 102 receives the data output from the DMA controller 105 in the host apparatus 102 and transmits the input data to the SATA controller 111 in the device 107. The SATA controller 111 in the device 107 receives the data transmitted by the SATA controller 106 in the host apparatus 102 and outputs the received data to the DMA controller 110 in the device 107. That is, the DMA controller 105 in the host apparatus 102 executes a DMA transfer process (step S154).

  The DMA controller 105 in the host device 102 reads the value stored in the Transfer count register, and adds the size of the transferred data to the read value. The DMA controller 105 in the host device 102 stores a value calculated as a result of the addition in the Transfer count register. That is, the DMA controller 110 in the host device 102 increases the value stored in the Transfer count register by the size of the transferred data (for example, the number of FIS) (step S155).

  The DMA controller 110 in the device 107 reads the data stored in the DMA base address register and the data stored in the Transfer count register, and adds the two read data. In this process, the value calculated by the DMA controller 110 represents a DMA address representing a storage area in which the DMA controller 110 stores received data.

  The DMA controller 110 in the device 107 receives the data output from the SATA controller 111 in the device 107, and stores the input data in a storage area starting from the calculated DMA address. That is, the DMA controller 110 in the device 107 executes a DMA transfer process (step S154).

  The DMA controller 110 in the device 107 reads a value stored in the Transfer count register, calculates a value obtained by adding the number of data stored in the storage area and the read value, and uses the calculated value as the Transfer count. Store in register. That is, the DMA controller 110 in the device 107 increases the value stored in the transfer count register by the size of the received data (step S155).

  That is, according to the processing shown in steps S152 to S155, the DMA controller 110 in the device 107 and the DMA controller 105 in the host apparatus 102 execute processing for transferring the data FIS related to the first target data.

  The DMA controller 105 in the host apparatus 102 inputs the notification signal output from the SATA controller 106 in the host apparatus 102 (step S156). The DMA controller 105 in the host apparatus 102 determines whether or not the notification signal received in step S156 is a retransmission notification signal (step S157). Hereinafter, when the notification signal is a retransmission notification signal, the retransmission setting information is also expressed as valid.

  When the notification signal is a retransmission notification signal (YES in step S157), the DMA controller 105 in the host apparatus 102 stores the value stored in the FIS index register in the PRD index register (step S158). Thereafter, the DMA controller 105 in the host apparatus 102 executes the process shown in step S135 (FIG. 7). When the notification signal is a retransmission notification signal, the DMA controller 105 in the host device 102 sets the value stored in the PRD index register to the value stored in step S152 by the process shown in step S158.

  If the notification signal is not a retransmission notification signal (NO in step S157), the DMA controller 105 in the host apparatus 102 determines whether or not all transfer processes relating to a plurality of target data have been completed (step S159).

  In step S159, the DMA controller 105 in the host apparatus 102 determines, for example, whether the most significant bit of the value stored in the PRD index register is “0” or “1”. By this processing, the DMA controller 105 in the host apparatus 102 determines whether or not the address set for which the transfer processing has been performed is the Nth target data. That is, when there are a plurality of target data, the DMA controller 105 in the host apparatus 102 determines whether or not the process of transferring the target data is completed for all the target data.

  When all the transfer processes related to the plurality of target data are completed (YES in step S159), the DMA controller 105 in the host apparatus 102 ends the process of transferring the target data. If there is target data for which transfer processing has not been completed (NO in step S159), the DMA controller 105 in the host apparatus 102 increases the value of the PRD index register by 1 (step S160). By the processing shown in step S160, the DMA controller 105 in the host apparatus 102 can start processing regarding the (I + 1) th target data.

  Similarly, the DMA controller 110 in the device 107 executes processing similar to the processing shown in steps S152 to S160 in the device 107.

  Next, effects achieved by the transfer device 104 according to the present embodiment will be described.

  According to the transfer device 104 according to the first embodiment, even when an error occurs in the data transfer process, the data can be transferred in a short period of time, and a hardware-related failure occurs. Even so, the processing can be stopped.

  The reason why the transfer device 104 according to the present embodiment has the above-described effect will be described below in comparison with Patent Document 1 and Patent Document 2.

  For example, it is assumed that an error occurs in two data FIS out of N data FIS transferred in the process of transferring the I-th (where 1 ≦ I ≦ N) target data. The two data FISs are an A-th data FIS and a B-th data FIS. Under this premise, the flow of processing in which the device disclosed in Patent Document 1 transfers the target data will be described, and then the flow of processing in which the transfer device 104 according to the present embodiment transfers the target data. explain. Thereafter, the reason why the difference between the two processes has the above-described effect will be described.

  The apparatus disclosed in Japanese Patent Laid-Open No. 2004-228688 roughly executes a preparation process (such as setting of various registers) related to a transfer process and a transfer process that transfers the target data when executing a process related to the target data. When an error occurs in the A-th data FIS, the apparatus re-executes processing related to the target data. That is, when an error occurs regarding the A-th data FIS, the apparatus re-executes the preparation process and the transfer process. Further, when an error occurs in the B-th data FIS in the process related to the target data, the apparatus re-executes the process related to the target data. That is, in the example as described above, the apparatus executes the preparation process and the transfer process three times.

  On the other hand, when an error occurs in the A-th data FIS, the transfer device 104 performs the transfer process (step S135) without executing the preparation process shown in steps S131 to S134 by the process shown in step S158. Through step S138 and step S152 through step S156). Further, when an error occurs in the B-th data FIS in the second transfer process, the transfer apparatus 104 performs the transfer process without executing the preparation processes shown in steps S131 to S134 for the same reason. Run. As a result, according to the transfer device 104 according to the present embodiment, only one (times) transfer process is required, so that the preparation process is less than that of the device disclosed in Patent Document 1. Therefore, according to the transfer apparatus 104 according to the present embodiment, data can be transferred efficiently in a situation where a transfer error occurs.

  Further, the apparatus disclosed in Patent Document 2 cannot end the process when hardware (for example, a storage area) storing target data fails. This is because the apparatus repeatedly repeats the transfer process for the data during the period in which the error is generated for the data causing the error. For example, when a storage area fails, with respect to data stored in the storage area, an error occurs each time the data is read. Since the apparatus repeatedly executes the transfer process in response to an error, the transfer process cannot be terminated.

  On the other hand, the transfer apparatus according to the first embodiment determines whether or not to execute a retransmission process based on the Count field shown in FIG. 4 (step S124 in FIG. 6). Repeat the transfer process. Therefore, according to the transfer apparatus according to the first embodiment, it is possible to stop processing even when a hardware-related failure occurs.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

  In the following description, the characteristic parts according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  With reference to FIG. 9, the configuration of the computer system 201 according to the second embodiment of the present invention will be described in detail. FIG. 9 is a block diagram showing a configuration of a computer system 201 according to the second embodiment of the present invention.

  A computer system 201 according to the second embodiment roughly includes a host device 202 and a device 207. The host device 202 includes a memory 103 and a transfer device 204. The device 207 includes a memory 108 and a transfer device 209. The transfer device 204 includes a DMA controller 205 and a SATA controller 206. The transfer device 209 includes a DMA controller 210 and a SATA controller 211. The host device 202 and the device 207 communicate information (data) via the SATA controller 206, the SATA controller 206, and a communication path (for example, the SATA interface 112) through which the SATA controller 206 and the SATA controller 206 can be connected. Can be sent and received.

  Processing in the transfer device 204 according to the second embodiment will be described with reference to FIG. FIG. 10 is a sequence diagram illustrating a processing flow in the transfer apparatus 204 according to the second embodiment when the host apparatus 202 performs a read command for reading data in the device 207.

  The SATA controller 206 in the host device 202 is configured to send a command FIS that represents a read command for the host device 202 to receive data from the device 207 or a write command for the host device 202 to transmit data to the device 207. (Step S201). The SATA controller 206 in the host device 202 outputs to the DMA controller 205 in the host device 202 (step S203).

  The DMA controller 205 in the host device 202 inputs the instruction FIS output from the SATA controller 206 in the host device 202 (step S204). The DMA controller 205 in the host device 202 starts processing such as reading command parameter information in response to inputting the command FIS.

  The SATA controller 211 in the device 207 receives the command FIS transmitted from the SATA controller 206 in the host device 202 (step S202), and outputs the received command FIS to the DMA controller 210 in the device 207 (step S205). . The DMA controller 210 in the device 207 starts processing in response to inputting the instruction FIS.

  Note that the manner in which the SATA controller 206 activates the DMA controller 205 in the process shown in step S203 (or step S205) is not limited to the above-described example (for example, FIS). A mode in which information is input and output may be used.

  In the transfer device 204, processing according to the write command or processing according to the read command is executed according to the contents of the command FIS. In the process according to the write command or the process according to the read command, the SATA controller 206 divides the data into FIS unit sizes and transmits / receives the FIS. In addition, the SATA controller 206 repeatedly executes the process according to the write command or the process according to the read command shown below in accordance with the received command with respect to all FISs constituting the data.

  First, processing when the received command is a write command will be described. The SATA controller 206 in the host device 202 receives the data FIS output in response to the DMA controller 205 in the host device 202 starting processing, and transmits the input data FIS to the SATA controller 211 in the device 207. The SATA controller 211 in the device 207 receives the data FIS transmitted from the SATA controller 206 in the host device 202, and outputs the received data FIS to the DMA controller 210 in the device 207.

  Next, processing when the received command is a read command will be described. When the received instruction is a write instruction, a process is executed in which the processes on the data receiving side and the data transmitting side are switched as compared with the process when the instruction is a read instruction. Therefore, in the following description, the processing in the transfer apparatus 204 according to the present embodiment will be described with reference to an example in which the received instruction is a read instruction. When the received instruction is a write instruction Description of is omitted.

  The DMA controller 210 in the device 207 reads the data FIS related to the I-th target data from the storage area storing the I-th (where 1 ≦ I ≦ N) target data, and uses the read data FIS as the SATA controller in the device 207 It outputs to 211 (step S207). For example, the DMA controller 210 in the device 207 divides the first target data into FIS units, and outputs the divided data FIS to the SATA controller 211 in the device 207.

  Hereinafter, processing in the transfer apparatus according to the present embodiment will be described with reference to an example in which the instruction received by the transfer apparatus 209 is a read command.

  The SATA controller 211 in the device 207 inputs the data FIS output from the DMA controller 210 in the device 207 (step S208), and transmits the input data FIS related to the first target data to the DMA controller 205 in the host device 202 (step S208). S209). The SATA controller 206 in the host device 202 receives the data FIS transmitted from the SATA controller 211 in the device 207 (step S210), and outputs the received data FIS to the DMA controller 205 in the host device 202 (step S211). .

  The DMA controller 205 in the host device 202 inputs the data FIS output from the SATA controller 206 in the host device 202 (step S212), and stores the input data FIS in the memory 103.

  For example, the transfer device 209 in the device 207 and the transfer device 204 in the host device 202 repeat the same processing as the processing shown in steps S207 to S212 for the first target data, thereby transferring the first target data. Are executed (steps S213 to S218).

  In the series of processes shown in steps S207 to S212 or the series of processes shown in steps S213 to S218, after the process of outputting the data FIS (step S211 or step S217), step S219 and The process shown in step S220 is executed. That is, the SATA controller 206 in the host device 202 receives the data FIS by executing the determination process shown in step S123 (FIG. 6) after the process of outputting the data FIS (step S211 or step S217), for example. It is determined whether or not the data FIS includes an error. The SATA controller 206 in the host device 202 creates a response signal according to the determination process, and transmits the created response signal to the SATA controller 211 in the device 207 (step S219). The SATA controller 211 in the device 207 receives the response signal transmitted by the SATA controller 206 in the host device 202 (step S220). In other words, Step S219 and Step S220 are executed after Step S211, and Step S219 and Step S220 are executed after Step S217.

  Next, a flow of transfer processing executed by the transfer device 204 will be described with reference to FIGS. 11 and 12. 11 and 12 are diagrams conceptually illustrating an example of data transmitted and received by the transfer device 204.

  Data transmitted and received in the transfer process is roughly divided into an instruction FIS, a data FIS, and a status FIS. The command FIS, data FIS, and status FIS have a configuration as shown in FIGS. 11 and 12, and the format of the DATA portion (“DATA” in “Data transmission” in FIGS. 11 and 12) is mutual. Is different.

  The state FIS is data relating to a state in the host apparatus 202 (or device 207) after a response signal is transmitted / received, for example.

  The data FIS includes CRC (“CRC” in FIG. 12) data that can at least detect whether the data FIS (or the first target data) regarding the first target data is correct data. CRC represents an abbreviation for Cyclic_Redundancy_Check. The apparatus that receives the data FIS can determine whether the received data FIS includes an error based on the CRC data.

  The “DATA” column capable of storing data includes a “CRC” column capable of storing a value calculated based on the data included in the “DATA” column.

  According to the interface standard related to SATA, the target data is divided every 8 kilobytes (= 16 sectors × 512 bytes), and the divided data is transferred as data FIS. The amount of data to be transferred can be specified by the number of sectors according to the instruction to be executed. According to the interface standard, the maximum number of sectors that can be specified is, for example, 65535 sectors. Therefore, according to the interface standard, when transferring a data amount having the maximum number of sectors that can be specified, the data amount is divided into 4096 (= 65535 ÷ 16) data FIS.

  In the following description, for convenience of explanation, it is assumed that data is divided into 16 sectors. Note that it is not necessarily divided into 16 sectors. That is, one FIS can have a maximum of 8 kilobytes of data. The FIS may be a size of 8 kilobytes or less.

  Next, processing in the computer system 201 according to the second embodiment will be described with reference to FIG. FIG. 13 is a sequence diagram illustrating a processing flow in the computer system 201 according to the second embodiment. For convenience of explanation, it is assumed that the SATA controller 206 in the host device 202 receives a read command for transferring data from the device 207 to the host device 202 from the external device.

  First, the SATA controller 206 in the host device 202 receives a read command transmitted from the external device, and starts processing to receive target data in accordance with the received read command. For example, in this process, the SATA controller 206 in the host device 202 creates a Count field as illustrated in FIG. 4 prior to the received read command, and sends the command “Set_Features” including the created Count field to the device 207. The data is transmitted to the SATA controller 211 (step S231). Further, the SATA controller 206 in the host device 202 transmits the received command (in this example, a read command) to the SATA controller 211 in the device 207. Note that the process for transmitting the status FIS from the device 207 to the host device 202 is also executed for “Set_Features”, but in this embodiment, the description regarding the process of the status FIS is omitted.

  The SATA controller 211 in the device 207 receives the command “Set_Features” and the read command transmitted by the SATA controller 206 in the host device 202 (step S232). The SATA controller 211 in the device 207 reads the number of repetitions (that is, the predetermined number shown in the first embodiment) included in the Count field in the received command “Set_Features”, and further receives the received read command. In response, processing for transmitting the target data is started.

  The SATA controller 211 in the device 207 determines whether or not the received data (that is, the read command) includes an error. When the received command FIS data includes an error, the SATA controller 211 in the device 207 creates an abnormal response signal notifying that the received command FIS includes an error. The data is transmitted to the SATA controller 206 in the host device 202. When the received data does not contain an error, the SATA controller 211 in the device 207 creates a normal response signal notifying that the received data does not contain an error, and the created normal response signal is sent to the host device 202. The data is transmitted to the SATA controller 206 (step S233). For convenience of explanation, FIG. 13 shows a process when no error occurs in the process of transmitting and receiving a read command.

  The SATA controller 206 in the host device 202 receives the response signal transmitted by the SATA controller 211 in the device 207 (step S237). When the received response signal is a normal response signal, the SATA controller 206 in the host device 202 ends the process of transmitting a read command normally. When the received response signal is an abnormal response signal, the SATA controller 206 in the host device 202 abnormally ends the process of transmitting the read command.

  The SATA controller 206 in the host device 202 creates command parameter information related to the instruction according to the read command (step S238), and then executes control to activate the DMA controller 205 in the host device 202 (step S239). For example, the command parameter information regarding the instruction according to the command includes the type of processing, the size of the target data, the position information storing the target data, and the like. The command parameter information relating to the instruction according to the command does not necessarily include all the items described above. The DMA controller 205 in the host device 202 starts up and executes processing based on the command parameter information created by the SATA controller 206 in the host device 202 in response to executing control to be started by the SATA controller 206 in the host device 202. . The DMA controller 205 will be described later with reference to FIGS.

  The SATA controller 211 in the device 207 creates instruction parameter information regarding an instruction according to the instruction (in this example, a read instruction) received in step S232 (step S234), and then activates the DMA controller 210 in the device 207. Control is executed (step S235). For example, the command parameter information regarding the instruction according to the command includes the type of processing, the size of the target data, the position information storing the target data, and the like. The DMA controller 210 in the device 207 is activated in accordance with execution of the control to activate the SATA controller 211 in the device 207, and executes processing based on the command parameter information created by the SATA controller 211 in the device 207. The DMA controller 205 will be described later with reference to FIGS.

  The SATA controller 211 in the device 207 inputs the data FIS output from the DMA controller 210 in the device 207 (step S236), and transmits the data FIS to the SATA controller 206 in the host device 202 (step S240). In this case, the SATA controller 211 in the device 207 transmits data FIS related to the first target data. The data FIS includes data (for example, data calculated according to CRC, hereinafter referred to as “CRC” data) that can detect an error related to the target data.

  The SATA controller 206 in the host device 202 receives the data FIS including the CRC data transmitted by the SATA controller 211 in the device 207 (step S241). The SATA controller 206 in the host device 202 outputs the received data FIS to the DMA controller 205 in the host device 202 (step S242). The DMA controller 205 in the host device 202 inputs the data FIS output from the SATA controller 206 in the host device 202 and stores the input data FIS in the memory 103.

  The SATA controller 206 in the host device 202 is based on the CRC data received together with the data FIS related to the I-th (where 1 ≦ I ≦ N, I is an integer) target data, and the data FIS received regarding the first target data includes an error. Whether or not (step S243).

  When the received data FIS does not include an error (NO in step S243), the SATA controller 206 in the host apparatus 202 normally ends the process of receiving the target data to the DMA controller 205 in the host apparatus 202. Is output (hereinafter referred to as “normal instruction information”) (step S244). After that, the SATA controller 206 in the host device 202 creates a normal response signal indicating that the data FIS related to the first target data has been correctly received, and transmits the created normal response signal to the SATA controller 211 in the device 207 (step). S250).

  When the received data FIS includes an error (YES in step S243), the SATA controller 206 in the host device 202 abnormally ends the process of receiving the target data to the DMA controller 205 in the host device 202. The instruction information (hereinafter, referred to as “abnormal instruction information”) is output (step S245). That is, the SATA controller 206 in the host apparatus 202 outputs information for ending the process of transmitting the data FIS related to the target data to the DMA controller 205 in the host apparatus 202 in the process shown in step S245. Thereafter, the SATA controller 206 in the host device 202 determines whether or not the retransmission process is in a valid state (step S246).

  When the process to be retransmitted is invalid (NO in step S246), the SATA controller 206 in the host device 202 creates an abnormal response signal (step S249), and the created abnormal response signal is sent to the SATA controller in the device 207. 211.

  When the retransmission process is in a valid state (YES in step S246), the SATA controller 206 in the host device 202 causes the command signal output from the DMA controller 205 in the host device 202 (step S276 in FIG. 16 or step S278). , Described later).

  When the input command signal is a continuation command signal (FIG. 16, described later) (YES in step S247), the SATA controller 206 in the host device 202 creates a normal response signal. (Step S248). The SATA controller 206 in the host device 202 transmits the created normal response signal to the SATA controller 211 in the device 207 (step S250). In the case of this example, the continuation command signal is a command signal output from the DMA controller 205 in the host device 202 as shown in step S275 in FIG.

  That is, the SATA controller 206 in the host device 202 sends a normal response signal when the continuation command signal is received even if the target data includes an error by the processing shown in step S247, and the SATA controller in the device 207. 211. The SATA controller 211 in the device 207 which is the side that transmits the target data receives the normal response signal, and executes processing based on the received normal response signal. In this case, the processing on the transmission side based on the normal response signal or the abnormal response signal may be processing in the transfer apparatus in the apparatus disclosed in Patent Document 1.

  When the input command signal is an abnormal command signal (NO in step S247), the SATA controller 206 in the host device 202 creates an abnormal response signal (step S249). The SATA controller 206 in the host device 202 transmits the created abnormal response signal to the SATA controller 211 in the device 207 (step S250). In this example, the abnormal command signal is a command signal output from the DMA controller 205 in the host device 202 as shown in step S278 in FIG. 16, and details will be described later.

  That is, the SATA controller 206 in the host device 202 transmits a normal response signal or an abnormal response signal to the SATA controller 211 in the device 207.

  The SATA controller 211 in the device 207 receives the response signal (that is, the normal response signal or the abnormal response signal) transmitted by the SATA controller 206 in the host device 202 (step S251). When the received response signal is a normal response signal (NO in step S252), the SATA controller 211 in the device 207 transmits a normal instruction signal to the DMA controller 210 in the device 207, and performs normal processing for transmitting and receiving target data. The process ends (step S253). When the received response signal is an abnormal response signal (YES in step S252), the SATA controller 211 in the device 207 transmits an abnormality instruction signal to the DMA controller 210 in the device 207 and abnormally transmits / receives the target data. The process ends (step S254). That is, in step S254 (that is, when an error occurs), the SATA controller 211 in the device 207 sends information for ending the process of receiving element data included in the target data to the DMA controller 210 in the device 207. Output.

  When there are a plurality of target data, the host apparatus 202 and the device 207 repeatedly execute the processes shown in Step S235, Step S236, and Step S239 to Step S254 in FIG.

  After the process of transmitting and receiving all target data, the SATA controller 211 in the device 207 creates a status signal indicating the status in the SATA controller 206, and transmits the created status signal to the SATA controller 206 in the host device 202. The state signal is, for example, a normal state signal indicating a normal state or an abnormal state signal indicating an abnormal state.

  The SATA controller 206 in the host device 202 receives the status signal (that is, the normal status signal or the abnormal status signal) transmitted by the SATA controller 211 in the device 207. The SATA controller 206 in the host device 202 determines whether or not an error is included in the received FIS as in the case of the data FIS, creates a response signal according to the determination result, and creates the response signal in the SATA controller 211 in the device 207. Send the response signal. The SATA controller 206 in the host device 202 transmits a signal indicating whether or not the FIS includes an error.

  The SATA controller 211 in the device 207 receives a response signal (that is, a normal response signal or an abnormal response signal) transmitted by the SATA controller 206 in the host device 202. When the received response signal is a normal response signal, the SATA controller 211 in the device 207 normally ends the process of transmitting and receiving the status signal. When the received response signal is an abnormal response signal, the SATA controller 211 in the device 207 abnormally ends the process of transmitting and receiving the status signal.

  Note that, referring to steps S232 to S236, step S240, and steps S251 to S254 in FIG. 13, these processes are the same as the processes executed by the apparatus according to the interface standard related to SATA. That is, according to the SATA controller according to the present embodiment, the SATA controller (SATA controller 211 in the device 207 in the example described above) that transmits the target data performs the same process as the process executed by the device that conforms to the interface standard related to SATA. Run.

  Next, processing in the DMA controller 205 (or the DMA controller 210) will be described.

  It is assumed that the DMA controller 205 according to the present embodiment has a storage area (memory 103, a register, etc.) capable of storing information relating to the state of processing relating to retransmission processing (hereinafter referred to as “retransmission processing information”) in the own controller. . The retransmission processing information is an effective state indicating a state in which processing for storing data in the memory 103 is executed in the retransmission processing, a preparation state indicating a state in which data is not stored in the memory 103 in the retransmission processing, or the retransmission processing is executed. This is an invalid state representing a state different from the state. Furthermore, it is assumed that the DMA controller 205 according to the present embodiment has a storage area (a memory 103, a register, or the like) that can store DMA transfer information indicating whether or not to perform transfer processing related to DMA. The DMA transfer information is a “valid state” indicating that the process stored in the memory is executed, or a “invalid state” indicating that the process stored in the memory is not executed.

  The instruction parameter information according to the present embodiment may include, for example, the type of processing, the size of the target data, position information storing the target data, and re-execution information indicating whether the processing is a re-execution process. Good. The command parameter information may further include retransmission setting information indicating whether the retransmission processing function is set to a valid state or an invalid state.

  Next, processing in the DMA controller 205 will be described with reference to FIGS. 14 to 17 are flowcharts showing the flow of processing in the DMA controller 205. Similar to the DMA controller in the transfer apparatus according to the SATA interface standard, the DMA controller 210 on the target data transmission side mainly executes only a part of the processes shown in FIGS.

  The DMA controller 205 in the host device 202 is activated in response to the control that the SATA controller 206 in the host device 202 is activated, and then reads the command parameter information created by the SATA controller 206 in the host device 202. Similarly, the DMA controller 210 in the device 207 is activated in accordance with the control that the SATA controller 211 in the device 207 is activated, and then reads the command parameter information created by the SATA controller 211 in the device 207.

  If the type of processing in the instruction parameter information is retransmission processing (YES in step S260), the DMA controller 205 in the host device 202 determines whether the retransmission processing information is in a ready state (step S261). If YES in step S261, the DMA controller 205 in the host device 202 sets a valid state in the retransmission processing information (step S262). In response to this process, the DMA controller 210 in the device 207 does not execute the processes shown in steps S260 to S262.

  The DMA controller 210 in the device 207 reads the target data number from the read instruction parameter information, and stores a storage area for storing a PRD table to be referred to in the transfer process in the memory 103 in the device 207 based on the read target data number. Secure (step S131). The DMA controller 210 in the device 207 stores the start address of the reserved storage area in the PRD table pointer register (step S132), and then reserves a DMA transfer area representing a storage area for temporarily storing data in the transfer process. (Step S133).

  The DMA controller 205 in the host device 202 executes the processes shown in steps S131 to S133 when NO in step S260.

  The DMA controller 210 in the device 207 stores a value (for example, “1”) indicating that processing related to the target data has not been executed yet in the PRD index register (step S134). Similarly, the DMA controller 205 in the host device 202 stores a value (for example, “1”) indicating that the processing related to the target data has not been executed yet in the PRD index register (step S134).

  The DMA controller 205 in the host device 202 reads the value stored in the PRD table pointer register and the value stored in the PRD index register, and adds, for example, the two read values. That is, the DMA controller 205 in the host device 202 calculates an address indicating a storage area in which an address set related to the first target data is stored (step S135). The DMA controller 205 in the host device 202 reads the address set in the PRD table from the storage area indicated by the calculated head address (step S136). By this processing, the DMA controller 205 in the host device 202 specifies the address of the storage area storing the first address of the first target data to be processed in the PRD table. Further, the DMA controller 205 in the host device 202 reads an address indicating a storage area indicating a storage destination of the target data from a storage area indicated by the identified address.

  The DMA controller 205 in the host device 202 reads the start address representing the storage area storing the data to be transferred by the DMA transfer process and the size of the data from the read address set. The DMA controller 205 in the host device 202 stores the read head address in the DMA base address register (step S137), and stores the read size in the DMA byte count register (step S138). That is, by the processing shown in step S135 and step S136, the DMA controller 205 in the host device 202 reads the head address indicating the storage area for storing the first target data to be processed, and the read head address is stored in the DMA base address register. The process etc. which are stored in are executed.

  Similarly, the DMA controller 210 in the device 207 executes processing similar to the processing shown in steps S135 to S138 in the device 207. By this processing, the DMA controller 210 in the device 207 specifies the address of the storage area storing the start address of the target data to be processed in the PRD table. The DMA controller 210 in the device 207 reads the address indicating the storage area storing the target data and the size of the target data from the storage area indicated by the identified address. The DMA controller 210 in the device 207 reads a head address indicating a storage area in which target data to be processed is stored, and executes a process of storing the read head address in the DMA base address register.

  Next, the DMA controller 205 in the host device 202 stores a value (for example, 1) indicating that the process has not yet been performed on the data FIS related to the target data in the Transfer count register in the host device 202 ( Step S263). The DMA controller 210 in the device 207 stores in the Transfer count register in the device 207 a value (for example, 1) indicating that processing has not yet been performed for the FIS relating to the target data. Note that the value stored in the Transfer count register represents, for example, the address where the FIS that is the processing target is stored among the FISs related to the target data. That is, by the processing shown in step S263, the DMA controller 205 in the host apparatus 202 (or device 207) sets a value (for example, 1) indicating that the FIS related to the target data has not been transmitted yet to the Transfer count register. Store.

  The DMA controller 205 in the host device 202 determines whether or not the retransmission processing information is in a ready state (step S264). When the retransmission processing information indicates the ready state (YES in step S264), the DMA controller 205 in the host device 202 sets an invalid state in the DMA transfer information (step S269). If the retransmission processing information is not in the ready state (NO in step S264), the DMA controller 205 in the host device 202 determines whether the retransmission processing information is in a valid state (step S265).

  When the retransmission processing information is invalid (YES in step S265), the DMA controller 205 in the host device 202 stores the value stored in the PRD index register in the FIS index register (step S152). Further, the DMA controller 205 in the host device 202 stores the value (for example, 1) stored in the Transfer count register in the FIS offset register (step S153). Thereafter, the DMA controller 205 in the host device 202 sets the DMA transfer information to be valid (step S270). By the processing shown in steps S152 and S153, the DMA controller 205 can store, for example, the value of the transfer count register at the time when the DMA transfer processing is started and the value stored in the PRD index register. . That is, even if an error occurs in the process of transferring the target data by the process shown in step S153, the Transfer count register stores, for example, an identifier that can identify the data FIS processed in step S154. Yes.

  When the retransmission processing information is valid (YES in step S265), the DMA controller 205 in the host device 202 determines whether the value stored in the PRD index register is larger than the value stored in the FIS index register. Compare

  When the value stored in the PRD index register is larger than the value stored in the FIS index register (YES in step S266), the DMA controller 205 in the host device 202 validates the DMA transfer information. (Step S270). The value stored in the PRD index register represents, for example, a number that can identify target data to be processed. Hereinafter, for convenience of explanation, it is assumed that the value stored in the PRD index register is a number that can identify the target data. The data stored in the FIS index register represents, for example, the number of the target data saved when processing the target data. Therefore, when the value stored in the PRD index register is larger than the value stored in the FIS index register, the target data to be processed by the transfer device 204 according to the present embodiment is still in the memory 103. Represents a state that is not stored (ie, unprocessed).

  When the value stored in the PRD index register is equal to or less than the value stored in the FIS index register (NO in step S266), the DMA controller 205 in the host device 202 determines whether the two values are equal. Is determined (step S267). If the two values are not equal (NO in step S267), the DMA controller 205 in the host device 202 sets an invalid state in the DMA transfer information (step S269). The state of NO in step S267 is a state in which the value stored in the PRD index register is less than the value stored in the FIS index register, that is, target data processed by the transfer device 204 according to the present embodiment. Represents a processed state (NO in step S267). For this reason, the DMA controller 205 in the host device 202 sets an invalid state in the DMA transfer information (step S269).

  When the value stored in the PRD index register is equal to the value stored in the FIS index register (YES in step S267), the DMA controller 205 in the host device 202 uses the data stored in the Transfer count register. Is compared with the data stored in the FIS offset register (step S268).

  If the data stored in the transfer count register is smaller (YES in step S268), the DMA controller 205 in the host device 202 sets an invalid state in the DMA transfer information (step S269). If NO in step S268, the DMA controller 205 in the host device 202 sets a valid state in the DMA transfer information (step S270). That is, the DMA controller 205 in the host device 202 that executes the process of storing data in the memory 103 by the process shown in step S268 stores the target data based on the FIS index register that stores the position where the error has occurred. Specify the storage area.

  The state of YES in step S267 indicates that the two target values are equal, that is, the first target data processed by the DMA controller 205 in the host device 202 is target data that is being re-executed. Further, in the case of YES in step S268, when the data stored in the transfer count register is smaller, that is, regarding the first target data processed by the DMA controller 205 in the host device 202, the first target data is related. It represents that the data FIS is already stored. The state of NO in step S268 indicates that the data FIS related to the first target data is in an unprocessed state (not transferred).

  The DMA controller 210 in the device 207 does not execute the processing shown in FIG. The DMA controller 210 in the device 207 executes step S154 (described later) shown in FIG. 16 after step S263 shown in FIG.

  In the processing shown in step S154, the DMA controller 210 in the device 207 adds the value stored in the DMA base address register and the value stored in the Transfer count register. By this processing, the DMA controller 210 in the device 207 calculates a DMA address that represents the head address of the storage area that stores the data FIS relating to the transfer data.

  The DMA controller 210 in the device 207 reads data of a predetermined size (for example, FIS size) from the memory area of the memory 103 having the calculated DMA address as the head address, and reads the read data in the device 207. Output to the SATA controller 211. In this case, the SATA controller 211 in the device 207 transmits the input data to the SATA controller 206 in the host device 202. That is, the transfer device 204 in the device 207 executes DMA transfer processing for transmitting the first target data to the transfer device 204 in the host device 202 (step S154).

  The DMA controller 210 in the device 207 reads the value stored in the Transfer count register, adds the number of data transferred in the transfer process, and the read value, and stores the calculated value in the Transfer count register. That is, the DMA controller 210 in the device 207 increases the value stored in the Transfer count register by the number of data of the transferred data FIS (step S155).

  The SATA controller 206 in the host apparatus 202 receives the data transmitted by the SATA controller 211 in the device 207 (transmitted in step S154), and outputs the received data to the DMA controller 205 in the host apparatus 202.

  The DMA controller 205 in the host device 202 inputs the data output from the SATA controller 206 in the host device 202. The DMA controller 205 in the host device 202 determines whether the DMA transfer information set in step S269 (FIG. 15) or step S270 (FIG. 15) is valid or invalid (step S271).

  When the DMA transfer information is in a valid state (YES in step S271), the DMA controller 205 in the host device 202 uses the value stored in the DMA base address register and the value stored in the Transfer count register. Add. The DMA controller 205 in the host device 202 stores the input data in a storage area (that is, a part of the memory 103) having the calculated DMA address as the head address in the memory 103. That is, when the DMA transfer information is valid (YES in step S271), the DMA controller 205 in the host device 202 executes a DMA transfer process related to the data FIS (step S154). When the DMA transfer information is invalid (NO in step S271), the DMA controller 205 in the host device 202 does not execute the DMA transfer process related to the first target data.

  In other words, the DMA controller 205 in the host device 202 controls whether or not to store the input data FIS in the memory 103 based on the DMA transfer information by the processes shown in steps S271, S154, and S155. That is, the DMA controller 205 in the host device 202 stores the input data in the memory 103 when the DMA transfer information is valid in the process of retransmitting the target data. The DMA controller 205 in the host device 202 does not store the input data in the memory 103 when the DMA transfer information is invalid in the process of retransmitting the target data.

  The DMA controller 205 in the host device 202 reads the value stored in the Transfer count register, adds the number of data transferred in the transfer process, and the read value, and stores the calculated value in the Transfer count register. By this processing, the DMA controller 210 in the device 207 increases the value stored in the Transfer count register by the number of data of the transferred data FIS, for example (step S155). In other words, the DMA controller 205 in the host device 202 updates the value stored in the Transfer count register even when the DMA transfer information is invalid. Next, the DMA controller 205 in the host device 202 determines whether or not the retransmission setting information is in a valid state (step S157).

  When the retransmission setting information is valid (YES in step S157), the DMA controller 205 in the host device 202 instructs the instruction information output by the SATA controller 206 in the host device 202 (step S244 in FIG. 13 or step S245). ). The DMA controller 205 in the host device 202 determines whether or not the input instruction information is normal instruction information (step S272). When the received instruction information is normal instruction information (YES in step S272) and the DMA transfer information is valid (YES in step S274), the DMA controller 205 in the host device 202 is invalid in the retransmission processing information. A state is set (step S277). If the DMA transfer information is valid (YES in step S274), and if the transfer process for the target data is normal (that is, normal instruction information) (YES in step S272), the data in which the error has occurred Indicates the status of correctly received. In this case, the DMA controller 205 in the host device 202 sets an invalid state in the retransmission processing information (step S277).

  The DMA controller 205 in the host device 202, when the received instruction information is normal instruction information (YES in step S272) and the value stored in the DMA transfer information is invalid (NO in step S274). The process shown in step S277 is not executed. The retransmission processing information is valid (YES in step S157), the DMA transfer information is invalid (that is, the data FIS is not stored in the memory 103), and the transfer processing related to the target data is normal (that is, normal) (Instruction information) (YES in step S272) represents a state in which the memory 103 stores data FIS in which an error has occurred.

When the instruction information output from the SATA controller 206 in the host device 202 is abnormality instruction information (NO in step S272), the DMA controller 205 in the host device 202 determines whether or not a predetermined condition is satisfied (step S273). The predetermined condition is whether or not the following condition 1 and condition 2 are satisfied. That is,
Condition 1: Whether the DMA transfer information is in an invalid state,
Condition 2: Whether the retransmission processing information is valid.

  If the DMA controller 205 in the host apparatus 202 is YES in Condition 1 and YES in Condition 2, the DMA controller 205 in the host apparatus 202 instructs the instruction signal to continue processing (that is, the continuation instruction). Signal). The DMA controller 205 in the host device 202 outputs the created continuation command signal to the SATA controller 206 in the host device 202 (step S275).

  When the conditions 1 and 2 are satisfied (YES in step S273), the case of YES in step S268 (FIG. 15) or the case of NO in step S267 is represented. This case represents a case where the data FIS stored in the memory 103 is not stored in the memory 103 before an error occurs in the process of executing the retransfer process for the target data. That is, in this case, even if an error has occurred with respect to the received data FIS, the DMA controller 205 in the host device 202 does not store the data FIS in the memory 103.

  If the instruction information output from the SATA controller 206 in the host apparatus 202 is abnormality instruction information (NO in step S272) and NO in step S273, the DMA controller 205 in the host apparatus 202 transmits retransmission processing information. The preparation state is set to (Step S276). Thereafter, the DMA controller 205 in the host apparatus 202 creates an instruction signal (that is, an abnormal instruction signal) instructing the abnormal termination of the processing, and transmits the created abnormal instruction signal to the SATA controller 206 in the host apparatus 202 ( Step S278).

  If NO in step S273, the DMA controller 205 in the host device 202 stores, in the memory 103, data FIS in which an error has occurred among the target data. Therefore, the memory 103 stores data FIS in which an error has occurred. In this case, the DMA controller 205 in the host device 202 sets a preparation state in the retransmission processing information (step S276). As a result, since YES is determined in step S264 included in the process of retransferring the data FIS, the transfer device 204 does not store the input information in the memory 103 in step S154. That is, the transfer device 204 does not store the data FIS subsequent to the data FIS in the memory 103 in the transfer process related to the target data. In other words, the transfer device 204 representing the receiving device that receives the target data stores, in the memory 103, the data FIS that follows the data FIS in which the error has occurred in response to an error occurring in the process of receiving the target data. Do not execute processing.

  In contrast to the processing of the SATA controller on the receiving side described above, the DMA controller 210 in the device 207 does not execute the processing shown in steps S157 and S272 to S278 regarding the processing shown in FIG. That is, the DMA controller 210 in the device 207 executes the process shown in step S281 shown in FIG. 17 after executing the process shown in step S155.

  The DMA controller 205 in the host device 202 compares the data stored in the DMA byte count register with the value stored in the Transfer count register. That is, by this processing, the DMA controller 205 in the host device 202 determines whether or not the processing for transferring the data FIS related to the target data has been completed (step S281). When the data stored in the DMA byte count register is different from the value stored in the Transfer count register (that is, when processing related to the target data is not completed), the DMA controller 205 in the host device 202 The process shown in step S264 (FIG. 15) is executed.

  Similarly, the DMA controller 205 in the device 207 executes processing similar to the processing shown in step S281 in the device 207.

When the data stored in the DMA byte count register matches the value stored in the Transfer count register (that is, when the processing related to the target data ends, YES in step S281), the host device The DMA controller 205 in 202 determines whether or not all target data has been transferred (step S159).
For example, the DMA controller 205 in the host device 202 reads the data stored in the PRD index register in the process shown in step S159, and determines whether the most significant bit of the read data is 0 (step S159). ).

  When the most significant bit of the read data is 0 (NO in step S159), the DMA controller 205 in the host device 202, for example, sets the value stored in the PRD index register to the size indicating the next target data Increase by the minute (for example, 1) (step S160). Thereafter, the DMA controller 205 in the host device 202 executes the processing shown in step S135 (FIG. 14). In this case, the DMA controller 205 in the host device 202 follows the processed target data by increasing the value stored in the PRD index register by a size (for example, 1) indicating the next target data. Processing related to the target data can be executed.

  The DMA controller 205 in the host device 202 ends the process when the transfer process for all target data is completed (YES in step S159).

  On the other hand, the DMA controller 205 in the device 207 executes the same processing as the processing shown in FIG.

  Next, effects produced by the transfer device 204 according to the present embodiment will be described.

  According to the transfer device 204 according to the second embodiment, even when an error occurs in the data transfer process, the data can be received in a short time. The reason for this is that even if an error occurs in transmission / reception related to the target data, among the FISs related to the target data, the processing that the transfer device 204 stores in the memory 103 is executed for the FIS that is normally transmitted / received Because it does not.

  According to the transfer apparatus 204 according to the second embodiment, the reason why the data can be received in a short period of time will be described in more detail in comparison with Patent Document 1 and Patent Document 2 in this embodiment. To do.

  According to the interface standard related to SATA, when the process of transferring the target data is abnormally terminated, it is necessary to transfer the target data again in order to transfer the target data correctly. In other words, when an apparatus that conforms to the interface standard detects an output indicating an abnormal end with respect to the data FIS, the instruction processing related to the data FIS is invalidated, and then the instruction processing is re-executed. For example, when the apparatus detects an output indicating abnormal termination after transmitting 4096 data FISs, the apparatus executes a process of transmitting 4096 data FISs. Therefore, according to this apparatus, the transmission time required for the process of transmitting 4096 FISs is wasted.

  On the other hand, when an error occurs due to the transfer of the data FIS, the transfer device 204 according to the present embodiment executes a process of storing the data FIS that causes the error in the memory 103. As a result, according to the transfer apparatus 204 according to the present embodiment, it is possible to reduce the processing time for re-execution of the processing related to the data FIS.

  For example, the reason why the above-described effect is achieved will be described with reference to an example in which the following states 1 to 3 are satisfied. For convenience of explanation, it is assumed that the target data includes N pieces of data FIS.

State 1: In the first processing, an error occurs in the transfer processing related to the E-th (where 1 ≦ E ≦ N) data FIS.
State 2: In the second processing, an error occurs in the transfer processing related to the F-th data FIS and the C-th data FIS (where 1 ≦ F <E <C ≦ N),
State 3: In the third process, an error occurs in the transfer process related to the D-th data FIS (where 1 ≦ D <C).

  As shown in the first embodiment, the devices shown in Patent Literature 1 and Patent Literature 2 transfer the target data again when an error occurs in the transfer processing related to the data FIS included in the target data. Execute the process. For example, in the case of an example satisfying the state 1 to the state 3, the apparatus, for the target data, is caused by the first E data FIS in the state 1 and the second and second F and C data FIS in the state 2. Times and in state 3, one re-transfer process caused by the C-th data FIS is executed. In other words, the apparatus executes a total of five transfer processes, including a transfer process that normally transfers the data after the state 3 with respect to the process of transferring the target data.

  On the other hand, the transfer device 204 according to the present embodiment can transfer the target data only by executing the transfer process three times. The reason for this will be described along the processing in the transfer device 204.

  The SATA controller 206 according to the present embodiment first executes a transfer process related to target data by transmitting a data FIS related to the target data. The DMA controller 205 stores the target data transferred by the SATA controller 206 in the memory 103, for example, in units of FIS. However, since the E-th data FIS is in error due to the state 1, the storage area stores target data including an error related to the E-th data FIS.

  Next, the SATA controller 206 executes a transfer process related to the target data by transmitting the data FIS related to the target data. The DMA controller 205 stores the data after the E-th data FIS in the memory 103 in accordance with the processing shown in FIGS. 15 and 16 among the target data transferred by the SATA controller 206. Therefore, even if the F-th data FIS is an error, the DMA controller 205 does not store the F-th data FIS existing before the E-th data FIS in the memory 103. On the other hand, the DMA controller 205 stores the C-th data FIS after the E-th data FIS in the memory 103. Therefore, the storage area stores target data including an error relating to the C-th data FIS.

  Next, the SATA controller 206 executes a transfer process related to the target data by transmitting the data FIS related to the target data. The DMA controller 205 stores the data after the C-th data FIS in the memory 103 according to the processing shown in FIGS. 15 and 16 among the target data transferred by the SATA controller 206. In the case of the state 3, an error occurs in the D data FIS existing before the C data FIS. The DMA controller 205 does not store the data FIS before the C-th data FIS in the memory 103 even if the SATA controller 206 transmits / receives an FIS including an error. Therefore, the storage area stores target data that does not include an error. As a result, the transfer device 204 can transfer the target data only by executing the transfer process three times.

  In the above description, the DMA controller creates the FIS for convenience of explanation. However, the SATA controller may create the FIS based on the data output from the DMA controller.

<Third Embodiment>
The configuration of the transfer apparatus 301 according to the third embodiment of the present invention and the processing flow in the transfer apparatus 301 will be described in detail with reference to FIGS. 18 and 19. FIG. 18 is a block diagram showing a configuration of the transfer apparatus 301 according to the third embodiment of the present invention. FIG. 19 is a sequence diagram illustrating a processing flow in the transfer apparatus 301 according to the third embodiment.

  A transfer device 301 according to the third embodiment includes a transmission unit 302 and a reception unit 303. The transfer device 301 may further include a memory 304 accessible by the transmission unit 302 and a memory 305 accessible by the reception unit 303.

  Assume that the transmission unit 302 executes transmission processing on the first data stored in the storage area represented by the first identifier in the memory 304. In addition, it is assumed that the reception unit 303 executes reception processing for storing the received first data in the storage area represented by the second identifier in the memory 305. It is assumed that the first identifier is updated to an identifier indicating the next storage area in the memory 304 according to the transmission process when there is no error in the transmission / reception process. Similarly, it is assumed that the second identifier is updated to an identifier indicating the next storage area in the memory 305 in accordance with the reception process when there is no error in the transmission / reception process.

  The transmitting unit 302 stores a first identifier indicating a storage area in which the first data is stored, for example, in a storage device (or memory 304) (step S301). Next, the transmitting unit 302 reads the first data from the storage area represented by the first identifier (step S302), and transmits the read first data to the receiving unit 303 (step S303).

  The receiving unit 303 stores a second identifier indicating a storage area for storing the received first data, for example, in the storage device (or the memory 305) (step S304). Next, the reception unit 303 receives the first data transmitted by the transmission unit 302 (step S305), and stores the received first data in the storage area represented by the second identifier (step S306).

  Next, the receiving unit 303 determines whether or not the received first data includes an error (step S307). For example, the receiving unit 303 determines whether or not the first data includes an error based on CRC data that can detect an error. If the first data includes an error (YES in step S307), receiving section 303 transmits a request signal requesting processing for retransmitting the first data to transmitting section 302 (step S308).

  The transmission unit 302 receives the request signal (step S309), reads the first identifier stored in the storage device in accordance with the received request signal (step S310), and from the storage area represented by the read first identifier, The second data is read (step S311). The transmission unit 302 transmits the read second data to the reception unit 303 (step S312).

  When receiving the request signal, the reception unit 303 reads the second identifier from the storage device (step S313). Next, the reception unit 303 receives the second data transmitted by the transmission unit 302 (step S314), and stores the received second data in the storage area indicated by the read second identifier (step S315).

  The transmission unit 302 and the reception unit 303 can be realized using, for example, the SATA controller and the DMA controller described in the first embodiment.

  Next, effects produced by the transfer apparatus 301 according to the present embodiment will be described.

  According to the transfer device 301 according to the third embodiment, even if an error occurs in the data transfer process, the data can be transferred in a short time. This is because, when an error occurs in the process of transferring the target data, the process of resending the target data is executed without executing a process such as securing a storage area associated with the transfer process. That is, when the target data includes an error, the transfer device 301 executes the transfer process again by reusing the reserved storage area.

  On the other hand, the apparatus disclosed in Patent Document 1 executes a process of transferring from the beginning when an error occurs in the transferred target data. Therefore, when a process for transferring target data is executed, the apparatus executes a process for securing a storage area associated with the transfer process each time the transfer process for the target data is executed. As a result, the amount of processing when performing transfer processing using the apparatus is larger than the amount of processing when performing transfer processing using the transfer apparatus 301 according to the present embodiment.

  In addition, Patent Document 2 describes a process of returning an address pointer to an address pointer in which an error has occurred in accordance with an instruction code in a process of retransmitting when an error occurs, but the specific process is described. It has not been.

  On the other hand, the transfer apparatus 301 according to the third embodiment stores the first identifier and the second identifier in the storage device before the transmission / reception process regarding the first data, and performs the transmission / reception process regarding the second data. Before that, the process of reading the identifier stored in the storage device is executed. Therefore, in the present embodiment, processing relating to an identifier indicating a storage area is specifically described.

  Therefore, according to the transfer device 301 according to the third embodiment, even if an error occurs in the data transfer process, the data can be transferred in a short time.

<Fourth Embodiment>
The configuration of the reception apparatus 404 according to the fourth embodiment of the present invention and the process flow in the reception apparatus 404 will be described in detail with reference to FIGS. FIG. 20 is a block diagram showing the configuration of the receiving apparatus 404 according to the fourth embodiment of the present invention. FIG. 19 is a flowchart showing the flow of processing in the receiving apparatus 404 according to the fourth embodiment.

  A reception device 404 according to the fourth embodiment includes a reception controller 401 and a memory storage unit 402. The receiving device 404 may further include, for example, a memory 403 as a storage area different from the memory storage unit 402.

  For convenience of explanation, it is assumed that the memory 403 can store target data that is a transferred target. It is assumed that the target data includes a plurality of element data.

  The reception controller 401 executes a reception process for receiving a plurality of element data in the target data (step S401). The reception controller 401 outputs the received element data to the memory storage unit 402.

  The memory storage unit 402 receives the element data output from the reception controller 401, and stores the input element data in the memory 403 (step S402). In step S402, the memory storage unit 402 stores the received target data in the memory 403 in the order of the received element data included in the target data.

  The reception controller 401 determines whether an error has occurred in the received element data. When the received element data includes an error, the reception controller 401 stores a position representing a storage area in which the element data including the error is stored (step S403).

  The receiving device 404 executes a re-receiving process for receiving again the target data in which an error has occurred (step S404).

  For convenience of explanation, it is assumed that the receiving device 404 stores each element data included in the re-received target data at the position where the element data is stored in step S402.

  Next, the receiving device 404 reads the position saved in step S403 with respect to the element data in the target data received again, and determines whether the element data is stored after the read position (step S405). When the element data received again is element data to be stored after the read position, the receiving apparatus 404 stores the element data in the memory 403 (step S406). If the element data received again is not element data to be stored after the read position, the receiving device 404 does not store the element data in the memory 403 (step S407).

  The position may be an identification number representing element data in which an error has occurred.

  The reception controller 401 can be realized by using, for example, the SATA controller shown in the second embodiment. The memory storage unit 402 can be realized using a DMA controller. The storage area necessary for the process of transferring the target data is, for example, a storage area that can store the PRD table or a transfer area that can temporarily store the target data. The element data may be data FIS related to the target data, for example.

  Next, effects produced by the receiving apparatus 404 according to the present embodiment will be described.

  According to the receiving device 404 according to the fourth embodiment, even if an error occurs in the process of transferring the target data, the target data can be received in a short time. This is because when an error occurs in the process of receiving the target data, the process of storing the data stored until the error occurs in the memory 403 is not executed again.

  On the other hand, the apparatus disclosed in Patent Document 1 executes a process of transferring from the beginning when an error occurs in the transferred target data. Therefore, when the process for transferring the target data is executed, the apparatus repeatedly executes the process for storing the received data in the memory in the transfer process every time the transfer process for the target data is executed. As a result, the amount of processing when transfer processing is performed using the device is larger than the amount of processing when transfer processing is performed using the receiving device 404 according to the present embodiment.

  Therefore, according to the receiving apparatus 404 according to the fourth embodiment, even if an error occurs in the data transfer process, the data can be received in a short time.

  The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.

In addition, a part or all of each embodiment mentioned above can be described also as the following additional remarks. However, the present invention described by way of example with the above-described embodiments is not limited to the following. That is,
(Appendix 1)
A receiving controller that receives element data included in target data and determines whether the received element data includes an error; and
A memory controller that stores the element data in a memory in the order in which the element data is received and stores the position where the element data including the error is stored when the reception controller determines that the element data includes the error And
When the memory controller re-receives the element data included in the target data, the memory controller follows the element data corresponding to the element data including the error among the re-received target data. A receiving apparatus that sequentially stores data to be stored in a storage area of the memory with reference to the stored position.

(Appendix 2)
The receiving device according to claim 1, wherein the memory controller does not store the element data received by the receiving controller after the element data in the memory when the receiving controller determines that the error is included.

(Appendix 3)
The memory controller stores the element data in the storage position information based on a relative positional relationship between the storage position information indicating the storage area in the memory for storing the element data and the stored position. The receiving device according to attachment 2, wherein it is determined whether or not to store in the area.

(Appendix 4)
The reception controller is a case where the error has occurred with respect to the element data, and further, when the memory controller does not store the element data in the memory, the element data is transmitted to a transmission source that has transmitted the element data. The receiving apparatus according to any one of appendix 1 to appendix 3, wherein a normal state signal indicating that the receiving process has been normally completed is transmitted.

(Appendix 5)
The memory controller is
Transfer information means capable of storing transfer information indicating whether it is a valid state for executing the process of storing the element data in the memory or an invalid state for not executing the process of storing the element data ,
The reception controller, when the received element data includes the error, transmits an abnormal signal indicating that the process of receiving the element data has ended abnormally to the memory controller;
The memory controller sets the transfer information based on the magnitude relationship and determines whether to store the element data based on the set transfer information. Reception according to any one of appendix 1 to appendix 4 apparatus.

(Appendix 6)
The memory controller sets the invalid state in the transfer information when storage position information indicating a storage area for storing the element data in the memory is a value smaller than the position, and the memory controller The receiving apparatus according to any one of appendix 1 to appendix 5, wherein the valid state is set in the transfer information when storage location information indicating a storage area for storing element data is a value greater than or equal to the location.

(Appendix 7)
The receiving device according to any one of supplementary notes 1 to 6,
Reading means for reading the target data in a predetermined unit from the storage area storing the target data;
A transmission controller that transmits the read target data to the reception controller;
A transfer device comprising:

(Appendix 8)
In an apparatus comprising a reception controller that receives element data included in target data and determines whether the received element data includes an error,
The element data is stored in the memory in the order received, and when the element data includes the error, the position where the element data including the error is stored is stored, and is included in the target data. When the received element data is received again, the subsequent data after the element data corresponding to the element data including the error is stored after the saved position among the re-received target data. Reception method.

(Appendix 9)
The reception method according to claim 8, wherein the element data received by the reception controller after the element data including the error is not stored in the memory.

(Appendix 10)
Whether or not to store the element data in the storage area pointed to by the storage position information based on the size relationship between the storage position information indicating the storage area for storing the element data in the memory and the stored position. The receiving method according to appendix 9.

(Appendix 11)
The first identifier indicating the storage area in which the first data to be transmitted is stored is stored in the first storage means, the first data is read from the storage area represented by the first identifier, and the read first A transmission means for transmitting data;
A second identifier indicating a storage area for storing the received first data is stored in a second storage means, the first data transmitted by the transmission controller is received, and the received first data is defined as the second identifier. A request for requesting processing for retransmitting the first data when the first data stored in the storage area represented by the received data includes an error and the first data includes the error. Receiving means for transmitting a signal to the transmitting means, and
In response to the request signal, the transmission means reads the first identifier from the first storage means, reads second data from the storage area indicated by the read first identifier, and reads the read second data. , Send to the receiving means,
The receiving means reads the second identifier from the second storage means when receiving the request signal to the transmitting means, receives the second data, and receives the received second data as the second identifier. A transfer device that stores in the storage area represented by

(Appendix 12)
The receiving unit transmits the request signal to the transmitting unit when the first data includes an error and the number of times the received first data includes an error is equal to or less than a predetermined number. The transfer device described.

101 Computer System 102 Host Device 103 Memory 104 Transfer Device 105 DMA Controller 106 SATA Controller 107 Device 108 Memory 109 Transfer Device 110 DMA Controller 111 SATA Controller 112 SATA Interface 121 DMA Controller 122 PRD Table Pointer Register 123 PRD Index Register 124 DMA Base Address Register 125 DMA byte count register 201 Computer system 202 Host device 204 Transfer device 205 DMA controller 206 SATA controller 207 Device 209 Transfer device 210 DMA controller 211 SATA controller 301 Transfer device 302 Transmitter 303 Receiver 304 Mori 305 memory 401 receives controller 402 memory storage unit 403 memory 404 receiving device

Claims (10)

A receiving controller that receives element data included in target data and determines whether the received element data includes an error; and
A memory controller that stores the element data in a memory in the order in which the element data is received and stores the position where the element data including the error is stored when the reception controller determines that the element data includes the error And
When the memory controller re-receives the element data included in the target data, the memory controller follows the element data corresponding to the element data including the error among the re-received target data. A receiving apparatus that sequentially stores data to be stored in a storage area of the memory with reference to the stored position. The receiving device according to claim 1, wherein the memory controller does not store, in the memory, the element data received by the receiving controller after the element data when the receiving controller determines that the error is included. The memory controller stores the element data in the storage position information based on a relative positional relationship between the storage position information indicating the storage area in the memory for storing the element data and the stored position. The receiving apparatus according to claim 2, wherein it is determined whether or not to store in an area. The reception controller is a case where the error has occurred with respect to the element data, and further, when the memory controller does not store the element data in the memory, the element data is transmitted to a transmission source that has transmitted the element data. The receiving apparatus according to any one of claims 1 to 3, wherein a normal state signal indicating that the receiving process is normally completed is transmitted. The memory controller is
Transfer information means capable of storing transfer information indicating whether it is a valid state for executing the process of storing the element data in the memory or an invalid state for not executing the process of storing the element data ,
The reception controller, when the received element data includes the error, transmits an abnormal signal indicating that the process of receiving the element data has ended abnormally to the memory controller;
The memory controller sets the transfer information based on the magnitude relationship, and determines whether to store the element data based on the set transfer information. Receiver. The memory controller sets the invalid state in the transfer information when storage position information indicating a storage area for storing the element data in the memory is a value smaller than the position, and the memory controller The receiving apparatus according to claim 1, wherein the valid state is set in the transfer information when storage position information indicating a storage area for storing element data is a value equal to or greater than the position. A receiving device according to any one of claims 1 to 6;
Reading means for reading the target data in a predetermined unit from the storage area storing the target data;
A transmission controller that transmits the read target data to the reception controller;
A transfer device comprising: In an apparatus comprising a reception controller that receives element data included in target data and determines whether the received element data includes an error,
The element data is stored in the memory in the order received, and when the element data includes the error, the position where the element data including the error is stored is stored, and is included in the target data. When the received element data is received again, the subsequent data after the element data corresponding to the element data including the error is stored after the saved position among the re-received target data. Reception method. The reception method according to claim 8, wherein the element data received by the reception controller after the element data including the error is not stored in the memory. Whether to store the element data in the storage area indicated by the storage position information based on the relative positional relationship between the storage position information indicating the storage area for storing the element data in the memory and the stored position The receiving method according to claim 9, wherein it is determined whether or not.

Images