JP2017045814A - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
JP2017045814A
JP2017045814A JP2015166304A JP2015166304A JP2017045814A JP 2017045814 A JP2017045814 A JP 2017045814A JP 2015166304 A JP2015166304 A JP 2015166304A JP 2015166304 A JP2015166304 A JP 2015166304A JP 2017045814 A JP2017045814 A JP 2017045814A
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strip
conductor pattern
insulating layer
wiring board
pattern
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JP2015166304A
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Japanese (ja)
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砂田　剛
Takeshi Sunada
砂田　　剛
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Kyocera Corp
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Kyocera Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a wiring board in which a strip conductor pattern of 10-15 μm wide extending to have an end between signal patterns can be prevented effectively from being exfoliated from an insulating layer.SOLUTION: In a wiring board including, on the upper surface of an insulating layer 1, two strip signal patterns 2a, 2b having parts in parallel with each other at a certain interval, and a strip conductor pattern 3a extending between the two signal patterns 2a, 2b, and having an end between the parts in parallel at a certain interval, a recess 1d partially filled with a part of the strip conductor pattern 3a is formed in the insulating layer 1 directly under the strip conductor pattern 3a.SELECTED DRAWING: Figure 1

Description

本発明は、半導体素子を搭載するため等に用いられる配線基板に関するものである。   The present invention relates to a wiring board used for mounting a semiconductor element.

半導体素子を搭載するため等に用いられる従来の配線基板を図３、図４に示す。なお図４は、図３のＢ−Ｂ切断線における要部断面図である。図３、図４に示すように、従来の配線基板は、絶縁層１１の表面に信号パターン１２と接地または電源パターン１３とを有している。   A conventional wiring board used for mounting a semiconductor element or the like is shown in FIGS. FIG. 4 is a cross-sectional view of the main part taken along the line BB of FIG. As shown in FIGS. 3 and 4, the conventional wiring board has a signal pattern 12 and a ground or power supply pattern 13 on the surface of the insulating layer 11.

信号パターン１２は、幅が１０〜１５μｍ程度の細長い帯状である。信号パターン１２は複数本が並行して絶縁層１１上を延在している。信号パターン１２の両端には直径が４０〜８０μｍ程度のランド１４が形成されている。ランド１４は、上層あるいは下層の絶縁層１１を貫通するビア導体（不図示）に接続されている。   The signal pattern 12 has an elongated strip shape with a width of about 10 to 15 μm. A plurality of signal patterns 12 extend in parallel on the insulating layer 11. Lands 14 having a diameter of about 40 to 80 μm are formed at both ends of the signal pattern 12. The land 14 is connected to a via conductor (not shown) that penetrates the upper or lower insulating layer 11.

接地または電源パターン１３は、幅の広い所謂ベタパターンである。接地または電源パターン１３は、信号パターン１２の周囲を１０〜２０μｍ程度の所定の間隔を空けて取り囲んでいる。また、隣接する２本の信号パターン１２の間に、それらの信号パターン１２を接地または電源パターン１３が所定の間隔を空けて１本ずつ取り囲むだけの間隔がない場合、ベタ状パターンからそれらの信号パターン１２の間に端部を有するように延在する幅が１０〜１５μｍ程度の帯状の導体パターン１３ａを設けることがある。   The ground or power supply pattern 13 is a so-called solid pattern having a wide width. The ground or power supply pattern 13 surrounds the signal pattern 12 with a predetermined interval of about 10 to 20 μm. In addition, when there is no interval between the adjacent two signal patterns 12 so that the signal patterns 12 are grounded or the power supply pattern 13 surrounds the signal patterns 12 one by one at a predetermined interval, those signals are output from the solid pattern. A strip-shaped conductor pattern 13 a having a width of about 10 to 15 μm may be provided so as to have an end between the patterns 12.

しかしながら、信号パターン１２の間に端部を有するように延在する幅が１０〜１５μｍ程度の帯状の導体パターン１３ａを設けた場合、図４に示すように、帯状の導体パターン１３ａが絶縁層１１から剥がれてしまうことがあった。   However, when the strip-shaped conductor pattern 13a having a width of about 10 to 15 μm extending so as to have an end portion between the signal patterns 12 is provided, the strip-shaped conductor pattern 13a is formed on the insulating layer 11 as shown in FIG. Sometimes peeled off.

特開平１１−１３５６７６号公報JP-A-11-135676

本発明が解決しようとする課題は、信号パターンの間に端部を有するように延在する幅が１０〜１５μｍ程度の帯状の導体パターンが絶縁層から剥がれてしまうことを有効に防止することが可能な配線基板を提供することにある。   The problem to be solved by the present invention is to effectively prevent the strip-shaped conductor pattern having a width of about 10 to 15 μm extending so as to have an end portion between signal patterns from being peeled off from the insulating layer. It is to provide a possible wiring board.

本発明の配線基板は、絶縁層の上面に、互いに一定の間隔で並行する部分を有する２本の帯状の信号パターンと、該２本の信号パターン間に延在し、前記一定の間隔で並行する部分の間に端部を有する帯状の導体パターンとを具備して成る配線基板であって、前記帯状の導体パターンの直下の前記絶縁層に前記帯状の導体パターンの一部が充填された窪み部が形成されていることを特徴とするものである。   The wiring board of the present invention has two strip-shaped signal patterns having portions parallel to each other at a constant interval on the upper surface of the insulating layer, and extends between the two signal patterns, and is parallel at the predetermined intervals. A wiring board comprising a strip-shaped conductor pattern having an end portion between the portions to be formed, wherein the insulating layer immediately below the strip-shaped conductor pattern is filled with a part of the strip-shaped conductor pattern A portion is formed.

本発明の配線基板によれば、信号パターンの間に延在する帯状の導体パターンの直下の絶縁層に、この帯状の導体パターンの一部が充填された窪み部が形成されていることから、帯状の導体パターンと絶縁層とが窪み部を介して互いに係止される。したがって、帯状の導体パターンが絶縁層から剥離することを有効に防止することができる。   According to the wiring board of the present invention, a recess filled with a part of the strip-shaped conductor pattern is formed in the insulating layer immediately below the strip-shaped conductor pattern extending between the signal patterns. The strip-shaped conductor pattern and the insulating layer are locked to each other through the recess. Therefore, it can prevent effectively that a strip | belt-shaped conductor pattern peels from an insulating layer.

図１は、本発明の配線基板の実施形態の一例を示す要部上面図である。FIG. 1 is a top view of an essential part showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板の要部断面図である。FIG. 2 is a cross-sectional view of a main part of the wiring board shown in FIG. 図３は、従来の配線基板の要部上面図である。FIG. 3 is a top view of an essential part of a conventional wiring board. 図４は、図３に示す配線基板の要部断面図である。4 is a cross-sectional view of the main part of the wiring board shown in FIG.

次に、本発明の配線基板の実施形態の一例を図１および図２を参照して説明する。なお、図２は、図１のＡ−Ａ切断線における要部断面図である。図１、図２に示すように、本例の配線基板は、絶縁層１の表面に信号パターン２と接地または電源パターン３とを有している。絶縁層１は、例えばエポキシ樹脂にシリカ等の無機絶縁物粉末を分散させた厚みが２０〜４０μｍ程度樹脂系の電気絶縁材料から成る。信号パターン２と接地または電源パターン３は、例えばセミアディティブ法により形成された厚みが５〜２０μｍ程度の銅めっき層から成る。   Next, an example of an embodiment of the wiring board of the present invention will be described with reference to FIGS. 2 is a cross-sectional view of the main part taken along the line AA of FIG. As shown in FIGS. 1 and 2, the wiring board of this example has a signal pattern 2 and a ground or power supply pattern 3 on the surface of the insulating layer 1. The insulating layer 1 is made of, for example, a resin-based electrical insulating material having a thickness of about 20 to 40 μm in which an inorganic insulating powder such as silica is dispersed in an epoxy resin. The signal pattern 2 and the ground or power supply pattern 3 are made of, for example, a copper plating layer having a thickness of about 5 to 20 μm formed by a semi-additive method.

信号パターン２は、幅が１０〜１５μｍ程度の細長い帯状である。信号パターン２は複数本が並行して絶縁層１上を延在している。信号パターン２の両端には直径が４０〜８０μｍ程度のランド４が形成されている。ランド４は、上層あるいは下層の絶縁層１を貫通するビア導体（不図示）に接続されている。接地または電源パターン３は、幅の広い所謂ベタパターンである。接地または電源パターン３は、信号パターン２の周囲を１０〜２０μｍの所定の間隔を空けて取り囲んでいる。   The signal pattern 2 has an elongated strip shape with a width of about 10 to 15 μm. A plurality of signal patterns 2 extend on the insulating layer 1 in parallel. Lands 4 having a diameter of about 40 to 80 μm are formed at both ends of the signal pattern 2. The land 4 is connected to a via conductor (not shown) that penetrates the upper or lower insulating layer 1. The ground or power supply pattern 3 is a so-called solid pattern having a wide width. The ground or power supply pattern 3 surrounds the signal pattern 2 with a predetermined interval of 10 to 20 μm.

本例では、隣接する２本の信号パターン２の間に、それらの信号パターン２を接地または電源パターン３が所定の間隔を空けて１本ずつ取り囲むだけの間隔がない信号パターン２ａ、２ｂがある。この２本の信号パターン２ａ、２ｂは、互いに一定の間隔で並行する部分と互いに間隔が拡がる部分とを有している。信号パターン２ａ、２ｂにおいて互いに一定の間隔で並行する部分同士の間隔は、４０〜５０μｍ程度である。接地または電源パターン３は、ベタ状パターンからこの信号パターン２ａ、２ｂの間の互いに一定の間隔で並行する部分に端部を有するように延在する帯状の導体パターン３ａを有している。帯状の導体パターン３ａの幅は１０〜１５μｍ程度である。   In this example, there are signal patterns 2a and 2b between two adjacent signal patterns 2 that are not spaced so that the signal patterns 2 are grounded or the power supply pattern 3 surrounds the signal patterns 2 one by one with a predetermined interval. . The two signal patterns 2a and 2b have a portion parallel to each other at a constant interval and a portion where the interval increases. In the signal patterns 2a and 2b, the interval between portions parallel to each other at a constant interval is about 40 to 50 μm. The ground or power supply pattern 3 has a strip-like conductor pattern 3a extending from the solid pattern so as to have ends at portions parallel to each other between the signal patterns 2a and 2b. The width of the strip-shaped conductor pattern 3a is about 10 to 15 μm.

本例においては、図２に示すように、帯状の導体パターン３ａの直下の絶縁層１に窪み部１ｄが形成されている。この窪み部１ｄ内には、導体パターン３ａの一部が充填されている。窪み部１ｄは、直径が１０〜３０μｍ程度であり、深さが１０〜２０μｍ程度である。窪み部１ｄは、絶縁層１の厚みの途中まで凹んでいる。したがって、絶縁層１の下面に別の導体層５がある場合であっても、導体パターン３ａと導体層５とが電気的に短絡することはない。窪み部１ｄは、例えばレーザ加工により形成されている。   In this example, as shown in FIG. 2, a recess 1d is formed in the insulating layer 1 immediately below the strip-shaped conductor pattern 3a. A part of the conductor pattern 3a is filled in the recess 1d. The indented portion 1d has a diameter of about 10 to 30 μm and a depth of about 10 to 20 μm. The recess 1 d is recessed to the middle of the thickness of the insulating layer 1. Therefore, even if there is another conductor layer 5 on the lower surface of the insulating layer 1, the conductor pattern 3a and the conductor layer 5 are not electrically short-circuited. The recess 1d is formed by, for example, laser processing.

このように、帯状の導体パターン３ａの直下の絶縁層１に、帯状の導体パターン３ａの一部が充填された窪み部１ｄが形成されていることから、帯状の導体パターン３ａと絶縁層１とが窪み部１ｄを介して互いに係止される。したがって、帯状の導体パターン３ａが絶縁層１から剥離することを有効に防止することができる。なお、窪み部１ｄは、剥がれをより有効に防止するために、帯状の導体パターン３ａの少なくとも先端部に形成することが好ましい。   As described above, since the recess 1d filled with a part of the strip-shaped conductor pattern 3a is formed in the insulating layer 1 immediately below the strip-shaped conductor pattern 3a, the strip-shaped conductor pattern 3a, the insulating layer 1, Are locked to each other via the recess 1d. Therefore, it is possible to effectively prevent the strip-shaped conductor pattern 3a from being peeled off from the insulating layer 1. In addition, in order to prevent peeling more effectively, it is preferable to form the hollow part 1d at least at the front-end | tip part of the strip | belt-shaped conductor pattern 3a.

１ 絶縁層
１ａ 窪み部
２ａ、２ｂ 信号パターン
３ａ 帯状の導体パターン DESCRIPTION OF SYMBOLS 1 Insulation layer 1a Indentation part 2a, 2b Signal pattern 3a Strip-shaped conductor pattern

Claims (1)

絶縁層の上面に、互いに一定の間隔で並行する部分を有する２本の帯状の信号パターンと、該２本の信号パターン間に延在し、前記一定の間隔で並行する部分の間に端部を有する帯状の導体パターンとを具備して成る配線基板であって、前記帯状の導体パターンの直下の前記絶縁層に前記帯状の導体パターンの一部が充填された窪み部が形成されていることを特徴とする配線基板。   Two strip-shaped signal patterns having portions parallel to each other at a constant interval on the upper surface of the insulating layer, and an end portion extending between the two signal patterns and between the portions parallel to each other at the constant intervals A wiring board comprising a strip-shaped conductor pattern having a recess portion in which a part of the strip-shaped conductor pattern is filled in the insulating layer immediately below the strip-shaped conductor pattern. A wiring board characterized by.
JP2015166304A 2015-08-26 2015-08-26 Wiring board Pending JP2017045814A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200010375A (en) 2017-07-20 2020-01-30 가부시키가이샤 무라타 세이사쿠쇼 Circuit module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340902A (en) * 1999-05-26 2000-12-08 Matsushita Electric Works Ltd Circuit member
JP2004128169A (en) * 2002-10-01 2004-04-22 Toshiba Corp Wiring board and semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340902A (en) * 1999-05-26 2000-12-08 Matsushita Electric Works Ltd Circuit member
JP2004128169A (en) * 2002-10-01 2004-04-22 Toshiba Corp Wiring board and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200010375A (en) 2017-07-20 2020-01-30 가부시키가이샤 무라타 세이사쿠쇼 Circuit module
US11322429B2 (en) 2017-07-20 2022-05-03 Murata Manufacturing Co., Ltd. Circuit module

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