JP2017038157A - Semiconductor device, and control method of pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain a clock signal of a frequency in a period where the carrier is in normal state, even in the 100% modulation period, even when unintended waveform disturbance of carrier occurs.SOLUTION: In a PLL circuit 120, a return signal is generated by dividing the frequency of an internal clock signal, an up signal UP and a down signal DN, representing the phase difference between a clock signal and return signal are generated, an up signal UPS and a down signal DNS are generated by adding a delay time td to the up signal UP and down signal DN, a charge/discharge current is generated according to the up signal UPS and down signal DNS, and converted into a control voltage smoothed according to the charge/discharge current, an internal clock signal of a frequency corresponding to the control voltage is oscillated, amplitude of the carrier is monitored and a detection signal is generated when the amplitude goes below a predetermined threshold. When the detection signal is generated, the operation for generating a charge/discharge current corresponding to the up signal UPS and down signal DNS is stopped.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a technique suitable for generating a clock signal in proximity communication using electromagnetic induction.

In proximity communication (NFC (Near Field Communication)) using electromagnetic induction, for example, near-field wireless communication is performed between a reader / writer (RW) and a tag (or card) using a frequency of 13.56 MHz, for example. ing.
The reader / writer (RW) modulates the carrier wave based on the data received from the host device and transmits the modulated carrier wave to the tag. In order to return a response to the data received from the reader / writer (RW), the tag extracts a clock signal from the carrier wave received from the reader / writer (RW), and controls to synchronize the internal clock signal with this clock signal. There is a need to do.
Therefore, the tag includes a PLL circuit having a phase comparison circuit or a phase frequency comparator inside.
The PLL circuit compares the phase difference between the clock signal extracted from the carrier wave and the internal clock signal from the PLL circuit, and smoothes the charge / discharge amount generated according to the phase difference to generate the control voltage. Further, the PLL circuit has a configuration in which the control voltage is input to the voltage controlled oscillation circuit to control to generate an internal clock signal synchronized with the clock signal extracted from the carrier wave.

However, amplitude shift modulation ASK (Amplitude Shift Keying) has a communication standard for modulating data by performing 100% modulation on a carrier wave. In this case, in the 100% modulation period, the carrier wave transmitted by the reader / writer (RW) is transmitted. The amplitude is ideally 0V. For this reason, the tag side loses the clock signal serving as a signal source synchronized with the 100% modulation period, and data processing inside the tag cannot be continued.
Therefore, as a conventional technique, when the 100% modulation period is detected, the voltage controlled oscillation circuit stops the charge / discharge operation to the voltage controlled oscillation circuit, so that the voltage controlled oscillation circuit has the frequency of the internal clock signal immediately before the transition to the 100% modulation period. It is already known that
In Patent Document 1, for the purpose of maintaining the frequency, when the NFC card side detects the 100% modulation period, the charging / discharging operation to the voltage controlled oscillation circuit provided in the PLL circuit is stopped, so that the 100% modulation period is reached. A configuration for maintaining the clock frequency immediately before transition is disclosed.

However, in the process of actually shifting the carrier wave amplitude from the normal state to the 100% modulation period, the carrier wave amplitude is changed from the normal state to the attenuated amplitude state, and further, the amplitude becomes zero, and the modulation is 100%. Transition to a period.
Here, in the process of shifting the amplitude of the carrier wave from the normal state to the attenuated amplitude state, an unintentional waveform disturbance may occur in the carrier wave, and the phase of the clock signal extracted from the carrier wave is different from the original phase. There may be differences.
In the conventional PLL circuit, the phase difference between the clock signal that is different from the original phase and the internal clock signal are compared, and the charge / discharge amount generated according to this phase difference is smoothed before voltage controlled oscillation Input to the circuit. Thereafter, the 100% modulation period of the carrier wave is detected and the charge / discharge operation is stopped.
That is, there is a problem that the clock frequency of the 100% modulation period is maintained in a clock frequency state different from the original clock frequency.

Patent Document 1 describes that the clock frequency is maintained by stopping the charge / discharge operation when a 100% modulation period of the carrier wave is detected.
However, Patent Document 1 does not describe the case where the waveform disturbance occurs immediately before the shift to the 100% modulation period of the carrier wave as described above. For this reason, in Patent Document 1, when waveform disturbance occurs in the carrier wave in the process of shifting from a period in which the carrier wave is in a normal state to the 100% modulation period, the difference in the process of shifting to the 100% modulation period. The problem of the maintained clock frequency state being maintained during the 100% modulation period cannot be solved.
The present invention has been made in view of the above. For the purpose of the present invention, even when an unintended carrier waveform disturbance occurs in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, The purpose is to maintain the clock signal of the frequency in the period in the normal state even in the 100% modulation period.

  In order to solve the above-mentioned problem, the invention according to claim 1 demodulates the received signal by inputting the amplitude-modulated carrier wave from the antenna, and receives the clock signal from the receiving circuit that extracts the clock signal from the carrier wave. A PLL circuit that controls to synchronize with the internal clock signal, and the PLL circuit divides the internal clock signal to generate a feedback signal, and the clock signal and the feedback signal. A phase comparison circuit for generating a first up signal and a first down signal representing a phase difference between the second up signal and a second up signal and a second down signal obtained by adding a delay time to the first up signal and the first down signal. A delay circuit for generating a charge, a charge pump circuit for generating a charge / discharge current according to the second up signal and the second down signal, and a smoothing according to the charge / discharge current A loop filter circuit for converting to a control voltage, a voltage control oscillation circuit for oscillating the internal clock signal having a frequency corresponding to the control voltage, and monitoring the amplitude of the carrier wave to reduce the amplitude to a predetermined threshold value or less. An amplitude monitoring circuit that generates a detection signal when the detection signal is generated, and the charge pump circuit generates a charge / discharge current according to the second up signal and the second down signal when the detection signal is generated The operation to stop is stopped.

  According to the present invention, in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, even if an unintended carrier wave waveform disturbance occurs, a clock signal having a frequency in the period in which the carrier wave is in a normal state is obtained. It can be maintained even during the 100% modulation period.

It is a block diagram which shows an example of the outline | summary of the near field communication system (NFC system) which concerns on the background art of this invention. It is a block diagram which shows an example of a general PLL circuit. It is a circuit diagram which shows an example of a charge pump circuit and a loop filter circuit. It is a timing chart which shows an example of a mode that the feedback signal produced | generated inside a PLL circuit is synchronized with a reference clock signal. It is a timing chart which shows the carrier wave waveform of an ASK100% modulation system. It is a timing chart showing an example of the operation of the PLL circuit when only the amplitude is attenuated while the carrier wave is in the form of an ideal sine wave by ASK 100% modulation. 10 is a timing chart showing an example of the operation of the PLL circuit when the carrier wave waveform is disturbed with respect to an ideal sine wave when the carrier wave amplitude is attenuated by ASK 100% modulation. 1 is a block diagram illustrating an example of a PLL circuit according to a first embodiment of the present invention. FIG. 9 is a circuit diagram illustrating an example of a delay circuit and a charge pump circuit illustrated in FIG. 8. 9 is a timing chart illustrating an example of the operation of the PLL circuit illustrated in FIG. 8. It is a block diagram which shows an example of the delay circuit which concerns on 2nd Embodiment of this invention. It is a block diagram which shows an example of the delay circuit which concerns on 3rd Embodiment of this invention. It is a block diagram which shows an example of the PLL circuit which concerns on 4th Embodiment of this invention. 14 is a timing chart showing an example of the operation of the PLL circuit shown in FIG. It is a block diagram which shows an example of the phase monitoring circuit which concerns on 5th Embodiment of this invention. 16 is a timing chart showing an example of the operation of the phase monitoring circuit shown in FIG. It is a block diagram which shows an example of the phase monitoring circuit which concerns on 6th Embodiment of this invention. 18 is a timing chart showing an example of the operation of the phase monitoring circuit shown in FIG.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
According to the present invention, in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, even if an unintended carrier wave waveform disturbance occurs, a clock signal having a frequency in the period in which the carrier wave is in a normal state is set to 100% In order to maintain the modulation period, the following configuration is provided.
In other words, the semiconductor device of the present invention inputs an amplitude-modulated carrier wave from an antenna to demodulate the received signal, and receives a clock signal from the carrier wave, and receives the clock signal to synchronize with the internal clock signal. A PLL circuit that performs control, wherein the PLL circuit divides the internal clock signal to generate a feedback signal, a first up signal that represents a phase difference between the clock signal and the feedback signal, and A phase comparison circuit for generating a first down signal, a delay circuit for generating a second up signal and a second down signal obtained by adding a delay time to the first up signal and the first down signal, a second up signal and a second A charge pump circuit that generates a charge / discharge current according to a down signal, a loop filter circuit that converts the control voltage to a smoothed control voltage according to the charge / discharge current, and a control voltage A charge pump circuit comprising: a voltage-controlled oscillation circuit that oscillates an internal clock signal having the same frequency; and an amplitude monitoring circuit that monitors the amplitude of the carrier wave and generates a detection signal when the amplitude decreases below a predetermined threshold value. Is characterized in that when the detection signal is generated, the operation of generating the charge / discharge current according to the second up signal and the second down signal is stopped.
With the above configuration, even when an unintended carrier wave waveform disturbance occurs in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, a frequency clock in the period in which the carrier wave is in a normal state The signal can be maintained even during the 100% modulation period.
Hereinafter, the features of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
A proximity communication system according to a first embodiment of the present invention will be described.
FIG. 1 is a block diagram showing an example of an overview of a near field communication system (NFC system) according to the background art of the present invention.
The NFC system includes a card 1 (CARD), a reader / writer 2 (RW), and a host device 3 (HST).
The reader / writer 2 (RW) is connected to the host device 3 (HST).
The host device 3 transmits a request (REQ) signal to the reader / writer 2 and receives a response (RSP) signal corresponding to the request (REQ) signal from the reader / writer 2.
The reader / writer 2 (RW) includes an antenna 21 and a controller 20 (CONT). Based on the request (REQ) signal received from the host device 3, the reader / writer 2 (RW) reads / writes data stored in the card 1 (CARD) by wireless communication and acquires it from the card 1 (CARD). The transmitted data is transmitted to the host device 3.

The card 1 (CARD) includes an antenna 10 and a chip 15 (CHIP).
The antenna 10 is configured by a loop-shaped coil, and radiates electromagnetic waves when the high-frequency current flowing through the coil changes. Further, when the magnetic flux passing through the coil as the antenna 10 changes, a high-frequency current flows through the antenna 10 and is supplied to the receiving circuit 11 (RX).
A chip 15 (CHIP) provided in the card 1 (CARD) is an example of a semiconductor device according to the present invention, and includes a receiving circuit 11 (RX), a PLL circuit 12 (PLL), and a transmitting circuit 13 (TX). It is equipped with. This semiconductor device is formed on one semiconductor substrate such as single crystal silicon by using a complementary MOS integrated circuit manufacturing technique or the like.
The reception circuit 11 (RX) receives the amplitude-modulated carrier wave from the loop antenna 10, receives the current flowing through the antenna 10, demodulates the received signal, supplies the received signal to the logic circuit 14 (LGC), and receives the current. A clock signal is extracted from the carrier wave. The extracted clock signal is referred to as a reference clock signal CLKREF.
The logic circuit 14 (LGC) processes the demodulated signal RXD supplied from the receiving circuit 11, encodes data to be transmitted to a device such as a reader / writer, and generates a modulation control signal TXD.

The transmission circuit 13 (TX) changes the impedance when the antenna 10 is viewed from the outside according to the modulation control signal TXD from the logic circuit 14 (LGC). When a magnetic field of high frequency is formed around the antenna 10 by outputting an electromagnetic wave as a carrier wave of the reader / writer 2 (RW), the impedance of the coil as the antenna 10 changes to change the magnetic field around the antenna 10. Changes. Thus, the carrier wave as the electromagnetic wave output from the reader / writer 2 (RW) is modulated according to the modulation control signal TXD, and the transmission data generated by the logic circuit 14 (LGC) is output from the reader / writer that outputs the electromagnetic wave. 2 (RW).
The PLL circuit 12 receives the reference clock signal CLKREF from the receiving circuit 11, generates an internal clock signal CLKPLL, and outputs the internal clock signal CLKPLL to the logic circuit 14 and the transmission circuit 13. At this time, the PLL circuit 12 performs control to synchronize the internal clock signal CLKPLL with the reference clock signal CLKREF, and outputs the internal clock signal CLKPLL to the logic circuit 14 and the transmission circuit 13.

FIG. 2 is a block diagram illustrating an example of a general PLL circuit 12.
The PLL circuit 12 includes a phase comparison circuit 100 (PD), a charge pump circuit 101 (CP) that charges and discharges a phase difference, a loop filter circuit 102 (LF), a voltage controlled oscillation circuit 103 (VCO), and a frequency divider. Circuit 104 (DIV).
The phase comparison circuit 100 (PD) receives the clock signal CLKREF extracted by the reception circuit 11 (RX) and the feedback signal CLKFB generated from the frequency dividing circuit 104 (DIV).
The phase comparison circuit 100 (PD) compares the rising or falling of the signal CLKFBS obtained by arbitrarily delaying the feedback signal CLKFB with respect to the clock signal CLKREF. Then, the phase comparison circuit 100 (PD) outputs an up signal (UP) (first up signal) and a down signal (DN) (first down signal) indicating the phase difference between the clock signal CLKREF and the feedback signal CLKFB. Generate.

The charge pump circuit 101 (CP) supplies the charge / discharge current CPTT corresponding to the up signal (UP) and the down signal (DN) to the loop filter circuit 102 (LF) and flows it.
The loop filter circuit 102 (LF) smoothes the voltage supplied from the charge pump circuit 101 (CP), and outputs the smoothed voltage to the voltage controlled oscillation circuit 103 (VCO) as the control voltage VCNT.
The voltage controlled oscillation circuit 103 (VCO) oscillates and outputs a clock signal having a frequency corresponding to the input control voltage VCNT.
The frequency dividing circuit 104 (DIV) divides the internal clock signal CLKPLL generated from the voltage controlled oscillation circuit 103 (VCO) by 1 / N to generate a feedback signal CLKFB. Note that the frequency dividing ratio of the frequency dividing circuit 104 (DIV) is 1 / N (N is a positive integer).

FIG. 3 is a circuit diagram showing an example of the charge pump circuit 101 (CP) and the loop filter circuit 102 (LF).
The charge pump circuit 101 (CP) is configured by a push-pull circuit having switches SW _UP and SW _DN , and generates a charge / discharge current CPTT corresponding to an up signal (UP) and a down signal (DN) to generate a loop filter circuit 102. (LF).
That is, the charge pump circuit 101 (CP) sets the switch SW _UP in a closed state in response to the up signal (UP), and is provided in the loop filter 102 (LF) through the output point P with a constant current from the power source. The capacitors C1 and C2 are charged. In addition, the charge pump circuit 101 sets the switch SW _DN to a closed state in response to the down signal (DN), and is determined from the capacitors C1 and C2 provided in the loop filter circuit 102 (LF) via the output point P. The current is discharged to GND.

The loop filter circuit 102 (LF) includes a resistor R1 and capacitors C1 and C2. The loop filter circuit 102 (LF) causes the charge / discharge current CPTT generated by the charge pump circuit 101 (CP) to flow to the capacitor C1 via the resistor R1, and at the same time flows to the capacitor C2 according to the charge / discharge current CPTT. Convert to smoothed voltage. The loop filter circuit 102 (LF) outputs the voltage smoothed by the resistor R1 and the capacitors C1 and C2 to the voltage controlled oscillation circuit 103 (VCO) as the control voltage VCNT.
The voltage controlled oscillation circuit 103 (VCO) generates an internal clock signal CLKPLL by oscillating a clock signal having a frequency corresponding to the potential of the control voltage VCNT input from the loop filter circuit 102 (LF). That is, in the voltage controlled oscillation circuit 103 (VCO), when the potential of the control voltage VCNT increases, the frequency of the internal clock signal CLKPLL increases, and when the potential of the control voltage VCNT decreases, the frequency of the internal clock signal CLKPLL decreases.

FIG. 4 is a timing chart showing an example of a state in which the feedback signal CLKFB generated inside the PLL circuit 12 is synchronized with the reference clock signal CLKREF.
The phase comparison circuit 100 (PD) includes a falling edge of the reference clock signal CLKREF extracted from the carrier wave CRR by the receiving circuit 11 (RX), a falling edge of the feedback signal CLKFB, and a feedback signal CLKFBS delayed in phase from the feedback signal CLKFB. Compare with falling.
As shown at time t15, when the fall of the reference clock signal CLKREF is earlier than the fall of the feedback signal CLKFB, the up signal UP is generated longer than the down signal DN.
When the up signal UP input from the phase comparison circuit 100 (PD) to the charge pump circuit 101 (CP) is longer than the down signal DN, the control voltage VCNT of the voltage controlled oscillation circuit 103 (VCO) becomes high, and the internal clock The frequency of the signal CLKPLL increases.

On the other hand, as shown at time t13, when the falling edge of the reference clock signal CLKREF is later than the falling edge of the feedback signal CLKFB, the down signal DN is generated longer than the up signal UP.
When the down signal DN output from the phase comparison circuit 100 (PD) to the charge pump 101 (CP) becomes longer than the up signal UP, the control voltage VCNT of the voltage controlled oscillation circuit 103 (VCO) becomes low, and the internal clock signal The frequency of CLKPLL is lowered.
The PLL circuit 12 synchronizes the reference clock signal CLKREF and the internal clock signal CLKPLL by such feedback control.

FIG. 5 is a timing chart showing a carrier waveform of the ASK 100% modulation method.
In the ASK 100% modulation method, the carrier wave CRR has disappeared during the 100% modulation period, which is the period from time t21 to t22 shown in FIG. 5, and the reference clock signal CLKREF cannot be extracted during that period.

FIG. 6 is a timing chart illustrating an example of the operation of the PLL circuit 12 when only the amplitude of the carrier wave CRR is attenuated in the form of an ideal sine wave by ASK 100% modulation.
When shifting to the ASK 100% modulation period, when the carrier wave CRR is attenuated only in amplitude in the form of an ideal sine wave, in a state where the receiving circuit 11 (RX) is equal to or larger than the amplitude at which the clock signal can be extracted, Extracted with the same clock width as in the case of no modulation. The receiving circuit 11 (RX) generates a reference clock signal CLKREF.
For this reason, the up signal UP and the down signal DN, which are phase difference signals output from the phase comparison circuit 100 (PD) to the charge pump 101 (CP), have the same signal width as that in the case of no modulation. Therefore, during the 100% modulation period (from t37), the voltage-controlled oscillation circuit 103 (VCO) maintains the frequency immediately before the 100% modulation period.

FIG. 7 shows an example of the operation of the PLL circuit 12 when the waveform of the carrier CRR is disturbed with respect to the ideal sine wave (FIG. 6) when the amplitude of the carrier CRR is attenuated by ASK 100% modulation. It is a timing chart which shows.
At the time before entering the ASK 100% modulation period (from t47), the actual carrier CRR does not attenuate only in the form of an ideal sine wave, and the waveform is distorted as shown at times t43 to t47. There is a case.
The reference clock signal CLKREF is basically binarized and extracted with reference to 1/2 of the amplitude level of the carrier wave CRR. For this reason, in a state in which the waveform of the carrier wave CRR is disturbed, the reference clock signal CLKREF may rise or fall faster or slower than when there is no modulation.

In the example shown in FIG. 7, the case where the fall of the carrier wave CRR is delayed due to the disturbance of the waveform of the carrier wave CRR is shown.
In the phase comparison circuit 100 (PD), in order to compare the fall of the reference clock signal CLKREF and the feedback signal CLKFB, as shown at time t45 and time t47, the up signal UP is not modulated (for example, time t41 and t43). ).
Immediately before time t45 or time t47, an up signal UP that is shorter than that at the time of no modulation and a down signal DN that has substantially the same width as that at the time of no modulation are output from the phase comparison circuit 100 (PD) to the charge pump circuit 101 (CP). ) Is output. For this reason, in the charge pump circuit 101 (CP), the signal width of the down signal DN is relatively longer than that of the up signal UP.

As a result, immediately before time t45 or time t47, the control voltage VCNT of the voltage controlled oscillation circuit 103 (VCO) is lower than, for example, the voltage at time t41 or time t43.
Thereafter, after time t48, the amplitude of the carrier wave CRR is attenuated and becomes smaller, the receiving circuit 11 (RX) cannot extract the reference clock signal CLKREF, and the reference clock signal CLKREF disappears (after time t48). For this reason, the up signal UP and the down signal DN output from the phase comparison circuit 100 (PD) also disappear, and the charge pump 101 (CP) is not charged or discharged.
As a result, after time t48, the frequency of the internal clock signal CLKPLL generated from the PLL circuit 12 is maintained at a frequency lower than the frequency at time t43. That is, the internal clock signal CLKPLL generated from the PLL circuit 12 is not synchronized with the reference clock signal CLKREF.
For this reason, data processing inside the tag cannot be continued.
Therefore, in the present embodiment, even when an unintended carrier wave waveform disturbance occurs in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, a clock signal having a frequency in the period in which the carrier wave is in a normal state. A configuration for maintaining the signal even in the 100% modulation period will be described.

FIG. 8 is a block diagram showing an example of the PLL circuit 120 according to the first embodiment of the present invention.
In the first embodiment, the card 1 (CARD) 1 includes a PLL circuit 120 shown in FIG. 8 in place of the PLL circuit 12 shown in FIGS.
The PLL circuit 120 shown in FIG. 8 includes a phase comparison circuit 100 (PD), a delay circuit 106 (DLY), a charge pump circuit 101 (CP), a loop filter circuit 102 (LF), and a voltage controlled oscillation circuit 103 (VCO). ), A frequency dividing circuit 104 (DIV), and an amplitude monitoring circuit 105 (VDET). In addition, since the code | symbol shown in FIG. 8 and the code | symbol shown in FIG. 2 is the same structure, the description is abbreviate | omitted.
In the first embodiment, the delay circuit 106 (DLY) is provided between the phase comparison circuit 100 (PD) and the charge pump circuit 101 (CP), and the amplitude monitoring circuit 105 (detects a decrease in the amplitude of the carrier wave CRR). VDET).

The amplitude monitoring circuit 105 (VDET) targets an amplitude attenuation period in which waveform disturbance may occur in the carrier wave in the process of shifting the carrier wave to the 100% modulation period.
Here, the amplitude decay period is a process in which the amplitude of the carrier wave shifts from the normal state to the 100% modulation period, and then the carrier wave amplitude shifts from the normal state to the attenuated amplitude state, and the amplitude becomes zero. The period during which the amplitude of the carrier wave attenuates until the 100% modulation period starts.
The amplitude monitoring circuit 105 (VDET) sends a low-level detection signal CPEN to the charge pump circuit 101 (CP) when the amplitude of the carrier wave CRR falls below a threshold voltage VDETCP (FIG. 9), which is an arbitrarily set threshold. Output.
The phase comparison circuit 100 (PD) compares the falling edge of the reference clock signal CLKREF with the falling edge of the feedback signal CLKFB, and outputs the extracted up signal UP and down signal DN as the first signal to the delay circuit 106 (DLY). ).
The delay circuit 106 (DLY) is a charge pump circuit for an up second signal UPS (second up signal) and a down second signal DNS (second down signal) obtained by adding a delay time td to the input up signal UP and down signal DN. 101 (CP).

The charge pump circuit 101 (CP) is configured by a push-pull circuit, generates a charge / discharge current CPTT corresponding to the up second signal UPS and the down second signal DNS, and supplies the charge / discharge current CPTT to the loop filter circuit 102 (LF).
Further, when the charge pump circuit 101 (CP) receives the detection signal CPEN from the amplitude monitoring circuit 105 (VDET), the charge pump circuit 101 (CP) changes the charge / discharge current according to the up-second signal UPS and the down-second signal DNS according to the phase difference. Stop the conversion operation. As a result, in the charge pump circuit 101 (CP), the switches SW _UP and SW _DN are in an open state during the amplitude decay period (the amplitude of the carrier wave CRR is equal to or less than the threshold) when the detection signal CPEN is at a low level, that is, the output point P There is no charge / discharge current.
Accordingly, the loop filter circuit 102 (LF) maintains the control voltage VCNT during the amplitude normal period (the amplitude of the carrier wave CRR is equal to or greater than the threshold) during which the detection signal CPEN is at the high level during the amplitude decay period. As a result, the voltage controlled oscillation circuit 103 (VCO) oscillates and outputs a clock signal having a frequency corresponding to the input control voltage VCNT, so that the clock signal having the frequency during the normal amplitude period can be maintained. it can.
Here, the normal amplitude period refers to a period in which the state of the amplitude of the carrier wave is not less than a predetermined reference value.

FIG. 9 is a circuit diagram showing an example of the delay circuit 106 (DLY) and the charge pump circuit 101 (CP) shown in FIG.
The up second signal UPS and the down second signal DNS generated from the delay circuit 106 (DLY) are output to the charge pump circuit 101 (CP).
The charge pump circuit 101 (CP) includes switches SW ₁ and SW ₂ configured by analog switches, for example, in addition to the configuration shown in FIG.
The switch SW ₁ has one contact connected to a terminal that outputs the up-second signal UPS of the delay circuit 106 (DLY), and the other contact connected to a control terminal of the switch SW _UP .
Switch SW ₂ is one contact is connected to a terminal for outputting a down-second signal DNS delay circuit 106 (DLY), the other contact is connected to the control terminal of the switch _{SW DN.}
The control terminals of the switches SW ₁ and SW ₂ are connected in common and are connected to a terminal that outputs the detection signal CPEN of the amplitude monitoring circuit 105 (VDET).

When the amplitude monitoring circuit 105 (VDET) does not output the detection signal CPEN (high level), the switch SW ₁ is in the closed state, and therefore the up-second signal UPS that has passed through the switch SW ₁ is the switch SW _UP. Input to the control terminal.
Similarly, if the amplitude monitoring circuit 105 (VDET) does not output a detection signal CPEN (high level), the switch SW ₂ is in閉結state, down second signal DNS that has passed through the switch SW ₂ is Input to the control terminal of the switch SW _DN .
On the other hand, when the detection signal CPEN (low level) from the amplitude monitoring circuit 105 (VDET) is received, the switches SW ₁ and SW ₂ are switched to the open state, so that the switches SW _UP and SW _DN are switched to the open state.
As a result, in the charge pump circuit 101 (CP), the switches SW ₁ , SW _2, SW _UP , and SW _DN are opened during the amplitude decay period (the amplitude of the carrier wave CRR is equal to or less than the threshold) when the detection signal CPEN is at a low level. State, and there is no charge / discharge current to the output point P.

FIG. 10 is a timing chart showing an example of the operation of the PLL circuit 120 shown in FIG.
The delay circuit 106 (DLY) receives the up signal UP and the down signal DN, and outputs the up second signal UPS and the down second signal DNS obtained by adding a delay time td to the signals to the charge pump circuit 101 (CP). To do.
At time t55, when the pulse widths of the up signal UP and the down signal DN are different from the original phase, the up second signal UPS and the down second signal DNS, which are the delayed signals, are changed to the charge pump circuit 101 (CP). At time t56 to t57.
On the other hand, the amplitude monitoring circuit 105 (VDET) detects that the amplitude of the carrier wave CRR has become the threshold voltage VDETCP or less at time t541 and outputs a detection signal CPEN (low level) to the charge pump circuit 101 (CP).
That is, at time t541 before the up second signal UPS and the down second signal DNS are input to the charge pump circuit 101 (CP) from time t56 to t57, the detection signal CPEN (low level) is supplied to the charge pump circuit 101 (CP). Entered.

As a result, in the charge pump circuit 101 (CP), the switches SW ₁ , SW ₂ , SW _UP , and SW _DN are opened according to the detection signal CPEN (low level) received at time t 541 during the amplitude decay period, and the output There is no charge / discharge current to the point P, and the charge / discharge operation stops.
In the present embodiment, at the time (t53 to t57) before the transition to the 100% modulation period (t57 to), the pulse widths of the up signal UP and the down signal DN are inherent due to the waveform disturbance of the carrier wave CRR. Assume a case where the phase is different and different.
When the detection signal CPEN (time t541) is switched from the high level to the low level, the charge / discharge operation of the charge pump circuit 101 (CP) is stopped.

According to the present embodiment, as shown in FIG. 10, in the normal amplitude period (t50 to t541), the up second signal UPS and the down second signal DNS when the detection signal CPEN (time t541) is in the high level state are Input from the delay circuit 106 (DLY) to the charge pump circuit 101 (CP).
In the charge pump circuit 101 (CP), the switches SW ₁ , SW ₂ , SW _UP , and SW _DN are opened according to the detection signal CPEN (low level) received at time t 541 during the amplitude decay period, and the output point P is reached. Thus, there is no charge / discharge current, and the charge / discharge operation stops.
Therefore, the loop filter circuit 102 (LF) maintains the control voltage VCNT during the amplitude normal period (the amplitude of the carrier wave CRR is equal to or greater than the threshold value) during which the detection signal CPEN is at the high level during the amplitude decay period (t541 to t541). To do. As a result, the voltage controlled oscillation circuit 103 (VCO) oscillates and generates a clock signal having a frequency corresponding to the input control voltage VCNT. Therefore, in the 100% modulation period (t57-), the normal amplitude period (t50). ˜t541), the clock signal having the frequency at the time can be maintained.

<Modification>
Instead of the above-described configuration, the amplitude monitoring circuit 105 (VDET) may detect the envelope of the carrier wave CRR inputted from the antenna 10 and integrate the detection signal to generate an envelope waveform. The amplitude monitoring circuit 105 (VDET) may be configured to generate the detection signal CPEN by determining whether or not the level of the envelope waveform is equal to or lower than a reference value.
Further, the carrier signal CRR inputted from the antenna 10 is converted into digital data by an A / D converter, and the detection signal CPEN is generated by determining whether or not the data value of the carrier wave CRR is equal to or less than a reference value. You may comprise as follows.
Further, the reference clock signal CLKREF and the feedback signal CLKFB are input to the phase comparison circuit 100 (PD). Instead of the phase comparison circuit 100 (PD), a phase frequency comparator may be provided. The phase frequency comparator may be configured to generate a difference between rising edges of the reference clock signal CLKREF and the feedback signal CLKFB as an up difference signal and a difference between falling edges as a down difference signal.
In the phase comparison circuit 100 (PD), the phase difference between the reference clock signal CLKREF and the feedback signal CLKFB is detected by comparing the falling edges of the reference clock signal CLKREF and the feedback signal CLKFB. Instead of such a configuration, the phase comparison circuit 100 (PD) may detect the phase difference between the reference clock signal CLKREF and the feedback signal CLKFB by comparing the rising edges thereof.

Second Embodiment
FIG. 11 is a block diagram showing an example of the delay circuit 106 (DLY) according to the second embodiment of the present invention.
The up signal UP and the down signal DN extracted by the phase comparison circuit 100 (PD) are input to the delay circuit 106 (DLY).
In the delay circuit 106 (DLY), n inverter circuits each having a delay time Δt are connected in series (n: even number). Here, the delay time generated from the input terminal of the inverter circuit I1 to the output terminal of the inverter circuit In is set to td = n × Δt, and this delay time td is set to coincide with the delay time td shown in FIG.
In the present embodiment, the up signal UP and the down signal DN extracted by the phase comparison circuit 100 (PD) are input to the delay circuit 106 (DLY). By applying to the delay circuit 106 a configuration in which a plurality of inverter circuits I1 to In are connected in series to the delay circuit 106 (DLY), the up signal UPS and the down signal DN added with the delay time td and The down signal DNS can be output to the charge pump circuit 101 (CP).

<Third Embodiment>
FIG. 12 is a block diagram showing an example of the delay circuit 106 (DLY) according to the third embodiment of the present invention.
The up signal UP and the down signal DN extracted by the phase comparison circuit 100 (PD) are input to the delay circuit 106 (DLY).
The delay circuit 106 (DLY) is configured to connect n sets in series of a primary CR low-pass filter and an inverter circuit connected in series. The delay circuit 106 (DLY) has a configuration in which a primary low-pass filter is interposed between the inverter circuits.
When the primary CR low-pass filter inputs an input signal to the inverter circuit I1 via the resistor R11, the connection point between the resistor R11 and the inverter circuit I1 is grounded to the GND by the capacitor C11. As a result, a delay time _tτ obtained by a natural logarithm function is given to the time constant τ by the resistor R11 and the capacitor C11.
In addition, since the inverter circuit I1 has a delay time Δt, the delay circuit 106 (DLY) can add the delay time td = n (t _τ + Δt) to the input signal. This delay time td is set to coincide with the delay time td shown in FIG.
When the pulse widths of the up signal UP and the down signal DN are narrow, the signal may be lost by the n-stage primary low-pass filter. For this reason, it may be eliminated by designing the pulse widths of the up signal UP and the down signal DN to be large. In addition, the time constant τ of the primary low-pass filter may be designed so that the signal does not disappear even when n stages of the primary low-pass filter and inverter circuit are connected in series.
In the present embodiment, the up signal UP and the down signal DN extracted by the phase comparison circuit 100 (PD) are input to the delay circuit 106 (DLY). The delay circuit 106 (DLY) applies a configuration in which a plurality of inverter circuits I1 to In are connected in series and a primary low-pass filter (R11, C11) is interposed between the inverter circuits to the delay circuit 106. Thus, the up signal UPS and the down signal DNS obtained by adding the delay time td to the up signal UP and the down signal DN can be output to the charge pump circuit 101 (CP).

<Fourth embodiment>
FIG. 13 is a block diagram showing an example of a PLL circuit 130 according to the fourth embodiment of the present invention.
In the fourth embodiment, the card 1 (CARD) 1 includes a PLL circuit 130 shown in FIG. 13 in place of the PLL circuit 12 shown in FIGS.
13 includes a phase comparison circuit 100 (PD), a delay circuit 106 (DLY), a charge pump circuit 101 (CP), a loop filter circuit 102 (LF), and a voltage controlled oscillation circuit 103 (VCO). ), A frequency dividing circuit 104 (DIV), and a phase monitoring circuit 107 (PDET). In addition, since the code | symbol shown in FIG. 12 and the same code | symbol shown in FIG. 2 are the same structures, the description is abbreviate | omitted.
In the fourth embodiment, a delay circuit 106 (DLY) is provided between the phase comparison circuit 100 (PD) and the charge pump circuit 101 (CP). In the fourth embodiment, a phase monitoring circuit 107 (PDET) that monitors the pulse widths of the up signal UP and the down signal DN extracted by the phase comparison circuit 100 (PD) is provided.

The phase monitoring circuit 107 (PDET) targets a phase abnormality period in which waveform distortion may occur in the carrier wave in the process of the carrier wave shifting to the 100% modulation period.
Here, the phase abnormality period refers to a cycle period in which the zero cross phase for each cycle of the carrier wave is different from the previous phase.
The phase comparison circuit 100 (PD) compares the falling edge of the reference clock signal CLKREF with the falling edge of the feedback signal CLKFB, and outputs the extracted up signal UP and down signal DN as the first signal to the delay circuit 106 (DLY). ).
The delay circuit 106 (DLY) outputs an up second signal UPS and a down second signal DNS obtained by adding a delay time td to the input up signal UP and down signal DN to the charge pump circuit 101 (CP).
The phase monitoring circuit 107 (PDET) monitors the pulse width of the pulse signal indicating the phase difference between the up signal UP and the first down signal DN, and detects the detection signal CPEN when the pulse width exceeds a predetermined width. Is output.
The phase monitoring circuit 107 (PDET) outputs a low level detection signal CPEN to the charge pump circuit 101 (CP) when the up signal UP or the down signal DN exceeds the arbitrarily set pulse width range.
Note that the phase monitoring circuit 107 (PDET) sets the phase normal period as the phase of the carrier wave CRR is not different when the up signal UP or the down signal DN is within the arbitrarily set pulse width range. The phase monitoring circuit 107 (PDET) maintains a high level output.

On the other hand, the phase monitoring circuit 107 (PDET) detects the phase abnormality period when the up signal UP or the down signal DN exceeds the arbitrarily set pulse width range due to the phase difference of the carrier wave CRR. As a result, the low level detection signal CPEN is generated.
The charge pump circuit 101 (CP) is configured by a push-pull circuit, generates a charge / discharge current CPTT corresponding to the up second signal UPS and the down second signal DNS, and supplies the charge / discharge current CPTT to the loop filter circuit 102 (LF).
Further, when the charge pump circuit 101 (CP) receives the detection signal CPEN from the phase monitoring circuit 107 (PDET), the charge pump circuit 101 (CP) generates charge / discharge currents corresponding to the up-second signal UPS and the down-second signal DNS according to the phase difference. Stop the conversion operation. As a result, the charge pump circuit 101 (CP) switches SW ₁ , SW ₂ , SW _UP , SW _DN during the phase abnormality period (period in which the phase of the carrier wave CRR is different) when the detection signal CPEN is at a low level. Becomes an open state, that is, there is no charge / discharge current to the output point P.

FIG. 14 is a timing chart showing an example of the operation of the PLL circuit 130 shown in FIG.
When the pulse widths of the up signal UP and the down signal DN differ from the original phase (time t65), the up-second signal UPS and the down-second signal DNS, which are the delayed signals (delay time td), are changed to the charge pump circuit 101 ( CP) at time t65 to t67.
On the other hand, when the up signal UP or the down signal DN exceeds the arbitrarily set pulse width range (time t65), the phase monitoring circuit 107 (PDET) outputs the low level detection signal CPEN to the charge pump circuit 101 (CP ).
That is, at time t651 before the up second signal UPS and the down second signal DNS are input to the charge pump circuit 101 (CP) from time t66 to t67, the detection signal CPEN (low level) is supplied to the charge pump circuit 101 (CP). Entered.

As a result, in the charge pump circuit 101 (CP), the switches SW ₁ , SW ₂ , SW _UP , and SW _DN are opened according to the detection signal CPEN (low level) received at the time t541 that is the phase abnormality period, and the output There is no charging / discharging current to the point P, and charging / discharging stops.
In the present embodiment, at the time (t65 to t67) before the transition to the 100% modulation period (t67 to), the pulse widths of the up signal UP and the down signal DN are the original due to the waveform disturbance of the carrier wave CRR. Assume a case where the phase is different and different.
When the detection signal CPEN (time t651) is switched from the high level to the low level, the charge / discharge operation of the charge pump circuit 101 (CP) is stopped.

According to the present embodiment, as shown in FIG. 14, in the normal phase period (t60 to t651), the up-second signal UPS and the down-second signal DNS when the detection signal CPEN (time t651) is in the high level state are Input from the delay circuit 106 (DLY) to the charge pump circuit 101 (CP).
In the charge pump circuit 101 (CP), the switches SW ₁ , SW ₂ , SW _UP , and SW _DN are opened according to the detection signal CPEN (low level) received at the time t651 when the phase is abnormal, and the output point P is reached. Thus, there is no charge / discharge current, and the charge / discharge operation stops.
For this reason, the loop filter circuit 102 (LF) maintains the control voltage VCNT during the phase normal period in which the detection signal CPEN is at the high level during the phase abnormality period (t651 to t651). As a result, the voltage controlled oscillation circuit 103 (VCO) oscillates and generates a clock signal having a frequency corresponding to the input control voltage VCNT. Therefore, during the 100% modulation period (t67-), the phase normal period (t60) ˜t651), the clock signal having the frequency can be maintained.

<Modification>
The phase comparison circuit 100 (PD) receives the reference clock signal CLKREF and the feedback signal CLKFB. Instead of the phase comparison circuit 100 (PD), a phase frequency comparator may be provided. The phase frequency comparator may be configured to generate a difference between rising edges of the reference clock signal CLKREF and the feedback signal CLKFB as an up difference signal and a difference between falling edges as a down difference signal.
In the phase comparison circuit 100 (PD), the phase difference between the reference clock signal CLKREF and the feedback signal CLKFB is detected by comparing the falling edges of the reference clock signal CLKREF and the feedback signal CLKFB. Instead of such a configuration, the phase comparison circuit 100 (PD) may detect the phase difference between the reference clock signal CLKREF and the feedback signal CLKFB by comparing the rising edges thereof.

<Fifth Embodiment>
FIG. 15 is a block diagram showing an example of the phase monitoring circuit 107 (PDET) according to the fifth embodiment of the present invention.
The up signal UP and the down signal DN extracted by the phase comparison circuit 100 (PD) are input to the phase monitoring circuit 107 (PDET).
The phase monitoring circuit 107 (PDET) includes an exclusive OR operation circuit XOR1, a transistor TR1, a capacitor C21, a resistor R21, and a comparator CMP1.
The exclusive OR operation circuit XOR1 receives the up signal UP and the down signal DN from the phase comparison circuit 100 (PD), performs an exclusive OR operation on both signals, and outputs a UDXOR signal (exclusive OR signal). Is output to the gate terminal of the transistor TR1.
The transistor TR1 has a drain terminal and a source terminal connected to both ends of the capacitor C21, a drain terminal connected to the power supply VDD via the resistor R21, and a source terminal grounded to GND.
The transistor TR1, the capacitor C21, and the resistor R21 constitute a signal generation circuit, and charge / discharge is generated according to the pulse width of the exclusive OR signal to generate a charge / discharge signal representing a voltage level.

When the UDXOR signal is input to the gate terminal of the transistor TR1, and the pulse width of the UDXOR signal is narrow and the ON time is short (t70, t71), the charge / discharge signal PCMP output from the drain terminal is in a high potential state. maintain. On the other hand, when the ON time represented by the pulse width of the UDXOR signal becomes longer (t72, t73), the charge / discharge time according to the values of the capacitor C21 and the resistor R21 is set so that the charge / discharge signal PCMP falls to a low potential. adjust.
The comparator CMP1 constitutes a detection circuit, and when detecting that the potential of the charge / discharge signal PCMP has dropped below a threshold value Vref (reference voltage) arbitrarily set, the detection signal CPEN signal is switched from a high level to a low level. Output to the charge pump circuit 101 (CP).

FIG. 16 is a timing chart showing an example of the operation of the phase monitoring circuit 107 (PDET) shown in FIG.
In a normal state (time t70 to t72) in which waveform distortion does not occur in the carrier wave CRR, the UDXOR signal generated from the exclusive OR operation circuit XOR1 has a narrow pulse width (for example, less than the width of the clock signal CKKPLL). The charge / discharge signal PCMP maintains a high potential state.
On the other hand, when the carrier wave CRR has waveform disturbance (t72, t73) and the up signal UP or the down signal DN is generated with a clock width different from the original (normal state), the clock width of the UDXOR signal becomes long. For this reason, the ON time of the transistor TR1 becomes longer and the voltage of the charge / discharge signal PCMP signal decreases.
When the comparator CMP1 detects that the potential of the charge / discharge signal PCMP is lower than the arbitrarily set potential value Vref, the comparator CMP1 switches the detection signal CPEN from the high level to the low level (t721), and switches to the charge pump circuit 101 (CP). Output.

As a result, in the charge pump circuit 101 (CP), the switches SW ₁ , SW ₂ , SW _UP , and SW _DN are opened according to the detection signal CPEN (low level) received at the time t721 that is the phase abnormality period, and the output There is no charge / discharge current to the point P, and the charge / discharge operation stops.
According to this embodiment, at the time (t72 to t73) before the transition to the 100% modulation period (t74 to), the pulse widths of the up signal UP and the down signal DN are inherently caused by the waveform disturbance of the carrier wave CRR. Assume that the phases differ from each other.
When the detection signal CPEN (time t721) is switched from the high level to the low level, the charge / discharge operation of the charge pump circuit 101 (CP) is stopped. As a result, as shown in FIG. 16, it is possible to maintain a clock signal having a frequency during the phase normal period (t70 to t72) during the 100% modulation period (t74 to t).

<Sixth Embodiment>
FIG. 17 is a block diagram showing an example of the phase monitoring circuit 107 (PDET) according to the sixth embodiment of the present invention.
The up signal UP and the down signal DN extracted by the phase comparison circuit 100 (PD) are input to the phase monitoring circuit 107 (PDET).
The phase monitoring circuit 107 (PDET) includes an exclusive OR operation circuit XOR1 and a counter circuit (CNT).
The exclusive OR operation circuit XOR1 receives the up signal UP and the down signal DN from the phase comparison circuit 100 (PD), performs an exclusive OR operation on both signals, and outputs the UDXOR signal to the counter circuit (CNT). Output to.
Note that the UDXOR signal indicates that the phase of the reference clock signal CLKREF and the feedback signal CLKFB differ as the high level width of the signal increases.

The counter circuit (CNT) receives the UDXOR signal from the exclusive OR operation circuit XOR1, counts the internal clock signal CLKPLL with the first counter CNT1 during the period when the UDXOR signal is at a high level, and counts the count value. D1 (count value) is obtained.
The counter circuit (CNT) switches the detection signal CPEN from the high level to the low level and outputs the detection signal CPEN to the charge pump circuit 101 (CP) when the count value D1 becomes equal to or greater than a certain set value Dref1.
When the detection signal CPEN is once switched to the low level, the counter circuit (CNT) counts the internal clock signal CLKPLL with the second counter CNT2 to obtain the count value D2.
The counter circuit (CNT) holds the detection signal CPEN in a low level state during a period until the count value D2 reaches a set value Dref2. Further, when the count value D2 becomes equal to or larger than the set value Dref2 + 1, the counter circuit (CNT) switches the detection signal CPEN from the low level state to the high level state, and once clears the count values D1 and D2.

FIG. 18 is a timing chart showing an example of the operation of the phase monitoring circuit 107 (PDET) shown in FIG.
In a normal state (time t80 to t82) in which waveform distortion does not occur in the carrier wave CRR, the UDXOR signal generated from the exclusive OR operation circuit XOR1 has a narrow pulse width, and thus the detection signal CPEN maintains a high level.
On the other hand, when the carrier wave CRR has a waveform disturbance (t82, t83-) and the up signal UP or the down signal DN is generated with a clock width different from the original (normal state), the clock width of the UDXOR signal becomes long. Therefore, the counter circuit (CNT) switches the detection signal CPEN from the high level to the low level (t821) because the count value D1 becomes equal to or greater than the set value Dref1, and the low-level detection signal CPEN is changed to the charge pump circuit 101. Output to (CP).

As a result, in the charge pump circuit 101 (CP), the switches SW ₁ , SW ₂ , SW _UP , SW _DN are opened according to the detection signal CPEN (low level) received at the time t821 when the phase is abnormal, and the output There is no charging / discharging current to the point P, and charging / discharging stops.
According to the present embodiment, at the time (t82 to t83) before the transition to the 100% modulation period (t84 to), the pulse widths of the up signal UP and the down signal DN are inherently caused by the waveform disturbance of the carrier wave CRR. Assume that the phases differ from each other.
When the detection signal CPEN (time t821) is switched from the high level to the low level, the charge / discharge operation of the charge pump circuit 101 (CP) is stopped. As a result, as shown in FIG. 18, a clock signal having a frequency during the phase normal period (t80 to t82) can be maintained during the 100% modulation period (t84 to t).

<Configuration, operation and effect of exemplary embodiment of the present invention>
<First aspect>
The chip 15 (semiconductor device) of this aspect receives the amplitude-modulated carrier wave from the antenna 10 to demodulate the reception signal RXD, and receives the clock signal CLKREF and the reception circuit 11 that extracts the clock signal CLKREF from the carrier wave. A PLL circuit 120 that controls to synchronize with the internal clock signal CLKPLL. The PLL circuit 120 divides the internal clock signal CLKPLL to generate the feedback signal CLKFB, and the clock signal CLKREF and feedback. A phase comparison circuit 100 that generates an up signal UP and a down signal DN representing a phase difference from the signal CLKFB, and an up signal UPS and a down signal DNS in which a delay time td is added to the up signal UP and the down signal DN. Delay circuit 106, up signal UPS and down Charge pump circuit 101 for generating charge / discharge current according to signal DNS, loop filter circuit 102 for converting to smoothed control voltage VCNT according to charge / discharge current, and internal clock signal having a frequency according to control voltage VCNT The charge pump circuit 101 includes a voltage controlled oscillation circuit 103 that oscillates CLKPLL, and an amplitude monitoring circuit 105 that monitors the amplitude of a carrier wave and generates a detection signal CPEN when the amplitude decreases below a predetermined threshold value VDETCP. When the detection signal CPEN is input, the operation of generating the charge / discharge current corresponding to the up signal UPS and the down signal DNS is stopped.

According to this aspect, in the PLL circuit 120, the frequency dividing circuit 104 divides the internal clock signal CLKPLL to generate the feedback signal CLKFB. The phase comparison circuit 100 generates an up signal UP and a down signal DN representing the phase difference between the clock signal CLKREF and the feedback signal CLKFB. The delay circuit 106 generates an up signal UPS and a down signal DNS obtained by adding a delay time td to the up signal UP and the down signal DN. The charge pump circuit 101 generates charge / discharge current in response to the up signal UPS and the down signal DNS. The loop filter circuit 102 converts it into a smoothed control voltage VCNT according to the charge / discharge current. The voltage controlled oscillation circuit 103 oscillates an internal clock signal CLKPLL having a frequency corresponding to the control voltage VCNT. The amplitude monitoring circuit 105 monitors the amplitude of the carrier wave and generates the detection signal CPEN when the amplitude decreases below a predetermined threshold value VDETCP. At this time, when the detection signal CPEN is input, the charge pump circuit 101 stops the operation of generating the charge / discharge current according to the up signal UPS and the down signal DNS.
Thereby, in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, for example, in the case of an unintentional carrier wave disturbance in the amplitude attenuation period shown in FIG. 10, the carrier wave is in a normal state. The clock signal having the frequency in the period can be maintained even in the 100% modulation period.

<Second aspect>
The chip 15 according to the present embodiment inputs a carrier wave subjected to amplitude modulation from the antenna 10 and demodulates the received signal, and also receives the clock signal CLKREF from the receiving circuit 11 that extracts the clock signal CLKREF from the carrier wave, and the internal clock signal CLKPLL. A PLL circuit 130 that performs control to be synchronized with the PLL circuit 130. The PLL circuit 130 divides the internal clock signal CLKPLL to generate a feedback signal CLKFB, and between the clock signal CLKREF and the feedback signal CLKFB A phase comparison circuit 100 for generating an up signal UP and a down signal DN representing a phase difference between the delay time 106 and a delay circuit 106 for generating an up signal UPS and a down signal DNS obtained by adding a delay time td to the up signal UP and the down signal DN; Charging according to up signal UPS and down signal DNS Charge pump circuit 101 for generating electric current, loop filter circuit 102 for converting to smoothed control voltage VCNT according to charge / discharge current, and voltage control for oscillating internal clock signal CLKPLL having a frequency according to control voltage VCNT An oscillation circuit 103 and a phase monitoring circuit that monitors a pulse width of a pulse signal representing a phase difference between the up signal UP and the down signal DN and generates a detection signal CPEN when the pulse width exceeds a predetermined width. 107, and the charge pump circuit 101 stops the operation of generating the charge / discharge current according to the up signal UPS and the down signal DNS when the detection signal CPEN is input.

According to this aspect, in the PLL circuit 130, the frequency dividing circuit 104 divides the internal clock signal CLKPLL to generate the feedback signal CLKFB. The phase comparison circuit 100 generates an up signal UP and a down signal DN representing the phase difference between the clock signal CLKREF and the feedback signal CLKFB. The delay circuit 106 generates an up signal UPS and a down signal DNS obtained by adding a delay time td to the up signal UP and the down signal DN. The charge pump circuit 101 generates charge / discharge current in response to the up signal UPS and the down signal DNS. The loop filter circuit 102 converts it into a smoothed control voltage VCNT according to the charge / discharge current. The voltage controlled oscillation circuit 103 oscillates an internal clock signal CLKPLL having a frequency corresponding to the control voltage VCNT. The phase monitoring circuit 107 monitors the pulse width of the pulse signal representing the phase difference between the up signal UP and the down signal DN generated from the phase comparison circuit 100 and detects when the pulse width exceeds a predetermined width. A signal CPEN is generated. At this time, when the detection signal CPEN is input, the charge pump circuit 101 stops the operation of generating the charge / discharge current according to the up signal UPS and the down signal DNS.
Thereby, in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, for example, in the phase abnormality period shown in FIG. The clock signal having the frequency in the period can be maintained even in the 100% modulation period.

<Third aspect>
The amplitude monitoring circuit 105 according to this aspect is characterized in that the amplitude attenuation period during which the waveform distortion may occur in the carrier wave in the process of the carrier wave shifting to the 100% modulation period is a target.
According to this aspect, the amplitude monitoring circuit 105 targets an amplitude decay period in which waveform disturbance may occur in the carrier wave in the process of the carrier wave shifting to the 100% modulation period.
Thus, for the amplitude decay period in which waveform disturbance may occur in the carrier wave, the carrier wave amplitude is monitored, and the detection signal CPEN can be generated when the amplitude decreases below a predetermined threshold value VDETCP. Even when the waveform of the carrier wave is disturbed, the clock signal having the frequency in the period in which the carrier wave is in a normal state can be maintained even in the 100% modulation period.

<4th aspect>
The phase monitoring circuit 107 according to this aspect is characterized by targeting a phase abnormality period in which waveform disturbance may occur in the carrier wave in the process of the carrier wave shifting to the 100% modulation period.
According to this aspect, the phase monitoring circuit 107 targets a phase abnormality period in which waveform disturbance may occur in the carrier wave in the process of the carrier wave shifting to the 100% modulation period.
As a result, since the phase abnormality period in which waveform disturbance may occur in the carrier wave is targeted, the pulse width of the pulse signal indicating the phase difference between the up signal UP and the down signal DN is monitored, and the pulse width is The detection signal CPEN can be generated when the width exceeds a predetermined width, and even when the waveform of the carrier wave is disturbed, the clock signal having the frequency in the period in which the carrier wave is in a normal state is maintained even during the 100% modulation period. can do.

<5th aspect>
The carrier wave of this aspect is a carrier wave of an ASK 100% modulation system.
According to this aspect, the carrier wave is a carrier wave of the ASK 100% modulation method.
As a result, since the carrier wave of the ASK 100% modulation system is targeted, even when an unintended carrier wave disturbance occurs during the transition from the period in which the carrier wave is in the normal state to the 100% modulation period, the carrier wave is in the normal state. A clock signal having a frequency in a certain period can be maintained even in a 100% modulation period.

<Sixth aspect>
The delay circuit 106 of this aspect has a configuration in which a plurality of inverter circuits I1 to In are connected in series, or a configuration in which a primary low-pass filter (R11, C11) is interposed between the inverter circuits. .
According to this aspect, the delay circuit 106 has a configuration in which a plurality of inverter circuits I1 to In are connected in series, or a configuration in which a primary low-pass filter (R11, C11) is interposed between the inverter circuits.
Accordingly, by applying a configuration in which a plurality of inverter circuits I1 to In are connected in series, or a configuration in which a primary low-pass filter (R11, C11) is interposed between the inverter circuits to the delay circuit 106, an up signal An up signal UPS and a down signal DNS obtained by adding a delay time td to the UP and down signals DN can be generated.

<Seventh aspect>
The phase monitoring circuit 107 of this aspect performs an exclusive OR operation on the up signal UP and the down signal DN from the phase comparison circuit 100 to generate an exclusive OR signal UDXOR ( XOR1), a signal generation circuit (TR1, C21, R21) that generates a charge / discharge signal representing a voltage level by charging / discharging according to the pulse width of the exclusive OR signal, and the voltage level of the charge / discharge signal is a predetermined level And a comparator (CMP1) that generates a detection signal CPEN when the voltage drops below the reference voltage Vref.
According to this aspect, in the phase monitoring circuit 107, the exclusive OR operation circuit (XOR1) performs an exclusive OR operation on the up signal UP and the down signal DN from the phase comparison circuit 100 to perform exclusive logic operation. A sum signal UDXOR is generated. The signal generation circuit (TR1, C21, R21) is charged / discharged according to the pulse width of the exclusive OR signal to generate a charge / discharge signal representing the voltage level. The comparator (CMP1) generates the detection signal CPEN when the voltage level of the charge / discharge signal falls below the predetermined reference voltage Vref.
Thereby, the phase monitoring circuit 107 monitors the pulse width of the pulse signal indicating the phase difference between the up signal UP and the down signal DN, and generates the detection signal CPEN when the pulse width exceeds a predetermined width. can do.

<Eighth aspect>
The phase monitoring circuit 107 of this aspect performs an exclusive OR operation on the up signal UP and the down signal DN from the phase comparison circuit 100 to generate an exclusive OR signal (XOR1). And a counter circuit (CNT) that counts the internal clock signal CLKPLL within a period related to the pulse width of the exclusive OR signal and generates the detection signal CPEN when the count value D1 exceeds a predetermined range. It is characterized by that.
According to this aspect, in the phase monitoring circuit 107, the exclusive OR operation circuit (XOR1) performs an exclusive OR operation on the up signal UP and the down signal DN from the phase comparison circuit 100 to perform exclusive OR operation. Generate a signal. The counter circuit (CNT) counts the internal clock signal CLKPLL within a period related to the pulse width of the exclusive OR signal, and generates a detection signal CPEN when the count value exceeds a predetermined range.
Thereby, the phase monitoring circuit 107 monitors the pulse width of the pulse signal indicating the phase difference between the up signal UP and the down signal DN, and generates the detection signal CPEN when the pulse width exceeds a predetermined width. can do.

<Ninth aspect>
According to the PLL circuit control method of this aspect, an amplitude-modulated carrier wave is input from the antenna 10 to demodulate the received signal, and the receiving circuit 11 that extracts the clock signal CLKREF from the carrier wave and the clock signal CLKREF are input to the internal circuit. A PLL circuit 120 that performs control to synchronize with the clock signal CLKPLL, and controls the PLL circuit 120 during a period before the carrier wave shifts to the 100% modulation period. The PLL circuit 120 includes: The internal clock signal CLKPLL is divided to generate the feedback signal CLKFB, the up signal UP and the down signal DN representing the phase difference between the clock signal CLKREF and the feedback signal CLKFB are generated, and the up signal UP and the down signal DN are generated. Up signal UPS and down signal DNS with delay time td The charge / discharge current is generated according to the up signal UPS and the down signal DNS, converted to the smoothed control voltage VCNT according to the charge / discharge current, and the internal clock signal CLKPLL having the frequency according to the control voltage VCNT is generated. When the amplitude of the carrier wave is monitored and the amplitude decreases below a predetermined threshold value VDETCP, a detection signal CPEN is generated. When the detection signal CPEN is generated, charging is performed according to the up signal UPS and the down signal DNS. The operation for generating the discharge current is stopped.

According to this aspect, the PLL circuit 120 divides the internal clock signal CLKPLL to generate the feedback signal CLKFB. The PLL circuit 120 generates an up signal UP and a down signal DN that represent a phase difference between the clock signal CLKREF and the feedback signal CLKFB. The PLL circuit 120 generates an up signal UPS and a down signal DNS obtained by adding a delay time td to the up signal UP and the down signal DN. The PLL circuit 120 generates a charge / discharge current according to the up signal UPS and the down signal DNS. The PLL circuit 120 converts the smoothed control voltage VCNT according to the charge / discharge current. The PLL circuit 120 oscillates an internal clock signal CLKPLL having a frequency corresponding to the control voltage VCNT. The PLL circuit 120 monitors the amplitude of the carrier wave and generates the detection signal CPEN when the amplitude decreases below a predetermined threshold value VDETCP. At this time, when the detection signal CPEN is generated, the PLL circuit 120 stops the operation of generating the charge / discharge current according to the up signal UPS and the down signal DNS.
Thereby, in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, for example, in the case of an unintentional carrier wave disturbance in the amplitude attenuation period shown in FIG. 10, the carrier wave is in a normal state. The clock signal having the frequency in the period can be maintained even in the 100% modulation period.

<10th aspect>
According to the PLL circuit control method of this aspect, an amplitude-modulated carrier wave is input from the antenna 10 to demodulate the received signal, and the receiving circuit 11 that extracts the clock signal CLKREF from the carrier wave and the clock signal CLKREF are input to the internal circuit. A PLL circuit 130 that performs control to synchronize with the clock signal CLKPLL, and controls the PLL circuit 130 during a period before the carrier wave shifts to the 100% modulation period. The internal clock signal is divided to generate the feedback signal CLKFB, the up signal UP and the down signal DN representing the phase difference between the clock signal CLKREF and the feedback signal CLKFB are generated, and delayed to the up signal UP and the down signal DN An up signal UPS and a down signal DNS with a time td are generated, and the up signal UPS is generated. A charge / discharge current is generated according to the signal UPS and the down signal DNS, converted to a smoothed control voltage VCNT according to the charge / discharge current, and an internal clock signal CLKPLL having a frequency according to the control voltage VCNT is oscillated and raised. When the pulse width of the pulse signal representing the phase difference between the signal UP and the down signal DN is monitored and the detection signal CPEN is generated when the pulse width exceeds a predetermined width, and the detection signal CPEN is generated In addition, the operation of generating the charge / discharge current according to the up signal UPS and the down signal DNS is stopped.

According to this aspect, the PLL circuit 130 divides the internal clock signal to generate the feedback signal CLKFB. The PLL circuit 130 generates an up signal UP and a down signal DN that represent a phase difference between the clock signal CLKREF and the feedback signal CLKFB. The PLL circuit 130 generates an up signal UPS and a down signal DNS obtained by adding a delay time td to the up signal UP and the down signal DN. The PLL circuit 130 generates a charge / discharge current according to the up signal UPS and the down signal DNS. The PLL circuit 130 converts the smoothed control voltage VCNT according to the charge / discharge current. The PLL circuit 130 oscillates an internal clock signal CLKPLL having a frequency corresponding to the control voltage VCNT. The PLL circuit 130 monitors the pulse width of the pulse signal representing the phase difference between the up signal UP and the down signal DN, and generates the detection signal CPEN when the pulse width exceeds a predetermined width. At this time, when the detection signal CPEN is generated, the PLL circuit 130 stops the operation of generating the charge / discharge current according to the up signal UPS and the down signal DNS.
Thereby, in the process of shifting from a period in which the carrier wave is in a normal state to a 100% modulation period, for example, in the phase abnormality period shown in FIG. The clock signal having the frequency in the period can be maintained even in the 100% modulation period.

DESCRIPTION OF SYMBOLS 1 ... Card, 2 ... Reader / writer, 3 ... Host apparatus, 10 ... Antenna, 11 ... Reception circuit, 12 ... PLL circuit, 13 ... Transmission circuit, 14 ... Logic circuit, 15 ... Chip, 100 ... Phase comparison circuit, 101 ... Charge pump circuit 102 ... Loop filter circuit 103 ... Voltage controlled oscillation circuit 104 ... Frequency divider circuit 105 ... Amplitude monitoring circuit 106 ... Delay circuit 107 ... Phase monitoring circuit

Japanese Patent No. 5323517

Claims (10)

A receiving circuit that receives an amplitude-modulated carrier wave from an antenna and demodulates a received signal, and extracts a clock signal from the carrier wave;
A PLL circuit that performs control to input the clock signal and synchronize with the internal clock signal,
The PLL circuit includes:
A frequency divider that divides the internal clock signal to generate a feedback signal;
A phase comparison circuit for generating a first up signal and a first down signal representing a phase difference between the clock signal and the feedback signal;
A delay circuit for generating a second up signal and a second down signal obtained by adding a delay time to the first up signal and the first down signal;
A charge pump circuit for generating a charge / discharge current in response to the second up signal and the second down signal;
A loop filter circuit for converting to a smoothed control voltage according to the charge / discharge current;
A voltage controlled oscillation circuit for oscillating the internal clock signal having a frequency according to the control voltage;
An amplitude monitoring circuit that monitors the amplitude of the carrier wave and generates a detection signal when the amplitude decreases below a predetermined threshold, and
The said charge pump circuit stops the operation | movement which produces | generates the charging / discharging electric current according to a said 2nd up signal and a 2nd down signal, when the said detection signal is produced | generated. A receiving circuit that receives an amplitude-modulated carrier wave from an antenna and demodulates a received signal, and extracts a clock signal from the carrier wave;
A PLL circuit that performs control to input the clock signal and synchronize with the internal clock signal,
The PLL circuit includes:
A frequency divider that divides the internal clock signal to generate a feedback signal;
A phase comparison circuit for generating a first up signal and a first down signal representing a phase difference between the clock signal and the feedback signal;
A delay circuit for generating a second up signal and a second down signal obtained by adding a delay time to the first up signal and the first down signal;
A charge pump circuit for generating a charge / discharge current in response to the second up signal and the second down signal;
A loop filter circuit for converting to a smoothed control voltage according to the charge / discharge current;
A voltage controlled oscillation circuit for oscillating the internal clock signal having a frequency according to the control voltage;
A phase monitoring circuit for monitoring a pulse width of a pulse signal representing a phase difference between the first up signal and the first down signal, and generating a detection signal when the pulse width exceeds a predetermined width; With
The said charge pump circuit stops the operation | movement which produces | generates the charging / discharging electric current according to a said 2nd up signal and a said 2nd down signal, when the said detection signal is produced | generated.   2. The semiconductor according to claim 1, wherein the amplitude monitoring circuit targets an amplitude attenuation period in which waveform distortion may occur in the carrier wave in a process in which the carrier wave shifts to a 100% modulation period. apparatus.   3. The semiconductor according to claim 2, wherein the phase monitoring circuit targets a phase abnormality period in which a waveform disturbance may occur in the carrier wave in a process in which the carrier wave shifts to a 100% modulation period. apparatus.   5. The semiconductor device according to claim 1, wherein the carrier wave is an ASK 100% modulation carrier wave.   6. The delay circuit according to claim 1, wherein the delay circuit has a configuration in which a plurality of inverter circuits are connected in series, or a configuration in which a first-order low-pass filter is interposed between the inverter circuits. A semiconductor device according to 1. The phase monitoring circuit includes:
An exclusive OR operation circuit that performs an exclusive OR operation on the first up signal and the first down signal from the phase comparison circuit to generate an exclusive OR signal;
A signal generation circuit that generates a charge / discharge signal representing a voltage level by charging and discharging according to a pulse width of the exclusive OR signal; and
8. A semiconductor device according to claim 2, further comprising: a detection circuit that generates a detection signal when a voltage level of the charge / discharge signal is lower than a predetermined reference voltage. . The phase monitoring circuit includes:
An exclusive OR operation circuit that generates an exclusive OR signal by performing an exclusive OR operation on the first up signal and the first down signal from the phase comparison circuit;
A counter circuit that counts the internal clock signal within a period related to a pulse width of the exclusive OR signal and generates a detection signal when the count value exceeds a predetermined range. The semiconductor device according to any one of claims 2 to 7. A receiving circuit that receives an amplitude-modulated carrier wave from an antenna and demodulates a received signal, and extracts a clock signal from the carrier wave;
And a PLL circuit that controls to input the clock signal and synchronize with an internal clock signal, and controls the PLL circuit during a period before the carrier wave shifts to a 100% modulation period. And
The PLL circuit includes:
Divide the internal clock signal to generate a feedback signal;
Generating a first up signal and a first down signal representing a phase difference between the clock signal and the feedback signal;
Generating a second up signal and a second down signal obtained by adding a delay time to the first up signal and the first down signal;
Generating a charge / discharge current in response to the second up signal and the second down signal;
Converted to a smoothed control voltage according to the charge / discharge current,
Oscillates the internal clock signal with a frequency according to the control voltage;
Monitoring the amplitude of the carrier wave to generate a detection signal when the amplitude decreases below a predetermined threshold;
A control method for a PLL circuit, wherein when the detection signal is generated, an operation of generating a charge / discharge current according to the second up signal and the second down signal is stopped. A receiving circuit that receives an amplitude-modulated carrier wave from an antenna and demodulates a received signal, and extracts a clock signal from the carrier wave;
And a PLL circuit that controls to input the clock signal and synchronize with an internal clock signal, and controls the PLL circuit during a period before the carrier wave shifts to a 100% modulation period. And
The PLL circuit includes:
Divide the internal clock signal to generate a feedback signal;
Generating a first up signal and a first down signal representing a phase difference between the clock signal and the feedback signal;
Generating the second up signal and the second down signal by adding a delay time to the first up signal and the first down signal;
Generating a charge / discharge current in response to the second up signal and the second down signal;
Converted to a smoothed control voltage according to the charge / discharge current,
Oscillates the internal clock signal with a frequency according to the control voltage;
Monitoring a pulse width of a pulse signal representing a phase difference between the first up signal and the first down signal, and generating a detection signal when the pulse width exceeds a predetermined width;
A control method for a PLL circuit, wherein when the detection signal is generated, an operation of generating a charge / discharge current according to the second up signal and the second down signal is stopped.

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