JP2017037409A - Printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase in a signal amplitude generated in a certain frequency band in a reception circuit connected to a signal line.SOLUTION: A memory system 100 includes: a mother board 200 which is formed with a bus wiring 201; and a plurality of memory devices 302A-302H which are installed on the mother board 200 and receive signals transmitted from a memory controller 301 through the bus wiring 201. The bus wiring 201 includes a main wiring 216 and a plurality of branched wirings 206A-206H branched from a plurality of different branch spots 207A-207D of the main wiring 216 and connected to the plurality of memory devices 302A-302H. A resistance element 208B which is serially connected to the main wiring 216 and has a higher electric resistance value than the electric resistance value of the main wiring 216 is provided between the branch spots 207B, 207C out of the plurality of branch spots 207A-207D.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a printed circuit board including a plurality of receiving circuits that receive signals via a signal line having a main wiring and a plurality of branch wirings.

  In general, a memory system includes a memory controller and a plurality of memory devices. As a memory device, DDR3-SDRAM (Double Data Rate 3 Synchronous Dynamic Random Access Memory) is generally known.

  The memory controller transmits an address signal or a command signal (address / command signal), and each memory device is controlled by receiving the address / command signal, and a data signal is transmitted between the memory controller and the plurality of memory devices. Transmission / reception is performed. In particular, a highly functional electronic device often uses a plurality of DDR3-SDRAMs in order to secure a memory capacity.

  A memory device that is a DDR3-SDRAM has a function of adjusting signal transmission timing. Each memory device is connected to a branch wiring that branches from a one-stroke main wiring called flyby capable of increasing the address / command signal speed (see Non-Patent Document 1). In Non-Patent Document 1, the wiring length of each part of a signal line having a fly-by wiring structure is strictly defined. The fly-by wiring structure is also decided to be adopted in the next generation DDR4-SDRAM.

  The operating speed range of the DDR3-SDRAM was 800 [Mbps] to 1600 [Mbps], but has been extended to 2133 [Mbps] by the update of the standard. Further, the operating speed range of DDR4-SDRAM is expected to be 1600 [Mbps] to 3200 [Mbps], but there is a possibility that it will be expanded further in the future.

JEDEC standard No. 21C PC3-6400 / PC3-8500 / PC3-10600 / PC3-12800 / PC3-1490 / PC3-17000 DDR3 Unbuffered SO-DIMM Reference Design Specification Revision 2.0

  However, it has been confirmed that when the data transmission speed of a signal applied to a signal line having a fly-by wiring structure is increased, the signal amplitude reaching the receiving circuit in a certain frequency band is remarkably increased. In particular, in the receiving circuit connected to the center of the signal line, the increase in signal amplitude tends to increase. Such an increase in signal amplitude in the receiving circuit causes a deterioration in the life or damage of the receiving circuit.

  Accordingly, an object of the present invention is to suppress an increase in signal amplitude that occurs in a certain frequency band in a receiving circuit connected to a signal line.

  The printed circuit board of the present invention includes a printed wiring board on which signal lines are formed, and a plurality of signals that are mounted on the printed wiring board and that receive signals transmitted from a transmission circuit via the signal lines of the printed wiring board. And the signal line branches from a plurality of different branch locations of the main wiring and the main wiring having a starting end connected to the transmission circuit, and is connected to the plurality of receiving circuits, respectively. A plurality of branch wirings, and among the plurality of branch points, a first branch point, adjacent to the first branch point, and farther from the start end than the first branch point. A resistance component having an electrical resistance value higher than the electrical resistance value of the main wiring, connected in series to the main wiring, is provided between the second branch portion.

  According to the present invention, an increase in signal amplitude that occurs in a certain frequency band can be suppressed in a receiving circuit connected to a signal line.

1 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to a first embodiment. It is a top view of the motherboard of the vicinity where the resistive element was mounted in 1st Embodiment. It is a wave form diagram of the signal received in each memory device in the memory system of a 1st embodiment. It is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to a second embodiment. It is a topology diagram which shows the wiring structure of the memory system as an example of the printed circuit board concerning 3rd Embodiment. It is a topology diagram which shows the wiring structure of the memory system as an example of the printed circuit board concerning 4th Embodiment. FIG. 10 is a topology diagram illustrating a wiring configuration of a memory system as an example of a printed circuit board according to a fifth embodiment. It is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to a sixth embodiment. It is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to a seventh embodiment. It is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board of a comparative example. It is a wave form diagram of the signal received in each memory device in the memory system of a comparative example. (A) is a schematic diagram which shows the state which transmitted the signal from the memory controller to each memory device in the memory system of a comparative example. (B) is the graph which showed the permeation | transmission characteristic of the signal from a memory controller to each memory device for every frequency in the memory system of a comparative example. (A) is a schematic diagram which shows the transmission characteristic of the signal between each memory device in the memory system of a comparative example. (B) is the graph which showed the transmission characteristic of the signal between each memory device for every frequency in the memory system of a comparative example.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to the first embodiment of the present invention. A memory system 100 that is a printed circuit board includes a motherboard 200 that is a printed wiring board, a memory controller 301 that is a transmission circuit, and a plurality (eight in the first embodiment) of memory devices 302A to 302H that are a plurality of reception circuits. And. In the first embodiment, the memory devices 302A to 302H are DDR3-SDRAM or DDR4-SDRAM. The memory controller 301 and the plurality of memory devices 302A to 302H are mounted on the mother board 200. More specifically, the memory controller 301 is mounted on either the front surface or the back surface of the motherboard 200. The memory devices 302A, 302C, 302E, and 302G are mounted on the front surface, and the memory devices 302B, 302D, 302F, and 302H are mounted on the back surface. The front surface and the back surface are relative, and the surface is also referred to as one surface or the first surface, and the back surface opposite to the surface is also referred to as the other surface or the second surface. Further, the surface of the mother board 200 is also referred to as a surface layer, and the back surface is also referred to as a back layer. Between the surface layer (conductor layer) and the back layer (conductor layer), an inner layer (conductor layer) is disposed via an insulator layer. The conductor layer is a layer in which a conductor pattern is disposed.

  The memory controller 301 controls the memory devices 302A to 302H. The memory controller 301 transmits digital signals to the memory devices 302 </ b> A to 302 </ b> H via the motherboard 200 in the first embodiment, which is an address / command signal that is a control signal.

  Each of the memory devices 302A to 302H receives an address / command signal transmitted from the memory controller 301 via the motherboard 200. The memory controller 301 and each of the memory devices 302A to 302H transmit and receive data signals.

  The memory controller 301 is a semiconductor package having a control cell 311 that is a transmission element, and a transmission terminal 312 connected to the control cell 311. The memory devices 302A to 302H are semiconductor packages having memory cells 321A to 321H as receiving elements and receiving terminals 322A to 322H connected to the memory cells 321A to 321H via internal wirings 323A to 323H. The internal wirings 323A to 323H are effective wirings of the memory devices 302A to 302H. Each of the memory devices 302A to 302H is a semiconductor package having the same configuration and having the same characteristics.

  The motherboard 200 includes a bus wiring 201 that is a signal line that connects the memory controller 301 (transmission element) and the memory devices 302A to 302H (reception elements) by a fly-by method. In the first embodiment, the address signal bus wiring and the command signal bus wiring have a fly-by wiring structure based on the fly-by method, and one bus wiring 201 of the plurality of bus wirings (signal lines) is illustrated in FIG. 1 shows.

  The bus wiring 201 has a main wiring 216 in which a start end 217 is electrically connected to the transmission terminal 312 of the memory controller 301 and a termination 218 is electrically connected to one end of a termination resistor (terminator) 310. The main wiring 216 is formed so as to extend from the start end 217 to the end 218 in a single stroke in the wiring direction. The other end of the termination resistor 310 is electrically connected to a termination wiring 211 to which a termination potential is applied. As described above, since the start end 217 of the main wiring 216 is electrically connected to the memory controller 301 and the termination 218 is electrically connected to the termination resistor (terminator) 310, the reflection of the signal at the termination 218 is caused by the termination resistor 310. It is suppressed by.

  The main wiring 216 has four branch points 207A to 207D as a plurality of branch points at different positions. Specifically, the main wiring 216 includes, in order from the side closer to the start end 217, a branch location 207A that is a start end side branch location, a branch location 207B that is a first branch location, and a branch location 207C that is a second branch location. And a branch point 207D which is a terminal side branch point. That is, the branch point 207C is a branch point adjacent to the branch point 207B and farther from the start end 217 than the branch point 207B. The branch point 207D is a branch point adjacent to the branch point 207C and farther from the start end 217 than the branch point 207C. The branch point 207A is a branch point adjacent to the branch point 207B and closer to the start end 217 than the branch point 207B.

  Further, the main wiring 216 has a partial wiring 203 between the start end 217 and the branch location 207A, and a partial wiring 204A between the branch location 207A and the branch location 207B. The main wiring 216 includes the partial wirings 204B1 and 204B2 between the branch point 207B and the branch point 207C, the partial wiring 204C between the branch point 207C and the branch point 207D, and between the branch point 207D and the end point 218. The partial wiring 205 is provided.

  The bus wiring 201 has a plurality of (two in the first embodiment) branch wirings 206A and 206B that branch from the branch point 207A and are electrically connected to the reception terminals 322A and 322B of the memory devices 302A and 302B. ing. In addition, the bus wiring 201 branches from the branch location 207B and includes a plurality of (two in the first embodiment) branch wirings 206C and 206D that are electrically connected to the reception terminals 322C and 322D of the memory devices 302C and 302D. Have. In addition, the bus wiring 201 branches from the branch location 207C and includes a plurality of (two in the first embodiment) branch wirings 206E and 206F electrically connected to the reception terminals 322E and 322F of the memory devices 302E and 302F. Have. In addition, the bus wiring 201 branches from the branch location 207D and includes a plurality (two in the first embodiment) of branch wirings 206G and 206H that are electrically connected to the receiving terminals 322G and 322H of the memory devices 302G and 302H. Have.

  Specifically, one end 219A in the wiring direction of the branch wiring 206A and one end 219B in the wiring direction of the branch wiring 206B are electrically connected to the branch location 207A. Also, one end 219C in the wiring direction of the branch wiring 206C and one end 219D in the wiring direction of the branch wiring 206D are electrically connected to the branch location 207B. Also, one end 219E in the wiring direction of the branch wiring 206E and one end 219F in the wiring direction of the branch wiring 206F are electrically connected to the branch location 207C. Also, one end 219G in the wiring direction of the branch wiring 206G and one end 219H in the wiring direction of the branch wiring 206H are electrically connected to the branch location 207D.

  The other ends 220A to 220H in the wiring direction of the branch wirings 206A to 206H are electrically connected to the reception terminals 322A to 322H of the memory devices 302A to 302H, respectively. The branch wirings 206A to 206H are set to have the same wiring length (length in the wiring direction).

  Thus, in the first embodiment, a plurality (two) of memory devices 302A and 302B are electrically connected to the branch location 207A, and a plurality (two) of memory devices 302C, 302B are connected to the branch location 207B. 302D is electrically connected. In addition, a plurality (two) of memory devices 302E and 302F are electrically connected to the branch location 207C, and a plurality (two) of memory devices 302G and 302H are electrically connected to the branch location 207D. Yes.

  In FIG. 1, one memory cell included in each of the memory devices 302 </ b> A to 302 </ b> H is illustrated. However, each memory device has a plurality of memory cells, and each memory cell in each memory device corresponds to each memory device. They are connected by bus wiring.

  Although the number of memory devices connected to each of the branch locations 207A to 207D is two, it may be three or more.

  In the first embodiment, the main wiring 216 is formed across the inner layer and the surface layer or the back layer of the mother board 200. The branch wirings 206A, 206C, 206E, and 206G are formed across the inner layer and the surface layer of the mother board 200. The branch wirings 206B, 206D, 206F, and 206H are formed across the inner layer and the back layer of the mother board 200.

  The memory devices 302A to 302H are BGA type semiconductor packages. The memory devices 302A, 302C, 302E, and 302G are mounted on the front surface of the motherboard 200, and the memory devices 302B, 302D, 302F, and 302H are mounted on the back surface of the motherboard 200, respectively.

  Here, the effective branch wiring length in the branch wiring 206C (206D) is the wiring length of the branch wiring 206C (206D) and the effective wiring length of the effective wiring 323C (323D) inside the memory device 302C (302D). Is the total wiring length. The effective branch wiring length in the branch wiring 206E (206F) is the wiring length of the branch wiring 206E (206F) and the effective wiring length of the effective wiring 323E (323F) inside the memory device 302E (302F). The total wiring length.

  In the first embodiment, as shown in FIG. 1, two branch points 207B and 207C are electrically connected between two branch points 207B and 207C adjacent to each other among a plurality of branch points 207A to 207D. A resistance element 208B which is a resistance component is provided. The resistance element 208B is a resistance element (chip resistance) having an electrical resistance value higher than that of the main wiring 216 and the branch wirings 206A to 206H (for example, about several mΩ). The resistance element 208 </ b> B is connected in series to the main wiring 216 and is mounted on the front surface or the back surface of the motherboard 200. That is, the resistance element 208B is provided in series with the main wiring 216 between the memory device 302C (302D) and the memory device 302E (302F).

  FIG. 2 is a plan view of the mother board in the vicinity where the resistance element is mounted in the first embodiment of the present invention. FIG. 2 illustrates the case where the resistance element 208B is mounted on the surface (mounting surface) on which the memory devices 302C and 302E are mounted.

  The branch wiring 206C includes a mounting pad 220C that constitutes the other end of the branch wiring 206C, a via 241C, and a wiring pattern 242C. The mounting pad 220C is a conductor pad to which the terminal 322C of the memory device 302C is bonded. The wiring pattern 242C is a conductor pattern that connects the mounting pad 220C and the via 241C. The via 241C is a via conductor connected to the main wiring 216 indicated by a dotted line in a different layer.

  Similarly, the branch wiring 206E includes a mounting pad 220E that constitutes the other end of the branch wiring 206E, a via 241E, and a wiring pattern 242E. The mounting pad 220E is a conductor pad to which the terminal 322E of the memory device 302E is bonded. The wiring pattern 242E is a conductor pattern connected to the mounting pad 220E and the via 241E. The via 241E is a via conductor connected to the main wiring 216 indicated by a dotted line in a different layer.

  In FIG. 2, a plurality (12) of main wirings 216 are shown, and each main wiring 216 is connected to a respective branch wiring.

  In addition, there are branch wirings such as mounting pads and vias in the area 400, and there are also main wirings in the same layer or different layers, but the illustration is omitted. Although not shown, a plurality of receiving terminals 322C and 322E are provided in an array on the bottom surface of the memory devices 302C and 302E. Therefore, the plurality of mounting pads 220C (220E) are arranged in an array. Each mounting pad 220C (220E) is electrically connected to the receiving terminal 322C (322E) of the memory device 302C (302E) by a connection conductor such as a solder ball (not shown).

  One terminal of the pair of terminals of the resistance element 208B is joined to the mounting pad 407-1 constituting the partial wiring 204B1 of the main wiring 216. The other terminal of the pair of terminals of the resistance element 208B is joined to the mounting pad 407-2 constituting the partial wiring 204B2 of the main wiring 216. The two mounting pads 407-1 and 407-2 are connected to the inner layer pattern via the vias 405-1 and 405-2, respectively.

  Although the case where the resistance element 208B is mounted on the front surface (mounting surface) on which the memory devices 302C and 302E are mounted has been described, the case where the resistance element 208B is mounted on the back surface (mounting surface) on which the memory devices 302D and 302F are mounted. Even so, the wiring structure is similar.

  Here, a case where there is no resistance element will be described as a comparative example. FIG. 10 is a topology diagram showing a wiring configuration of a memory system 100X as an example of a printed circuit board of a comparative example. Note that the memory system 100X illustrated in FIG. 10 includes a motherboard 200X. The motherboard 200X has a bus wiring 201X. The bus wiring 201X has a main wiring 216X.

  The main wiring 216X shown in FIG. 10 does not have the resistance element 208B compared to the main wiring 216 shown in FIG. 1, and the other configuration is the same as that of the memory system 100 of the first embodiment. That is, the main wiring 216X has a partial wiring 204B having a total length of the partial wiring 204B1 and the partial wiring 204B2 of the first embodiment, which connects the branch location 207B and the branch location 207C.

  When the frequency of the signal to be applied is increased under the fly-by wiring conditions of this comparative example, a signal increase phenomenon (resonance phenomenon) occurs in a frequency band having a high frequency. In particular, the increase in voltage amplitude of signals received by the memory devices 302C, 302D, 302E, and 302F at the center of the bus wiring 201X having the fly-by wiring structure becomes large.

  FIG. 11 is a waveform diagram of signals received by each memory device in the memory system of the comparative example.

  The simulation conditions are shown below. For the topology of FIG. 10, the voltage of the signal (pulse) transmitted by the memory controller 301 is 1.2 [V], the internal characteristic impedance is 50 [Ω], and a sine wave of only the applied frequency component is applied. The memory devices 302A to 302H approximated the load at 1.7 [pF]. The characteristic impedance of all wirings was 50 [Ω].

  The propagation delay time of the partial wiring 203 was set to 500 [pS]. The propagation delay time of the partial wirings 204A, 204B, and 204C is 120 [pS]. The propagation delay time of the partial wiring 205 is 66 [pS]. The resistance value of the termination resistor 310 was 50 [Ω], and the termination potential applied to the termination wiring 211 was 0.6 [V]. Further, the total wiring length (effective branch wiring length) of the branch wirings 206A to 206H of the motherboard 200 and the effective wiring length inside the memory devices 302A to 302H was set to 180 [pS]. . Here, FIG. 11 illustrates a case where the frequency of the signal transmitted from the memory controller 301 is 1 [GHz]. FIG. 11 illustrates signal waveforms received by the memory devices 302A, 302C, 302E, and 302G mounted on the surface of the motherboard 200X.

  As shown in FIG. 11, it can be confirmed that the signals received by the memory devices 302A, 302C, 302E, and 302G, particularly the memory devices 302C and 302E, are amplified with respect to the applied signal. Although illustration is omitted, the same tendency applies to signals received by the memory devices 302B, 302D, 302F, and 302H.

  As a result of analyzing the phenomenon of FIG. 11 from the transmission characteristics of the bus wiring 201X of the fly-by wiring structure, it was found that a resonance phenomenon depending on the wiring distance between the memory devices occurred.

  FIG. 12A is a schematic diagram illustrating a state in which a signal is transmitted from the memory controller 301 to each of the memory devices 302A, 302C, 302E, and 302G in the memory system 100X of the comparative example.

  The simulation conditions are shown below. In the topology of FIG. 10, a port of 50 [Ω] is set instead of the memory controller 301, and a port of 1000 [Ω] is set instead of the memory devices 302A to 302H. The characteristic impedance of all wirings was 50 [Ω].

  The propagation delay time of the partial wiring 203 was set to 500 [pS]. The propagation delay time of the partial wirings 204A, 204B, and 204C is 120 [pS]. The propagation delay time of the partial wiring 205 is 66 [pS]. The resistance value of the termination resistor 310 was 50 [Ω], and the potential of the termination wiring 211 was 0 [V].

  Further, the total wiring length (effective branch wiring length) of the branch wirings 206A to 206H of the motherboard 200 and the effective wiring length inside the memory devices 302A to 302H was set to 180 [pS]. .

  As shown in FIG. 12A, among the signals transmitted from the memory controller 301, the transmission characteristics of the signals received by the memory devices 302A, 302C, 302E, 302G are respectively S-1, S-2, S-3 and S-4. That is, S-1 is a signal transmission characteristic from the memory controller 301 to the closest memory device 302A. S-2 is a transmission characteristic of a signal from the memory controller 301 to the second closest memory device 302C. S-3 is a signal transmission characteristic from the memory controller 301 to the third closest memory device 302E. S-4 is a transmission characteristic of a signal from the memory controller 301 to the fourth closest memory device 302G.

  FIG. 12B is a graph showing signal transmission characteristics S-1 to S-4 for each frequency from the memory controller to each memory device in the memory system of the comparative example. In FIG. 12B, the horizontal axis represents the frequency and the vertical axis represents the transmission amount.

  It has been found that the transmission characteristics S-2 and S-3 are particularly large in the high frequency band (1 [GHz]) where the signal increase phenomenon occurs. Since a pair of memory devices branched from each branch point are basically the same, only one characteristic was confirmed, and a total of four characteristics were confirmed. As a result of studying this frequency, it has been found that the frequency band has an effective distance between adjacent memory devices on the wiring of λ / 2.

  Here, an effective distance between adjacent memory devices on the wiring will be described. A propagation delay to the memory cell 321 exists inside the memory device 302 due to package wiring and internal capacitance. A value obtained by replacing this propagation delay with the length on the printed wiring board is considered as the effective wiring length of the internal wiring 323. The effective distance between the memory devices is the branch wiring length including the effective internal wiring 323, that is, the total wiring length of the internal wiring 323 and the branch wiring 206, the length of the main wiring, The total of the branch wiring length including the wiring length of the internal wiring 323 is obtained. The branch wiring length including the effective internal wiring 323, i.e., the total wiring length of the internal wiring 323 and the branch wiring 206 varies, and is considered wider considering the difference between memory vendors and generations. There is a need. Therefore, in an actual product, resonance may occur in a wide range near the frequency at which resonance occurs.

  FIG. 13A is a schematic diagram illustrating signal transmission characteristics between the memory devices 302A, 302C, 302E, and 302G in the memory system 100X of the comparative example. The simulation conditions are the same as those in FIG. As shown in FIG. 13A, S-12 is a signal transmission characteristic from the memory device 302A closest to the memory controller 301 to the memory device 302C closest to the second. S-13 is a signal transmission characteristic from the memory device 302A closest to the memory controller 301 to the memory device 302E closest to the third. S-14 is a signal transmission characteristic from the memory device 302A closest to the memory controller 301 to the memory device 302G closest to the fourth. S-23 is a transmission characteristic of a signal from the memory device 302C closest to the memory controller 301 to the memory device 302E closest to the third. S-24 is a signal transmission characteristic from the memory device 302C closest to the memory controller 301 to the memory device 302G closest to the fourth. S-34 is a transmission characteristic of a signal from the third closest memory device 302E to the fourth closest memory device 302G with respect to the memory controller 301.

  FIG. 13B is a graph showing signal transmission characteristics between the memory devices for each frequency in the memory system of the comparative example. In FIG. 13B, the horizontal axis represents the frequency and the vertical axis represents the transmission amount. In the high frequency region (1 [GHz]) where the signal increase phenomenon occurs, the signal transmission characteristic S-23 is the largest. The second closest memory device 302C (memory cell 321C) and the third closest memory device 302E (memory cell 321E) are because signals are likely to increase because signals return from two adjacent memory devices. I think that. For this reason, it is considered that the signal going between the second memory device and the third memory device tends to increase. The same phenomenon occurs in the memory devices 302A and 302D at the ends, but it is relatively small because half of the signal reflection is hardly transmitted back to the memory controller 301 side or the terminal side.

  Therefore, in the first embodiment, the resistance element 208B connected in series to the main wiring 216 is provided between the branch point 207B and the branch point 207C among the four branch points 207A to 207D.

  The resistance element 208B attenuates a signal propagating between the memory device 302C (memory cell 321C) and the memory device 302E (memory cell 321E). Therefore, the frequency depending on the propagation time of the total length of the effective branch line length in the branch line 206C (206D) and the branch line 206E (206F) and the length between the branch point 207B and the branch point 207C of the main line 216. The signal amplification that occurs in can be suppressed. That is, resonance of a signal generated between the memory device 302C (memory cell 321C) and the memory device 302E (memory cell 321E) can be suppressed.

  Next, a description will be given of a result of simulation performed with the configuration of the memory system 100 illustrated in FIG. The simulation conditions are shown below. The voltage of the signal (pulse) transmitted by the memory controller 301 was 1.2 [V], the internal characteristic impedance was 50 [Ω], and a sine wave of only the frequency component to be applied was applied. The memory devices 302A to 302H approximated the load at 1.7 [pF]. The characteristic impedance of all wirings was 50 [Ω].

  The propagation delay time of the partial wiring 203 was set to 500 [pS]. The propagation delay time of the partial wirings 204A and 204C is 120 [pS]. The propagation delay time of the partial wirings 204B1 and 204B2 is set to 60 [pS]. The propagation delay time of the partial wiring 205 is 66 [pS]. The resistance value of the termination resistor 310 was 50 [Ω], and the termination potential applied to the termination wiring 211 was 0.6 [V].

  Further, the total wiring length (effective branch wiring length) of the branch wirings 206A to 206H of the motherboard 200 and the effective wiring length inside the memory devices 302A to 302H was set to 180 [pS]. .

  FIG. 3 is a waveform diagram of signals received by the memory devices 302A, 302C, 302E, and 302G in the memory system 100 of the first embodiment. Here, FIG. 3 illustrates a case where the frequency of the signal transmitted from the memory controller 301 is 1 [GHz]. The electrical resistance value of the resistance element 208B was 5 [Ω].

  As shown in FIG. 3, in comparison with the comparative example of FIG. 11, amplification of signals received by the memory devices 302A, 302C, 302E, and 302G, particularly the memory devices 302C and 302E, is suppressed with respect to the applied signal. It can be confirmed. Although illustration is omitted, the same tendency applies to signals received by the memory devices 302B, 302D, 302F, and 302H.

  Table 1 below shows the results of changing the electrical resistance value of the resistance element 208B from 1 to 10 [Ω] in increments of 1 [Ω] under the above conditions. Note that the data transmission rate of the applied signal was 2 [Gbps] (corresponding to a frequency of 1 [GHz]), and the voltage was a signal for 20 cycles, which was confirmed by the received voltage of all memory devices.

  Under all conditions, that is, when the electric resistance value is 1 [Ω] or more, the effect of lowering the maximum voltage value and raising the minimum voltage value can be confirmed. However, when the electric resistance value of the resistance element 208B is increased, the minimum amplitude of the voltage tends to decrease. If the minimum amplitude of the voltage is reduced, the signal may not be transmitted correctly. It is desirable that the voltage amplitude is secured to ± 100 [mV] or more, and about 20% is required as a noise margin, that is, more effective if considered to be 240 [mV] that is 20% of 1.2 [V]. A typical electric resistance value range is 1 [Ω] or more and 6 [Ω] or less. Therefore, by setting the electric resistance value of the resistance element 208B to a value not less than 1 [Ω] and not more than 6 [Ω], an increase in signal amplitude generated in a certain frequency band (1 [GHz] in the first embodiment), that is, Resonance can be effectively suppressed.

  In the first embodiment, the case where the resistance element 208B is provided between the memory device 302C (302D) and the memory device 302E (302F), that is, between the branch point 207B and the branch point 207C has been described. It is not limited to.

  The first branch point and the second branch point are relative. For example, if the first branch point is the branch point 207A, the second branch point is the branch point 207B. If the first branch point is the branch point 207C, the second branch point is the branch point 207D. That is, a resistance element may be provided between the memory device 302A (302B) and the memory device 302C (302D), that is, between the branch point 207A and the branch point 207B. Further, a resistance element may be provided between the memory device 302E (302F) and the memory device 302G (302H), that is, between the branch point 207C and the branch point 207D.

[Second Embodiment]
Next, a printed circuit board according to a second embodiment of the present invention will be described. FIG. 4 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to the second embodiment of the present invention. Note that in the second embodiment, identical symbols are assigned to configurations similar to those in the first embodiment and descriptions thereof are omitted.

  A memory system 100A according to the second embodiment includes a motherboard 200A that is a printed wiring board, a memory controller 301 that is a transmission circuit, and a plurality (eight in the second embodiment) of memory devices 302A to 302H that are a plurality of reception circuits. And.

  The motherboard 200A has a bus wiring 201A that is a signal line for connecting the memory controller 301 and the memory devices 302A to 302H. The bus wiring 201 </ b> A has a main wiring 216 </ b> A having a start end 217 electrically connected to the transmission terminal 312 of the memory controller 301 and a termination 218 electrically connected to one end of a termination resistor (terminator) 310.

  As with the first embodiment, the main wiring 216A has four branch locations 207A to 207D as a plurality of branch locations at different positions. The main wiring 216A has a partial wiring 203 between the start end 217 and the branching point 207A, and partial wirings 204A1 and 204A2 between the branching point 207A and the branching point 207B. Further, the main wiring 216A has partial wirings 204B1 and 204B2 between the branching points 207B and 207C, and partial wirings 204C1 and 204C2 between the branching points 207C and 207D. Further, the main wiring 216A has a partial wiring 205 between the branch point 207D and the terminal end 218.

  In the second embodiment, among the plurality of branch points 207A to 207D, a resistance element that is a resistance component that electrically connects two branch points 207B and 207C between two branch points 207B and 207C adjacent to each other 208B is provided. Furthermore, in the second embodiment, a termination-side resistance component that electrically connects two branch points 207C and 207D between two branch points 207C and 207D adjacent to each other among the plurality of branch points 207A to 207D. A certain resistance element 208C is provided. Furthermore, in the second embodiment, a start-end-side resistance component that electrically connects two branch points 207A and 207B between two branch points 207A and 207B adjacent to each other among a plurality of branch points 207A to 207D. A certain resistance element 208A is provided. The resistance elements 208A to 208C are resistance elements (chip resistance) having an electrical resistance value higher than the electrical resistance values (for example, about several mΩ) of the main wiring 216A and the branch wirings 206A to 206H. The resistance elements 208A to 208C are connected in series to the main wiring 216A and are mounted on the front surface or the back surface of the motherboard 200A. The electrical resistance value of each of the resistance elements 208A to 208C is 1 [Ω] or more and 6 [Ω] or less, as in the first embodiment.

  Thus, in the second embodiment, as in the first embodiment, the resistance element 208B is connected between the partial wiring 204B1 and the partial wiring 204B2. Furthermore, in the second embodiment, the resistance element 208A is connected between the partial wiring 204A1 and the partial wiring 204A2, and the resistance element 208C is connected between the partial wiring 204C1 and the partial wiring 204C2. Other configurations are the same as those in the first embodiment.

  According to the second embodiment, as in the first embodiment, a certain frequency band (for example, 1 [GHz]) generated between the memory device 302C (302D) and the memory device 302E (302F) by the resistance element 208B. The resonance of the signal can be effectively suppressed. Further, according to the second embodiment, resonance of a signal in a certain frequency band (for example, 1 [GHz]) generated between the memory device 302A (302B) and the memory device 302C (302D) is caused by the resistance element 208A. It can be effectively suppressed. Furthermore, according to the second embodiment, resonance of a signal in a certain frequency band (for example, 1 [GHz]) generated between the memory device 302E (302F) and the memory device 302G (302H) is caused by the resistance element 208C. It can be effectively suppressed.

  In the second embodiment, the case where the memory system 100A includes the resistance elements 208A to 208C has been described. However, the present invention is not limited to this. For example, any one of the resistance elements 208A to 208C may be omitted.

[Third Embodiment]
Next, a printed circuit board according to a third embodiment of the invention will be described. FIG. 5 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to the third embodiment of the present invention. Note that in the third embodiment, identical symbols are assigned to configurations similar to those in the other embodiments and descriptions thereof are omitted.

  A memory system 100B according to the third embodiment includes a mother board 200B that is a printed wiring board, a memory controller 301, and a plurality of (four in the third embodiment) memory devices 302A, 302C, 302E, and 302G. .

  The motherboard 200B has a bus wiring 201B that is a signal line that connects the memory controller 301 and the memory devices 302A, 302C, 302E, and 302G.

  Similar to the second embodiment, the bus wiring 201B includes a main wiring 216A having four branch points 207A to 207D. In addition, the bus wiring 201B includes four branch wirings 206A, 206C, 206E, and 206G that branch from the branch locations 207A to 207D, respectively, in a smaller number than in the second embodiment. That is, one branch wiring is branched from each of the branch locations 207A to 207D.

  In the third embodiment, the memory devices 302A, 302C, 302E, and 302G are mounted on one mounting surface of the pair of mounting surfaces of the motherboard 200B. That is, in the third embodiment, the memory device on one side and its branch wiring are eliminated from the memory system 100A shown in FIG.

  In the third embodiment, as in the first and second embodiments, among the plurality of branch locations 207A to 207D, two branch locations 207B and 207C are electrically connected between two adjacent branch locations 207B and 207C. There is provided a resistance element 208B connected to the. Furthermore, in the third embodiment, as in the second embodiment, among the plurality of branch points 207A to 207D, two branch points 207C and 207D are electrically connected between two branch points 207C and 207D adjacent to each other. A resistance element 208C is provided. Furthermore, in the third embodiment, as in the second embodiment, among the plurality of branch points 207A to 207D, two branch points 207A and 207B are electrically connected between two branch points 207A and 207B adjacent to each other. A resistance element 208A is provided.

  Resonance due to the spacing of the memory devices occurs in the same way even in the single-sided mounting form. Therefore, similarly to the second embodiment, resonance of signals between the memory devices 302A and 302C, between the memory devices 302C and 302E, and between the memory devices 302E and 302G can be suppressed.

  Of the resistance elements 208A to 208C, two resistance elements may be omitted, or one resistance element may be omitted.

[Fourth Embodiment]
Next, a printed circuit board according to a fourth embodiment of the invention will be described. FIG. 6 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to the fourth embodiment of the present invention. Note that in the fourth embodiment, identical symbols are assigned to configurations similar to those in the other embodiments and descriptions thereof are omitted.

  The memory system 100C of the fourth embodiment is obtained by omitting the memory devices 302A and 302B and the branch wirings 206A and 206B from the memory system 100A of FIG.

  That is, the memory system 100C includes a motherboard 200C and six memory devices 302C to 302H. The motherboard 200C has a bus wiring 201C that is a signal line. The bus wiring 201C includes a main wiring 216C and branch wirings 206C to 206H that branch from the branch locations 207B, 207C, and 207D of the main wiring 216C.

  A resistance element 208B is provided between the branch location 207B and the branch location 207C, and a resistance element 208C is provided between the branch location 207C and the branch location 207D. Resonance due to the interval between the memory devices occurs in this form as well, and therefore, the presence of the resistance elements 208B and 208C has a resonance suppression effect. Note that either one of the resistance elements 208B and 208C may be omitted.

[Fifth Embodiment]
Next, a printed circuit board according to a fifth embodiment of the invention will be described. FIG. 7 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to the fifth embodiment of the present invention. Note that in the fifth embodiment, identical symbols are assigned to configurations similar to those in the other embodiments and descriptions thereof are omitted.

  The memory system 100D of the fifth embodiment is obtained by omitting the memory device 302A and its branch wiring 206A from the memory system 100B of FIG. That is, the memory devices 302D, 302F, and 302H and their branch wirings 206D, 206F, and 206H are omitted from the memory system 100C of FIG.

  The memory system 100D includes a motherboard 200D and three memory devices 302C, 302E, and 302G. The motherboard 200D has a bus wiring 201D that is a signal line. The bus wiring 201D includes a main wiring 216C similar to that of the fourth embodiment and branch wirings 206C, 206E, and 206G that branch from the branch locations 207B, 207C, and 207D of the main wiring 216C.

  A resistance element 208B is provided between the branch location 207B and the branch location 207C, and a resistance element 208C is provided between the branch location 207C and the branch location 207D. Resonance due to the interval between the memory devices occurs in this form as well, and therefore, the presence of the resistance elements 208B and 208C has a resonance suppression effect. Note that either one of the resistance elements 208B and 208C may be omitted.

[Sixth Embodiment]
Next, a printed circuit board according to a sixth embodiment of the invention will be described. FIG. 8 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to the sixth embodiment of the present invention. Note that in the sixth embodiment, identical symbols are assigned to configurations similar to those in the other embodiments and descriptions thereof are omitted.

  The memory system 100E of the sixth embodiment is obtained by omitting the memory devices 302G and 302H and their branch wirings 206G and 206H from the memory system 100C shown in FIG.

  That is, the memory system 100E includes a motherboard 200E and four memory devices 302C to 302F. The motherboard 200E has a bus wiring 201E that is a signal line. The bus line 201E includes a main line 216E and branch lines 206C to 206F that branch from the branch points 207B and 207C of the main line 216E.

  A resistance element 208B is provided between the branch point 207B and the branch point 207C. Resonance due to the interval between the memory devices is generated in this form as well, and the presence of the resistance element 208B has a resonance suppression effect.

[Seventh Embodiment]
Next, a printed circuit board according to a seventh embodiment of the invention will be described. FIG. 9 is a topology diagram showing a wiring configuration of a memory system as an example of a printed circuit board according to the seventh embodiment of the present invention. Note that in the seventh embodiment, identical symbols are assigned to configurations similar to those in the other embodiments and descriptions thereof are omitted.

  The memory system 100F of the seventh embodiment is obtained by omitting the memory device 302G and its branch wiring 206G from the memory system 100D of FIG. That is, the memory devices 302D and 302F and their branch wirings 206D and 206F are omitted from the memory system 100E of FIG.

  The memory system 100F includes a motherboard 200F and two memory devices 302C and 302E. The motherboard 200F has a bus wiring 201F that is a signal line. The bus wiring 201F includes a main wiring 216E similar to that of the sixth embodiment, and branch wirings 206C and 206E that branch from the branch locations 207B and 207C of the main wiring 216E.

  A resistance element 208B is provided between the branch point 207B and the branch point 207C. Resonance due to the interval between the memory devices is generated in this form as well, and the presence of the resistance element 208B has a resonance suppression effect.

  The present invention is not limited to the embodiment described above, and many modifications are possible within the technical idea of the present invention. In addition, the effects described in the embodiments of the present invention only list the most preferable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments of the present invention.

  In the above embodiment, the case where the signal transmitted through the bus wiring is the address / command signal has been described. However, the present invention is not limited to this and may be a differential signal such as a CLK signal.

  In the above-described embodiment, the case where the printed circuit board is a memory system and the printed wiring board is a motherboard on which the memory device and the memory controller are mounted has been described. However, the present invention is not limited to this. The printed circuit board may be a memory module (DIMM) composed of a module board as a printed wiring board and a memory device mounted on the module board. In this case, the memory controller is mounted on the motherboard, and the memory controller and the memory device are electrically connected by connecting the memory module to the motherboard with a connector or the like.

  Moreover, although the said embodiment demonstrated the case where a resistance component, a starting point side resistance component, and a termination side resistance component were resistance elements, it is not limited to this, The conductor pattern which narrowed the wiring width with respect to the main wiring For example, the electrical resistance value may be increased.

DESCRIPTION OF SYMBOLS 100 ... Memory system (printed circuit board), 200 ... Mother board (printed wiring board), 201 ... Bus wiring (signal wiring), 206A-206H ... Branch wiring, 207A ... Branch location (start side branch location), 207B ... Branch location (First branch point), 207C... Branch point (second branch point), 207D... Branch point (termination side branch point), 208B... Resistance element (resistance component), 216. ), 302A to 302H... Memory device (receiving circuit)

Claims (13)

A printed wiring board on which signal lines are formed;
A plurality of receiving circuits mounted on the printed wiring board and receiving signals transmitted from the transmitting circuit via the signal lines of the printed wiring board;
The signal line includes a main wiring having a starting end connected to the transmission circuit, a plurality of branch wirings branched from a plurality of different branch locations of the main wiring and respectively connected to the plurality of receiving circuits, Have
Among the plurality of branch locations, the main wiring is between a first branch location and a second branch location adjacent to the first branch location and farther from the start end than the first branch location. A printed circuit board comprising a resistance component having an electrical resistance value higher than the electrical resistance value of the main wiring connected in series.   The printed circuit board according to claim 1, wherein the resistance component is a resistance element mounted on the printed wiring board.   The printed circuit board according to claim 1, wherein an electrical resistance value of the resistance component is 1 [Ω] or more and 6 [Ω] or less.   Among the plurality of branch points, the main branch point is between the second branch point and a terminal-side branch point adjacent to the second branch point and farther from the start end than the second branch point. 4. The terminal-side resistance component having an electrical resistance value higher than the electrical resistance value of the main wiring, which is connected in series with the wiring, is provided. 5. Printed circuit board.   The printed circuit board according to claim 4, wherein the termination resistance component is a resistance element mounted on the printed wiring board.   6. The printed circuit board according to claim 4, wherein an electrical resistance value of the terminating resistance component is 1 [Ω] or more and 6 [Ω] or less.   Among the plurality of branch points, the main branch point is between the first branch point and a start end side branch point adjacent to the first branch point and closer to the start end than the first branch point. The start end side resistance component having an electrical resistance value higher than the electrical resistance value of the main wiring, which is connected in series with the wiring, is provided. Printed circuit board.   The printed circuit board according to claim 7, wherein the start-side resistance component is a resistance element mounted on the printed wiring board.   9. The printed circuit board according to claim 7, wherein an electric resistance value of the starting end side resistance component is 1 [Ω] or more and 6 [Ω] or less.   10. The printed circuit board according to claim 1, wherein the number of the branch wiring branches from each branch point is one or two. 11.   The printed circuit board according to claim 1, wherein the transmission circuit is mounted on the printed wiring board and connected to the starting end. The transmission circuit is a memory controller;
The printed circuit board according to claim 1, wherein the receiving circuit is a memory device controlled by the memory controller.   The printed circuit board according to claim 12, wherein the memory device is a DDR3-SDRAM or a DDR4-SDRAM.

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