JP2017037321A - Image processing apparatus, control method of the same, and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device which is capable of acquiring auxiliary data of a plurality of input terminals with one CPU and has a simpler configuration than before, and to provide a control method of the image display device.SOLUTION: An image processing apparatus includes an acquisition means having input means of any one of a plurality of input means for a synchronous processing object and input means of other input means for an asynchronous processing object, for acquiring auxiliary data from storage means corresponding to the input means for the synchronous processing object at a predetermined cycle, and performing acquisition processing for acquiring the auxiliary data from the storage means corresponding to at least one input means of the input means for the asynchronous processing object in synchronization with acquisition of the auxiliary data from the storage means corresponding to the input means for the synchronous processing object.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an image processing apparatus, a control method therefor, and an image display apparatus.

  A technique is known in which data different from the pixel value of an image is superimposed during the blanking period of the image signal and transmitted simultaneously with the image signal. For example, there is an SDI (Serial Digital Interface) signal defined by the SMPTE (the Society of Motion Picture and Television Engineers). In the SMPTE ST 291: 2010 standard, a method for superimposing and transmitting Ancillary Data (auxiliary data) in the horizontal and vertical blanking periods of an SDI signal is defined. Various types of auxiliary data are defined. For example, the Time Code defined by SMPTE 12M-2-2008 and the Video Payload Identification Code (hereinafter abbreviated as Payload) defined by SMPTE ST 352: 2010 are known.

  Time Code is data of “hour”, “minute”, “second”, and “frame number” at the time of shooting each frame of the image signal (may be each field in the case of interlace). Used for time alignment. Time Code is displayed as a character string in a format such as “01: 23: 45: 01”. Since the Time Code is data including a “frame number”, it normally changes for each frame (in some cases, for interlace, for each field). Payload is data representing a color format (such as 4: 2: 2 Y / Cb / Cr) and a frame rate (such as 24 / 1.001 Hz) of an image signal, and is used for image processing control of the image processing apparatus. Payload is data that changes simultaneously when the format of the image signal changes, and is usually not data that changes frequently. In SMPTE ST 352: 2010, the color format is expressed as “sampling structure”. Further, the frame rate is expressed as “picture rate”.

  The auxiliary data is started from special pixel values 000h, 3FFh, 3FFh (hexadecimal number, Ancillary Data Flag) as defined in SMPTE ST 291: 2010. Therefore, it is possible to acquire auxiliary data by means comprising hardware that detects the pixel value and records subsequent auxiliary data in the memory and a CPU that reads and processes the data from the hardware memory. . For example, Patent Document 1 discloses a method of acquiring data superimposed on an analog video signal, and the same idea can be applied to a digital SDI. Since the Time Code is data that changes for each frame (may be for each field in the case of interlace), the acquisition processing by the hardware and CPU described above is also performed for each frame (may be for each field in the case of interlace). Need to be done.

In recent years, image processing apparatuses that handle high-definition image signals such as so-called 4K × 2K have been put into practical use. In such an image processing apparatus, in order to input an image signal having a number of pixels that greatly exceeds the conventional number of pixels, an image signal may be input using a plurality of image input interfaces simultaneously in parallel. In such an image processing apparatus, for example, an image signal is input using four or eight SDI input means terminals. In an image processing apparatus having a plurality of image input terminals, an operation of inputting an image signal of the same format to each input terminal and an operation of inputting an image signal of a different format can be considered. When the format is different for each input terminal, the frame rate of the image signal and the frame switching timing are also different for each terminal. When the above-described auxiliary data acquisition is performed under conditions of different formats, it is necessary to perform acquisition processing by hardware and CPU for each terminal for each frame. Moreover, the processing timing for each frame differs for each terminal.

  Therefore, conventionally, in order to acquire auxiliary data from a plurality of input terminals having different formats, it has been common to have a plurality of hardware and CPUs according to the number of input terminals. In addition, all processes related to auxiliary data are implemented as hardware, and a plurality of hardware may be provided according to the number of input terminals. For example, as processing related to Time Code, there is processing for taking out Time Code from an SDI signal, analyzing it, converting it into character string data, converting it into an image using font data, and superimposing the image on the image signal. A series of these processes was implemented as hardware.

JP-A-9-289628

  However, in the above-described conventional technology, it is necessary to provide a plurality of hardware and CPUs according to the number of input terminals, which leads to complication of the image processing apparatus. Therefore, an object of the present invention is to provide an image processing apparatus having a simpler configuration than the conventional one and a control method thereof by making it possible to acquire auxiliary data of a plurality of input terminals with a single CPU.

The present invention includes a plurality of input means for inputting image signals independently,
A plurality of storage means that are provided for each of the input means and store the auxiliary data when an image signal on which the auxiliary data is superimposed is input;
One of the plurality of input means is set as an input means for synchronous processing, and the other input means is set as an input means for asynchronous processing, and is assisted at a predetermined cycle from a storage means corresponding to the input means for synchronous processing. Acquires auxiliary data from storage means corresponding to at least one of the input means for asynchronous processing in synchronization with acquisition of auxiliary data from the storage means corresponding to the input means targeted for synchronous processing. An image processing apparatus comprising: an acquisition unit that performs an acquisition process.

The present invention includes a plurality of input means for inputting image signals independently,
A method for controlling an image processing apparatus, comprising: a plurality of storage units that are provided for each input unit and store auxiliary data when an image signal on which auxiliary data is superimposed is input;
One of the plurality of input means is set as an input means for synchronous processing, and the other input means is set as an input means for asynchronous processing, and is assisted at a predetermined cycle from a storage means corresponding to the input means for synchronous processing. Acquires auxiliary data from storage means corresponding to at least one of the input means for asynchronous processing in synchronization with acquisition of auxiliary data from the storage means corresponding to the input means targeted for synchronous processing. And a step of performing an acquisition process for acquiring the image processing apparatus.

  Even if there are a plurality of input terminals, a single CPU can acquire auxiliary data of a plurality of input terminals, whereby the image processing apparatus can have a simpler configuration than the conventional one.

The figure which shows the structure of the image display apparatus which concerns on an Example. The figure which shows the control by CPU, the SDI input means, and the process by an SDI receiver The flowchart which shows the process of CPU which concerns on Example 1. FIG. Flowchart showing processing of CPU according to embodiment 3

Example 1
In the present embodiment, an example in which the present invention is applied to an image display apparatus having four SDI input means as image input means will be described. The image display apparatus according to the present embodiment selects one time code (time code) from four SDI input units as a time code acquisition target, and acquires the time code from the selected SDI input unit. The image display apparatus according to the present embodiment obtains the payload from all four SDI input means. In this embodiment, an application example of the present invention to an image processing apparatus that constitutes a part of an image display apparatus will be described. However, in the present invention, it is not essential to have a display function, and an image that does not have a display function. The present invention can also be applied to a processing apparatus.

  The configuration of the image display apparatus in this embodiment will be described. FIG. 1 is a diagram illustrating a configuration of an image display apparatus according to the present embodiment. The image display apparatus has SDI input means 101, SDI input means 102, SDI input means 103, and SDI input means 104 as four SDI input means. The image display apparatus includes an SDI receiver 1, an SDI receiver 2, an SDI receiver 3, and an SDI receiver 4 as four SDI receivers. The SDI receiver 1 includes an internal processing unit 121, a detection unit 131, and a FIFO 141 therein. The SDI receiver 2 includes an internal processing unit 122, a detection unit 132, and a FIFO 142 therein. The SDI receiver 3 includes an internal processing unit 123, a detection unit 133, and a FIFO 143 therein. The SDI receiver 4 includes an internal processing unit 124, a detection unit 134, and a FIFO 144 therein.

  The internal configurations of the SDI receiver 2, the SDI receiver 3, and the SDI receiver 4 are not shown in FIG. In the image display apparatus, the image signal 151, the image signal 152, the image signal 153, and the image signal 154 output from each SDI receiver are transmitted through four image signal paths. The image display device further includes a selector 161, a CPU 162, an image processing unit 163, a video combining unit 164, an enlargement / reduction unit 165, a video graphics composition unit 166, a graphics generation unit 167, and a liquid crystal panel 168. The image display device includes a time code storage unit 169, a payload storage unit 111, a payload storage unit 112, a payload storage unit 113, and a payload storage unit 114.

  Each element constituting the image display device will be described. The SDI input means 101 to 104 are means for inputting SDI signals, and are connected to the SDI receivers 1 to 4, respectively. The SDI receivers 1 to 4 receive the SDI signal and convert the SDI signal into image signals 151 to 154 of another format such as an LVTTL (Low Voltage Transistor-Transistor Logic) level signal. Further, the SDI receivers 1 to 4 extract auxiliary data from the SDI signal. The internal processing unit 121 performs processing including NRZI (Non Return to Zero) conversion defined in the SMPTE 292-2008 standard or the like, but a detailed description thereof is omitted.

The detection unit 131 detects auxiliary data from the image signal output by the internal processing unit 121 according to a format defined in SMPTE ST 291: 2010, and writes the detected data in the FIFO 141. The FIFO 141 stores auxiliary data written by the detection unit 131. The selector 161 selects one image signal from the image signals 151 to 154 and outputs it as a reference signal (interrupt source) that causes the CPU 162 to generate an interrupt. The CPU 162 executes various controls according to the present embodiment implemented as software. C
The PU 162 reads auxiliary data from the FIFOs 141 to 144. Further, the CPU 162 can use the image signal selected by the selector 161 as an interrupt source and control the operation timing according to the change of the image signal selected by the selector 161.

  The image processing unit 163 performs image signal processing such as color space conversion on the image signals 151 to 154 under the control of the CPU 162. The video combining unit 164 combines four image signals into one system. The enlargement / reduction unit 165 performs enlargement or reduction processing on the image signal. The video graphics synthesis unit 166 synthesizes the image signal output from the enlargement / reduction unit 165 and the graphics signal output from the graphics generation unit 167. The graphics generation unit 167 generates a graphics signal under the control of the CPU 162. The liquid crystal panel 168 is a display device that displays an image signal output from the video graphics combining unit.

  The time code storage unit 169 is a memory for storing the time code acquired by the CPU 162. The payload storage unit 111 is a memory for storing the payload acquired from the SDI receiver 1 by the CPU 162. The Payload storage unit 112 is a memory for storing the Payload acquired by the CPU 162 from the SDI receiver 2. The Payload storage unit 113 is a memory for storing the Payload acquired by the CPU 162 from the SDI receiver 3. The payload storage unit 114 is a memory for storing the payload acquired from the SDI receiver 4 by the CPU 162.

  As described above, the image display apparatus according to the present embodiment selects one of the SDI input units 101 to 104 for the time code, and acquires the time code from the selected SDI input unit. As a selection method, for example, there is a method in which a user interface for selection by the operator is provided, and the Time Code is acquired from the SDI input means selected by the operator. Hereinafter, a case where the SDI input unit 101 is selected as a time code acquisition target will be described as an example.

  The control by the CPU 162 in the present embodiment will be described including the SDI signal input from the SDI input means 101 to 104 and the temporal relationship with the processing by the SDI receivers 1 to 4. FIG. 2 is a diagram showing the control by the CPU 162, the SDI signals input from the SDI input means 101 to 104, the processing by the SDI receivers 1 to 4, and their time relations.

The SDI input means 101 to 104 will be described with reference to FIG.
The SDI input means 101 is one of SDI input means for inputting an SDI signal to the image display device. The SDI signal is roughly divided into a vertical blanking period and a vertical effective image period. Here, the vertical blanking period is a period composed of lines that do not include effective pixels in one line period. The vertical effective image period is a period that is not a vertical blanking period among all image periods. Furthermore, Time Code and Payload are included in the vertical blanking period. For simplification of the drawing, FIG. 2 represents Time Code as TC and Payload as PL.

  The insertion timing of Time Code and Payload is defined in detail in SMPTE 12M-2-2008 and SMPTE ST 352: 2010. In the present embodiment, an example will be described in which the insertion timing of Time Code and Payload is included in the vertical blanking period. The period from the start of the vertical blanking period to the end of the vertical effective image period is one frame period in the case of a progressive image, and one field period in the case of an interlaced or progressive segmented frame signal.

  The SDI input means 102 is one of SDI input means for inputting an SDI signal to the image display device. Compared to the SDI signal input from the SDI input means 101, the length of one frame period (in the case of an interlaced signal, one field period; the same applies hereinafter) is the same, but the start position of one frame period (one field period) is Different.

  The SDI input means 103 is one of SDI input means for inputting an SDI signal to the image display device. Compared to the SDI signal input from the SDI input means 101, the length of one frame period (one field period) is different.

  The SDI input means 104 is one of SDI input means for inputting an SDI signal to the image display device. Compared to the SDI signal input from the SDI input means 101, the length of one frame period (one field period) is different. Further, the SDI signal input from the SDI input unit 104 is equal in length to one frame period (one field period) compared to the SDI signal input from the SDI input unit 103, but one frame period (one field). The start position of (period) is different.

  The format of the SDI signal input from the SDI input means 101 to 104 shown in FIG. 2 described above is an example for explanation, and the present invention is also applied to an image display device to which an image signal different from the above format is input. The invention is applicable.

The processing of the SDI receivers 1 to 4 will be described with reference to FIG.
Processing of the SDI receiver 1 will be described. When the time code is transmitted to the SDI input unit 101, the detection unit 131 of the SDI receiver 1 detects the time code and writes it in the FIFO 141. As the detection method, the time code DID is 60h (hexadecimal number) and the SDID is 60h (hexadecimal number) (refer to SMPTE 12M-2-2008 for details). To do. Here, DID is Data Identifier, and SDID is Secondary Data Identifier.

  When Payload is transmitted to the SDI input unit 101, the detection unit 131 of the SDI receiver 1 detects Payload and writes it to the FIFO 141. As a detection method, Payload DID is 41h (hexadecimal number) and SDID is 01h (hexadecimal number) (for details, refer to SMPTE ST 352: 2010). Payload is detected by finding the value.

  Processing of the SDI receiver 2 will be described. When Payload is transmitted to the SDI input unit 102, the detection unit 132 of the SDI receiver 2 detects the Payload and writes it into the FIFO 142. The detection method is the same as the processing of the SDI receiver 1. Since the SDI input unit 102 is not selected as the acquisition target of Time Code (is an asynchronous processing target), the processing of the SDI receiver 2 does not include processing for acquiring Time Code.

  Processing of the SDI receiver 3 will be described. Similar to the SDI receiver 2, the SDI receiver 3 acquires Payload and does not acquire Time Code.

  Processing of the SDI receiver 4 will be described. Similar to the SDI receiver 2, the SDI receiver 4 acquires Payload and does not acquire Time Code.

As described above, the operator selects one from the SDI input units 101 to 104 as a time code acquisition target (synchronization processing target). A method for controlling the operations of the SDI receivers 1 to 4 according to the operator's selection will be described. As stipulated in detail in SMPTE ST 291: 2010, auxiliary data including Time Code and Payload can be identified by DID and SDID. Therefore, the image display apparatus sets the SDI receiver 1 to take in auxiliary data having DID and SDID indicating Time Code and Payload. The image display apparatus sets the SDI receivers 2 to 4 to take in auxiliary data having a DID and SDID indicating Payload. With the above settings, the SDI receiver 1 can acquire Time Code and Payload, and the SDI receivers 2 to 4 can acquire Payload.

The processing of the CPU 162 will be described.
The CPU 162 sets the selector 161 in accordance with the SDI input means selected as the time code acquisition target by the operator, and selects the interrupt source of the CPU 162 from the image signals 151-154. In the present embodiment, since the operator selects the SDI input unit 101 as the time code acquisition target, the CPU 162 selects the image signal 151 of the SDI input unit 101 as an interrupt source.

  More specifically, the CPU 162 generates an interrupt when the image signal 151 transits from the vertical blanking period to the vertical effective image period. For example, the CPU 162 generates an interrupt when the value of the V bit of SAV (Start of Active Video) and EAV (End of Active Video) included in the image signal 151 changes from 1 to 0. This is because the value of the V bit is 1 when the image signal 151 is in the vertical blanking period and 0 when the image signal 151 is in the vertical effective image period (for details, refer to SMPTE 292-2008).

  The generation timing of the interrupt depends on the image signal 151. In FIG. 2, the interrupt is generated when the SDI signal input from the SDI input means 101 transitions from the vertical blanking period to the vertical effective image period. It is described. The delay amount between the SDI signal input from the SDI input means 101 and the image signal 151 is small. Therefore, the timing of transition from the vertical blanking period to the vertical effective image period can be regarded as almost the same between the SDI signal input from the SDI input unit 101 and the image signal 151. Therefore, for simplification of the drawing, only the SDI signal input from the SDI input means 101 is shown in FIG. 2, and the image signal 151 is not shown.

The processing of the CPU 162 will be described in the order of passage of time with reference to FIG.
A period 207 (a period including the periods 201 to 206) will be described. The CPU 162 starts processing when the SDI signal input from the SDI input unit 101 transits from the vertical blanking period to the vertical effective image period due to the interruption described above. The CPU 162 reads the time code from the FIFO 141 of the SDI receiver 1 (period 201). The CPU 162 reads Payload from the FIFO 141 of the SDI receiver 1 (period 202). The CPU 162 reads Payload from the FIFO 142 of the SDI receiver 2 (period 203).

Subsequently, the CPU 162 reads the time read from the FIFO 141 of the SDI receiver 1.
Code is analyzed (period 204). Specifically, the CPU 162 performs analysis according to the time code format defined in SMPTE 12M-2-2008. The CPU 162 analyzes the Payload read from the FIFO 141 of the SDI receiver 1 (period 205). Specifically, the CPU 162 performs analysis according to the Payload format defined in SMPTE ST 291: 2010. The CPU 162 analyzes the Payload read from the FIFO 142 of the SDI receiver 2 (period 206).

  A period 217 (a period in which the periods 211 to 216 are combined) will be described. The period 211, the period 212, the period 214, and the period 215 are the same as the period 201, the period 202, the period 204, and the period 205. The CPU 162 reads Payload from the FIFO 143 of the SDI receiver 3 (period 213). The CPU 162 analyzes the payload read from the FIFO 143 of the SDI receiver 3 (period 216).

  The period 227 (a period combining the periods 221 to 226) will be described. The period 221, the period 222, the period 224, and the period 225 are the same as the period 201, the period 202, the period 204, and the period 205. The CPU 162 reads Payload from the FIFO 144 of the SDI receiver 4 (period 223). The CPU 162 analyzes the payload loaded from the FIFO 144 of the SDI receiver 4 (period 226).

  In the period 207 (periods 201 to 206), the CPU 162 acquires auxiliary data from the SDI signal input from the SDI input unit 101 and the SDI signal input from the SDI input unit 102. In the period 217 (periods 211 to 216), the CPU 162 acquires auxiliary data from the SDI signal input from the SDI input unit 101 and the SDI signal input from the SDI input unit 103. In the period 227 (periods 221 to 226), the CPU 162 acquires auxiliary data from the SDI signal input from the SDI input unit 101 and the SDI signal input from the SDI input unit 104. Thereafter, the CPU 162 repeats the processes for the three periods 207, 217, and 227 described above.

  Therefore, the CPU 162 acquires the time code and the payload from the SDI input unit 101 selected as the time code acquisition target once every frame period (one field period). Further, the CPU 162 acquires Payload from the SDI input means 102 to 104 not selected as the Time Code acquisition target once every three frame periods (three field periods). In other words, for each frame period (one field period), the CPU 162 sequentially selects one of the three SDI input units 102 to 104 that are not selected as the Time Code acquisition target, and acquires Payload. That is, the CPU 162 repeats the above processing with a period of three frame periods (three field periods). That is, the acquisition of auxiliary data from the SDI input unit 101 that is the target of Time Code acquisition and the acquisition of auxiliary data from any of the SDI input units 102 to 104 synchronized therewith are regarded as one (one unit) acquisition process. Then, the auxiliary data is acquired from all the asynchronous processing target SDI input means by the predetermined number of acquisition processes (three times in the present embodiment).

  The processing (acquisition processing) of the CPU 162 in the periods 201 to 206, the periods 211 to 216, and the periods 221 to 226 will be described in detail with reference to flowcharts. FIG. 3 is a flowchart showing the processing of the CPU 162. The processing of steps S301 to S314 represents acquisition processing performed in each of the period 207 (period 201 to 206), the period 217 (period 211 to 216), and the period 227 (period 221 to 226). Hereinafter, each step will be described in detail.

  Step S301: The CPU 162 substitutes 2 for N. N is a variable that represents the number of an SDI receiver that is a PL acquisition target among the three SDI receivers other than the SDI receiver 1. In this embodiment, N = 2, 3, and 4. As described above, in this embodiment, for each unit of acquisition processing in the above processing that repeats three frame periods (three field periods) as a cycle, the SDI receiver N that is a PL acquisition target other than the SDI receiver 1 is: It is switched in the order of N = 2, 3, and 4.

  Step S302: The CPU 162 waits until the SDI signal input from the SDI input means 101 transits from the vertical blanking period to the vertical effective image period and an interrupt is generated in the CPU 162.

  Step S303: When an interrupt occurs, the CPU 162 reads the time code from the FIFO 141 of the SDI receiver 1. Step S303 corresponds to the processing in the period 201, the period 211, and the period 221 in FIG.

  Step S304: The CPU 162 reads Payload from the FIFO 141 of the SDI receiver 1. Step S304 corresponds to the processing in the period 202, the period 212, and the period 222 in FIG.

  Step S305: The CPU 162 reads Payload from the FIFO of the SDI receiver N. More specifically, when N is 2, the CPU 162 reads Payload from the FIFO 142 of the SDI receiver 2. When N is 3, the CPU 162 reads Payload from the FIFO 143 of the SDI receiver 3. When N is 4, the CPU 162 reads the payload from the FIFO 144 of the SDI receiver 4. Step S305 corresponds to the processing in the period 203, the period 213, and the period 223 in FIG.

  Step S306: The CPU 162 analyzes the time code read from the FIFO 141 of the SDI receiver 1. Step S306 corresponds to the processing in the period 204, the period 214, and the period 224 in FIG.

  Step S307: The CPU 162 writes the time code of the SDI receiver 1 analyzed in step S306 to the time code storage unit 169, and updates the time code data of the SDI receiver 1 stored therein. This data is used when the image display device displays Time Code as graphics.

  Step S308: The CPU 162 analyzes the payload read from the FIFO 141 of the SDI receiver 1. Step S308 corresponds to the processing in the period 205, the period 215, and the period 225 in FIG.

  Step S309: The CPU 162 writes the Payload of the SDI receiver 1 analyzed in Step S308 to the Payload storage unit 111, and updates the Payload data of the SDI receiver 1 stored therein. This data is used when the image display apparatus controls image processing based on Payload.

  Step S310: The CPU 162 analyzes the Payload read from the FIFO of the SDI receiver N. More specifically, when N is 2, the CPU 162 analyzes the Payload read from the FIFO 142 of the SDI receiver 2. When N is 3, the CPU 162 analyzes the Payload read from the FIFO 143 of the SDI receiver 3. When N is 4, the CPU 162 analyzes the Payload read from the FIFO 144 of the SDI receiver 4. Step S310 corresponds to the processing in the period 206, the period 216, and the period 226 in FIG.

Step S311: The CPU 162 confirms whether the Payload of the SDI receiver N analyzed in Step S310 is valid (normal). The payload of the SDI receiver N may be read at the timing when the payload is transmitted to the SDI input means 102 to 104 or during the transmission. In that case, Payload may be invalid (abnormal) data. Therefore, here, it is confirmed whether Payload is valid.

  As a specific method of confirmation, as specified in SMPTE ST 252: 2010, there is a method of checking the consistency between DC and Checksum because Payload includes DC (Data Count, number of data) and Checksum. . When Payload is valid, the CPU 162 proceeds to step S312. When Payload is invalid, the CPU 162 proceeds to step S313.

  Step S312: The CPU 162 writes the Payload of the SDI receiver N analyzed in Step S310 to the storage unit corresponding to the SDI receiver N among the Payload storage units 112 to 114. More specifically, when N is 2, the CPU 162 writes the payload of the SDI receiver 2 in the payload storage unit 112. When N is 3, the CPU 162 writes the payload of the SDI receiver 3 to the payload storage unit 113. When N is 4, the CPU 162 writes the payload of the SDI receiver 4 in the payload storage unit 114. This data is used when the image display apparatus controls image processing based on Payload.

  When Payload is invalid, Step S312 is not executed, and Payload data of the SDI receiver N stored in the Payload storage units 112 to 114 is not updated. In this case, the payload data previously acquired and stored in the payload storage unit is continuously used for image processing control described later.

  Step S313: The CPU 162 increments N by one.

  Step S314: When N exceeds 4, the CPU 162 proceeds to step S301 and substitutes 2 for N again. When N is 4 or less, the CPU 162 proceeds to step S302. By step S314, a process of repeating the above-described three frame periods (three field periods) as a cycle is realized.

  Control related to the image processing unit 163 by the CPU 162 will be described. The image processing unit 163 performs various types of image processing. For example, there is a process of converting a color difference color space signal into an RGB color space signal. The CPU 162 acquires Payload from the SDI input means 101 to 104 and stores it. As specified in SMPTE ST 252: 2010, Payload includes color space information. Therefore, the CPU 162 controls the image processing unit 163 according to the payload read from the payload storage units 111 to 114, and converts the image signal into a color space suitable for the liquid crystal panel 168 to display. Since the color space may be different depending on the SDI signal input from the SDI input means 101 to 104, the control of the color space conversion is also performed independently for each SDI signal input from the SDI input means. .

  Control regarding the graphics generation unit 167 by the CPU 162 will be described. The graphics generation unit 167 generates a graphics image under the control of the CPU 162. The graphics image also includes a character image generated from Time Code data using font data built in the image display device. The CPU 162 acquires the Time Code from the SDI input unit 101 and stores it. The CPU 162 controls the graphics generation unit 167 according to the time code read from the time code storage unit 169 to generate a character image from the acquired time code.

Among the steps shown in the flowchart of FIG. 3, the “CPU 162 processing” in FIG. It is shown in the column. For simplification of the drawings, some of the processes corresponding to the other steps are not shown.

  The image display apparatus according to the present embodiment acquires Time Code and Payload in accordance with the start timing of the vertical image signal for one SDI input unit selected as a Time Code acquisition target (synchronization processing). The vertical image signal start timing is a timing of transition from the vertical blanking period to the vertical effective image period. Furthermore, the image display apparatus according to the present embodiment acquires Payload for the remaining three SDI input means not selected as the Time Code acquisition target regardless of the vertical image signal start position (asynchronous processing). That is, in the present image display device, one CPU included in the image display apparatus synchronizes with one SDI input unit selected as a time code acquisition target, acquires the time code of the SDI input unit, and all the The SDI input means performs Payload acquisition processing.

  Therefore, even when there are a plurality of input terminals, auxiliary data of a plurality of input terminals can be acquired by one CPU, and the configuration of a conventional image display apparatus having a plurality of hardware and CPUs according to the number of input terminals. Can also be a simple configuration.

  In addition, in a conventional image display device in which all processes related to auxiliary data are implemented as hardware and the hardware is provided in accordance with the number of input terminals, auxiliary data is provided between the image processing unit and each of the plurality of SDI receivers. Processing hardware will be implemented. In such a configuration, an image signal obtained by synthesizing a Time Code graphic image is input to the image processing unit. Therefore, the enlargement / reduction unit 165 performs an enlargement / reduction process on the image signal obtained by combining the graphic images, and there is a problem that the Time Code graphic image becomes unclear. Further, since the reduction process involves thinning out pixels, there is a problem that pixel loss occurs in the Time Code graphic image.

  On the other hand, in the case of the configuration of the image display apparatus according to the present embodiment, the video graphics composition unit 166 synthesizes the graphic image of Time Code after the enlargement / reduction processing by the enlargement / reduction unit 165. Therefore, the time code graphic image is not subjected to the enlargement / reduction processing by the enlargement / reduction unit 165, and the problem that the time code graphic image is unclear and the problem of pixel loss are solved.

  In this embodiment, the case where the number of SDI input means is four has been described. However, the present invention can be applied to any image display device having two or more SDI input means such as eight SDI input means.

  The length of one frame period (one field period), the length of the vertical blanking period, and the vertical effective image period of the SDI signal input from the SDI input means 101 to 104 shown in FIG. 2 are merely examples. The present invention can be applied even if the content of the SDI signal input from the SDI input means 101 to 104 is different from that shown in FIG.

In this embodiment, the case where the image signal input interface to the image display apparatus is SDI has been described as an example. If the auxiliary data is transmitted during the vertical blanking period of the image signal and the CPU can read the data from the FIFO during the vertical effective image period, the present invention can also be applied to an image display device having another image signal input interface. It is. For example, a method of superimposing auxiliary data in the vertical blanking period of an analog composite video signal is known, but the present invention can also be applied to an image display device having a plurality of such image signal input interfaces. Furthermore, the present invention can also be applied to an image display apparatus in which auxiliary data is transmitted during a vertical effective image period of an image signal and the CPU can read out the data from the FIFO during a vertical blanking period. The present invention can also be applied to an image display device in which auxiliary data is transmitted during a specific period of the image signal and the CPU can read the data from the FIFO during a period when the auxiliary data is not transmitted.

(Example 2)
In the first embodiment, an example in which Time Code and Payload are transmitted to all SDI input means has been described. Actually, when only Time Code is transmitted in the SDI signal, or when only Payload is transmitted, both may not be transmitted. In this embodiment, an example in which at least one of Time Code and Payload is not transmitted will be described.

Hereinafter, the difference from the first embodiment will be mainly described.
As defined in the SMPTE standard, each auxiliary data has a specific DID and SDID. Therefore, by analyzing the data read from the FIFOs 141 to 144 of the SDI receivers 1 to 4, it is possible to determine whether Time Code or Payload is included in the SDI signal input from the SDI input means 101 to 104. In addition, although the DID and SDID of Time Code or Payload are included in the data read from the FIFOs 141 to 144 of the SDI receivers 1 to 4, this embodiment can also be applied when there is a mismatch in Checksum.

When the time code is not included in the SDI signal input from the SDI input means (SDI input means 101 in the second embodiment) that is the target of time code acquisition, the image display device stops graphics drawing of the time code. Alternatively, the image display device draws a special character string such as “-:-:-:-” indicating that the Time Code is not included, by graphics. However, in the case of an interlace signal, the Time Code may be included only in one field. For this reason, it is better to do the following. That is, when the time code is not included in a certain field, the image display device draws the graphics with the time code if the time code is included in the immediately preceding field. On the other hand, if the image display device does not include the time code continuously for two or more fields, the graphic indicating that the time code is not included, such as “-:-:-:-”. Draw a file.

  When Payload is not included in the SDI signal, the image display apparatus performs some prescribed processing as image processing for the SDI signal input from the SDI input means that does not include Payload. For example, when the process for the color difference color space signal is defined as the specified process, the image display apparatus regards the SDI signal input from the SDI input means that does not include Payload as the color difference color space signal, and converts the RGB color from the color difference color space. Perform conversion to space.

  Since the image display apparatus according to the present embodiment asynchronously acquires the payload from the SDI input unit that is not the target for acquiring the time code, there is a possibility that the reading of the payload is performed during the transmission of the payload and the acquisition of the payload may fail. . In this case, there is a possibility that it is erroneously determined that the signal is an SDI signal that does not include Payload although it originally includes Payload. Therefore, in view of the fact that Payload has a small change frequency, for example, the following may be performed. That is, when there is a payload that can be acquired within a predetermined number of frames (for example, within 5 frames), the image display apparatus controls image processing using the payload. On the other hand, when the payload cannot be acquired beyond the predetermined number of frames, it is determined that the SDI signal does not include the payload and the prescribed processing is performed.

According to the present embodiment, the Time Code and Payload from a plurality of SDI input means.
Even when an SDI signal that is not transmitted is input, it is possible to perform time code display and image processing without failure.

(Example 3)
In the image display apparatus according to the first embodiment, Payload is acquired by asynchronous processing from an SDI input unit that is not a target of Time Code acquisition. Therefore, the temporal phase relationship between the SDI input means that are not subject to Time Code acquisition and the SDI input means that are not subject to Time Code influence the probability of successful Payload acquisition from SDI input means that are not subject to Time Code acquisition. . Here, successful acquisition of Payload means that the acquired Payload has no abnormality (is valid data). In the present embodiment, a method for increasing the probability of successful Payload acquisition from an SDI input unit that is not a Time Code acquisition target will be described.

  FIG. 4 is a flowchart showing processing of the CPU 162. In the present embodiment, the processing by the CPU 162 is partially changed from the first embodiment as shown in FIG. In addition, about the process content of each step, about the same thing as Example 1, the detailed description is omitted using the same code | symbol as FIG.

  The changes from the first embodiment will be described in detail. In step S311, the CPU 162 determines whether or not the payload from the SDI input means that is not the time code acquisition target is valid (the checksum is inconsistent). If the payload is invalid, the process proceeds to step S315. In step S315, the CPU 162 analyzes the data read from the FIFO of the SDI receiver, and determines whether the DID and SDID indicating Payload are read from the FIFO.

  When the DID and SDID indicating Payload are read from the FIFO (step S315: Yes), the CPU 162 proceeds to step S314. In this case, since N does not increase, in the next frame (field in the case of interlace) of the SDI signal input from the SDI input means that is the target of Time Code acquisition, again from the SDI input means that failed to acquire Payload. Payload acquisition is attempted. That is, Payload acquisition from the same SDI input unit is performed again in the next acquisition process. Therefore, the probability of successful Payload acquisition increases.

  On the other hand, when the DID and SDID indicating Payload are not read from the FIFO (step S315: No), the CPU 162 proceeds to step S313. In this case, since N increases, it is possible to prevent the SDI input means for acquiring Payload from being switched in asynchronous processing when an SDI signal not including Payload is input.

  According to this embodiment, the probability of successful Payload acquisition from the SDI input means for acquiring Payload by asynchronous processing increases, and appropriate image processing control using Payload included in the SDI signal becomes possible.

Various modifications can be made to the above-described embodiment within the scope of the present invention. In the first embodiment, one processing cycle is a period of three frames of the SDI signal input from the SDI input unit that is the target of Time Code acquisition. Then, in one processing cycle, acquisition of auxiliary data by synchronous processing was performed once, and acquisition of auxiliary data by asynchronous processing was performed once for each SDI input unit to be processed asynchronously. On the other hand, auxiliary data acquisition by asynchronous processing may be performed a plurality of times for each SDI input means for asynchronous processing per processing cycle. Alternatively, for each processing cycle, the acquisition of auxiliary data by asynchronous processing is performed for each processing cycle.
You may make it perform once about DI input means.

1, 2, 3, 4 SDI receiver 101, 102, 103, 104 SDI input means 162 CPU
163 Image processing unit

The present invention includes a plurality of input means for inputting image signals independently,
Provided for each said input means, a plurality of storage means for storing auxiliary data transmitted by being superimposed on images signal,
Any one of the input means of synchronous Target of the plurality of input means, and other asynchronous subject to the input means an input unit, the period in which the auxiliary data is transmitted to the input means of the synchronized after There ended, the obtains the storage means whether et auxiliary data corresponding to the input means of the synchronization Target, auxiliary data acquisition and synchronization from the storage means corresponding to the input means of said synchronization Target at least one acquisition means for performing acquisition processing from the storage means to obtain the auxiliary data corresponding to the input means of the input means of said asynchronous Target and,
An image processing apparatus comprising:
The present invention comprises a first input means for inputting a first image signal;
A second input means for inputting a second image signal;
First storage means for storing first type auxiliary data and second type auxiliary data superimposed on the first image signal;
Second storage means for storing a second type of auxiliary data superimposed on the second image signal;
In response to a predetermined signal input to the first input means, the first storage means
A first type of auxiliary data and a second type of auxiliary data superimposed on the first image signal are obtained, and further, a second type of auxiliary data superimposed on the second image signal from the second storage means. An acquisition means for acquiring auxiliary data;
An image processing apparatus comprising:

The present invention includes a plurality of input means for inputting image signals independently,
Provided for each said input means, a plurality of storage means for storing auxiliary data transmitted by being superimposed on images signal,
An image processing apparatus control method comprising:
Any one of the input means of synchronous Target of the plurality of input means, and other asynchronous subject to the input means an input unit, the period in which the auxiliary data is transmitted to the input means of the synchronized after There ended, the obtains the storage means whether et auxiliary data corresponding to the input means of the synchronization Target, auxiliary data acquisition and synchronization from the storage means corresponding to the input means of said synchronization Target a method of controlling an image processing apparatus characterized by comprising a step of performing an acquisition process of acquiring auxiliary data from the storage means corresponding to at least one input means of the input means of said asynchronous Target with.
The present invention comprises a first input means for inputting a first image signal;
A second input means for inputting a second image signal;
First storage means for storing first type auxiliary data and second type auxiliary data superimposed on the first image signal;
Second storage means for storing a second type of auxiliary data superimposed on the second image signal;
An image processing apparatus control method comprising:
First type auxiliary data and second type auxiliary data superimposed on the first image signal from the first storage unit in response to a predetermined signal input to the first input unit. Acquiring, and further acquiring a second type of auxiliary data superimposed on the second image signal from the second storage means
A control method for an image processing apparatus, comprising:

Claims (10)

A plurality of input means for independently inputting image signals;
A plurality of storage means that are provided for each of the input means and store the auxiliary data when an image signal on which the auxiliary data is superimposed is input;
One of the plurality of input means is set as an input means for synchronous processing, and the other input means is set as an input means for asynchronous processing, and is assisted at a predetermined cycle from a storage means corresponding to the input means for synchronous processing. Acquires auxiliary data from storage means corresponding to at least one of the input means for asynchronous processing in synchronization with acquisition of auxiliary data from the storage means corresponding to the input means targeted for synchronous processing. An image processing apparatus comprising: an acquisition unit that performs an acquisition process.   The acquisition means is a target for acquiring auxiliary data among the input means for asynchronous processing so that the auxiliary data is acquired from the storage means corresponding to all the input means for asynchronous processing by a predetermined number of acquisition processes. The image processing apparatus according to claim 1, wherein the input unit is switched every time auxiliary data is acquired from a storage unit corresponding to the input unit to be synchronized.   When there is an abnormality in the auxiliary data acquired from the storage unit corresponding to the asynchronous processing target input unit, the acquisition unit again acquires the auxiliary data from the asynchronous processing target storage unit in the next acquisition process. The image processing apparatus according to claim 1.   The image processing apparatus according to any one of claims 1 to 3, wherein the predetermined period is one frame period or one field period of an image signal input to an input unit to be synchronized. The auxiliary data is transmitted during a blanking period of the image signal,
5. The image processing apparatus according to claim 1, wherein the acquisition unit starts the acquisition process at a timing when a blanking period of the image signal input to the input unit to be synchronized is completed. The auxiliary data includes a time code and a payload,
The acquisition unit acquires a time code and a payload at the predetermined cycle from a storage unit corresponding to a synchronous processing target input unit, and acquires a payload from a storage unit corresponding to an asynchronous processing target input unit. The image processing apparatus according to claim 5.   The processing unit according to any one of claims 1 to 6, further comprising a processing unit that independently performs signal processing on a plurality of image signals input from the plurality of input units based on auxiliary data acquired by the acquiring unit. Image processing apparatus.   The image processing apparatus according to claim 7, wherein the signal processing by the processing unit includes processing for combining an image based on a time code with an image based on an image signal, and image processing based on a payload.   An image display device comprising: the image processing device according to claim 1; and display means for displaying an image based on an image signal. A plurality of input means for independently inputting image signals;
A method for controlling an image processing apparatus, comprising: a plurality of storage units that are provided for each input unit and store auxiliary data when an image signal on which auxiliary data is superimposed is input;
One of the plurality of input means is set as an input means for synchronous processing, and the other input means is set as an input means for asynchronous processing, and is assisted at a predetermined cycle from a storage means corresponding to the input means for synchronous processing. Acquires auxiliary data from storage means corresponding to at least one of the input means for asynchronous processing in synchronization with acquisition of auxiliary data from the storage means corresponding to the input means targeted for synchronous processing. A control method for an image processing apparatus, comprising a step of performing an acquisition process.