JP2017027432A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means for eliminating a performance bottleneck in a processor that is capable of executing a plurality of execution slots conforming to the same instruction in parallel.SOLUTION: Provided is an SIMD-type processor capable of parallel execution that has a plurality of execution slots for making the same instruction adaptable to a plurality of data simultaneously. When an atomic instruction included in the same instruction is executed, the processor determines execution slots, out of the plurality of execution slots corresponding to the atomic instruction, the designated addresses of which overlap, executes one execution slot out of the execution slots having overlapping addresses, and returns the result of the execution. For the remaining other execution slots, the processor returns a result indicating that instruction execution has failed, without executing instructions.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a SIMD (Single Instruction Multi Data) processor that is provided with a plurality of execution slots and can be executed in parallel in order to simultaneously adapt the same instruction to a plurality of data.

  In recent years, various processors equipped with multimedia instructions suitable for image processing and sound processing have been put into practical use. Multimedia instructions are primarily intended for applications where the same operation must be repeated for multiple data. SIMD (Single Instruction Multiple Data) is known as one of implementation methods for realizing multimedia instructions.

  In SIMD, in response to an instructed single command, a plurality of execution slots to which different data are input respectively execute processing in synchronization with each other. That is, the SIMD type processor supports a combination of a single instruction stream and a plurality of data streams.

  As an example of the SIMD type processor, an SIMT (Single Instruction Stream Multiple Thread) type processor has been proposed. In the SIMT type processor, each execution unit manages whether to enable or disable the instruction execution on the slot according to the branch instruction, thereby completing the execution of the assigned thread. Since a plurality of threads are executed in parallel, programming can be performed without being aware of the parallel number even when the parallel number is increased.

  For example, US Pat. No. 7,627,723 (Patent Document 1) shows an example of a SIMT type processor. In the parallel processing subsystem described in Patent Document 1, each of a plurality of ROP (Raster Operation) units is responsible for a specific address range of the memory, and accesses the assigned address range to execute the assigned thread.

US Pat. No. 7,627,723

  In a SIMT type processor, each execution slot executes a thread independently. The processing of each thread may include, for example, processing for writing back data obtained by executing processing to a common memory. In such processing, it is necessary to maintain atomicity (inseparability). Therefore, in the SIMT type processor, an atomic instruction is prepared and used for synchronization processing between threads.

  The atomic instruction typically includes reading data from the memory (read), calculating updated data (modify), and writing updated data to the memory (write). While an execution slot responsible for execution of a thread is executing an atomic process in accordance with an atomic instruction, an operation for eliminating access to the same memory in the execution slot responsible for execution of another thread is executed. In this way, in an SIMT type processor, by giving an atomic instruction to a plurality of threads, the processing of a plurality of threads accessing the same memory is executed serially. Maintains atomicity.

  However, serialization of thread processing to maintain atomicity may cause a performance bottleneck in the SIMT type processor. Therefore, an object of the present invention is to provide one solution means for eliminating such a performance bottleneck.

  According to one aspect of the present invention, there is provided a SIMD (Single Instruction Multi Data) type processor that is provided with a plurality of execution slots and can be executed in parallel so that the same instruction can be simultaneously applied to a plurality of data. The The same instruction reads the data stored at the specified address for each execution slot, and when the read data satisfies a predetermined condition, performs the process of writing the data to the specified address. Includes atomic instructions to execute while maintaining sex. When the atomic instruction is executed, the processor identifies an execution slot in which the designated address is duplicated among a plurality of execution slots corresponding to the atomic instruction, and selects one of the execution slots in which the address is duplicated. An instruction is executed in the execution slot, and the result of the execution is returned. For the remaining execution slots, a result indicating that the execution of the instruction has failed is returned without executing the instruction.

  Preferably, the processor returns a result indicating that the instruction execution has failed for the remaining execution slots before executing the instruction of one execution slot among the execution slots having overlapping addresses.

  Preferably, the processor returns the value read from the designated address as a further result after executing the instruction in one execution slot among the execution slots having the same address, and the address is duplicated for the remaining execution slots. If execution of an instruction in one execution slot is successful, the value written to the memory by the instruction in the one execution slot is returned as a further result, and one of the execution slots with duplicate addresses is returned. When the instruction execution in the execution slot fails, the value read from the memory during the instruction execution by the one execution slot is returned as a further result.

  Preferably, the processor determines one execution slot to be executed based on a number assigned to the execution slot among execution slots having overlapping addresses.

  Preferably, the processor includes a plurality of processor cores and a memory shared between the plurality of processor cores.

  According to the present invention, a performance bottleneck in a processor capable of executing a plurality of threads following the same instruction in parallel can be solved.

FIG. 3 is a schematic diagram showing a device configuration of a computer according to the first embodiment. It is a schematic diagram for demonstrating the process sequence of the atomic instruction which concerns on related technology. It is a figure for demonstrating the process for determining the execution slot which should perform an instruction. It is a flowchart which shows the process sequence of the lock-free algorithm using the CAS instruction | command 1 which concerns on related technology. FIG. 5 is a diagram for explaining changes in data stored in a memory in the execution process of the lock-free algorithm shown in FIG. 4 (when the number of execution slots is 4). It is a figure for demonstrating another example of the change of the data stored in the memory in the execution process of the lock-free algorithm shown in FIG. 4 (when the number of execution slots is 8). It is a schematic diagram for explaining the processing procedure of CAS instruction 2 according to the first embodiment. It is a flowchart which shows the process sequence of the lock-free algorithm 300 using the CAS instruction | command 2 according to Embodiment 1. FIG. 9 is a diagram for explaining a change in data stored in a memory in the execution process of the lock-free algorithm shown in FIG. 8 (when the number of execution slots is 4). It is a figure for demonstrating another example of the change of the data stored in the memory in the execution process of the lock-free algorithm shown in FIG. 8 (when the number of execution slots is 8). FIG. 11 is a schematic diagram for describing an atomic instruction processing procedure according to the second embodiment. 10 is a flowchart showing a processing procedure of a lock-free algorithm 350 using a CSW instruction according to the second embodiment. FIG. 10 is a schematic diagram showing a device configuration of a computer according to a third embodiment. FIG. 10 is a schematic diagram showing a device configuration of a computer according to a fourth embodiment. It is a schematic diagram which shows the structural example of the local storage shown in FIG. It is a flowchart for demonstrating the memory access processing procedure in the computer according to Embodiment 4 shown in FIG. It is a schematic diagram which shows the example of a data structure of the access flag used in the process sequence defined by the flowchart of FIG. FIG. 16 is a schematic diagram showing a hardware configuration related to a computer according to a fifth embodiment. It is a figure which shows an example of the microcode for implement | achieving an atomic process.

  Embodiments of the present invention will be described in detail with reference to the drawings. In addition, about the same or equivalent part in a figure, the same code | symbol is attached | subjected and the description is not repeated.

<A. Overview>
The processor according to the present embodiment is directed to a SIMD (Single Instruction Multi Data) type processor that is provided with a plurality of execution slots and can be executed in parallel, so that the same instruction can be simultaneously applied to a plurality of data. In such a processor capable of executing a plurality of threads that follow the same instruction in parallel, if parallel execution of a thread with overlapping access destination addresses is instructed, access between the same addresses will not conflict. Exclusive processing is executed. As a result, processing of threads with overlapping addresses is serialized and executed. The inventor of the present application has found a new finding that the serialization of the thread is a performance bottleneck when executing a certain atomic instruction.

  Therefore, even when there are a plurality of threads having overlapping addresses of access destinations, the inventors have come up with another solution that improves processing performance, not serializing threads. Hereinafter, a new atomic instruction conceived by the present inventor will be described.

  Any method may be used for mounting the atomic instruction on the processor according to the present embodiment. For example, a CISC (Complex Instruction Set Computer) processor such as a CPU (Central Processing Unit) called an x86 system may be implemented as a single processor instruction. Further, RISC processors such as PowerPC (registered trademark) and SPARC (registered trademark) may be realized by a combination of a plurality of types of processor instructions. In this case, two types of processor instructions called Load-Link and Store-Conditional may be used.

  In addition, a GPU (Graphics Processing Unit) may be implemented as a single processor instruction in the form of SIMD operation. Alternatively, the processing procedure according to the present embodiment may be divided into a plurality of processor instructions and mounted.

  An instruction sequence optimized using a compiler or an assembler is generated from a program created in a high-level language in accordance with a processor instruction installed in the processor. In this case, from the viewpoint of creating a program, there is no need to be aware of differences in processor architecture.

<B. Embodiment 1>
(B1: Device configuration)
First, as Embodiment 1, a configuration in which atomic processing according to this embodiment is mounted on a multi-core SIMD type processor will be described. Typically, the processor according to the first embodiment assumes a SIMT type in which a plurality of threads following the same instruction can be executed in parallel. However, the technical scope of the present invention should be determined based on the description of the scope of claims, and does not exclude, for example, a new architecture to be put into practical use in the future.

  FIG. 1 is a schematic diagram showing a device configuration of a computer 1 according to the first embodiment. Referring to FIG. 1, computer 1 according to the first embodiment includes a multi-core processor 10, an external memory 180, and an external device 190.

  The multi-core processor 10 includes a plurality of processor cores 100-1 and 100-2 (hereinafter also collectively referred to as “processor core 100”), a shared cache 110, a memory controller 120, and an IO controller 130. These components are connected to each other via an internal bus 140 so as to exchange data. The shared cache 110 is shared between the plurality of processor cores 100-1 and 100-2. FIG. 1 illustrates a configuration including two processor cores 100 for convenience of explanation, but the number of processor cores 100 is not particularly limited.

  The multi-core processor 10 (or each of the processor cores 100) is a processor having a plurality of execution slots so that a plurality of threads following the same instruction can be executed in parallel. In the first embodiment, it is assumed that a SIMD instruction set is implemented in each processor core 100. The SIMD instruction set includes atomic instructions for executing read-modify-write in parallel for a plurality of data addresses on the shared cache 110. In this atomic instruction, it is assumed that atomicity is maintained between read-modify-write executed in parallel. In this specification, “read / modify / write” is a general term for processing of reading data from memory (reading), calculating updated data (modify), and writing updated data to memory (write). is there. However, “read / modify / write” may include a case where only a part of the three processes is executed.

  The shared cache 110 is a memory area that can be accessed by each of the processor cores 100.

  The memory controller 120 exchanges data with the external memory 180 connected via the external memory bus 160. The memory controller 120 is connected to the shared cache 110 via the internal bus 150. The memory controller 120 typically writes data read from the external memory 180 to the shared cache 110 and writes data read from the shared cache 110 to the external memory 180.

  The IO controller 130 exchanges data with the external device 190 connected via the external device bus 170. The IO controller 130 typically writes data read from the external device 190 to the shared cache 110 and writes data read from the shared cache 110 to the external device 190.

  The external memory 180 is a memory area with a larger storage capacity although the access speed is lower than that of the shared cache 110. The external device 190 includes various input / output devices and an external storage device.

(B2: Atomic instruction processing procedure according to related technology)
First, in the computer 1 according to the first embodiment, an atomic instruction processing procedure according to related technology will be described. FIG. 2 is a schematic diagram for explaining an atomic instruction processing procedure according to the related art. The SIMD instruction 200 # given to the multi-core processor 10 is applied to the four execution slots 201 to 204 (slot 0 to slot 3). In each of the execution slots 201 to 204, the same atomic instruction to be executed in parallel and independent input data are designated.

  The instruction sequence including the SIMD instruction 200 # is given to one or both of the plurality of processor cores 100-1 and 100-2 (see FIG. 1) according to a predetermined logic.

  Corresponding to the execution slots 201 to 204, flag areas 211 to 214 and return value areas 221 to 224 are provided in the memory area, respectively. The flag areas 211 to 214 are areas for storing the execution state of the instruction specified in the corresponding execution slot. The return value areas 221 to 224 are areas for storing return values obtained by executing instructions specified in the corresponding execution slots. The flag areas 211 to 214 and the return value areas 221 to 224 may be mounted using a specific address range of the shared cache 110 or may be mounted using a special register.

  First, when the execution of the SIMD instruction 200 # is started ((1) instruction execution start), the respective values stored in the flag areas 211 to 214 are initialized. In the processing procedure shown in FIG. 2, a value meaning “unprocessed” or “processed” is set in each of the flag areas 211 to 214 for the instruction specified in the corresponding execution slot.

  In initialization, a value indicating “unprocessed” is set in the flag area corresponding to the execution slot in which the instruction is designated as valid, and the flag area corresponding to the execution slot in which the instruction is designated as invalid. Is set to a value meaning “processed”.

  For example, when the flag areas 211 to 214 are mounted using a specific address range of the memory, a special value (for example, “−1” or “FFFF”) corresponding to the state value is designated, or a flag When the areas 211 to 214 are implemented by special registers, the values of these special registers are set to off or on according to the state value.

  In FIG. 2, “address A”, “address B”, and “address C” described in the SIMD instruction 200 # are the instructions specified before the atomic instructions in the corresponding execution slots 201 to 204 act. It means the address where data is read. In the example shown in FIG. 2, execution slots 201 and 203 are both designated to perform processing on “address A”.

  When the initialization is completed, the processor core 100 specifies an execution slot that is simultaneously processed among execution slots that are set to “unprocessed”, and there is an overlap in addresses accessed by the execution slots that are simultaneously processed. ((2) Address duplication check). That is, the processor core 100 determines whether there is the same address corresponding to the execution slot.

  In an atomic instruction, exclusive processing is executed between execution slots so that accesses to the same address do not compete. That is, when there is an overlap in the address, the processor core 100 keeps only one of the execution slots with the overlapping address in “unprocessed”, and the other execution slots are temporarily Invalidate (execution slot indicated by reference numeral 242 in FIG. 2).

  (2) When considering a specific procedure example for address duplication confirmation, it is necessary to consider the following hardware restrictions.

  As shown in FIG. 1, in the multi-core processor 10, a plurality of processor cores 100 are connected so as to share a shared cache 110. Within the multiprocessor 10, there is a restriction that only a limited number of cache lines defined in advance by hardware of the shared cache 110 can be accessed within one memory cycle. Therefore, when executing a SIMD instruction that performs a memory operation on a plurality of addresses, such as a SIMD atomic instruction, the processor core 100 executes only an execution slot that accesses a limited number of the same cache lines in parallel in each memory cycle. However, the instruction is executed over one or more memory cycles before the instruction of all execution slots is completed. In the following description, the number of cache lines that can be accessed in one memory cycle is assumed to be 1. However, even when the number of cache lines that can be accessed in one memory cycle is 2 or more, a plurality is selected in the determination part of the cache line to be accessed. By considering that only the relevant execution slot is valid for each cache line, the same processing can be performed. A specific procedure for address duplication confirmation will be described below under such constraints.

  The processor core 100 extracts the execution slot having the smallest execution slot number from the execution slots set to “unprocessed”, and sets the address corresponding to the extracted execution slot as the address X. Then, the processor core 100 compares each address corresponding to another execution slot set to “unprocessed” with the address X, and temporarily executes an execution slot not at the address on the same cache line. Disable it. Further, for each address in the same cache line, processing for determining an execution slot in which an instruction is to be executed is performed.

  FIG. 3 is a diagram for explaining processing for determining an execution slot in which an instruction is to be executed.

Typically, the number of addresses that can be simultaneously processed in the same cache line is determined by the cache line size and the data width of the atomic instruction. As shown in FIG. 3A, for example, when the cache line size is 64 bytes (2 ⁶ ) and the data width is 32 bits (= 4 bytes (2 ² )), The number of addresses that can be processed is 64/4 = 16 (2 ⁴ ). Numbers 0-15 are assigned in the order of these addresses, and a flag indicating the number of execution slots is provided for each number. As shown in FIG. 3B, each bit of the flag becomes “1” when the corresponding execution slot is an access to the address, and when it is different (that is, when the execution slot is invalid, or It is set to “0” when the address is not accessed.

  For the flag for each address thus determined, the smallest bit number that is “1” is the number of the execution slot that is allowed to access the address. Each execution slot temporarily invalidates the execution slot when the number of the execution slot permitted to access is different from the number of its own execution slot, which is determined from the flag of the address corresponding to the action address of the instruction.

  Referring to FIG. 3, an execution slot in which an instruction is to be executed is determined by the following procedure. First, the cache line is determined by the upper address, and the address is classified by the lower part of the same cache line address, and an execution slot for accessing each address is determined. In this case, (1) the cache line of execution slot 0 is selected, (2) execution slot 3 having a different cache line is temporarily invalidated, and (3) execution slots having access requests for different addresses of the cache line are aggregated. (Aggregation results are stored in the table of FIG. 3B). (4) An execution slot for accessing each address is determined. In this example, execution slot 1 can access address 1, and execution slot 0 can access address 3. The other execution slots (slot 2) are invalidated.

  If the number of execution slots that can be executed in parallel is small, a flag is not generated for each different address of the cache line, but the bits indicating the address in the cache line of the addresses corresponding to each execution slot are all compared. Thus, it may be implemented so as to eliminate duplication.

  As described above, the processor core 100 enables only one of a plurality of accesses to the same address and temporarily disables other accesses. In the example shown in FIG. 2, since access to “address A” is specified in both the execution slot 201 and the execution slot 203, only the execution slot 201 is validated, and the execution slot 203 is temporarily stored. It is invalidated.

  Subsequently, the processor core 100 performs atomic processing (read-modify-write: reading data from the memory) for the address specified in the execution slot set to “unprocessed” (that is, enabled). , Calculation of post-update data, and writing of post-update data into memory) ((3) atomic processing). The processor core 100 writes the value obtained by reading the data from the first memory into the corresponding return value area. Then, the processor core 100 sets the execution slot in which the designated atomic process is completed to “processed”.

  In the example illustrated in FIG. 2, the processor core 100 writes success / failure result values 231, 232, and 234 that indicate successful execution of instructions to the return value areas 221, 222, and 224. Further, the processor core 100 resets the flag area 213 corresponding to the execution slot 203 temporarily invalidated to “unprocessed”.

  Then, the processor core 100 determines whether or not there is an execution slot set to “unprocessed” ((4) confirmation of an unprocessed execution slot). If there is an execution slot set to “unprocessed”, the above-described processing (three processes indicated by reference numeral 240 # in FIG. 2) is repeated, otherwise, the SIMD instruction 200 Execution of # ends.

  In the example shown in FIG. 2, since the execution slot 203 remains “unprocessed”, (5) address duplication confirmation, (6) atomic processing, and (7) unprocessed execution slot confirmation are executed. As a result, the processor core 100 writes the success flag 233 in the return value area 223. When all the execution slots are set to “processed” by repeatedly executing the three processes indicated by reference numeral 240 # a plurality of times (in the example of FIG. 2, twice), the SIMD instruction 200 # Execution is complete.

  As shown in FIG. 2, in the atomic instruction processing procedure according to the related art, among the execution slots included in the SIMD instruction 200 #, the atomic process is executed only once for each of the enabled execution slots. At this time, since the execution slots assigned with the overlapping addresses cannot be executed in parallel, if the addresses are overlapping, only one of the execution slots is enabled and the other execution slots are also enabled. The process is repeated until all execution slots have been processed in the procedure of postponing the process. By such a processing procedure, read-modify-write is processed atomically with respect to the data at the address specified for each execution slot.

(B3: CAS instruction)
Hereinafter, as an example of an SIMD instruction processed atomically, a compare-and-swap instruction (hereinafter also collectively referred to as “CAS instruction”) is executed according to the above-described processing procedure shown in FIG. The case where it does is demonstrated.

  The CAS instruction reads data (value) stored at a specified address, returns it as a result of the instruction, compares the read first data with the specified second data, This is an atomic instruction for writing the third data to the designated address when the data are equal.

  If a CAS instruction is specified in the execution slot, data is read from the specified address in the memory, the read data is compared with the old data, and the new data is only read if both data match. A process of writing to the memory is executed. In the CAS instruction, the comparison result of the read data is returned as the execution result (return value). That is, the result (return value) is written to the return value area corresponding to the corresponding execution slot.

(B4: CAS instruction implementation / operation according to related technology and lock-free algorithm using the same)
Hereinafter, a CAS instruction implemented according to the processing procedure according to the related art shown in FIG. 2 (hereinafter, for the sake of convenience, in order to distinguish this embodiment from the implementation form, “CAS instruction 1” or “atomic-compare-and-swap1”). The processing procedure is also described. In addition, the lock-free algorithm using the CAS instruction 1 will be described.

  The lock-free algorithm is an algorithm for executing processing without locking any data shared between a plurality of threads (typically, data stored in the shared cache 110). It is. That is, a plurality of threads can read and write simultaneously and in parallel without damaging the shared data. For example, data necessary for execution of a certain thread is locked by another thread, and the execution of the thread is not waited until the lock is released.

  Such a lock-free algorithm is used for processing such as weighted histogram calculation and multiple types of queue registration.

  FIG. 4 is a flowchart showing the processing procedure of the lock-free algorithm 300 # using the CAS instruction 1 according to the related art. The flowchart shown in FIG. 4 shows a part of processing of a program executed by the multi-core processor 10, and shows an example of code used in the program in association with each step.

  Referring to FIG. 4, processor core 100 prepares for data update (step S100). Specifically, the processor core 100 sets a variable% input for calculating post-update data from pre-update data stored at a specified address (code 302).

  Subsequently, the processor core 100 reads pre-update data (step S102). Specifically, the processor core 100 reads the pre-update data stored in the designated address (addressX) and sets the variable% old (code 304).

  Subsequently, the processor core 100 calculates updated data (step S104). Specifically, the processor core 100 calculates post-update data (variable% new) using the variable% old and the variable% input as parameters according to the specified arithmetic expression (code 306).

  Subsequently, the processor core 100 tries to write updated data (step S106). Specifically, the processor core 100 executes CAS instruction 1 (atomic-compare-and-swap1) to calculate data stored at a specified address (addressX) and updated data. The data before update (that is, the value of variable% old) is compared, and if the two data match, the data after update (that is, the value of variable% new) is written to the designated address (code 308). . The return value of the CAS instruction 1 (atomic-compare-and-swap1) is data stored at the specified address, and is set in the variable% ret. Therefore, the data stored at the specified address in the current step (ie, the value of variable% ret) is compared with the pre-update data (ie, the value of variable% old) used in calculating the updated data. If the two data match, “true (true)” is set to the variable% cond. Otherwise, “false (false)” is set to the variable% cond (code 310).

  If writing of the updated data is successful (in step S106, if variable% cond = true: code 312), the process ends. On the other hand, if the writing of the updated data fails (in step S106, the variable% cond == false: code 314), the processor core 100 determines that the updated data is to be recalculated. Is updated (step S108). In this case, it means that another thread has changed the data at the target address while the post-update data is being calculated by the executing thread, and it is necessary to update the pre-update data. Specifically, the processor core 100 sets the value of the variable% ret to the variable% old (code 316). And the process after step S104 is performed again.

(B5: The number of atomic processes of a plurality of execution slots for the same address when applied to the lock-free algorithm using the CAS instruction (CAS instruction 1) according to the related technology)
(I) When the Number of Execution Slots is 4 FIG. 5 is a diagram for explaining changes in data stored in the memory during the execution process of the lock-free algorithm 300 # shown in FIG. 4 (the number of execution slots is 4). in the case of).

  FIG. 5 shows a case where the number of execution slots of the SIMD instruction is four. When the lock-free algorithm 300 # shown in FIG. 4 is executed by a plurality of threads, the processing for the four threads is converted into a processor instruction sequence including the SIMDCAS instruction 1 as a single instruction stream on the multi-core processor 10 by the compiler. (Step S106 in FIG. 4). FIG. 5 shows an operation example when the SIMDCAS instruction 1 in the lock-free algorithm 300 # given to the multi-core processor 10 is executed.

  In the example shown in FIG. 5, it is assumed that “address A” is designated as the operation target address of the CAS instruction 1 in the execution slots 201 and 203 (corresponding to addressX in the code 308 in FIG. 4). Therefore, three processes (address duplication confirmation, atomic process, and confirmation of unprocessed execution slots) indicated by reference numeral 240 # in FIG. 5A are repeated twice.

  However, when the execution of the instruction specified in the execution slot 203 is completed, the return value (corresponding to the variable% ret in the code 308 in FIG. 4) is set to the address A by the execution of the instruction specified in the execution slot 201. It becomes the post-update data written, which is different from the value before the normal update. That is, in step S106 of the lock-free algorithm 300 # shown in FIG. 4, it is determined that writing of the updated data has failed. Therefore, steps S104 and S106 shown in FIG. 4 are executed again. That is, as shown in FIG. 5B, the CAS instruction 1 is executed again.

  As shown in FIG. 5B, in the second CAS instruction 1, only the instruction specified in the execution slot 203 is executed among the plurality of instructions specified in the SIMD instruction 200 #.

  As shown in FIGS. 5A and 5B, when the lock-free algorithm 300 # shown in FIG. 4 is executed, three processes (address duplication confirmation) indicated by reference numeral 240 # in FIG. , Atomic processing, confirmation of unprocessed execution slots) is repeated three times in total.

(Ii) When the Number of Execution Slots is 8 FIG. 6 is a diagram for explaining another example of change in data stored in the memory in the execution process of the lock-free algorithm 300 # shown in FIG. When the number of slots is 8.)

  As shown in FIG. 6A, when execution of the first CAS1 instruction (SIMD instruction 200 #) is started ((1) instruction execution start), the processor core 100 performs predetermined processing such as initialization. After that, it is determined whether or not there is duplication in the addresses accessed by the simultaneously executed execution slots ((2) address duplication confirmation). In the example shown in FIG. 6A, since access to “address A” is specified in any of execution slots 201, 203, and 206, only execution slot 201 is validated and execution slots 203 and 206 are displayed. Is temporarily invalidated (see * 1 in FIG. 6A). In addition, since access to “address C” is specified in both execution slots 204 and 208, only the execution slot 204 is enabled and the execution slot 208 is temporarily disabled (FIG. 6). (See * 2 in (A)). In this state, the processor core 100 executes an atomic process (CAS instruction 1) for the instruction specified in the activated execution slot ((3) atomic process). As the CAS instruction 1 is executed, the processor core 100 updates the memory on the working address of each execution slot and writes the value read from the memory in the return value area. In addition, the flag area 213 is set as processed for the execution slots 201, 202, 204, 205, and 207 that have executed the atomic process. Further, the processor core 100 resets the flag area 213 corresponding to the execution slots 203, 206, 208 temporarily invalidated to “unprocessed”.

  Then, the processor core 100 determines whether or not there is an execution slot set to “unprocessed” ((4) confirmation of an unprocessed execution slot). Subsequently, (5) address duplication confirmation, (6) atomic processing, and (7) unprocessed execution slot confirmation are executed. At this time, since access to “address A” is specified in both execution slots 203 and 206, only the execution slot 203 is enabled and the execution slot 206 is temporarily disabled again ( (See * 3 in FIG. 6A).

  Even after three processes indicated by reference numeral 240 # are repeated twice, the execution slot 206 is still “unprocessed”, so (8) address duplication confirmation, (9) atomic process, (10) Confirmation of unprocessed execution slots is performed.

  Even if execution of the first CAS instruction 1 shown in FIG. 6A is completed, the return values corresponding to the execution slots 203, 206, and 208 (corresponding to the variable% ret in the code 308 of FIG. 4) are The updated data is changed by another execution slot. That is, in the lock-free algorithm 300 # (see FIG. 4) respectively corresponding to the execution slots 203, 206, and 208, it is determined in step S106 that the writing of the updated data has failed. Therefore, as shown in FIG. 6B, the CAS instruction 1 is executed again.

  In FIG. 6B, since access to “address A” is designated in both execution slots 203 and 206, three processes indicated by reference numeral 240 # in FIG. , Atomic processing, confirmation of unprocessed execution slots) is repeated twice. Even if the execution of the second CAS instruction 1 shown in FIG. 6B is completed, the return value corresponding to the execution slot 206 (corresponding to the variable% ret in the code 308 of FIG. 4) is the other execution slot. The updated data is changed by. Therefore, as shown in FIG. 6C, the CAS instruction 1 is executed again.

  In FIG. 6C, in the third CAS instruction 1, three processes indicated by reference numeral 240 (address duplication confirmation, atomic process, confirmation of unprocessed execution slot) for the instruction specified in the execution slot 206 Is executed once.

  As shown in FIGS. 6A to 6C, when the lock-free algorithm 300 # shown in FIG. 4 is executed, three processes (address duplication confirmation) indicated by reference numeral 240 # in FIG. , Atomic processing, confirmation of unprocessed execution slots) is repeated six times in total.

  The number of executions of the atomic process with the atomic instruction (CAS instruction 1) according to the related art will be described. In the following description, for the sake of explanation, it is assumed that all different addresses are on the same cache line and can be processed in parallel. When different cache line addresses are included, the number of executions of the atomic process is calculated for each cache line, and the sum of all the numbers is the actual number of atomic processes.

  As shown in FIG. 5, when the address A is duplicated in two execution slots, the number of atomic processes (reference numeral 240 #) is the same as the maximum number of duplicates N (= 2) in the first CAS instruction 1. The three processes shown are executed. In the atomic process executed a plurality of times, writing of updated data is successful only for one execution slot among a plurality of execution slots having overlapping addresses. That is, the second CAS instruction 1 is executed in a state where there is a number of address duplications obtained by subtracting 1 from the maximum duplication number N. As a result, when the first CAS instruction 1 is executed, the atomic process is executed twice. When the second CAS instruction 1 is executed, the atomic process is executed once, and the total number of executions of the atomic process is three. .

  As shown in FIG. 6, when address A is overlapped in three execution slots and address C is overlapped in two execution slots, the maximum overlap number N in the first CAS instruction 1 The same number of atomic processes (three processes indicated by reference numeral 240 #) are executed as many times as (= 3). In the atomic process executed a plurality of times, writing of updated data is successful only for one execution slot among a plurality of execution slots having overlapping addresses. That is, the subsequent CAS instruction 1 is executed in a state where there is a number of address duplications obtained by subtracting 1 from the maximum duplication number N.

  As a result, when the first CAS instruction 1 is executed, the atomic process is executed three times, when the second CAS instruction 1 is executed, the atomic process is executed twice, and when the third CAS instruction 1 is executed, the atomic process is executed twice. The process is executed once, and the total number of executions of the atomic process is 6.

  As described above, when the lock-free algorithm 300 # is executed once, the total number of executions of the atomic process is N × (N + 1) / 2 times at the minimum. Here, N indicates the maximum overlapping number N of addresses included in the same SIMD instruction 200 #.

  Note that when another thread executed independently by another processor core 100 existing in the multi-core processor 10 simultaneously accesses the same address, the number of processes further increases.

(B6: Implementation and operation of CAS-like instruction according to Embodiment 1, and lock-free algorithm using the same)
A description will be given of the implementation and operation of an instruction similar to the CAS instruction according to the related technology, which is employed in multi-core processor 10 (or each of processor cores 100) according to the first embodiment. Hereinafter, an instruction similar to the CAS instruction according to the related art is also referred to as “CAS instruction 2” or “atomic-compare-and-set2” for convenience of explanation. The CAS instruction 2 defined on the SIMD instruction set reads data (value) stored at an address designated by each execution slot, and reads the read first data and designated second data. In comparison, when both data are equal, it is an instruction that atomically performs a series of processes of writing the third data to the designated address, assuming that the instruction has been successfully executed. If they are equal in the comparison, a return value indicating success (usually 1) is returned, and if they are not equal, a return value indicating failure (usually 0) is returned. However, when there are multiple execution slots that access the same address, only the actual atomic processing is performed for only one execution slot, and atomic processing is not performed for the other execution slots, and a return value indicating failure is always returned. .

  When the SIMD instruction 200 in which the CAS instruction 2 is specified is executed, the following operation is performed.

  A processing procedure of CAS instruction 2 implemented in computer 1 according to the first embodiment will be described. FIG. 7 is a schematic diagram for explaining the processing procedure of CAS instruction 2 according to the first embodiment. Referring to FIG. 7, SIMD instruction 200 given to multi-core processor 10 is applied to four execution slots 201 to 204 (slot 0 to slot 3). In each of the execution slots 201 to 204, the same atomic instruction (CAS instruction 2) executed in parallel and different input data are designated in each execution slot.

  Corresponding to the execution slots 201 to 204, flag areas 211 to 214 and return value areas 221 to 224 are provided in the memory area, respectively. The flag areas 211 to 214 are areas for storing the execution state of the instruction specified in the corresponding execution slot. The return value areas 221 to 224 are areas for storing return values obtained by executing instructions specified in the corresponding execution slots. The flag areas 211 to 214 and the return value areas 221 to 224 may be mounted using a specific address range of the shared cache 110 or may be mounted using a special register.

  First, when execution of the SIMD instruction 200 in which the CAS instruction 2 is specified in each execution slot is started ((1) instruction execution start), the respective values stored in the flag areas 211 to 214 are initialized. The In the processing procedure shown in FIG. 7, a value indicating “unprocessed” or “processed” is set in each of the flag areas 211 to 214 for the CAS instruction 2 specified in the corresponding execution slot. .

  In initialization, a value corresponding to “unprocessed” is set in the flag area corresponding to the execution slot in which the CAS instruction 2 is effectively specified, and the flag corresponding to the execution slot in which the instruction is specified as invalid A value meaning “processed” is set in the area.

  For example, when the flag areas 211 to 214 are mounted using a specific address range of the memory, a special value (for example, “−1” or “FFFF”) corresponding to the state value is designated, or a flag When the areas 211 to 214 are implemented by special registers, the values of these special registers are set to off or on according to the state value.

  In FIG. 7, “address A”, “address B”, and “address C” described in the SIMD instruction 200 mean destination addresses to which the CAS instruction 2 of the corresponding execution slots 201 to 204 acts. In the example shown in FIG. 7, execution slots 201 and 203 are both designated to perform processing on “address A”.

  When the initialization is completed, the processor core 100 specifies an execution slot that is simultaneously processed among execution slots that are set to “unprocessed”, and there is an overlap in addresses accessed by the execution slots that are simultaneously processed. ((2) Address duplication check). That is, the processor core 100 specifies an execution slot in which the designated address is duplicated among a plurality of execution slots corresponding to the CAS instruction 2. In other words, the processor core 100 determines whether there is the same address corresponding to the execution slot.

  As described above, in the multiprocessor 10, there is a restriction that only a limited number of cache lines defined in advance by the hardware of the shared cache 110 can be accessed within one memory cycle. Therefore, when the processor core 100 executes a SIMD instruction that performs a memory operation on a plurality of addresses such as a SIMD atomic instruction, only the execution slots that access a limited number of the same cache lines are executed in parallel in each memory cycle. The instruction is executed over one or more memory cycles before the instruction in all execution slots is completed. In the following description, the number of cache lines that can be accessed in one memory cycle is assumed to be 1. However, even when the number of cache lines that can be accessed in one memory cycle is 2 or more, a plurality of cache lines are selected in the determination of the cache line to be accessed By considering that only the relevant execution slot is valid for each cache line, the same processing can be performed. A specific procedure for address duplication confirmation will be described below under such constraints.

  When there is an overlap in the address, the processor core 100 keeps only one of the execution slots with the duplicate address “unprocessed”, and sets the other execution slots to “processed”. Set. At the same time, the processor core 100 writes a result (return value) indicating that the execution of the CAS instruction 2 has failed in the corresponding return value area for the execution slot set to “processed” due to address duplication.

(2) As a specific procedure example of address duplication confirmation, the following processing is executed.
The processor core 100 determines one execution slot to be executed based on the number assigned to the execution slot among the execution slots having overlapping addresses. More specifically, the processor core 100 extracts an execution slot having the smallest (or largest) execution slot number from the execution slots set to “unprocessed”, and the extracted execution slot. Is set as the address X. Then, the processor core 100 compares each address corresponding to another execution slot set to “unprocessed” with the address X, and temporarily selects an execution slot not on the same cache line as the address X. Disable to. Further, for each address in the same cache line, processing for determining an execution slot in which an instruction is to be executed is performed.

Typically, the number of addresses that can be simultaneously processed in the same cache line is determined by the cache line size and the data width of the atomic instruction. As shown in FIG. 3A, for example, when the cache line size is 64 bytes (2 ⁶ ) and the data width is 32 bits (= 4 bytes (2 ² )), The number of addresses that can be processed is 64/4 = 16 (2 ⁴ ). Numbers 0-15 are assigned in the order of these addresses, and a flag indicating the number of execution slots is provided for each number. As shown in FIG. 3B, each bit of the flag becomes “1” when the corresponding execution slot is an access to the address, and when it is different (that is, when the execution slot is invalid, or It is set to “0” when the address is not accessed.

  For the flag for each address thus determined, the smallest bit number that is “1” is the number of the execution slot that is allowed to access the address.

  If the number of execution slots that can be executed in parallel is small, a flag is not generated for each different address of the cache line, but the bits indicating the address in the cache line of the addresses corresponding to each execution slot are all compared. Thus, it may be implemented so as to eliminate duplication.

  Each execution slot is set to “processed” when the number of the execution slot permitted to access is determined from the flag of the address corresponding to the action address of the instruction and the number of the execution slot of the execution slot. A result (return value) indicating that the execution of Failed has been written to the corresponding return value area. On the other hand, for an execution slot which is an address on the same cache line and access to the address is permitted according to the flag state, the process proceeds to the subsequent processing.

  In this way, the processor core 100 enables only one of a plurality of accesses to the same address, and sets the other accesses to “processed” (however, execution of the CAS instruction 2 has failed). . In the example illustrated in FIG. 7, the processor core 100 writes the failure result value 233F into the return value area 223.

  Subsequently, for the CAS instruction 2 specified in the execution slot set to “unprocessed” (that is, enabled), the processor core 100 performs atomic processing (read / modify / write: read from the memory). Data reading, calculation of updated data, and writing of updated data to memory are executed ((3) atomic processing). The processor core 100 writes the result (return value) indicating the success obtained by reading data from the first memory into the corresponding return value area. Then, for each execution slot, the processor core 100 writes a success / failure result value indicating success or failure in the corresponding return value area based on the comparison result performed during the atomic processing of the CAS instruction 2. Then, the processor core 100 sets the execution slot in which the designated atomic process is completed to “processed”.

  In the example illustrated in FIG. 7, the processor core 100 writes the success / failure result values 231, 232, and 234 to the return value areas 221, 222, and 224 depending on the success or failure of the atomic processing of the CAS instruction 2.

  As described above, the processor core 100 executes the atomic process only in one execution slot among the CAS instruction 2 and the input data specified in the execution slot having the duplicate address, and returns the result of the execution. For the remaining execution slots, a result indicating that execution of the CAS instruction 2 has failed is returned without executing the atomic process. As shown in FIG. 7, in the first embodiment, the processor core 100 executes the CAS instruction 2 for the remaining execution slots before executing the instructions for one execution slot among the execution slots having overlapping addresses. Returns a result indicating that failed. First, by writing a failure result value indicating that execution of the CAS instruction 2 has failed, it is possible to simplify the process of confirming the subsequent unprocessed execution slot.

  However, for the sake of processing, the failure result value 233F may be written to the return value area 223 at the same time as the success / failure result values 231, 232, 234 are written to the return value areas 221, 222, 224.

  Then, the processor core 100 sets the execution slot temporarily invalidated to the “unprocessed” state, and determines whether or not there is an execution slot set to “unprocessed” ((4 ) Check for outstanding execution slots). In the SIMD instruction 200 according to the first embodiment, when there are a plurality of execution slots in which duplicate addresses are specified, only one execution slot is validated, and for other execution slots, “processing” "Completed" (ie, invalid).

  For this reason, at the time of executing a single SIMD atomic instruction, processing to the same address is required only once.

  As shown in FIG. 7, in the processing procedure of CAS instruction 2 according to the first embodiment, if there are execution slots in which duplicate addresses are designated among execution slots included in SIMD instruction 200, Atomic processing (typically, processing including access to memory) is executed for only one execution slot, and execution of CAS instruction 2 has failed for other execution slots without executing atomic processing. A result (return value) is returned. Thus, the repeated atomic process as shown in FIG. 2 is not executed. That is, before the atomic process is executed, address duplication is compared, and a result indicating that the CAS instruction 2 has been successfully executed or failed is returned based on the comparison result.

  FIG. 8 is a flowchart showing a processing procedure of the lock-free algorithm 300 using the CAS instruction 2 according to the first embodiment. The flowchart shown in FIG. 8 shows a part of processing of a program executed by the multi-core processor 10, and shows an example of code used in the program in association with each step.

  Referring to FIG. 8, processor core 100 prepares for data update (step S100). Specifically, the processor core 100 sets a variable% input for calculating post-update data from pre-update data stored at a specified address (code 302).

  Subsequently, the processor core 100 reads pre-update data (step S102). Specifically, the processor core 100 reads the pre-update data stored in the designated address (addressX) and sets the variable% old (code 304).

  Subsequently, the processor core 100 calculates updated data (step S104). Specifically, the processor core 100 calculates post-update data (variable% new) using the variable% old and the variable% input as parameters according to the specified arithmetic expression (code 306).

  Subsequently, the processor core 100 tries to write the updated data (step S110). Specifically, the processor core 100 executes CAS instruction 2 (atomic-compare-and-set2) to calculate data stored at a specified address (addressX) and updated data. The data before update (that is, the value of variable% old) is compared, and if the two data match, the data after update (that is, the value of variable% new) is written to the designated address (code 318). . The return value of the CAS instruction 2 (atomic-compare-and-set2) is a Boolean type, and when writing of the updated data is successful, “true (true)” is returned, otherwise “false ( False) ”. That is, if the data stored at the specified address in the current step and the pre-update data (that is, the value of the variable% old) used in calculating the updated data match, the variable% cond “True” is set, otherwise “false” is set in the variable% cond.

  If writing of the updated data is successful (in step S110, if variable% cond = true: code 320), the process ends. On the other hand, when the writing of the updated data fails (in the case of variable% cond == false in step S110: code 322), the processing in step S102 and subsequent steps is executed again. In this case, it means that another thread has changed the data at the target address while the post-update data is being calculated by the executing thread, and it is necessary to reread the pre-update data.

  Unlike the lock-free algorithm 300 # shown in FIG. 4, in the lock-free algorithm 300 using the CAS instruction 2 according to the first embodiment, the data before update stored in the specified address is not an atomic process. Reading is performed every time. This is because the CAS instruction 2 has a different specification regarding the return value from the CAS instruction 1, and the latest data for the memory cannot be acquired as the return value. However, since the pre-update data read process is not an atomic process, it can be accessed at a much higher speed by using a cache as compared to the atomic process. Further, even if there is another execution slot for designating a duplicate address, at the time of execution of CAS instruction 2 which is an atomic instruction, only one access is required, so that the processing load related to memory access increases. Absent.

(B7: The number of atomic processings of a plurality of execution slots for the same address when applied to the lock-free algorithm using the CAS-like instruction (CAS instruction 2) according to the first embodiment)
In the following description, for the sake of explanation, it is assumed that all different addresses are on the same cache line and can be processed in parallel. When different cache line addresses are included, the number of executions of the atomic process is calculated for each cache line, and the sum of all the numbers is the actual number of atomic processes.

(I) When the Number of Execution Slots is 4 FIG. 9 is a diagram for explaining changes in data stored in the memory during the execution process of the lock-free algorithm 300 shown in FIG. 8 (the number of execution slots is 4). If).

  FIG. 9 shows the operation when the SIMD instruction 200 including four atomic instructions is given to the multi-core processor 10 as in FIG.

  In the example shown in FIG. 9 as well, in the two instructions specified in the execution slots 201 and 203, “address A” is specified as the action address (corresponding to addressX in the code 318 in FIG. 8). And In this case, the instructions specified in the execution slots 201, 202, and 204 are executed in parallel, and the instruction specified in the execution slot 203 is assigned a failure result value 233F to “processed”. Is set. That is, with respect to the execution slot 203, “false (false)” indicating that the execution of the instruction has failed is returned as a return value (corresponding to the variable% cond in the code 318 in FIG. 8).

  When three processes (address duplication confirmation, atomic process, confirmation of unprocessed execution slot) indicated by reference numeral 240 in FIG. 9A are executed once, the execution of the first CAS instruction 2 is completed. . However, since the instruction set in the execution slot 203 is in a state where “false (false)” is set as a return value, the corresponding thread reads the pre-update data and calculates the post-update data. Then, an attempt to write updated data (steps S102, S104, S110 in FIG. 8) is executed again. By executing the data write attempt after update (step S110) again, the second CAS instruction 2 is executed as shown in FIG. 9B. Also in the second CAS instruction 2, the three processes indicated by reference numeral 240 (address duplication confirmation, atomic process, and confirmation of unprocessed execution slots) are executed once.

(Ii) When the Number of Execution Slots is 8 FIG. 10 is a diagram for explaining another example of change in data stored in the memory in the execution process of the lock-free algorithm 300 shown in FIG. If the number is 8).

  On the other hand, a case where CAS instruction 2 according to the first embodiment is used will be described. FIG. 10 shows the operation when the SIMD instruction 200 is given to the multi-core processor 10 as in FIG.

  Also in the example shown in FIG. 10, it is assumed that “address A” is designated as the action address in the execution slots 201, 203, and 206 (corresponding to addressX in the code 318 in FIG. 8). In each of the execution slots 204 and 208, “address C” is designated as an action address.

  When the three processes indicated by reference numeral 240 in FIG. 10A (address duplication confirmation, atomic process, and confirmation of an unprocessed execution slot) are executed once, the execution of the first CAS instruction 2 is completed. . Since the instructions set in the execution slots 203, 206, and 208 are all in a state in which “false” is set as a return value, the pre-update data is read, the post-update data is calculated, and the post-update An attempt to write data (steps S102, S104, and S110 in FIG. 8) is executed again. By executing the data write attempt after the update (step S110) again, the second CAS instruction 2 is executed as shown in FIG. 10B. Also in the second CAS instruction 2, the three processes indicated by reference numeral 240 (address duplication confirmation, atomic process, and confirmation of unprocessed execution slots) are executed once.

  Further, since the instruction set in the execution slot 206 is in a state where “false” is set as a return value, reading of pre-update data, calculation of post-update data, and writing of post-update data are attempted. (Steps S102, S104, and S110 in FIG. 8) are executed again. By executing the data write attempt after update (step S110) again, the third CAS instruction 2 is executed as shown in FIG. Also in the CAS instruction 2 for the third time, three processes indicated by reference numeral 240 (address duplication confirmation, atomic process, and confirmation of unprocessed execution slots) are executed once.

  As shown in FIG. 9, when address A overlaps in two execution slots, atomic processing (three processes indicated by reference numeral 240) is executed once by the first CAS instruction 2. Of the plurality of execution slots having overlapping addresses, the updated data is successfully written in only one execution slot. The second CAS instruction 2 is executed in a state where there is a number of address duplications obtained by subtracting 1 from the maximum duplication number N. However, in each execution of the CAS instruction 2, the atomic process (three processes indicated by reference numeral 240) is executed only once. As a result, when the first and second CAS instructions 2 are executed, each atomic process is executed once, and the total number of executions of the atomic process is two.

  In addition, as shown in FIG. 10, when address A overlaps in three execution slots and address C overlaps in two execution slots, atomic processing is performed with the first CAS instruction 2 (reference numeral 240). The three processes shown are executed once. Of the plurality of execution slots having overlapping addresses, the updated data is successfully written in only one execution slot. That is, the subsequent CAS instruction 2 is executed in a state where there is a number of address duplications obtained by subtracting 1 from the maximum duplication number N.

  As a result, when the first to third CAS instruction 2 is executed, each atomic process is executed once, and the total number of executions of the atomic process is three.

  As described above, when the lock-free algorithm 300 is executed once, the total number of executions of the atomic processing is N at a minimum. Here, N indicates the maximum overlapping number N of addresses included in the same SIMD instruction 200.

  In addition, when another thread that is executed independently accesses the same address at the same time, the number of processes further increases.

  In summary, when the maximum duplication number of addresses specified in a plurality of execution slots executed in parallel by the multi-core processor 10 is N, the lock-free algorithm 300 # using the CAS instruction 1 according to the related technology Under the condition that no external data is written, N × (N + 1) / 2 atomic processes are executed. In contrast, in the lock-free algorithm 300 using the CAS instruction 2 according to the first embodiment, N atomic processes are executed.

  The time required to execute the lock-free algorithm shown in FIGS. 4 and 8 is the time required to execute the process of reading the pre-update data (step S102) and the time required to write the post-update data (step S106, It can be estimated as the sum of S110).

  Here, the time for reading the pre-update data (the time required for executing step S102 in FIGS. 4 and 8) is t1. In addition, the address duplication confirmation process and the unprocessed execution slot confirmation process shown in FIGS. 2, 3, 6 to 9 are pipelined in the multi-core processor 10, so that the processing time is substantial. Can be ignored. Therefore, only atomic processing needs to be considered. Hereinafter, the time required for the atomic process is assumed to be t2.

  Therefore, the time T1 required to execute the lock-free algorithm 300 # shown in FIG. 4 can be expressed as the following equation (1).

T1 = t1 × 1 + t2 × N × (N + 1) / 2 (1)
Further, the time T2 required to execute the lock-free algorithm 300 shown in FIG. 8 can be expressed by the following equation (2).

T2 = (t1 + t2) × N (2)
Here, in the middle of the atomic process, a data reading process from the memory similar to the normal process occurs. Therefore, the time t2 required for the atomic process >> the data reading time t1 before the update is established. Here, the atomic processing requires a very high processing load compared to normal memory access (data reading processing from the memory) in consideration of the load on the bus and the like. For this reason, the time t2 required for the atomic process is a sufficiently large value compared to the read time t1 of the pre-update data.

Examining the equations (1) and (2), the following is obtained.
(I) When the maximum overlap number N = 1 T1 = t1 + t2 × 1 × 2/2 = t1 + t2
T2 = (t1 + t2) × 1 = t1 + t2 = T1
(Ii) When the maximum overlap number N = 2 T1 = t1 + t2 × 2 × 3/2 = t1 + 3 × t2
T2 = (t1 + t2) × 2 = t1 × 2 + t2 × 2 = T1 + (t2−t1)> T1
Therefore, T2 <T1 is always established when the maximum overlap number N ≧ 2. That is, if there is an overlap between addresses specified in a plurality of execution slots executed in parallel in multi-core processor 10, the execution time of lock-free algorithm 300 according to the present embodiment is the lock-free algorithm according to the related technology. This means that it can be shortened from the execution time of 300 #.

  As described above, by using CAS instruction 2 that is an atomic instruction according to the first embodiment, the implementation of the lock-free algorithm can be further optimized. By this optimization, the same lock-free algorithm can be realized with a smaller number of executions of the atomic process as compared with the case where the CAS instruction 1 which is an atomic instruction according to the related art is used.

<C. Second Embodiment>
In the CAS instruction 2 according to the first embodiment described above, a result indicating success or failure is returned as a return value, but a plurality of results may be returned. Hereinafter, in the second embodiment, a CSW instruction that returns a plurality of results in accordance with the external operation specifications of the “atomic :: compare_exchange_weak” function defined in the C ++ (ISO / IEC 14882: 2011) core language (hereinafter, The instruction is also described as “atomic-compare-swap-weak”).

  Since the computer on which the CSW instruction according to the second embodiment is implemented and the multi-core processor included in the computer are the same as those in the first embodiment, detailed description will not be repeated.

  When a SIMD instruction in which a plurality of CSW instructions that are atomic instructions are specified in each execution slot is given to the multi-core processor 10, it is determined whether or not there is an overlap in the addresses accessed by the execution slots that are simultaneously processed. When there are a plurality of execution slots in which overlapping addresses are specified, only one execution slot is validated, and the other execution slots are invalidated. In other words, when there are execution slots in which duplicate addresses are designated, atomic processing (typically, processing including access to the memory) is executed for only one execution throttle, and for other execution slots Returns a result (return value) indicating that the execution of the instruction has failed without executing the atomic process.

  For the execution slot where the atomic processing is actually executed, a result (flag value) indicating whether or not the instruction has been successfully executed is returned as a result 1, and data (value) read at the time of the atomic processing is returned as a result 2. Is returned. As described above, the multi-core processor 10 uses the value read from the designated address as the further result (result 2) after executing the instruction in one execution slot among the atomic instructions designated in the execution slot having the duplicate address. return.

  For an execution slot that is not executing an atomic process, a result (flag value) indicating that the execution of the instruction has failed is returned as result 1. As a result 2 for an execution slot that is not executing an atomic process, (1) if the result 1 of the execution slot in which the atomic process is actually executed indicates success, the instruction in the execution slot is written to the memory. Data (value) is returned, and (2) if the result 1 of the execution slot in which the atomic process is actually executed indicates failure, the value read from the memory by the one execution slot during execution of the instruction (ie, , The same value as the result 2 of the executed execution slot) is returned.

  As described above, when the executed one of the remaining atomic instructions that are not executed among the atomic instructions specified in the execution slots having overlapping addresses is successfully executed, The value written by the atomic instruction is returned as a further result (result 2). On the other hand, when the execution of one executed atomic instruction fails, the multi-core processor 10 returns the value read by the one atomic instruction as a further result (result 2).

  FIG. 11 is a schematic diagram for describing a processing procedure of an atomic instruction according to the second embodiment. Referring to FIG. 2, SIMD instruction 200 given to multi-core processor 10 includes four execution slots 201-204 (slot0-slot3). In this example, it is assumed that a CSW instruction according to the second embodiment is designated in each of execution slots 201-204.

  When the execution of the SIMD instruction 200 is started ((1) instruction execution start), a flag area for storing the result 1 and the result 2 for each execution slot is initialized. When the initialization is completed, the processor core 100 specifies an execution slot that is simultaneously processed among execution slots that are set to “unprocessed”, and there is an overlap in addresses accessed by the execution slots that are simultaneously processed. ((2) Address duplication check). That is, the processor core 100 determines whether there is the same address corresponding to the execution slot. Then, the processor core 100 validates only one of a plurality of accesses to the same address and sets other accesses to “processed”. In the example illustrated in FIG. 7, the processor core 100 writes the failure result value 233F in the flag area corresponding to the execution slot 203. That is, the processor core 100 returns a result indicating that the execution of the instruction has failed as a result 1 of the CSW instruction specified in the execution slot 203.

  Subsequently, the processor core 100 executes an atomic process (CSW instruction) for the instruction specified in the execution slot set to “unprocessed” (that is, enabled) ((3) atomic processing). At this time, the processor core 100 returns each data (value) read at the time of atomic processing as the result 2 of each CSW instruction specified in the execution slots 201, 202, and 204.

  Subsequently, the processor core 100 determines whether or not each of the data stored at the specified address and the pre-update data match as the result 1 of each of the CSW instructions specified in the execution slots 201, 202, and 204. In response to this, a result (flag value) indicating that the execution of the instruction has succeeded or failed is returned ((4) generation of result 1).

  Further, the processor core 100 designates the execution slot 201 as the result 2 of the CSW instruction set in the execution slot 203 that is not executed due to the duplication of the address according to the processing result of the execution slot 201 having the same address. Data (value) written by the executed CSW instruction (when success is returned as the result 1 of the execution slot 201), or the same data (value) as the result 2 of the CSW instruction specified in the execution slot 201 ( (When failure is returned as the result 1 of the execution slot 201)) ((5) generation of the result 2).

  When the atomic process is executed once in this way, the execution of the SIMD instruction 200 ends.

  FIG. 12 is a flowchart showing a processing procedure of the lock-free algorithm 350 using the CSW instruction according to the second embodiment. The flowchart shown in FIG. 12 shows a part of processing of a program executed by the multi-core processor 10, and shows an example of code used in the program in association with each step.

  Referring to FIG. 12, processor core 100 prepares for data update (step S100). Specifically, the processor core 100 sets a variable% input for calculating post-update data from pre-update data stored at a specified address (code 302).

  Subsequently, the processor core 100 reads pre-update data (step S102). Specifically, the processor core 100 reads the pre-update data stored in the designated address (addressX) and sets the variable% old (code 304).

  Subsequently, the processor core 100 calculates updated data (step S104). Specifically, the processor core 100 calculates post-update data (variable% new) using the variable% old and the variable% input as parameters according to the specified arithmetic expression (code 306).

  Subsequently, the processor core 100 tries to write updated data (step S120). Specifically, the processor core 100 uses a CSW instruction (atomic-compare-swap-weak) to calculate data stored at a specified address (addressX) and updated data. The data before update (that is, the value of variable% old) is compared, and if the two data match, the data after update (that is, the value of variable% new) is written to the designated address (code 328). The result 1 of the CSW instruction (atomic-compare-swap-weak) is set to the variable% cond, and the result 2 is set to the variable% old.

  If writing of the updated data is successful (in step S120, variable% cond = true: code 330), the process ends. On the other hand, when the writing of the updated data has failed (in the case of variable% cond == false in step S120: code 332), the processing from step S104 onward is executed again. If writing of the updated data fails, each data (value) read at the time of the atomic process is returned as a result 2. Therefore, it is not necessary to re-read the data before updating (step S102). If execution of the CSW instruction fails, it means that another thread has changed the data at the target address, but it is not necessary to re-read the data before update, and an increase in processing load related to memory access can be suppressed. .

  The CSW instruction according to the second embodiment complies with the operation of a function prepared in a standard programming language (for example, C ++ core language), although the circuit area required for hardware implementation increases. Therefore, the CSW instruction according to the second embodiment can be used without modifying an existing program. Further, when the lock-free algorithm as shown in FIG. 12 is implemented, it is possible to reduce the addition of memory access (reading process of pre-update data) in the loop process.

  In the CSW instruction according to the second embodiment, the data (value) returned as the result 2 for the execution slot that is not executing the atomic process changes according to the result 1 of the execution slot in which the atomic process is actually executed. This is to realize an interface in which each execution slot is executed in series, and programming can be facilitated by preparing such an interface.

<D. Embodiment 3>
Next, a configuration in which the atomic processing according to the present embodiment is implemented in a shared memory type (NUMA: Non-Uniform Memory Access) multiprocessor computer system will be described as a third embodiment.

  FIG. 13 is a schematic diagram showing a device configuration of a computer 1A according to the third embodiment. Referring to FIG. 13, computer 1A according to the third embodiment includes two multi-core processors 10-1, 10-2, external memories 180-1, 180-2, and external devices 190-1, 190-2. including. The multi-core processor 10-1 and the multi-core processor 10-2 are connected to each other via a processor interconnect bus 144 so that data can be exchanged.

  It is assumed that atomic instructions (CAS instruction 2 and / or CSW instruction) according to the first embodiment are implemented in multi-core processors 10-1 and 10-2 (that is, processor cores 100-1 to 100-4). .

  The multi-core processor 10-1 has processor cores 100-1 and 100-2, and the multi-core processor 10-2 has processor cores 100-3 and 100-4. The processor cores 100-1 and 100-2 can access the shared cache 110-2 in the multi-core processor 10-2 via the processor interconnect bus 144. Similarly, the processor cores 100-3 and 100-4 can access the shared cache 110-1 in the multi-core processor 10-1 via the processor interconnect bus 144.

  When it is necessary to access a memory area connected to a multicore processor 10 different from the multicore processor 10 executing a certain instruction, the time required for executing the atomic process becomes longer. That is, while a certain processor core 100 is executing an atomic instruction, a specified address X is shared memory ("remote memory") connected to a processor core 100 different from the processor core 100 executing the atomic instruction. If it exists in the area), it is accessed via the processor interconnect bus 144.

  That is, during the atomic process, data reading (read) from the remote memory area and writing (write) to the remote memory area are executed via the processor interconnect bus 144. As a result, the occupation time of hardware resources increases, and the time required for atomic processing itself also increases. That is, the number of executions of atomic processing itself has a greater influence on performance.

  In other words, the performance improvement effect by implementing the CAS instruction 2 according to the first embodiment and / or the CSW instruction according to the second embodiment is the same as that of the shared memory type multiprocessor computer system shown in FIG. Becomes more prominent.

  Since other configurations are the same as those of computer 1 shown in FIG. 1, detailed description will not be repeated.

<E. Embodiment 4>
Next, a configuration in which the atomic processing according to the present embodiment is implemented in a multiprocessor computer system provided with a local storage for each processor core will be described as a fourth embodiment. Such a configuration in which a local storage is provided for each processor core is typically applied to an image processing engine (GPU) or the like.

  FIG. 14 is a schematic diagram showing a device configuration of a computer 1B according to the fourth embodiment. Referring to FIG. 14, computer 1B according to the fourth embodiment includes a multi-core processor 10B, an external memory 180, and an external device 190.

  The multi-core processor 10B includes a plurality of processor cores 100-1 and 100-2, a shared cache 110, a memory controller 120, and an IO controller 130. The processor cores 100-1 and 100-2 are connected to local storages 102-1 and 102-2 (hereinafter also collectively referred to as “local storage 102”) via storage buses 104-1 and 104-2, respectively. Is done. FIG. 14 illustrates a configuration including two processor cores 100 for convenience of explanation, but the number of processor cores 100 is not particularly limited.

  In the computer 1B, a local storage 102 corresponding to each processor core 100 is mounted as hardware. The memory area of the local storage 102 can be shared only between specific threads. In other words, the memory area of the local storage 102 does not need to be shared between the processor cores 100. Further, the required memory capacity of the local storage 102 is limited. For this reason, each local storage 102 is arranged in the immediate vicinity of each processor core 100.

  The multi-core processor 10B as shown in FIG. 14 can realize, for example, a platform similar to a local address space in OpenCL (Open Computing Language).

  In the multi-core processor 10B as shown in FIG. 14, it is preferable to adopt a multi-bank configuration so that data is stored in a different bank for every predetermined number of adjacent data (for example, every 32 bits). By adopting such a multi-bank configuration, parallel memory access performance equivalent to the data parallelism handled by the processor core 100 can be realized even during random access.

  FIG. 15 is a schematic diagram showing a configuration example of the local storage 102 shown in FIG. Referring to FIG. 15, each local storage 102 includes a plurality of bank memories 1021, 1022, 1023, and 1024. For convenience of explanation, FIG. 15 shows a configuration example including four bank memories, but any number of bank memories may be used.

  The storage bus 104 (see FIG. 14) is parallelized corresponding to the number of bank memories so that the processor core 100 can access the bank memories 1021, 1022, 1023, and 1024 in parallel. A processing procedure for memory access when an atomic instruction (CAS instruction 2) according to the first embodiment is executed in computer 1B according to the fourth embodiment shown in FIG. 14 will be described.

  FIG. 16 is a flowchart for illustrating a memory access processing procedure in computer 1B according to the fourth embodiment shown in FIG. The processing procedure shown in FIG. 16 is executed in parallel for each bank memory. FIG. 17 is a schematic diagram showing an example of the data structure of the access flag 108 used in the processing procedure defined by the flowchart of FIG.

  Referring to FIG. 16, processor core 100 updates access flag 108 indicating whether or not an instruction specified in each execution slot requests access to which bank memory (step S200). ). As shown in FIG. 17, as many access flags 108 as the number of execution slots are provided for each bank memory. That is, the access flag 108 can store at least as many flags as the product of the number of bank memories and the number of execution slots.

Thereafter, steps S202 to S216 are executed in parallel by the number of bank memories.
The processor core 100 determines whether or not there is an execution slot requesting access to the target bank memory in the access flag 108 updated in step S200 (step S202). That is, it is determined whether or not any of the flags of the target bank memory is set to “true (true)” or “1”. If there is no execution slot requesting access to the target bank memory (NO in step S202), the process proceeds to step S220.

  If there is an execution slot that requests access to the target bank memory (YES in step S202), the processor core 100 requests access to the target bank memory (typically, One execution slot is selected from the execution slots set to “true (true)” or “1” (step S204). Let n be the slot number of the selected execution slot.

  Subsequently, the processor core 100 determines whether or not there is another execution slot that specifies the same address as the address specified in the selected execution slot (step S206). More specifically, the processor core 100 sets the address specified in the selected execution slot as the address X, and for each of the other execution slots in which access to the same bank memory is specified. The designated address is compared with the address X. That is, “true (true)” or “1” is set for the target bank memory in the access flag 108 and the slot number of the execution slot is not n, the designated address and Address X is compared.

  If there is another execution slot that specifies the same address as that specified for the selected execution slot (YES in step S206), processor core 100 specifies the same address in access flag 108. The flags corresponding to the other execution slots are rewritten to “false” or “0” (step S208). At the same time, the processor core 100 writes a result (return value) indicating that the instruction execution has failed into the return value area corresponding to the other execution slot (step S210).

  If there is no other execution slot that specifies the same address as the address specified for the selected execution slot (NO in step S206), the processing in steps S208 and S210 is skipped.

  Subsequently, the processor core 100 executes the CAS instruction 2 according to the first embodiment on the data stored in the address X designated in the execution slot of the slot number n selected in the target bank memory. (Step S212). That is, the processor core 100 reads data from the designated address X of the target bank memory, compares the read data with the old data, and writes new data to the memory only when the two data match. The process is executed. Then, the processor core 100 writes the comparison result between the read data and the old data in the corresponding return value area as the execution result (return value) (step S214). Then, the processor core 100 rewrites the flag corresponding to the execution slot of the slot number n of the target bank memory to “false” or “0” in the access flag 108 (step S216). And the process after step S202 is repeated.

  In step S220, the number of bank memories determined to have no execution slot requesting access is managed. If there is no execution slot requesting access for all bank memories (YES in step S220), the execution of the instruction ends. That is, in the access flag 108, when there is no flag set to “true (true)” or “1” for all the bank memories, the execution of the instruction ends.

  Through the processing as described above, the atomic instruction according to the first embodiment can be realized even when a local storage having a multi-bank configuration is adopted. Since the CSW instruction according to the second embodiment can be implemented in the same manner as described above, detailed description will not be repeated.

<F. Embodiment 5>
Next, as a fifth embodiment, a configuration in which atomic processing according to the present embodiment is implemented using microcode (a kind of firmware) will be described. FIG. 18 is a schematic diagram showing a hardware configuration related to the computer according to the fifth embodiment.

  In the hardware configuration as shown in FIG. 14 and FIG. 15, in order to execute atomic processing in parallel for each of a plurality of memory banks, the same number of atomic operation units as the memory banks are provided in association with each memory bank. Is preferred. More specifically, as shown in FIG. 18A, the same number of atomic calculators 1001 to 1004 are provided in the processor core 100 in association with the bank memories 1021 to 1024 in the local storage 102.

  On the other hand, the hardware configuration as shown in FIG. 8A has a drawback that the mounting cost increases. In this case, a single atomic calculator 1006 is provided for the bank memories 1021 to 1024 as shown in FIG. 8B, and one bank memory is selected at each timing among the bank memories 1021 to 1024. A mechanism to access only the software is implemented in software.

  For example, a lock mechanism for locking access to an arbitrary bank memory may be implemented. Specifically, a special register that indicates the lock state by this lock mechanism is provided, and a set of instructions that access the special register and read its value and a special memory write instruction that releases the lock To do. The atomic processing may be realized by using the set of instructions and locking the access to a specific bank memory and executing a normal operation instruction.

  FIG. 19 is a diagram illustrating an example of microcode for realizing atomic processing. FIG. 19A shows an example of microcode corresponding to CAS instruction 1 according to the related art, and FIG. 19B shows an example of microcode corresponding to CAS instruction 2 according to the first embodiment. FIG. 19 shows a code example in the case of using a pseudo instruction according to the Fermi architecture of NVIDIA Corporation (Santa Clara, California, USA).

  In microcode 400A shown in FIG. 19A, loop processing shown in the drawing is executed until execution of atomic processing is completed for all threads. In the microcode 400A, the instruction “SEL% out,% new,% ret, P1” instructs execution of the CAS instruction 1. The LDSLK instruction shown in FIG. 19A can only lock at most one execution slot with respect to a plurality of execution slots in which memory banks designated as access destinations overlap each other. For this reason, an instruction designated in a memory slot different from the target memory slot is awaited until the next loop processing.

  On the other hand, in microcode 400B shown in FIG. 19B, loop processing is executed using CAS instruction 2 according to the first embodiment. In the microcode 400B, the instruction “SEL% out,% new,% ret, P1” instructs the execution of the CAS instruction 2.

  In the microcode 400B, the instruction “XXX% addrX, P0,% addr” (reference numeral 402 in FIG. 19B) is stored in the same memory bank as the variable% addr in the variable P0 == true (true). This is an instruction for setting an address (variable% addr) as an address X (variable% addrX). In other words, this corresponds to the pre-processing of the process (reference numeral 404 in FIG. 19B) for executing a determination as to whether or not there remains an overlapping memory address.

  Since the CSW instruction according to the second embodiment can be implemented in the same manner as described above, detailed description will not be repeated.

<G. Summary>
In a general SIMD / SIMT type processor, when executing a CAS instruction used for performing complex atomic processing, the execution of a plurality of instructions having overlapping addresses is serialized in the same manner as in normal atomic processing. To avoid access conflicts. Adopting such serialization results in an increase in wasted memory access and a performance bottleneck.

  The inventor of the present application has found such a new problem, and has adopted the following means for solving the problem. That is, when an atomic CAS instruction is simultaneously executed by a plurality of threads processed in parallel by hardware, only one thread is processed at most for a single address. For a thread that has been successfully executed, a result indicating success is returned. For other threads, serialization processing is not performed, and a result indicating failure is immediately returned.

  As described above, by adding a state specific to the SIMT type processor for the condition indicating that the execution of the instruction has failed, it is possible to reduce the frequency of atomic memory access, and a performance bottleneck in the SIMT type processor. The bottleneck can be eliminated. That is, by adding such an atomic instruction, the performance of the processor can be improved.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10, 10B, 10-1, 10-2 Multi-core processor, 100 processor core, 102 local storage, 104 storage bus, 108 access flag, 110 shared cache, 120 memory controller, 130 controller, 140, 150 internal bus, 144 processor interconnect Bus, 160 External memory bus, 170 External device bus, 180 External memory, 190 External device, 200, 200 # SIMD instruction, 201-208 Execution slot, 211-214 Flag area, 221-224 Return value area, 1001-1004 1006 Atomic computing unit, 1021-1024 bank memory.

Claims (5)

A SIMD (Single Instruction Multi Data) processor capable of executing in parallel and having a plurality of execution slots to enable the same instruction to be simultaneously applied to a plurality of data,
The same instruction reads data stored at an address designated for each execution slot, and writes the data to the designated address when the read data satisfies a predetermined condition. Includes atomic instructions to execute while maintaining atomicity,
When the atomic instruction is executed, the processor
Identify the execution slot where the specified address is duplicated among the execution slots corresponding to the atomic instruction,
An instruction is executed in one execution slot among the execution slots having the same address, the result of the execution is returned, and the instruction execution failed for the remaining execution slots without executing the instruction. A processor that returns a result indicating   2. The processor according to claim 1, wherein the processor returns a result indicating that the execution of the instruction has failed for the remaining execution slots before executing the instruction of one execution slot among the execution slots having the same address. Processor. The processor is
A value read from a specified address is returned as a further result after executing an instruction in one execution slot among the execution slots having the same address,
For the remaining execution slots,
If execution of an instruction in one execution slot among the execution slots having the same address is successful, the value written in the memory by the instruction in the one execution slot is returned as a further result,
2. When the instruction execution in one execution slot among the execution slots having the same address fails, the value read from the memory during the execution of the instruction by the one execution slot is returned as a further result. The processor according to 2.   4. The processor according to claim 1, wherein the processor determines one execution slot to be executed based on a number assigned to the execution slot among execution slots having the same address. 5. Processor.   The processor according to any one of claims 1 to 4, wherein the processor includes a plurality of processor cores and a memory shared among the plurality of processor cores.