JP2017027156A - Arithmetic processing device and method for controlling arithmetic processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the access latency of a cache memory in an arithmetic processing device having a plurality of banks and a cache memory shared by a plurality of arithmetic units.SOLUTION: The arithmetic processing device has: a plurality of cores 11; a last level (LL) cache memory having a plurality of banks shared by the plurality of cores; a pipeline selection unit <1>15 for selecting a request to be outputted from other than requests for new data from the cores among requests to the cache memory; and pipeline selection units <2>17-1, 17-2 for selecting, for each bank of the cache memory, a request from requests for new data and requests selected by the pipeline selection unit <1> and outputting the selected request to the pipeline of the LL cache memory. The pipeline selection units <2> are placed at positions closer to the cache memory than is the pipeline selection unit <1>, and thereby a path in which signals pertaining to requests for new data is shortened and the access latency of the LL cache memory is improved.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an arithmetic processing device and a control method for the arithmetic processing device.

  The cache memory is used for storing request data from the arithmetic processing unit of the processor to improve performance. The processor generally includes a plurality of cores (arithmetic units) and an LL (Last Level) cache memory shared by the plurality of cores (arithmetic units). Each core (arithmetic unit) has a high-speed and small-capacity primary (level 1) cache memory (which may also have a secondary (level 2) cache memory, etc.) that can be directly accessed from the arithmetic processing pipeline. When a cache miss occurs in the primary cache memory, the LL cache memory is accessed.

  An example of a conventional processor layout is shown in FIG. FIG. 9 shows an example having four cores (core <0> to core <3>) and one bank of LL cache memory shared by the four cores. Each core 901 includes a calculation unit and a primary (level 1) cache memory. The LL cache memory includes an LL (last level) cache tag unit 906 and an LL (last level) cache data unit 907. The external port 908 is an interface for requests to communicate with the outside of the processor.

  For example, a path through which a signal (request, data, etc.) when requested data from the core <3> 901 hits a cache hit in the LL cache memory is shown by a broken line in FIG. That is, core <3> 901 → port (various ports 903) which is an interface for various requests from the core → pipeline selection unit 905 of the pipeline control unit 904 that determines a request from the core to be pipelined according to priority. → LL cache tag part 906 → LL cache data part 907 → core <3> 901.

  In recent processors, the number of cores (arithmetic units) tends to increase to improve performance, and the capacity of the LL cache memory also increases to maintain the cache hit rate. Accordingly, in order to use the LL cache memory efficiently, a method of dividing the LL cache memory as shown in FIG. 10 into a plurality of banks is used. FIG. 10 is a diagram showing a layout example of a conventional processor in which the LL cache memory is divided into a plurality of banks. 10, components having the same functions as those shown in FIG. 9 are given the same reference numerals.

  FIG. 10 shows an example in which the LL cache memory has two banks, that is, one bank having an LL cache tag unit 906-1 and an LL cache data unit 907-1, an LL cache tag unit 906-2, and an LL cache data unit. An example is shown in which two banks are included, one bank having 907-2. A path through which a signal (request, data, etc.) when requested data from the core <7> 901 hits a cache hit in the LL cache memory is indicated by a broken line.

  In an SMT (Simultaneous Multi Thread) type processor, a cache control technique for controlling an access request to a cache memory shared by threads executed simultaneously has been proposed (see Patent Document 1). In Japanese Patent Laid-Open No. 2004-228688, a process for selecting an access request from access requests issued by a thread held by a port unit by controlling the port unit holding the access request so as to be divided according to the thread configuration is used. By doing so, the resources required for the access processing can be efficiently used to execute the access processing to the cache memory.

International Publication No. 2008/155822

  As shown in an example in FIG. 10, when the LL cache memory shared by a plurality of cores is divided into a plurality of banks, considering the distance to access each bank of the LL cache memory, etc., it is input to the pipeline The pipeline selection unit 905 that selects a request to be performed is normally arranged at the center of the pipeline control unit 904. Therefore, as the number of banks of the LL cache memory is increased, the physical distance between the pipeline selection unit of the pipeline control unit and the LL cache tag unit of the LL cache memory is increased, and the access latency of the LL cache memory is deteriorated. Invite.

  In one aspect, an object of the present invention is to improve an access latency of a cache memory in an arithmetic processing unit having a plurality of banks and having a cache memory shared by a plurality of arithmetic units.

  One aspect of the arithmetic processing device includes a plurality of arithmetic units, a plurality of banks, a cache memory shared by the plurality of arithmetic units, and a request other than the first request from the arithmetic unit among requests for the cache memory A first selection unit that selects a request to be output from the requests and a request selected from the first request and the request selected by the first selection unit for each bank of the cache memory, And a second selection unit that outputs to the pipeline. The second selection unit is arranged at a position closer to the cache memory than the first selection unit.

  In one aspect of the invention, the first request and the second selection unit for selecting and outputting the request from the request selected by the first selection unit are arranged in the vicinity of the cache memory, thereby providing the first request. The path through which the signal flows can be shortened, and the access latency of the cache memory can be improved.

It is a figure which shows the example of the layout of the arithmetic processing unit in embodiment of this invention. It is a figure which shows the structural example of the pipeline selection part in this embodiment. It is a figure for demonstrating access to the cache memory in this embodiment. It is a figure for demonstrating access to the cache memory in a prior art. It is a figure for comparing the access latency of the cache memory in this embodiment and a prior art. It is a figure which shows the example of the throughput improvement in the arithmetic processing unit in this embodiment. It is a figure which shows the operation example of the pipeline selection part in this embodiment. It is a figure which shows the comparative example of the pipeline slot in this embodiment and a prior art. It is a figure which shows the other example of the layout of the arithmetic processing unit in this embodiment. It is a figure which shows the layout of the conventional processor. It is a figure which shows the layout of the conventional processor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an example of the layout of a processor as an arithmetic processing unit according to an embodiment of the present invention. The processor according to the present embodiment includes a plurality of cores (arithmetic units) and a cache memory having a plurality of banks shared by the plurality of cores. FIG. 1 shows an example having eight cores (core <0> to core <7>) and two banks of LL (last level) cache memory shared by the eight cores.

  Each core 11 includes an arithmetic unit that performs arithmetic processing and the like and a primary (level 1) cache memory. Each core 11 may further include a secondary (level 2) cache memory. In the LL cache memory, the LL cache tag unit 18-1 and the LL cache data unit 19-1 constitute one bank, and the LL cache tag unit 18-2 and the LL cache data unit 19-2 include One bank is configured. In the LL cache tag units 18-1 and 18-2, tags of data stored in the LL cache data units 19-1 and 19-2 (information indicating data addresses, data states, and the like) are stored. .

  The core 11 (core <0> to core <7>) and the LL cache memory (LL cache tag units 18-1 and 18-2 and LL cache data units 19-1 and 19-2) are connected via the transfer bus 12. It is connected so that it can communicate. Access to the LL cache memory based on a request from the core 11 (core <0> to core <7>) or a request from outside the processor is a pipeline that performs pipeline control such as request reception, selection, and tag search. It is executed by the control unit 14.

  The processor according to the present embodiment includes new request ports 16-1 and 16-2 which are interfaces for new data requests (new requests) having the highest request frequency among requests from the core 11, and requests from the core 11. And various ports 13 which are interfaces for various requests other than new requests. Requests from the core 11 other than new requests include, for example, a snoop response for rewriting data. In addition, the processor according to the present embodiment has an external port 20 that is an interface for requests to communicate with the outside of the processor.

  In this embodiment, the pipeline selection unit in the pipeline control unit 14 includes a pipeline selection unit <1> 15 that selects a request to be output from requests other than the new request, and a new request and pipeline selection unit. <1> Select one of the requests selected by 15 as a pipeline input request, and select the pipeline selection units <2> 17-1 and 17-2 to be passed to the LL cache tag units 18-1 and 18-2. Have. The pipeline selection unit <1> 15 and the pipeline selection units <2> 17-1 and 17-2 select requests according to preset priorities.

  FIG. 2 is a diagram illustrating a configuration example of the pipeline selection units 15 and 17 in the present embodiment. In this embodiment, the request ports to be entered into the pipeline are four ports, that is, a new request port, a snoop response port, a load buffer port, and an external snoop port, and the priority of entry is the highest in the snoop response port. , Load buffer port, external snoop port, and the new request port is the lowest. The pipeline selection unit <1> 15 includes AND (logical product operation) circuits 201, 202, and 203 and a selection circuit 204. The pipeline selection unit <2> 17 includes an AND circuit 206 and a selection circuit 207.

  The AND circuit 201 receives a snoop response port signal SRPT and a snoop response port suppression signal SRPT_INH. The AND circuit 202 receives the load buffer port signal LDPT, the load buffer port suppression signal LDPT_INH, and the snoop response port signal SRPT. The AND circuit 203 also receives the external snoop port signal OSPT, the external snoop port suppression signal OSPT_INH, the snoop response port signal SRPT, and the load buffer port signal LDPT. The selection circuit 204 selectively outputs the outputs of the AND circuits 201, 202, and 203.

  The AND circuit 206 receives the output of the AND circuit 205 to which the new request port signal RQPT and the new request port suppression signal RQPT_INH are input, and the output of the selection circuit 204 of the pipeline selection unit <1> 15. . The selection circuit 207 selectively outputs the output of the selection circuit 204 and the output of the AND circuit 206 of the pipeline selection unit <1> 15.

  Here, the signals SRPT, LDPT, OSPT, and RQPT are “1” when there is a request for each port, and “0” when there is no request. The signals SRPT_INH, LDPT_INH, OSPT_INH, and RQPT_INH are signals that are set to “1” when the request timing is not appropriate for each port. For example, if the memory read takes 4 cycles in total, the next output is output until 4 cycles elapse (the previous memory read is completed) when the next memory read signal comes within 3 cycles. It is a signal to be suppressed.

  The pipeline selection unit <1> 15 having the configuration shown in FIG. 2 has a snoop response port signal SRPT of “1” and a snoop response port suppression signal SRPT_INH of “0” (input state 1). Outputs a snoop response request. When the snoop response port signal SRPT is “0”, the load buffer port signal LDPT is “1”, and the load buffer port suppression signal LDPT_INH is “0” (input state 2), the load buffer Output the request. Further, the signal SRPT of the snoop response port is “0”, the signal LDPT of the load buffer port is “0”, the signal OSPT of the external snoop port is “1”, and the suppression signal OSPT_INH of the external snoop port is “1”. When 0 "(input state 3), an external snoop request is output. If none of the input state 1, input state 2, or input state 3 described above, the pipeline selection unit <1> 15 does not output a request.

  Also, the pipeline selection unit <2> 17 having the configuration shown in FIG. 2 selects the pipeline when the pipeline selection unit <1> 15 outputs any of the snoop response, load buffer, and external snoop requests. The request output by the part <1> 15 is output. Further, the pipeline selection unit <1> 15 does not output any of the snoop response, the load buffer, and the external snoop request, the signal RQPT of the new request port is “1”, and the suppression signal of the new request port When RQPT_INH is “0”, a new request is output. In other cases, the pipeline selection unit <2> 17 does not output a request.

  Thus, in the present embodiment, the pipeline selection unit <1> 15 and the pipeline selection units <2> 17-1, 17-2 are arranged, and the pipeline selection unit <1> 15 makes requests other than new requests. The pipeline selection units <2> 17-1 and 17-2 select either a new request or the request selected by the pipeline selection unit <1> 15 to select the LL cache tag units 18-1 and 18 -2. In addition, as request interfaces from the core 11, new request ports 16-1 and 16-2 for new requests and various ports 13 for requests other than new requests are provided separately.

  As a result, as shown in FIG. 1, the new request ports 16-1 and 16-2 and the pipeline selection units <2> 17-1 and 17-2 are connected to the LL cache tag more than the pipeline selection unit <1> 15. It becomes possible to arrange in the vicinity near the parts 18-1 and 18-2. Therefore, for example, as shown by the broken line in FIG. 1, the request data from the core <7> 11 is cache hit in the bank constituted by the LL cache tag unit 18-2 and the LL cache data unit 19-2 of the LL cache memory. In this case, since there is no need to go through the center of the pipeline control unit 14 as in the prior art, the path through which the signal flows is shortened, and the access latency of the LL cache memory can be shortened. Note that, for example, the request data from the core <7> 11 is cache hit in a bank configured with the LL cache tag unit 18-1 and the LL cache data unit 19-1 far from the core <7> 11 in the LL cache memory. Even so, since the path through which the signal flows is the same distance as the path through the center of the conventional pipeline control unit 14, the access latency of the LL cache memory does not deteriorate.

  With reference to FIG. 3A and FIG. 3B, access to the LL cache memory in this embodiment will be described. FIG. 3A is a diagram for explaining access to the LL cache memory in the present embodiment, and FIG. 3B is a diagram for explaining access to the LL cache memory in the conventional processor shown in FIG. . 3A and 3B, each of the periods ST1, ST2, ST3, ST4, ST5, and ST6 corresponds to one cycle period of the operating frequency of the processor.

  As shown in FIG. 3B, in the conventional processor shown in FIG. 10, a new request from the core 301 is input to the new request port 361 corresponding to each core in the period ST2. Then, in the next cycle period ST3, the oldest new request is selected and output by the LRU (Least Recently Used) control unit 371. In the next period ST4, when selected by the pipeline selection unit 381 that selects a request to enter the pipeline according to a predetermined priority, the LL cache tag unit 351 is reached in the period ST6. The period ST5 is provided as a period required for transfer between the pipeline selection unit 381 and the LL cache tag unit 351.

  Similarly, a snoop response request from the core 301 is input to the snoop response port 362 corresponding to each core in the period ST2, and the oldest snoop response request is received by the LRU control unit 372 in the period ST3 of the next cycle. Is selected and output. Subsequently, when selected by the pipeline selection unit 381 in the period ST4, the LL cache tag unit 351 is reached in the period ST6.

  Requests for external snoops from the memory control unit 302, requests for load buffers from the memory control unit 303, requests for error processing from other functional units 304, etc. are sent to the corresponding ports 363, 364, 365 in the period ST2, respectively. Entered. Then, when selected by the pipeline selection unit 381 in the period ST4, the LL cache tag unit 351 is reached in the period ST6.

  As described above, in the conventional processor shown in FIG. 10, it takes 6 cycles to reach the LL cache tag unit 351 regardless of the type of request.

  On the other hand, as shown in FIG. 3A, in the processor according to the present embodiment, a new request from the core 301 is input to the new request port 331 corresponding to each core in the period ST2. Then, when the oldest new request is selected and output by the LRU control unit 341 in the period ST3 of the next cycle and further selected by the pipeline selection unit <2> 342, the LL cache tag unit 351 is reached in the period ST4. To do.

  The request for the snoop response from the core 301 is input to the snoop response port 311 corresponding to each core in the period ST2. When the pipeline selection unit <1> 321 is selected in the period ST3 of the next cycle and the pipeline selection unit <2> 342 is selected in the period ST5, the LL cache tag unit 351 is reached in the period ST6. The period ST5 is provided as a period required for transfer between the pipeline selection unit <1> 321 and the pipeline selection unit <2> 342.

  Requests for external snoops from the memory control unit 302, requests for load buffers from the memory control unit 303, requests for error processing from other functional units 304, etc. are sent to the corresponding ports 312, 313, and 314 in the period ST2, respectively. Entered. When the pipeline selection unit <1> 321 is selected in the period ST3 of the next cycle and the pipeline selection unit <2> 342 is selected in the period ST5, the LL cache tag unit 351 is reached in the period ST6.

  As described above, in this embodiment, the pipeline selection unit <1> 321 and the pipeline selection unit <2> 342 are divided into two, and the new request port 331 and the pipeline selection unit <2> 342 are divided into LL cache tags. By placing it at a position close to the unit 351, requests other than new requests reach the LL cache tag unit 351 in a time corresponding to 6 cycles as in the conventional case, but new requests from the core 301 take time for 4 cycles. Thus, the LL cache tag unit 351 can be reached.

  That is, a request for new data (new request) from the core is a time corresponding to four cycles through the new request port and the pipeline selection unit <2> in the processor according to the present embodiment, as shown in FIG. It is possible to reach the LL cache tag unit 351 in (ST1 to ST4). On the other hand, in the conventional processor, as shown in FIG. 4B, it takes six cycles (ST1 to ST1) to reach the LL cache tag unit 351 via the new request port in each port and the pipeline selection unit. ST6) is required.

  As described with reference to FIGS. 3A, 3B, and 4, the processor according to the present embodiment is divided into the pipeline selection unit <1> 321 and the pipeline selection unit <2> 342. As a result, the number of logical stages in the path related to the new request can be reduced, and the access latency of the LL cache memory can be shortened.

  Further, in the present embodiment, since a new request can reach the LL cache tag unit in a shorter time than a request other than the new request, the throughput can be improved. For example, as shown in FIG. 5, it is assumed that a request is issued for each cycle in the order of R (request other than a new request), E (no request), R, R, and N (new request). At this time, in STAGE0, R, E, R, R, and N become N, but since N (new request) reaches the LL cache tag part in STAGE4, N (new request) is subsequently added to the E (no request) portion. It can be seen that the throughput is improved.

  Here, as described above, when the priority for entering the pipeline is highest in the snoop response port, lower in the order of the load buffer port and the external snoop port, and the lowest in the new request port, the pipeline in the conventional processor The selection unit is configured as shown in FIG. 6B, for example. FIG. 6B illustrates a configuration example of a pipeline selection unit in a conventional processor, which includes AND circuits 601, 602, 603, 604, and a selection circuit 605.

  The AND circuit 601 receives a snoop response port signal SRPT and a snoop response port suppression signal SRPT_INH. The AND circuit 602 receives the load buffer port signal LDPT, the load buffer port suppression signal LDPT_INH, and the snoop response port signal SRPT. The AND circuit 603 receives an external snoop port signal OSPT, an external snoop port suppression signal OSPT_INH, a snoop response port signal SRPT, and a load buffer port signal LDPT. The AND circuit 604 receives a new request port signal RQPT, a new request port suppression signal RQPT_INH, a snoop response port signal SRPT, a load buffer port signal LDPT, and an external snoop port signal OSPT. The selection circuit 605 selectively outputs the outputs of the AND circuits 601, 602, 603, and 604.

  In the pipeline selection unit configured as shown in FIG. 6B, depending on the input order of requests, no request may be selected and throughput may be reduced. For example, if the requests from the core are in the order of snoop response port → load buffer port → snoop response port and new request port (simultaneous), the order to be put into the pipeline follows the priority order, the snoop response port → Load buffer port → snoop response port → new request port.

  However, at the timing when the snoop response port and the new request port (simultaneously) are coming, the snoop response port signal SRPT, the snoop response port suppression signal SRPT_INH, and the new request port signal RQPT are “1”. When the signals LDRT and OSPT and the suppression signals LDRT_INH, OSPT_INH, and RQPT_INH are “0”, a request for a snoop response port with a high priority is received, but a request for a snoop response port is not transmitted due to the suppression signal SRPT_INH of the snoop response port. . Also, a request for a new request port does not pass because a request for a snoop response port with a high priority is received. Therefore, the outputs of the AND circuits 601, 602, 603, and 604 are “0”, and the selection circuit 605 of the pipeline selection unit does not select any request.

  On the other hand, according to the present embodiment, as shown in FIG. 6A, the snoop response port signal SRPT, the snoop response port suppression signal SRPT_INH, and the new request port signal RQPT are “1”. When the other signals LDRT, OSPT and the suppression signals LDRT_INH, OSPT_INH, RQPT_INH are “0”, the selection circuit 204 of the pipeline selection unit <1> does not select any request. In this embodiment, since the pipeline selection unit <2> selects a new request and a request other than the new request, the selection circuit 207 of the pipeline selection unit <2> selects the request for the new request port. Can be output.

  That is, when the requests from the core are in the order of snoop response port → load buffer port → snoop response port and new request port (simultaneous), in the conventional processor, as shown in FIG. Response port-> load buffer port-> (no instruction)-> snoop response port-> new request port. On the other hand, according to the present embodiment, as shown in FIG. 7A, it is possible to enter the pipeline in the order of snoop response port → load buffer port → new request port → snoop response port. Line slots can be used efficiently, and throughput can be improved.

  In the above description, an example having eight cores (core <0> to core <7>) and two banks of LL cache memory shared by these cores has been shown. It is not limited to. The number of cores included in the processor and the number of banks of the LL cache memory in this embodiment may be any plural number. For example, as shown in FIG. 8, the present invention can also be applied to a processor having eight cores (core <0> to core <7>) and four banks of LL cache memory shared by the eight cores. is there.

  FIG. 8 is a diagram illustrating another example of the layout of the processor as the arithmetic processing device according to the present embodiment. 8, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  In the example shown in FIG. 8, in the LL cache memory, the LL cache tag unit 18-1 and the LL cache data unit 19-1 constitute one bank, and the LL cache tag unit 18-2 and the LL cache data unit 19-2 constitute one bank. Further, the LL cache tag unit 18-3 and the LL cache data unit 19-3 constitute one bank, and the LL cache tag unit 18-4 and the LL cache data unit 19-4 constitute one bank. doing.

  Also, new request ports 16-1, 16-2, 16-3, 16-4 and pipeline selection units <2> 17-1, 17-2, 17- are associated with each bank of the LL cache memory. 3 and 17-4 are provided and arranged closer to the LL cache tag units 18-1, 18-2, 18-3, and 18-4 than the pipeline selection unit <1> 15. In this way, the new request port and the pipeline selection unit <2> may be divided and arranged so as to be adjacent to each bank of the LL cache memory. As a result, for example, as indicated by a broken line in FIG. 8, when the requested data from the core 11 has a cache hit in the bank of the LL cache memory close to the core, the path through which the signal flows is shortened, and the access latency of the LL cache memory is reduced. Can be shortened.

  According to the present embodiment, the pipeline selection unit <1> is divided into the pipeline selection unit <2>, and the new request port and the pipeline selection unit <2> are arranged at positions close to the LL cache memory. The physical distance of the path related to a request for new data having the highest request frequency among the requests from the core to the LL cache memory can be shortened, the access latency of the LL cache memory can be improved, and the entire processor Processing performance can be improved.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

11 Core 12 Transfer bus 13 Various ports 14 Pipeline controller 15 Pipeline selector <1>
16 New request port 17 Pipeline selection section <2>
18 LL (last level) cache tag part 19 LL (last level) cache data part 20 External port

Claims (7)

A plurality of arithmetic units;
A cache memory having a plurality of banks and shared by the plurality of arithmetic units;
A first selection unit that selects a request to be output from requests other than the first request from the arithmetic unit among the requests to the cache memory;
Each bank of the cache memory is arranged at a position closer to the cache memory than the first selection unit, and selects and selects a request from the first request and the request selected by the first selection unit And a second selection unit that outputs a request to a pipeline related to access to the cache memory.   A port unit that is arranged together with the second selection unit at a position closer to the cache memory than the first selection unit for each bank of the cache memory, and that receives a request for the cache memory other than the first request The arithmetic processing unit according to claim 1, further comprising a first port unit that receives the different first requests.   The arithmetic processing apparatus according to claim 1, wherein the first request is a request having a lower priority than a request selected by the first selection unit. A plurality of arithmetic units;
A cache memory having a plurality of banks and shared by the plurality of arithmetic units;
A first selection unit that selects a request to be output from requests other than the first request from the arithmetic unit among the requests to the cache memory;
For each bank of the cache memory, a request is selected from the first request and the request selected by the first selection unit, and the selected request is output to a pipeline related to the access to the cache memory. And an arithmetic processing unit having two selection units.   5. The first port unit that receives the first request different from a port unit that receives a request for the cache memory other than the first request is provided for each bank of the cache memory. Arithmetic processing unit.   The arithmetic processing apparatus according to claim 1, wherein the first request is a request for new data from the arithmetic unit. A control method of an arithmetic processing unit having a plurality of arithmetic units and a cache memory having a plurality of banks and shared by the plurality of arithmetic units,
The first selection unit of the arithmetic processing unit selects a request to be output from a request other than the first request from the arithmetic unit among the requests for the cache memory,
The second selection unit of the arithmetic processing unit provided for each bank of the cache memory selects a request from the first request and the request selected by the first selection unit, and selects the selected request A control method for an arithmetic processing unit, characterized by outputting to a pipeline related to access to a cache memory.

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