JP2017017562A - Solid-state image pickup device and data receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow for identification of a long-time exposure image and a short-time exposure image on the receiver side.SOLUTION: A packet data generation unit 13A transmits packet data PD, packetizing the imaging data DA for each line, for each frame. An exposure information addition unit 13B adds the exposure information capable of identifying the exposure time of the imaging data DA to the packet data PD. A packet data receiving section 14A receives the packet data PD, packetizing the imaging data DA for each line, for each frame. An identification information extraction unit 14B extracts exposure information capable of identifying the exposure time of the imaging data DA added to the packet data PD. An exposure time determination unit 14C determines the exposure time of the imaging data DA based on the exposure information.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a solid-state imaging device and a data receiving device.

  Some solid-state imaging devices synthesize a long-time exposure image and a short-time exposure image in order to expand the dynamic range. In order to synthesize these images on the host side, it is necessary to distinguish between the long exposure image and the short exposure image.

JP2013-59017A

  An object of one embodiment of the present invention is to provide a solid-state imaging device and a data receiving device that can identify a long-exposure image and a short-exposure image on the receiver side.

  According to one embodiment of the present invention, a packet data transmission unit and an exposure information addition unit are provided. The packet data transmission unit transmits packet data in which imaging data is packetized for each line for each frame. The exposure information adding unit adds exposure information that can identify an exposure time of the imaging data to the packet data.

FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging device and a data receiving device according to the first embodiment. FIG. 2 is a diagram illustrating a method for adding exposure information when transmitting imaging data according to the first embodiment. FIG. 3 is a diagram illustrating a method for adding exposure information when transmitting imaging data according to the second embodiment. FIG. 4 is a block diagram illustrating a configuration example of the imaging unit in FIG. FIG. 5 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG. 6A is a timing chart showing voltage waveforms of the respective parts of the pixel of FIG. 5 during long exposure, and FIG. 6B is timings showing voltage waveforms of the respective parts of the pixel of FIG. 5 during short exposure. It is a chart. FIG. 7 is a block diagram illustrating a schematic configuration of a digital camera according to the third embodiment.

  Hereinafter, a solid-state imaging device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging device and a data receiving device according to the first embodiment.
In FIG. 1, the camera 11 is connected to a receiver 14. The camera 11 can take an image and packetize the imaged data DA that has undergone the imaging process. The imaging data DA can include imaging data with different exposure times. The receiver 14 can receive packetized imaging data DA from the camera 11. Further, the receiver 14 can expand the dynamics of the imaging data DA by synthesizing the imaging data DA with different exposure times. The receiver 14 may be a processor or a host computer.

  The camera 11 is provided with an imaging unit 12 and an interface unit 13. The imaging unit 12 can perform imaging and imaging processing according to imaging conditions. This imaging condition can include an exposure time. The interface unit 13 can transmit packet data PD obtained by packetizing the imaging data DA generated by the imaging unit 12 to the receiver 14 for each frame. The interface unit 13 can operate by a self-clock (source synchronization) method. At this time, the interface unit 13 can also transmit the clock CLK to the receiver 14. The packet data PD and the clock CLK can be differentiated. The interface unit 13 can communicate with the receiver 14 based on CSI (Camera Serial Interface) 2 standard. A physical layer that defines electrical specifications called MIPI (Mobile Industry Processor Interface) D-PHY can be provided above the CSI2 protocol. The interface unit 13 is provided with a packet data generation unit 13A and an exposure information addition unit 13B. The packet data generation unit 13A transmits packet data PD obtained by packetizing the imaging data DA for each line for each frame. The exposure information adding unit 13B adds exposure information that can identify the exposure time of the imaging data DA to the packet data PD.

The receiver 14 includes a packet data receiving unit 14A, an identification information extracting unit 14B, and an exposure time determining unit 14C. The packet data receiving unit 14A receives packet data PD in which the imaging data DA is packetized for each line for each frame. The identification information extraction unit 14B extracts exposure information that is added to the packet data PD and that can identify the exposure time of the imaging data DA. The exposure time determination unit 14C determines the exposure time of the imaging data DA based on the exposure information.
The imaging unit 12 generates imaging data DA having different exposure times by changing the exposure time during imaging. The exposure time may be different for each line or may be different for each frame.

The interface unit 13 packetizes the imaging data DA for each line, thereby generating packet data PD. At this time, exposure information that can identify the exposure time of the imaging data DA is added to the packet data PD. Here, when the exposure information is added to the packet data PD, the exposure information can be set in the data identification information accompanying the imaging data DA. For example, in the case of the CSI2 standard, exposure information can be set in DI (Data Identifier). When the receiver 14 receives the packet data PD to which the exposure information is added, the exposure information is extracted from the packet data PD, and the exposure time of the imaging data DA is determined based on the exposure information. Here, the camera 11 and the receiver 14 can define exposure information in advance and hold the exposure information. Then, by comparing the exposure information sent from the camera 11 with the exposure information held by the receiver 14, the imaging time can be determined on the receiver 14 side. Then, the image data DA with different exposure times is combined into one frame, thereby generating an image with an expanded dynamic range.
Here, by adding exposure information to a predetermined position of the packet data PD sent from the camera 11, even when the exposure time is alternately and repeatedly changed for each line, the determination of the exposure time on the receiver 14 side is performed. Can be facilitated. For this reason, on the receiver 14 side, the composition of the imaging data DA with different exposure times can be made efficient.

FIG. 2 is a diagram illustrating a method for adding exposure information when transmitting imaging data according to the first embodiment. In FIG. 2, the CSI2 standard is taken as an example. Further, in FIG. 2, an example is given in which exposure information indicating long exposure and short exposure is added for each line. Further, FIG. 2 shows data for two frames (N (N is a positive integer) frame and N + 1 frame) when there are data for eight lines in one frame.
In FIG. 2, when the imaging data DA is packetized, a packet header PH is added to the head for each line. The packet header PH stores an identifier DI, a word counter WC, and an error correction code ECC. The word counter WC can indicate how many pixels are in one line. The identifier DI stores a virtual channel identifier VC and DT Type. In the CSI2 standard, when data is multiplexed and transmitted, a plurality of channels can be used. At this time, the virtual channel identifier VC can indicate which channel is assigned to each data. Two bits can be assigned to the virtual channel identifier VC. The DT Type can indicate the format and content of the imaging data DA. Six bits can be assigned to DT Type. A user-defined area can be provided in DT Type.
A frame start packet FS is added to the beginning of each frame, and a frame end packet FE is added to the end of each frame. In the frame start packet FS and the frame end packet FE, an identifier DI, a frame counter FC, and an error correction code ECC are stored, respectively. This identifier DI also stores the virtual channel identifier VC and DT Type. The frame counter FC can indicate the frame number of its own frame. The DT Type of the frame start packet FS can be fixed at 6′h00. The DT Type of the frame end packet FE can be fixed to 6′h01.

  Here, it is assumed that long-time exposure data DA1 and short-time exposure data DA2 are generated in the imaging unit 12 by performing long-time exposure and short-time exposure alternately every two lines. When the long exposure data DA1 and the short exposure data DA2 are sent from the imaging unit 12 to the interface unit 13, the long exposure data DA1 and the short exposure data DA2 are packetized for each line, and the packet header. PH is added to the head. Further, a frame start packet FS is added to the beginning of each frame, and a frame end packet FE is added to the end of each frame. In the virtual channel identifier VC of the packet header PH added to the long exposure data DA1, exposure information VC_long indicating long exposure is set, and the virtual channel identifier VC of the packet header PH added to the short exposure data DA2 is set. Can set exposure information VC_short indicating short-time exposure.

  When the long-time exposure data DA1 and the short-time exposure data DA2 are received by the receiver 14, the virtual channel identifier VC of the packet header PH is referred to. When the exposure information VC_long and VC_short is set in the virtual channel identifier VC of the packet header PH, it is determined from the exposure information VC_long and VC_short whether it is the long exposure data DA1 or the short exposure data DA2. When exposure information VC_long and VC_short are set in the virtual channel identifier VC of the packet header PH, the channel assigned to the long exposure data DA1 and the short exposure data DA2 is the frame start packet FS or the frame end packet FE. It may be determined from the virtual channel identifier VC. Alternatively, when the exposure information VC_long and VC_short are set in the virtual channel identifier VC of the packet header PH, the channels assigned to the long exposure data DA1 and the short exposure data DA2 are set as defaults between the camera 11 and the receiver 14. You may make it set.

  Note that the exposure information VC_long indicating long exposure may be set in the DT Type of the packet header PH instead of being set in the virtual channel identifier VC of the packet header PH added to the long exposure data DA1. Further, instead of setting the exposure information VC_short indicating the short exposure to the virtual channel identifier VC of the packet header PH added to the short exposure data DA2, the DT Type of the packet header PH added to the short exposure data DA2. You may make it set to. When the exposure information VC_long and VC_short are set in the DT Type, they may be set in the user-defined area of the DT Type. In FIG. 2, the method in which long-time exposure and short-time exposure are alternately performed every two lines is taken as an example. However, the method is not necessarily limited to a method in which long-time exposure and short-time exposure are alternately performed every two lines. For example, it may be applied to a method in which long exposure and short exposure are alternately performed line by line, or a method in which long exposure for one line and short exposure for two lines are alternately performed. You may apply to.

(Second Embodiment)
FIG. 3 is a diagram illustrating a method for adding exposure information when transmitting imaging data according to the second embodiment. In FIG. 3, the CSI2 standard is taken as an example. FIG. 3 shows an example in which exposure information indicating long exposure and short exposure is added for each frame. Further, FIG. 3 shows data for two frames (N (N is a positive integer) frame and N + 1 frame) when there are data for eight lines in one frame. Further, the same configuration as that of FIG. 1 can be used also in the method of FIG.
In FIG. 3, it is assumed that long-time exposure data DA1 and short-time exposure data DA2 are generated in the imaging unit 12 by performing long-time exposure and short-time exposure alternately for each frame. Then, when the long exposure data DA1 and the short exposure data DA2 are sent from the imaging unit 12 to the interface unit 13, N frames of short exposure data DA2 are packetized for each line, and N + 1 frames of long exposure are performed. Data DA1 is packetized for each line, and a packet header PH is added for each line. Further, a frame start packet FS is added to the beginning of each frame, and a frame end packet FE is added to the end of each frame. Exposure information VC_long indicating long exposure is set in the virtual channel identifier VC of the frame start packet FS and frame end packet FE of the frame in which the long exposure data DA1 is stored, and the frame in which the short exposure data DA2 is stored. In the virtual channel identifier VC of the frame start packet FS and frame end packet FE, exposure information VC_short indicating short-time exposure can be set.

  When the long-time exposure data DA1 and the short-time exposure data DA2 are received by the receiver 14, the virtual channel identifier VC of the frame start packet FS and the frame end packet FE is referred to. When the exposure information VC_long and VC_short are set in the virtual channel identifier VC of the frame start packet FS and the frame end packet FE, the long exposure data DA1 or the short exposure data DA2 is obtained from the exposure information VC_long and VC_short. Is determined. When the exposure information VC_long and VC_short are set in the virtual channel identifier VC of the frame start packet FS and the frame end packet FE, the channels assigned to the long exposure data DA1 and the short exposure data DA2 are set in the packet header PH. It may be determined from the virtual channel identifier VC. Alternatively, when the exposure information VC_long and VC_short are set in the virtual channel identifier VC of the frame start packet FS and the frame end packet FE, the channels assigned to the long exposure data DA1 and the short exposure data DA2 are the cameras 11 and The default may be set between the receivers 14.

  Note that the exposure information VC_long indicating long exposure is added to the long exposure data DA1 instead of being set in the virtual channel identifier VC of the frame start packet FS and frame end packet FE added to the long exposure data DA1. You may make it set to the virtual channel identifier VC of packet header PH, and you may make it set to DT Type of packet header PH. Further, instead of setting the exposure information VC_short indicating the short exposure to the virtual channel identifier VC of the frame start packet FS and the frame end packet FE added to the short exposure data DA2, it is added to the short exposure data DA2. You may make it set to the virtual channel identifier VC of packet header PH, and you may make it set to DT Type of packet header PH.

FIG. 4 is a block diagram illustrating a configuration example of the imaging unit in FIG.
In FIG. 4, a pixel array unit 1 is provided in the imaging unit. In the pixel array section 1, pixels PC that accumulate photoelectrically converted charges are arranged in a matrix in the row direction RD and the column direction CD. In the pixel array unit 1, a horizontal control line Hlin for performing readout control of the pixel PC is provided in the row direction RD, and a vertical signal line Vlin for transmitting a signal read from the pixel PC is provided in the column direction CD. Is provided.

  In addition, the image pickup unit performs a source follower operation with the vertical scanning circuit 2 that scans the pixel PC to be read in the vertical direction and the pixel PC, so that a signal is output from the pixel PC to the vertical signal line Vlin for each column. The reference voltage is applied to the load circuit 3, the column ADC circuit 4 for detecting the signal component of each pixel PC for each column by the CDS, the horizontal scanning circuit 5 for scanning the pixel PC to be read in the horizontal direction, and the column ADC circuit 4. A reference voltage generation circuit 6 that outputs VREF and a timing control circuit 7 that controls the timing of reading and storage of each pixel PC are provided. Note that a ramp wave can be used as the reference voltage VREF.

  In the pixel array unit 1, in order to colorize the captured image, a Bayer array HP in which four pixels PC are set as one set can be formed. In this Bayer array HP, two green pixels g are arranged in one diagonal direction, and one red pixel r and one blue pixel b are arranged in the other diagonal direction. Since this Bayer array HP extends over two lines, long-time exposure and short-time exposure can be performed alternately every two lines. For this reason, as shown in FIG. 2, long exposure data DA1 and short exposure data DA2 can be transmitted alternately every two lines.

  The timing control circuit 7 is provided with a long exposure reset timing controller 7A, a short exposure reset timing controller 7B, and a readout timing controller 7C. The long exposure reset timing control unit 7 </ b> A controls the reset timing of charges accumulated in the pixels PC on the first line of the pixel array unit 1. The short exposure reset timing controller 7B controls the reset timing of the charges accumulated in the pixels PC on the second line so that the exposure period is shorter than the pixels PC on the first line of the pixel array unit 1. . The read timing control unit 7C controls the read timing of the charges accumulated in the pixel PC. The first line and the second line can be alternately set on the pixel array unit 1. For example, in the Bayer array HP, the first line is the 4n + 1 (n is an integer greater than or equal to 0) row and 4n + 2 row of the pixel array unit 1, and the second line is the 4n + 3 row and 4n + 4 row of the pixel array unit 1. Can be set to

  Then, the pixel PC is selected in the row direction RD by the vertical scanning circuit 2 scanning the pixel PC in the vertical direction. Then, in the load circuit 3, a source follower operation is performed with the pixel PC, whereby a signal read from the pixel PC is transmitted via the vertical signal line Vlin and sent to the column ADC circuit 4. In the reference voltage generation circuit 6, a ramp wave is set as the reference voltage VREF and sent to the column ADC circuit 4. Then, the column ADC circuit 4 performs a clock counting operation until the signal level read from the pixel PC and the reset level coincide with the ramp wave level, and the difference between the signal level and the reset level at that time is taken. Thus, the signal component of each pixel PC is detected by the CDS and output as the output signal S1.

FIG. 5 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG.
In FIG. 5, the pixel PC is provided with a photodiode PD, a row selection transistor Ta, an amplification transistor Tb, a reset transistor Tc, and a readout transistor Td. In addition, a floating diffusion FD is formed as a detection node at a connection point between the amplification transistor Tb, the reset transistor Tc, and the read transistor Td.

The source of the read transistor Td is connected to the photodiode PD, and the read signal READ is input to the gate of the read transistor Td. The source of the reset transistor Tc is connected to the drain of the read transistor Td, the reset signal RESET is input to the gate of the reset transistor Tc, and the drain of the reset transistor Tc is connected to the power supply potential VDD. The row selection signal ADRES is input to the gate of the row selection transistor Ta, and the drain of the row selection transistor Ta is connected to the power supply potential VDD. The source of the amplification transistor Tb is connected to the vertical signal line Vlin, the gate of the amplification transistor Tb is connected to the drain of the read transistor Td, and the drain of the amplification transistor Tb is connected to the source of the row selection transistor Ta. Yes.
Note that the horizontal control line Hlin in FIG. 4 can transmit the read signal READ, the reset signal RESET, and the row selection signal ADRES to the pixel PC for each row.

6A is a timing chart showing voltage waveforms of the respective parts of the pixel of FIG. 5 during long exposure, and FIG. 6B is timings showing voltage waveforms of the respective parts of the pixel of FIG. 5 during short exposure. It is a chart.
6A, the first exposure period EX1 is set for the pixels PC on the first line of the pixel array unit 1 of FIG. 4, and in FIG. 6B, the second of the pixel array unit 1 of FIG. A second exposure period EX2 is set for the pixels PC on the line. The first exposure period EX1 is longer than the second exposure period EX2.

  As shown in FIG. 6A, in the pixel PC on the first line, when the row selection signal ADRES is at a low level, the row selection transistor Ta is turned off, and the pixel signal VSIG is not output to the vertical signal line Vlin. . At this time, when the read signal READ and the reset signal RESET become high level (ta1), the read transistor Td is turned on, and the charge accumulated in the photodiode PD in the first non-exposure period NX1 is discharged to the floating diffusion FD. . Then, it is discharged to the power supply VDD through the reset transistor Tc.

After the charge accumulated in the photodiode PD in the first non-exposure period NX1 is discharged to the power supply VDD, when the read signal READ goes to a low level, the photodiode PD starts accumulating effective signal charges. The non-exposure period NX1 shifts to the first exposure period EX1.
Next, when the row selection signal ADRES becomes a high level (ta2), the row selection transistor Ta of the pixel PC is turned on, and the power supply potential VDD is applied to the drain of the amplification transistor Tb.

Then, when the reset signal RESET becomes high level with the row selection transistor Ta being on (ta3), the reset transistor Tc is turned on, and excess charge generated due to leakage current or the like is reset in the floating diffusion FD. Then, a voltage corresponding to the reset level of the floating diffusion FD is applied to the gate of the amplification transistor Tb, and the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb, whereby the pixel signal VSIG at the reset level. Is output to the vertical signal line Vlin.
The reset level pixel signal VSIG is input to the column ADC circuit 4 and compared with the reference voltage VREF. Based on the comparison result, the pixel signal VSIG at the reset level is converted to a digital value and held.

Next, when the read signal READ becomes high level with the row selection transistor Ta of the pixel PC turned on (ta4), the read transistor Td is turned on, and the charge accumulated in the photodiode PD during the first exposure period EX1 is increased. It is transferred to the floating diffusion FD. Then, a voltage corresponding to the signal read level of the floating diffusion FD is applied to the gate of the amplification transistor Tb, and the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb. The signal VSIG is output to the vertical signal line Vlin.
The pixel signal VSIG at the signal readout level is input to the column ADC circuit 4 and compared with the reference voltage VREF. Based on the comparison result, the difference between the pixel signal VSIG at the reset level and the pixel signal VSIG at the signal readout level is converted into a digital value and output as an output signal S1 corresponding to the first exposure period EX1. The output signal S1 at this time is sent to the interface unit 13 as long-time exposure data DA1.

On the other hand, as shown in FIG. 6B, in the pixel PC on the second line, when the row selection signal ADRES is at a low level, the row selection transistor Ta is turned off, and the pixel signal VSIG is not output to the vertical signal line Vlin. . At this time, when the read signal READ and the reset signal RESET become high level (tb1), the read transistor Td is turned on, and the charge accumulated in the photodiode PD in the second non-exposure period NX2 is discharged to the floating diffusion FD. . Then, it is discharged to the power supply VDD through the reset transistor Tc.
After the charge accumulated in the photodiode PD in the second non-exposure period NX2 is discharged to the power supply VDD, when the read signal READ goes to a low level, the photodiode PD receives effective signal charges in the second non-exposure period NX2. Accumulation is started, and the second non-exposure period NX2 shifts to the second exposure period EX2.
Next, when the row selection signal ADRES becomes high level (tb2), the row selection transistor Ta of the pixel PC is turned on, and the power supply potential VDD is applied to the drain of the amplification transistor Tb.

Then, when the reset signal RESET becomes high level with the row selection transistor Ta turned on (tb3), the reset transistor Tc is turned on, and excess charge generated by a leakage current or the like is reset in the floating diffusion FD. Then, a voltage corresponding to the reset level of the floating diffusion FD is applied to the gate of the amplification transistor Tb, and the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb, whereby the pixel signal VSIG at the reset level. Is output to the vertical signal line Vlin.
The reset level pixel signal VSIG is input to the column ADC circuit 4 and compared with the reference voltage VREF. Based on the comparison result, the pixel signal VSIG at the reset level is converted to a digital value and held.

Next, when the read signal READ becomes high level with the row selection transistor Ta of the pixel PC turned on (tb4), the read transistor Td is turned on, and the charge accumulated in the photodiode PD in the second exposure period EX2 is increased. It is transferred to the floating diffusion FD. Then, a voltage corresponding to the signal read level of the floating diffusion FD is applied to the gate of the amplification transistor Tb, and the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb. The signal VSIG is output to the vertical signal line Vlin.
The pixel signal VSIG at the signal readout level is input to the column ADC circuit 4 and compared with the reference voltage VREF. Then, based on the comparison result, the difference between the pixel signal VSIG at the reset level and the pixel signal VSIG at the signal readout level is converted into a digital value and output as an output signal S1 corresponding to the second exposure period EX2. The output signal S1 at this time is sent to the interface unit 13 as short-time exposure data DA2.

(Third embodiment)
FIG. 7 is a block diagram illustrating a schematic configuration of a digital camera according to the third embodiment.
In FIG. 7, the digital camera 21 includes a camera module 22 and a post-processing unit 23. The camera module 22 includes an imaging optical system 24 and a solid-state imaging device 25. The post-processing unit 23 includes an image signal processor (ISP) 26, a storage unit 27, and a display unit 28. Note that the solid-state imaging device 25 can use the configuration of the imaging unit 12 of FIG. At this time, the interface unit 13 may be incorporated in the ISP 26. Further, at least a part of the configuration of the ISP 26 may be integrated into one chip together with the solid-state imaging device 25.

  The imaging optical system 24 takes in light from the subject and forms a subject image. The solid-state imaging device 25 captures a subject image. The ISP 26 processes an image signal obtained by imaging with the solid-state imaging device 25. The storage unit 27 stores an image that has undergone signal processing in the ISP 26. The storage unit 27 outputs an image signal to the display unit 28 according to a user operation or the like. The display unit 28 displays an image according to the image signal input from the ISP 26 or the storage unit 27. The display unit 28 is, for example, a liquid crystal display. In addition to the digital camera 21, the camera module 22 may be applied to an electronic device such as a mobile terminal with a camera.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  11 camera, 12 imaging unit, 13 interface unit, 13A packet data generation unit, 13B, exposure information addition unit, 14 receiver, 14A packet data reception unit, 14B identification information extraction unit, 14C exposure time determination unit

Claims (5)

A packet data transmission unit that transmits packet data in which imaging data is packetized for each line;
A solid-state imaging device comprising: an exposure information adding unit that adds exposure information that can identify an exposure time of the imaging data to the packet data.   The solid-state imaging device according to claim 1, wherein exposure information indicating long exposure or short exposure is added for each line to a VC (Virtual Channel Identifier) or DT Type of a packet header in CSI (Camera Serial Interface) 2 standard.   The solid-state imaging device according to claim 1, wherein exposure information indicating long exposure or short exposure is added to a VC of a frame start packet or a frame end packet in the CSI2 standard for each frame. A packet data receiving unit that receives packet data in which imaging data is packetized for each line for each frame;
An identification information extraction unit that extracts exposure information that is added to the packet data and that can identify an exposure time of the imaging data;
A data receiving apparatus comprising: an exposure time determination unit that determines an exposure time of the imaging data based on the exposure information.   5. The exposure information is added for each line to VC or DT Type of a packet header in the CSI2 standard, or added to a VC of a frame start packet or a frame end packet in the CSI2 standard for each frame. The data receiving device described.

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