JP2017017190A - Secondary battery and secondary battery manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a secondary battery having high input/output density and a large capacity.SOLUTION: A secondary battery 10 includes a first electrode 1, a second electrode 2, and a charging layer 3 sandwiched between the first electrode 1 and the second electrode 2 and having an insulator 4 and a semiconductor 6. The charging layer 3 accumulates carriers at both the ends of a forbidden band under a strong inversion state that the difference between the intrinsic Fermi level as the energy level at the center of the forbidden band of the semiconductor 6 and the energy level at the center of the forbidden band at the interface between the semiconductor 6 and the insulator 4 is twice or more the difference between the intrinsic Fermi level and the Fermi level of the semiconductor 6. The semiconductor 6 is plural semiconductor fine particles 5 dispersed in the insulator 4.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a secondary battery.

  An electric vehicle using a motor as a driving force source and a hybrid vehicle using a motor and an internal combustion engine have been put into practical use. An automobile without an overhead line for supplying electric power, such as a railway, includes a direct current power source such as a battery or a capacitor as a power supply source. Such a DC power source is required to have a high volumetric energy density so that a large amount of power can be stored in a smaller size. Such a DC power source is also required to have a high power input / output density so that power can be supplied quickly and charged in a short time when necessary. In general, a chemical battery represented by a secondary battery such as lithium ion has a high volumetric energy density but a low input / output density. In addition, so-called electron batteries such as electric double layer capacitors have a high input / output density but a low volume energy density. It would be desirable to overcome both disadvantages and provide an ideal DC power source. For example, in International Publication WO2012 / 046325 (Patent Document 1), a new energy level is formed in a forbidden band (band gap) in an inorganic solid by utilizing a photoexcitation structure change of a metal oxide. A secondary battery based on the operating principle of capturing electrons is disclosed. However, there are many unexplained points in the photoexcited structure change, and there seems to be a problem in application to secondary batteries with stable quality and supply.

International Publication WO2012 / 046325

  In view of the above, it is desired to provide a secondary battery having a high input / output density and a large capacity.

  As one aspect, a secondary battery in view of the above includes a first electrode, a second electrode, a charge layer that is sandwiched between the first electrode and the second electrode, and includes an insulator and a semiconductor; The charge layer includes a difference between an intrinsic Fermi level, which is an energy level at the center of the forbidden band of the semiconductor, and an energy level at the center of the forbidden band, at the interface between the semiconductor and the insulator. However, in the strong inversion state, which is at least twice the difference between the intrinsic Fermi level and the semiconductor Fermi level, carriers are accumulated at both ends of the forbidden band. A plurality of semiconductor fine particles dispersed in the body.

  By dispersing the semiconductor fine particles in the insulator, many core shells of the capacitor are formed by MIS junction (Metal-Insulator-Semiconductor Junction) in which the first electrode, the second electrode, the insulator, and the semiconductor fine particles are joined. Can do. Since a plurality of capacitors can be provided in parallel connection between the first electrode and the second electrode, the capacity of the secondary battery can be increased. In addition, the secondary battery does not require special measures such as photoexcitation structure change and accumulates carriers at both ends of the forbidden band in the strong inversion state, so that the secondary battery can be configured easily. Further, since the secondary battery is not a chemical battery but an electron battery using MIS junction, a high input / output density can be obtained. Thus, according to this configuration, a secondary battery having a high input / output density and a large capacity can be provided.

Moreover, as one aspect, a secondary battery that manufactures a secondary battery that includes at least a first electrode, a second electrode, and a charging layer sandwiched between the first electrode and the second electrode. The manufacturing method is
An electrode formation first step of forming a thin film to be any one of the first electrode and the second electrode on a substrate;
After the electrode formation first step, a charge layer forming step of forming the charge layer using a charge layer material in which a plurality of semiconductor fine particles are dispersed in an insulator;
After the charging layer forming step, an electrode forming second step of forming a thin film to be either the first electrode or the second electrode is provided.

  By forming a charge layer using a charge layer material in which a plurality of semiconductor fine particles are dispersed in an insulator, a large number of core shells of MIS junction capacitors can be formed in the charge layer. Further, since the semiconductor fine particles are dispersed in the insulator while maintaining an appropriate separation distance in the charge layer material, a secondary battery can be stably formed.

  Further features and advantages of the secondary battery will become clear from the following description of embodiments described with reference to the drawings.

Schematic diagram showing an example of the configuration of a secondary battery Schematic diagram showing another example of the configuration of the secondary battery Energy band diagram of MIS junction using p-type semiconductor Energy band diagram of MIS junction using n-type semiconductor Diagram showing the trend of carriers when the MIS junction (p-type) is in a strong inversion state Diagram showing the trend of carriers when the MIS junction (n-type) is in a strong inversion state MIS junction (n-type) capacitor energy band diagram and carrier trend diagram Energy band diagram of capacitor with blocking layer in MIS junction (n-type) and diagram showing carrier trends Energy band diagram when charging a capacitor Energy band diagram when discharging from a capacitor Equivalent circuit diagram showing a configuration in which a secondary battery is constituted by a plurality of capacitors Flow chart showing an example of a procedure for manufacturing a secondary battery The flowchart which shows the other example of the procedure which manufactures a secondary battery Flow chart showing an example of a procedure for producing a ZnO dispersion Flow chart showing an example of a procedure for generating a TiO ₂ dispersion Flow chart showing an example of a procedure for generating a SiO ₂ dispersion The flowchart which shows an example of the procedure which produces | generates the liquid mixture used as charging layer material Flow chart showing an example of the procedure for generating the material of the blocking layer

Hereinafter, an embodiment of a secondary battery will be described based on the drawings. As shown in FIGS. 1 and 2, the secondary battery 10 includes a first electrode 1, a second electrode 2, and a charging layer 3 sandwiched between the first electrode 1 and the second electrode 2. Yes. The charging layer 3 includes an insulator 4 and a semiconductor 6. In the present embodiment, a plurality of semiconductor fine particles 5 (nanoparticles) are dispersed in the insulator 4 as the semiconductor 6. Although details will be described later, FIG. 2 further restricts the movement of carriers (electrons, holes) to the second electrode 2 between the second electrode 2 and the charge layer 3 with respect to the configuration of FIG. The structure provided with the blocking layer 7 is illustrated. For example, the thicknesses of the first electrode 1 and the second electrode 2 are 200 to 400 [nm], the diameter r of the semiconductor fine particles 5 (semiconductor nanoparticles) is 4 to 20 [nm], and the distance d between the semiconductor fine particles 5 is 1 to 5. [Nm], the thickness of the blocking layer 7 is 100 to 200 [nm]. Although details will be described later, the charge layer 3 is formed at the interface between the intrinsic Fermi level (E _i ) that is the energy level in the center of the band gap of the semiconductor 6 and the semiconductor 6 and the insulator 4. In the state where the difference (φ _S ) from the energy level at the center of the forbidden band is more than twice the difference (φ _F ) between the intrinsic Fermi level (E _i ) and the Fermi level (E _FS ) of the semiconductor 6 In a strong inversion state, carriers (electrons and holes) are accumulated at both ends of the forbidden band.

Here, the strong inversion state will be described. 3 and 4 are energy band diagrams of a MIS junction (Metal-Insulator-Semiconductor Junction) in which a conductor (metal), an insulator, and a semiconductor are joined in this order. In the figure, “M” indicates a conductor (metal), “I” indicates an insulator, and “S” indicates a semiconductor. As the MIS junction, a MOS junction (Metal-Oxide-Semiconductor Junction) using an oxide such as SiO ₂ as an insulator can be employed. The energy band diagram shown in FIG. 3 and the like indicates that the potential energy increases as it goes upward in the figure. 3 and 4, a state in which no bias voltage is applied to the MIS junction (left) and a state in which a large bias voltage is applied (right) are shown side by side. FIG. 3 shows a MIS junction using a p-type semiconductor, and the bias voltage is a positive voltage (V> 0). FIG. 4 shows an MIS junction using an n-type semiconductor, and the bias voltage is a negative voltage (V <0).

3 and 4, “E _V ” indicates an energy level having the highest potential energy in the valence band. In the figure, “E _C ” indicates an energy level having the lowest potential energy in the conduction band. There is a band gap between “E _V ” and “E _C ”. In the figure, “E _FM ” indicates the Fermi level of metal (M), and “E _FS ” indicates the Fermi level of the semiconductor. In the semiconductor or an insulator, the Fermi level E _F is present in the forbidden band. As shown in FIGS. 3 and 4, in a non-biased state in which no bias voltage is applied, the Fermi levels E _F (here, “E _FM ” and “E _FS ”) of bonded (contacted) substances are present. ) Matches.

  As described above, the diagrams on the right side of FIGS. 3 and 4 show band diagrams when a large bias voltage is applied to the metal (M). As shown in FIGS. 3 and 4, the energy band is greatly deviated near the junction surface (interface) between the insulator (I) and the semiconductor (S) due to the bias voltage. Of course, the forbidden band is also greatly displaced with it.

In the figure, “E _i ” indicates the intrinsic Fermi level, which is the energy level at the center of the forbidden band. “Ψ _F ” indicates the difference between intrinsic Fermi level E _i and Fermi level E _F (Semiconductor Fermi level E _FS ). “Φ _S ” indicates the difference between the energy level at the center of the forbidden band and the intrinsic Fermi level E _{i at} the interface between the insulator (I) and the semiconductor (S). On the right side of the energy band diagram of FIG. 3, the center of the energy level of the forbidden band in the interface is below the semiconductor Fermi level E _FS. Further, in the right side of the energy band diagram of FIG. 4, the center of the energy level of the forbidden band in the interface is above a semiconductor Fermi level E _FS. That is, the intrinsic Fermi level E _i is deflected beyond the Fermi level E _FS of the semiconductor for both p-type and n-type. Such a state is called “inversion”. The state illustrated in FIGS. 3 and 4 is a state in which the energy band and the forbidden band are further shifted to a state where “φ _S ≧ 2ψ _F ”, and this state is referred to as a “strong inversion state”. Called. In the inversion state and the strong inversion state, a depletion layer having a width “xd” appears at the boundary between the insulator (I) and the semiconductor (S).

  By the way, the MIS junction has a kind of capacitor structure. 5 and 6 show how carriers (electrons and holes) are accumulated when the MIS junction is in the strong inversion state described above. Similar to FIGS. 3 and 4, FIG. 5 shows an example using a p-type semiconductor, and FIG. 6 shows an example using an n-type semiconductor. In the figure, carriers indicated by “+” indicate holes, and carriers indicated by “−” indicate electrons. As shown in FIG. 5, when a MIS junction using a p-type semiconductor is in a strong inversion state, holes collect on the surface of the semiconductor (S), and the interface between the insulator (I) and the semiconductor (S). Collect electrons. As shown in FIG. 6, when the MIS junction using the n-type semiconductor is in a strong inversion state, electrons gather on the surface of the semiconductor (S), and the insulator (I) and the semiconductor (S) Holes collect at the interface. Electrons have the property of moving to lower potential energy. In the MIS junction using the p-type semiconductor, the energy band is shifted in the direction where the potential energy is low at the interface between the insulator (I) and the semiconductor (S), so that electrons gather at the interface. On the other hand, in the MIS junction using an n-type semiconductor, the energy band is shifted in the direction in which the potential energy is high at the interface between the insulator (I) and the semiconductor (S). Gather.

By the way, the carriers (electrons or holes) collected in this way may move to the metal (M) side. FIG. 7 illustrates an MIS junction using an n-type semiconductor, and includes a first electrode 1 and a second electrode 2 as illustrated in FIG. The Fermi level “E _FM ” of the second electrode 2 is an energy level lower than the lowest energy level “E _C ” of the conduction band. As described above, electrons have a property of moving toward a lower energy level, so that electrons collected on the surface of the semiconductor (I) move to the second electrode 2. In the AC circuit, since positive and negative are periodically switched, electrons do not move unilaterally to the second electrode 2. Therefore, the MIS junction capacitor having the structure illustrated in FIG. 7 is used in the AC circuit. Is preferred. On the other hand, in the DC circuit, as will be described later with reference to FIG. 8, it is preferable to add a function (blocking layer 7) for limiting the movement of carriers (electrons).

  FIG. 8 shows a structure in which a blocking layer 7 that restricts the movement of carriers to the second electrode 2 is provided between the semiconductor (I) and the second electrode 2 with respect to the structure of FIG. 7. For this reason, the blocking layer 7 has a forbidden band width wider than the forbidden band width of the semiconductor fine particles 5. Further, the blocking layer 7 may not have a forbidden band wider than the forbidden band of the semiconductor (I) as long as the following conditions are satisfied. Of course, the forbidden bandwidth is wider than the forbidden bandwidth of the semiconductor (I), and the following conditions may be satisfied. This condition is that when the semiconductor fine particles 5 are n-type, the energy level of the conduction band of the blocking layer 7 is higher than the energy level of the conduction band of the semiconductor fine particles 5, and the energy of the valence band of the blocking layer 7. The level is higher than the energy level of the valence band of the semiconductor fine particles 5. Alternatively, when the semiconductor fine particle 5 is p-type, the energy level of the conduction band of the blocking layer 7 is lower than the energy level of the conduction band of the semiconductor fine particle 5, and the energy level of the valence band of the blocking layer 7. However, it is lower than the energy level of the valence band of the semiconductor fine particles 5.

The case where the semiconductor fine particles 5 are n-type will be described as an example. In the blocking layer 7, the energy level higher than the lowest energy level “E _C ” of the conduction band of the semiconductor (I) is the lowest energy level of the conduction band. It is made of a certain semiconductor material. For example, as shown in FIG. 8, the forbidden band of the blocking layer 7 has a higher energy level than the energy level of the higher forbidden band of the semiconductor 6 (semiconductor fine particles 5) constituting the charging layer 3. It is preferable that the higher and lower energy levels have at least a lower bandwidth than the Fermi level (E _FM ) of the second electrode 2. When such a condition is satisfied, the movement of carriers (electrons) from the semiconductor 6 constituting the charging layer 3 to the second electrode 2 is limited.

  As described above, in the present embodiment, as shown in FIGS. 1 and 2, the semiconductor 6 is a plurality of semiconductor fine particles 5 arranged dispersed in the insulator 4. Therefore, one semiconductor fine particle 5 is covered with an insulator. In a cross-sectional view, the semiconductor 6 (semiconductor fine particles 5) is sandwiched between the insulators 4 on both sides connecting both electrodes (1, 2). FIG. 9 and FIG. 10 illustrate energy band diagrams of the secondary battery 10 of such a mode. 9 and 10 illustrate energy band diagrams in the structure in which the blocking layer 7 is provided as described above. Further, FIG. 9 shows an energy band diagram during charging, and FIG. 10 shows an energy band diagram during discharging.

As described above, electrons have a property of trying to move toward a lower energy level. As shown in FIG. 9, when a negative bias voltage is applied to the first electrode 1 to make a strong inversion state, electrons are accumulated on the surface of the semiconductor fine particles 5. The energy level of the second electrode 2 is lower than the lowest energy level “E _C ” of the conduction band of the semiconductor fine particles 5, but the movement of electrons is hindered by the blocking layer 7, so that the charged state is maintained. In this embodiment, since the lowest energy level of the blocking layer 7 is higher than the lowest energy level “E _V ” of the forbidden band, holes move to the second electrode 2. can do. During discharging, the absolute value of the bias voltage of the first electrode 1 is reduced as shown in FIG. When the energy level of the first electrode 1 becomes lower than the lowest energy level “E _C ” of the conduction band of the semiconductor fine particles 5, electrons move from the surface of the semiconductor fine particles 5 to the first electrode 1.

  In the above, the principle of a single capacitor obtained by applying a bias voltage to the MIS junction to obtain a strong inversion state has been described. Hereinafter, formation of a large-capacity capacitor using such a principle will be described.

  The first condition for increasing the capacity is to use a plurality of capacitors. When a plurality of capacitors are connected in parallel, the combined capacity is the sum of the capacities of the plurality of capacitors. As illustrated in FIGS. 1 and 2, in the present embodiment, since the plurality of semiconductor fine particles 5 are dispersed and arranged in the insulator 4, between the first electrode 1 and the second electrode 2. Are formed with a plurality of MIS junctions in which each semiconductor fine particle 5 is a semiconductor 6. That is, as shown in FIG. 11, a plurality of capacitors (core shells) are formed between the electrodes, and are connected in parallel to both electrodes. Therefore, the capacity of the secondary battery 10 can be increased.

Further, the capacitance “C ₀ ” of the capacitor is defined as “C ₀ = εS ₀ //, where“ S ₀ ”is the surface area of the electrodes,“ d ₀ ”is the distance between the electrodes, and“ ε ”is the dielectric constant between the electrodes. d ₀ ″. By including a plurality of semiconductor fine particles 5 in the charge layer 3, a large surface area “S ₀ ” can be taken. If the semiconductor fine particles 5 are small, the gaps in the charging layer 3 can be reduced, and the semiconductor fine particles 5 can be densely distributed. As a result, the total surface area “S ₀ ” also increases. As one aspect, the diameter r of the semiconductor fine particles 5 is preferably 4 to 2000 nm. The surface area “So” of the semiconductor fine particles 5 increases as the diameter r of the semiconductor fine particles 5 increases, but the number of the semiconductor fine particles 5 per unit volume in the charging layer 3 decreases. The larger the number of semiconductor fine particles 5 in the charging layer 3, the larger the total surface area “So” as a capacitor. Accordingly, the diameter r of the semiconductor fine particles 5 is preferably set to an optimum value that increases the total surface area “So” including the interval of the semiconductor fine particles 5 described later. For example, when miniaturization is possible, the diameter of the semiconductor fine particles 5 is preferably 4 to 200 nm. Further, when further miniaturization is possible, the diameter of the semiconductor fine particles 5 is preferably 4 to 20 nm.

Further, since the distance “d ₀ ” between the electrodes is preferably shorter than “C ₀ = εS ₀ / d ₀ ”, the thickness of the insulator 4 in the charging layer 3 is preferably thin. The thickness of the insulator 4 can be set as the interval between the semiconductor fine particles 5 in the charging layer 3. As one aspect, the interval d between the semiconductor fine particles 5 in the charging layer 3 is preferably 1 to 2000 nm (see FIG. 9 and FIG. 10 and the like). As described above, the distance “d ₀ ” between the electrodes is preferably short, and more preferably, the interval between the plurality of semiconductor fine particles 5 in the charging layer 3 is 1 to 200 nm. Naturally, the interval between the plurality of semiconductor fine particles 5 in the charging layer 3 is further preferably 1 to 20 nm.

  Furthermore, since it is better that the dielectric constant “ε” is large, the semiconductor fine particles 5 are preferably formed using a semiconductor material having a relatively high dielectric constant. However, as the dielectric constant “ε” increases, the physical properties approach an insulator, so the type of the semiconductor 6 (semiconductor fine particles 5) is selected within the appropriate relationship between the required conductivity and the dielectric constant “ε”. It is preferable. Specific semiconductor materials will be described later together with a method for manufacturing the secondary battery 10.

  Hereinafter, a preferable method for manufacturing the secondary battery 10 will be described. FIG. 12 illustrates the procedure of forming the first electrode 1 in order on the substrate serving as the base material. FIG. 13 exemplifies a procedure of forming the substrate as a base material in order from the second electrode 2, contrary to FIG. 12.

As shown in FIG. 12, the thin film used as the 1st electrode 1 with respect to a board | substrate material is first formed into a film by sputtering (# 1: 1st electrode formation process (electrode formation 1st process)). The thickness of the thin film (first electrode 1) is preferably 100 to 500 [nm], for example. In addition to sputtering, a thin film may be formed by vapor deposition or plating. As the substrate material, it is preferable to use ceramics such as SiO ₂ or insulating materials such as a resin sheet. Moreover, when the mounting property to the apparatus as the secondary battery 10 is considered, it is preferable that the substrate material is a flexible substrate or the like. The material of the first electrode 1 (including the second electrode 2) is copper, gold, silver, platinum, titanium nitride, aluminum titanium, zinc, chromium, ITO (Indium Tin Oxide: indium tin oxide (tin-doped indium oxide)), FTO (Fluorine Doped Tin Oxide) can be used.

  Next, the charge layer 3 is formed on the first electrode 1 (# 2: charge layer forming step). As described above, in the charging layer 3, the semiconductor fine particles 5 are dispersedly arranged in the insulator 4. For this reason, the charge layer material for forming the charge layer 3 is a material in which the insulator 4 and the semiconductor 6 (semiconductor fine particles 5) are mixed. In this embodiment, after the single layer of the semiconductor fine particles 5 is generated, the layer of the insulator 4 is not formed so as to fill the gap between the semiconductor fine particles 5, but the semiconductor fine particles 5 are formed in the insulator 4. The charge layer 3 is generated at once using a so-called dispersed liquid charge layer material in which is dispersed. A method for producing the charge layer material will be described later with reference to FIGS.

  In the charge layer forming step # 2, first, the charge layer material is spin-coated on the electrode thin film (here, the first electrode 1) (# 2a). For example, as one aspect, 2000-4000 [rpm], 1-2 [min. ] Spin coating is carried out under the conditions. Note that not only spin coating but also techniques such as dip coating, spraying, and doctor blade may be used. Next, it is dried in a state where the charge layer material spreads on the electrode thin film (# 2b). For example, as one aspect, on a hot plate kept at 50 to 70 [° C.], 20 to 60 [min. ] During drying. Thereafter, annealing is performed to form the charge layer 3 (# 2c). For example, as one aspect, 300 to 400 [° C.] and 20 to 60 [min. ], Annealing is performed. The thickness of the charging layer 3 is preferably, for example, 500 to 3000 [nm].

  When the charge layer 3 is formed, the blocking layer 7 is formed thereon (# 3: blocking layer forming step). The blocking layer 7 may be formed by spin coating and annealing similarly to the charging layer 3 (# 3a, # 3b), or may be formed by sputtering similarly to the electrode thin film (# 3c). Since the blocking layer 7 is provided to limit the movement of carriers, it is preferable that the blocking layer 7 is formed by a method that does not allow a gap such as a pinhole. The thickness of the blocking layer 7 is preferably 100 to 400 [nm], for example. A method for producing the material of the blocking layer 7 (blocking layer material) will be described later with reference to FIG. Moreover, as one aspect, annealing is performed at 300 to 400 [° C.] for 10 to 20 [min. It is carried out. Finally, a thin film to be the second electrode 2 is formed on the blocking layer 7 by sputtering (# 4: second electrode formation step (electrode formation second step)). Similar to the first electrode 1, a thin film may be formed by vapor deposition or plating in addition to sputtering. Similar to the first electrode 1, the thickness of the thin film (second electrode 2) is preferably, for example, 100 to 500 [nm].

  In the above, as a preferable dimension range, the thickness of the first electrode 1 and the second electrode 2 is about 100 to 500 [nm], the thickness of the charging layer 3 is about 500 to 3000 [nm], and the blocking layer 7 It was exemplified that the thickness was about 100 to 400 [nm]. For example, as one aspect, the secondary battery 10 has a thickness of the first electrode 1 and the second electrode 2 of 300 [nm], a thickness of the charging layer 3 of 1000 [nm], and a thickness of the blocking layer 7 of 200. It is preferable to be configured as [nm].

  By the way, blocking layer production | generation process # 3 is a process of forming blocking layer 7 using blocking layer material, but when semiconductor fine particle 5 is n type, blocking layer material is the conduction band of blocking layer material. The semiconductor material has a higher energy level than the energy level of the conduction band of the semiconductor fine particles 5, and the energy level of the valence band of the blocking layer material is higher than the energy level of the valence band of the semiconductor fine particles 5. In addition, when the semiconductor fine particles 5 are p-type, the blocking layer material has a lower energy level of the conduction band of the blocking layer material than the energy level of the conduction band of the semiconductor fine particles 5, and the valence band of the blocking layer material. This is a semiconductor material whose energy level is lower than the energy level of the valence band of the semiconductor fine particles 5. Alternatively, the blocking layer material is a semiconductor material in which the forbidden band of the blocking layer 7 is wider than the forbidden band of the semiconductor fine particles 5.

  As described above, FIG. 13 exemplifies the procedure of forming the substrate as a base material in order from the second electrode 2, contrary to FIG. 12. That is, the secondary battery 10 is manufactured by performing each step in the order of the second electrode forming step # 4, the blocking layer forming step # 3, the charging layer forming step # 2, and the first electrode forming step # 1. The details of each step are as described above with reference to FIG. In the procedure of FIG. 13, the second electrode formation step # 4 is the first electrode formation step, and the first electrode formation step # 1 is the second electrode formation step. When the blocking layer 7 is not provided, the blocking layer forming step # 3 may be omitted in the flowcharts of FIGS.

Hereinafter, an example of creating the charge layer material will be described later with reference to FIGS. FIG. 14 shows an example of producing a dispersion of semiconductor fine particles 5 using zinc oxide (ZnO) as the semiconductor 6. FIG. 15 shows an example of producing a dispersion of semiconductor fine particles 5 using titanium dioxide (TiO ₂ ) as the semiconductor 6. FIG. 16 shows an example of generating a dispersion of semiconductor fine particles 5 using silicon dioxide (SiO ₂ ) as the semiconductor 6. FIG. 17 shows an example in which a mixed liquid of the dispersion liquid (inorganic oxide material) of the semiconductor fine particles 5 generated according to FIGS. 14 to 16 and the insulator material is generated.

  As shown in FIG. 14, in the production of the ZnO dispersion, first, a mixed liquid of zinc acetate dihydrate and methanol is produced (# 11). Next, the mixed solution is heated and stirred. During the stirring, potassium hydroxide is dropped into the mixed solution (# 12). As one aspect, the liquid mixture is heated and stirred while being kept at 50 to 70 [° C.], and potassium hydroxide is added dropwise during the stirring. Thereafter, the mixture is further stirred under nitrogen gas flow conditions, for example, 1.5 to 2.5 [h] (# 13). Next, the mixed solution is centrifuged (# 14). After centrifugation, the unnecessary liquid is discarded, and the remaining precipitate is washed with methanol (# 15) and dried with nitrogen dry gas (# 16). Finally, a ZnO dispersion is produced by dispersing in butanol (# 17).

As shown in FIG. 15, in the production of the TiO ₂ dispersion, first, a mixture of TTIP (Titanium TetraIsoPropoxide: tetraisopropyl orthotitanate), IPA (IsoPropyl Alcohol = Isopropanol = 2-propanol) and water is produced. (# 21A). At this time, a small amount of nitric acid may be added as a catalyst. Then, this mixed liquid is heated and stirred, and a TiO ₂ dispersion liquid is generated by a so-called sol-gel method involving hydrolysis (# 22). As one aspect, for example, it is preferable that the above mixed solution is stirred for 7 to 9 [h] while being heated and kept at 50 to 70 [° C.].

The SiO ₂ dispersion is produced in the same manner as the TiO ₂ dispersion. As shown in FIG. 16, in the generation of the SiO ₂ dispersion, first, a mixed liquid of TEOS (Tetra Ethoxy Silane), ethanol, and water is generated (# 21B). In this case as well, a small amount of nitric acid may be added as a catalyst. Then, this mixed solution is heated and stirred to produce a SiO ₂ dispersion (# 22). Similar to the generation of the TiO ₂ dispersion, as one aspect, for example, the above mixed liquid is preferably stirred for 7 to 9 [h] while being heated and kept at 50 to 70 [° C.]. It is.

As described above, the TiO ₂ dispersion and the SiO ₂ dispersion are produced in the same procedure. That is, a sol containing an alkoxide such as TTIP or TEOS is generated (# 21: FIGS. 15 and 16), and is heated and stirred to be in a gel state (# 22). Material is generated.

  The charge layer material is generated using the inorganic oxide material (dispersion liquid containing the semiconductor fine particles 5) generated as described above. As shown in FIG. 17, first, a mixed liquid of an inorganic oxide material (a dispersion liquid containing semiconductor fine particles 5) and an insulator material is generated (# 31). And this liquid mixture is 3-5 [min.] Using a vortex mixer etc., for example. ] To produce the charge layer material (# 32).

In the above, ZnO, TiO ₂ , and SiO ₂ are exemplified as the inorganic oxide material (inorganic oxide semiconductor), but doped with AZO (Al doped ZnO), GZO (Ga doped ZnO), and niobium (Nb). A highly conductive semiconductor material such as TiO ₂ may be used. As the insulator material, ceramics (SiO ₂ ) or an insulating resin is preferably used.

FIG. 18 shows an example of a procedure for generating the material of the blocking layer 7 (blocking layer material). As described above, the semiconductor of the blocking layer 7 has a wider band gap than the semiconductor of the charge layer 3 (for example, ZnO, TiO ₂ , SiO _2, etc.). In the present embodiment, a procedure for generating a solution containing nickel oxide (NiO) as such a semiconductor is exemplified. As shown in FIG. 18, first, a mixed solution of nickel acetate (II) and methanol is generated (# 41). Next, the mixed liquid is stirred at room temperature, and diethanolamine is added dropwise during the stirring (# 42). Thereafter, for example, stirring is continued for 1 to 3 [h], and a NiO solution is generated (# 43). As a material for the blocking layer 7, ZiO or an organic semiconductor can be used.

In the above, the case where the secondary battery 10 accumulates carriers at both ends of the forbidden band in the strong inversion state is exemplified. However, the secondary battery 10 is manufactured by the manufacturing method described with reference to FIGS. The secondary battery 10 can accumulate carriers even in other states. For example, the carriers may be accumulated not in the strong inversion state of “φ _S ≧ 2ψ _F ” but in the inversion state of “0 <φ _S <2ψ _F ”. Further, in the inversion state and the strong inversion state, carriers may be accumulated in a state where a reverse bias voltage is applied, that is, in a so-called accumulation state in which a depletion layer is not formed.

  In the above description, the secondary battery 10 using an n-type semiconductor as the semiconductor fine particle 5 is illustrated with reference to FIGS. 7 to 10. However, the semiconductor fine particle 5 may be a p-type semiconductor.

[Outline of Embodiment]
Hereinafter, the outline of the secondary battery (10) described above will be briefly described.

As one aspect, the secondary battery (10) is sandwiched between the first electrode (1), the second electrode (2), and the first electrode (1) and the second electrode (2). And a charge layer (3) having an insulator (4) and a semiconductor (6), wherein the charge layer (3) is an intrinsic Fermi that is at the center energy level of the forbidden band of the semiconductor (6). The difference (φ _S ) between the level (E _i ) and the energy level at the center of the semiconductor forbidden band at the interface between the semiconductor (6) and the insulator (4) is the intrinsic Fermi level ( In a strong inversion state that is twice or more the difference (ψ _F ) between E _i ) and the Fermi level (E _FS ) of the semiconductor, carriers are accumulated at both ends of the forbidden band, (6) is a plurality of semiconductor fine particles (5) dispersed in the insulator (4).

  By dispersing the semiconductor fine particles (5) in the insulator (4), the first electrode (1), the second electrode (2), the insulator (4), and the semiconductor fine particles (5) are joined. A large number of core shells of metal-insulator-semiconductor junction capacitors can be formed. Since a plurality of capacitors can be provided in parallel connection between the first electrode (1) and the second electrode (2), the capacity of the secondary battery (10) can be increased. In addition, the secondary battery (10) does not require any special treatment such as photoexcitation structure change and stores carriers at both ends of the forbidden band in the strong inversion state, so that the secondary battery (10) can be easily installed. Can be configured. Moreover, since this secondary battery (10) is not a chemical battery but an electron battery using MIS junction, a high input / output density can be obtained. Thus, according to this configuration, it is possible to provide a secondary battery (10) having a high input / output density and a large capacity.

  Moreover, as one aspect, the secondary battery (10) is a blocking that restricts the movement of carriers to the second electrode (2) between the second electrode (2) and the charging layer (3). When the semiconductor fine particle (5) is an n-type, the energy level of the conduction band of the blocking layer (7) is more than the energy level of the conduction band of the semiconductor fine particle (5). The energy level of the valence band of the blocking layer (7) is higher than the energy level of the valence band of the semiconductor fine particles (5), and the semiconductor fine particles (5) are p-type. The energy level of the conduction band of the blocking layer (7) is lower than the energy level of the conduction band of the semiconductor fine particles (5), and the energy level of the valence band of the blocking layer (7) is Of valence band of semiconductor fine particles (5) It is lower and more suitable than energy levels. Alternatively, as one aspect, the secondary battery (10) is a blocking device that restricts carrier movement to the second electrode (2) between the second electrode (2) and the charging layer (3). A layer (7) is provided, and the forbidden band of the blocking layer (7) is preferably wider than the forbidden band of the semiconductor fine particles (5). According to this configuration, the carrier is prevented from moving from the charge layer (3) to the second electrode (2), and the storage state of the secondary battery (10) can be appropriately maintained.

  As one aspect, the semiconductor fine particles (5) preferably have a diameter of 4 to 2000 nm. According to this configuration, since the semiconductor fine particles (5) can be densely dispersed in the charge layer (3), the capacity of the secondary battery (10) can be increased. More preferably, the diameter of the semiconductor fine particles (5) is 4 to 200 nm. Further, it is more preferable that the diameter of the semiconductor fine particles (5) is 4 to 20 nm.

  As one aspect, the interval between the plurality of semiconductor fine particles (5) in the charge layer (3) is preferably 1 to 2000 nm. The capacity of the capacitor increases as the distance between the electrodes decreases. Therefore, the capacity of the secondary battery (10) is increased when the distance between the semiconductor fine particles (5), which can be regarded as the distance between the electrodes, that is, the thickness of the semiconductor (4) in the charging layer (3) is thin. be able to. More preferably, the interval between the plurality of semiconductor fine particles (5) in the charging layer (3) is 1 to 200 nm. Further, it is more preferable that the interval between the plurality of semiconductor fine particles (5) in the charge layer (3) is 1 to 20 nm.

  As one aspect, when the semiconductor fine particle is an n-type semiconductor, charging is performed by applying a negative bias voltage to the first electrode, and when the semiconductor fine particle is a p-type semiconductor, It is preferable to perform charging by applying a positive bias voltage to the first electrode. According to this configuration, the secondary battery (10) can be used by appropriately realizing the strong inversion state according to the characteristics of the n-type semiconductor and the p-type semiconductor.

Moreover, as one aspect, the charge layer (3) sandwiched between the first electrode (1), the second electrode (2), and the first electrode (1) and the second electrode (2). And a secondary battery manufacturing method for manufacturing a secondary battery (10) having at least
An electrode formation first step (# 1, # 4) for forming a thin film to be one of the first electrode (1) and the second electrode (2) on the substrate;
After the first electrode formation step (# 1, # 4), the charge layer (3) is formed using a charge layer material in which a plurality of semiconductor fine particles (5) are dispersed in an insulator (4). Charging layer forming step (# 2);
After the charge layer forming step (# 2), an electrode forming second step (# 4, # 1) for forming a thin film to be the other of the first electrode (1) and the second electrode (2). And).

  By forming the charge layer (3) using a charge layer material in which a plurality of semiconductor fine particles are dispersed in an insulator, a large number of core shells of MIS junction capacitors can be formed in the charge layer (3). it can. Moreover, since the semiconductor fine particles (5) are dispersed in the insulator (4) while maintaining an appropriate separation distance in the charge layer material, the secondary battery (10) can be stably formed.

  Moreover, as one aspect, the secondary battery (10) restricts carrier movement to the second electrode (2) between the second electrode (2) and the charging layer (3). A blocking layer (7), wherein the secondary battery manufacturing method is a step performed after the first electrode formation step (# 4) and before the charging layer formation step (# 2), or Blocking that is performed after the charge layer forming step (# 2) and before the second electrode forming step (# 4), and forming the blocking layer (7) using a blocking layer material A layer forming step (# 3), wherein the blocking layer material has an energy level of a conduction band of the blocking layer material when the semiconductor fine particles (5) are n-type. Higher than the energy level of the conduction band of the When the energy level of the valence band of the king layer material is higher than the energy level of the valence band of the semiconductor fine particles (5), and the semiconductor fine particles (5) are p-type, the blocking is performed. The energy level of the conduction band of the layer material is lower than the energy level of the conduction band of the semiconductor fine particles (5), and the energy level of the valence band of the blocking layer material is the valence band of the semiconductor fine particles (5). A semiconductor material having a lower energy level is preferable. Alternatively, as one aspect, the blocking layer material is preferably a semiconductor material in which the forbidden band of the blocking layer (7) is wider than the forbidden band of the semiconductor fine particles (5). According to this method, the blocking layer (7) can be appropriately formed. And a blocking layer (7) prevents a carrier from moving from a charge layer (3) to a 2nd electrode (2), and can maintain the electrical storage state of a secondary battery (10) appropriately.

1: First electrode 2: Second electrode 3: Charging layer 4: Insulator 5: Semiconductor fine particle 6: Semiconductor 10: Secondary battery E _i : Intrinsic Fermi level E _FS : Fermi level of semiconductor ψ _F : Intrinsic Fermi Difference between level and Fermi level φ _s : Difference between the energy level at the center of the forbidden band and the intrinsic Fermi level at the interface between the semiconductor and the insulator E _C : Minimum energy level of the conduction band of semiconductor fine particles

Claims (9)

A first electrode;
A second electrode;
A charge layer sandwiched between the first electrode and the second electrode and having an insulator and a semiconductor,
The charging layer has a difference between an intrinsic Fermi level that is an energy level at the center of the semiconductor forbidden band and an energy level at the center of the semiconductor forbidden band at the interface between the semiconductor and the insulator. In the strong inversion state, which is a state of at least twice the difference between the intrinsic Fermi level and the semiconductor Fermi level, carriers are accumulated at both ends of the forbidden band,
The secondary battery, wherein the semiconductor is a plurality of semiconductor fine particles dispersed in the insulator. A blocking layer that restricts the movement of carriers to the second electrode between the second electrode and the charging layer,
When the semiconductor fine particles are n-type, the energy level of the conduction band of the blocking layer is higher than the energy level of the conduction band of the semiconductor fine particles, and the energy level of the valence band of the blocking layer is Higher than the energy level of the valence band of fine particles,
When the semiconductor fine particles are p-type, the energy level of the conduction band of the blocking layer is lower than the energy level of the conduction band of the semiconductor fine particles, and the energy level of the valence band of the blocking layer is The secondary battery according to claim 1, wherein the secondary battery is lower than an energy level of a valence band of fine particles. A blocking layer that restricts the movement of carriers to the second electrode between the second electrode and the charging layer,
The secondary battery according to claim 1, wherein a forbidden band of the blocking layer is wider than a forbidden band of the semiconductor fine particles.   The secondary battery according to any one of claims 1 to 3, wherein the semiconductor fine particles have a diameter of 4 to 2000 nm.   The secondary battery according to any one of claims 1 to 4, wherein an interval between the plurality of semiconductor fine particles in the charge layer is 1 to 2000 nm. When the semiconductor fine particle is an n-type semiconductor, charging is performed by applying a negative bias voltage to the first electrode,
6. The secondary battery according to claim 1, wherein when the semiconductor fine particle is a p-type semiconductor, charging is performed by applying a positive bias voltage to the first electrode. A secondary battery manufacturing method for manufacturing a secondary battery comprising at least a first electrode, a second electrode, and a charging layer sandwiched between the first electrode and the second electrode,
An electrode formation first step of forming a thin film to be any one of the first electrode and the second electrode on a substrate;
After the electrode formation first step, a charge layer forming step of forming the charge layer using a charge layer material in which a plurality of semiconductor fine particles are dispersed in an insulator;
After the charging layer forming step, an electrode forming second step of forming a thin film that becomes the other electrode of the first electrode and the second electrode,
A secondary battery manufacturing method comprising: The secondary battery includes a blocking layer that restricts carrier movement to the second electrode between the second electrode and the charging layer,
A step performed after the electrode formation first step and before the charge layer formation step, or a step performed after the charge layer formation step and before the electrode formation second step, A blocking layer forming step of forming the blocking layer using a blocking layer material,
The blocking layer material is
When the semiconductor fine particles are n-type, the energy level of the conduction band of the blocking layer material is higher than the energy level of the conduction band of the semiconductor fine particles, and the energy level of the valence band of the blocking layer material is It is a semiconductor material that is higher than the energy level of the valence band of the semiconductor fine particles,
When the semiconductor fine particles are p-type, the energy level of the conduction band of the blocking layer material is lower than the energy level of the conduction band of the semiconductor fine particles, and the energy level of the valence band of the blocking layer material is The secondary battery manufacturing method of Claim 7 which is a semiconductor material lower than the energy level of the valence band of the said semiconductor fine particle. The secondary battery includes a blocking layer that restricts carrier movement to the second electrode between the second electrode and the charging layer,
A step performed after the electrode formation first step and before the charge layer formation step, or a step performed after the charge layer formation step and before the electrode formation second step, A blocking layer forming step of forming the blocking layer using a blocking layer material,
The secondary battery manufacturing method according to claim 7 or 8, wherein the blocking layer material is a semiconductor material in which a forbidden band of the blocking layer is wider than a forbidden band of the semiconductor fine particles.

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