JP2017005600A - Serial data receiver, serial data transmission system, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial data receiver capable of securely detecting a burst error.SOLUTION: A receiver 20 includes a deserializer circuit 21 for detecting a level of a received serial data signal, an error detection circuit 22 for detecting an error of the received serial data signal, and a control circuit 26 for controlling operation of the receiver 20 based on the level of the received serial data signal and an error. If the error detection circuit 22 detects an error of the received serial data signal and an amplitude of the received serial data signal is larger than a first threshold value Th1, or if the amplitude of the received serial data signal is smaller than a second threshold value Th2, smaller than the first threshold value Th1, or if a center voltage of the received serial data signal is out on a predetermined voltage range, the control circuit 26 halts serial data signal reception.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a serial data receiving device, a serial data transmission system, and an electronic device.

  In order to cope with an increase in transmission speed and to suppress an increase in the number of signal lines, a parallel interface is being replaced with a serial interface (see, for example, Patent Document 1).

  In a serial data transmission system including a transmission device and a reception device having a serial interface, a signal line for transmitting a data signal may be shared in order to transmit a clock signal from the transmission device to the reception device. In this case, the receiving device regenerates the clock signal from the received data signal.

  In high-speed serial communication, compared to parallel communication, communication quality is likely to be degraded due to the influence of noise generated on the transmission path. In order to avoid the influence of this noise, data including a transmission device that transmits a data signal to which an error correction code is added, and a reception device that corrects an error in the data signal generated on the transmission path using the error correction code A transmission system is known (see, for example, Patent Document 2). In addition, a technique is known in which the error correction code is changed according to the communication quality (transmission path quality) on the transmission path, and the noise resistance is further improved.

  The invention of Patent Document 2 uses FEC (Forward Error Correction) to control the communication speed based on the data reception state including either or both of data error and delay in the communication network, and transmits the data. To do. In the invention of Patent Document 2, when information on data error is received, it is determined whether the data error occurrence pattern in the communication network is bursty according to the data communication speed, and based on the determination result. To calculate FEC parameters. In this way, it is determined whether or not the generated error is bursty, and the FEC redundancy is excessively increased by changing the FEC redundancy to a value suitable for the error excluding the burst error. Bad effects are prevented. In addition, by calculating the optimum FEC parameters according to the communication speed acquired from the communication speed control function, it is possible to change the FEC parameters in cooperation with the communication speed control function.

  In the invention of Patent Document 2, it is determined whether or not a burst error has occurred based on the error rate after error correction or based on whether or not the error continuous size before and after error correction is greater than or equal to a threshold value. doing. However, when the receiving apparatus includes a digital circuit that operates based on a clock signal reproduced from the received data signal, there are the following problems. When a burst error occurs in the data signal received by the receiving device, the receiving device cannot recover the clock signal from the data signal. In this case, since the digital circuit of the receiver does not operate, error correction cannot be performed to detect a burst error, and a request signal (such as a signal for changing the error correction code) is transmitted from the receiver to the transmitter. You can't do that either. For this reason, the state in which the transmission device and the reception device cannot communicate with each other continues, and communication must be reset after a predetermined time has elapsed.

  For this reason, a new method for reliably detecting the occurrence of a burst error in the receiving apparatus is required.

  An object of the present invention is to provide a serial data receiving apparatus capable of reliably detecting the occurrence of a burst error.

According to the serial data receiving device of one aspect of the present invention,
In a serial data receiving device that receives a serial data signal from a serial data transmitting device, the serial data receiving device includes:
A level detection circuit for detecting the level of the received serial data signal;
An error detection circuit for detecting an error in the received serial data signal;
A control circuit for controlling the operation of the serial data receiving device based on the level and error of the received serial data signal,
The control circuit includes:
When an error of the received serial data signal is detected by the error detection circuit; and
When the amplitude of the received serial data signal is larger than a first threshold value, or when the amplitude of the received serial data signal is smaller than a second threshold value smaller than the first threshold value When small, or when the center voltage of the received serial data signal is outside a predetermined voltage range,
The reception of the serial data signal is stopped.

  According to the serial data receiving apparatus according to the aspect of the present invention, it is possible to reliably detect the occurrence of a burst error.

1 is a block diagram showing a configuration of a serial data transmission system 1 according to a first embodiment of the present invention. It is a figure explaining the random error which generate | occur | produces by the random noise in the signal wire | line 31 of FIG. It is a figure explaining the burst error which arises by the burst noise in the signal line 31 of FIG. It is a wave form diagram which shows the normal serial data signal received by the receiver 20 of FIG. It is a wave form diagram which shows the serial data signal which has the abnormally big amplitude received by the receiver 20 of FIG. It is a wave form diagram which shows the serial data signal which has the abnormally small amplitude received by the receiver 20 of FIG. It is a wave form diagram which shows the serial data signal which has the unusually big center voltage received by the receiver 20 of FIG. It is a flowchart which shows the data reception process performed by the control circuit 26 of the receiver 20 of FIG. It is a block diagram which shows the structure of 1 A of serial data transmission systems which concern on the 2nd Embodiment of this invention. 10 is a timing chart showing transmission of a serial data signal and a control signal in the serial data transmission system 1A of FIG. It is a block diagram which shows the structure of the serial data transmission system 1B which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of 1 C of serial data transmission systems which concern on the 4th Embodiment of this invention. FIG. 13 is a diagram showing data signal interleaving and deinterleaving in the serial data transmission system 1 </ b> C of FIG. 12. It is a block diagram which shows the structure of serial data transmission system 1D which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the structure of the serial data transmission system 1E which concerns on the 6th Embodiment of this invention.

  Features of the serial data transmission system according to the embodiment of the present invention will be described in detail with reference to the following drawings.

First embodiment.
FIG. 1 is a block diagram showing a configuration of a serial data transmission system 1 according to the first embodiment of the present invention. The serial data transmission system 1 includes a transmission device 10 and a reception device 20 that are connected to each other via signal lines 31 and 32. The transmission device 10 and the reception device 20 are a serial data transmission device and a serial data reception device that transmit a serial data signal via a signal line 31 that is a serial bus, respectively. The transmission device 10 converts the original parallel data signal input from the preceding circuit via the parallel bus into a serial data signal, and transmits the serial data signal to the reception device 20 via the signal line 31. The receiving device 20 converts the serial data signal received from the transmitting device 10 via the signal line 31 into an original parallel data signal, and outputs the original parallel data signal to a subsequent circuit via the parallel bus.

  The signal line 31 is a harness including a differential signal line such as, for example, PCI Express. The signal line 32 is a harness including an arbitrary signal line for sending a control signal from the reception device 20 to the transmission device 10.

  The transmission apparatus 10 includes an error correction encoding circuit 11, an 8B10B encoding circuit 12, a serializer circuit 13, and a control circuit 14.

  The error correction coding circuit 11 calculates an error correction code with respect to the input original parallel data signal by selectively using one of a plurality of error correction codes under the control of the control circuit 14. Append. The error correction coding circuit 11 can use, for example, a plurality of error correction codes each having a different coding rate. The output signal of the error correction encoding circuit 11 is sent to the 8B10B encoding circuit 12 as an 8-bit parallel data signal.

  The 8B10B encoding circuit 12 converts each 8-bit symbol of the signal sent from the error correction encoding circuit 11 into a predetermined 10-bit symbol for 8B10B encoding in order to suppress the DC component. The output signal of the 8B10B encoding circuit 12 is sent to the serializer circuit 13 as a 10-bit parallel data signal.

  The serializer circuit 13 converts the parallel data signal sent from the 8B10B encoding circuit 12 into a serial data signal, and transmits the serial data signal to the receiving device 20 via the signal line 31.

  The control circuit 14 of the transmission device 10 controls the operation of the transmission device 10 according to the control signal transmitted from the reception device 20. In particular, the control circuit 14 sets an error correction code used in the error correction coding circuit 11 and changes the error correction code used in the error correction coding circuit 11 according to the control signal sent from the receiving device 20. To do. Further, the control circuit 14 stops the transmission of the serial data signal by the transmission device 10 according to the control signal transmitted from the reception device 20.

  The receiving device 20 includes a deserializer circuit 21, an error detection circuit 22, a 10B8B decoding circuit 23, an error correction decoding circuit 24, a register 25, and a control circuit 26.

  The deserializer circuit 21 converts the serial data signal received from the transmission device 10 via the signal line 31 into a parallel data signal. The output signal of the deserializer circuit 21 is sent to the error detection circuit 22 and the 10B8B decoding circuit 23 as a 10-bit parallel data signal. The deserializer circuit 21 also operates as a level detection circuit that detects the level of the received serial data signal. The deserializer circuit 21 compares the detected level with a voltage threshold preset in the register 25, and determines whether the level of the received serial data signal is normal or abnormal. The voltage threshold will be described later with reference to FIGS. The deserializer circuit 21 sends a signal indicating the comparison result (whether the level of the received serial data signal is normal or abnormal) to the control circuit 26. Further, the deserializer circuit 21 includes a clock recovery circuit, and recovers a clock signal for internal operation of the receiving device 20 from the received serial data signal.

  The error detection circuit 22 detects an error in the received serial data signal by comparing each 10-bit symbol of the signal sent from the deserializer circuit 21 with a predetermined 10-bit symbol of 8B10B encoding. The error detection circuit 22 sends a signal indicating the presence / absence of an error in the received serial data signal to the control circuit 26.

  The 10B8B decoding circuit 23 converts a 10-bit symbol of the signal sent from the deserializer circuit 21 into a predetermined 8-bit symbol for 8B10B encoding. The output signal of the 10B8B decoding circuit 23 is sent to the error correction decoding circuit 24 as an 8-bit parallel data signal.

  The error correction decoding circuit 24 selectively uses one of a plurality of error correction codes under the control of the control circuit 26. The error correction decoding circuit 24 corrects the error of the data signal sent from the 10B8B decoding circuit 23 using the error correction code added by the error correction encoding circuit 11 of the transmission apparatus 10. The error correction decoding circuit 24 outputs the original parallel data signal.

  The control circuit 26 of the reception device 20 controls the operation of the reception device 20 based on the level of the serial data signal detected by the deserializer circuit 21 and the error of the serial data signal detected by the error detection circuit 22. When detecting an error in the serial data signal, the control circuit 26 determines whether a random error has occurred or a burst error has occurred based on the level of the serial data signal. The control circuit 26 controls the control signal for changing the error correction code used in the error correction coding circuit 11 or the transmission of the serial data signal by the transmission device 10 based on the determination result of the random error or the burst error. The signal is sent to the transmitter 10. When a control signal for stopping the transmission of the serial data signal is sent to the transmission device 10, the control circuit 26 of the reception device 20 further stops the error detection by the error detection circuit 22, and the number of error detections counted during communication. To reset.

  For example, the control circuit 14 of the transmission device 10 resumes transmission of the serial data signal when a predetermined time elapses after receiving a control signal instructing to stop transmission of the serial data signal. In the receiving device 20, if the error information detected by the error detection circuit 22 before the serial data signal transmission is stopped remains after the transmission of the serial data signal is resumed, the transmission path quality cannot be accurately determined. In the present embodiment, this problem is avoided by resetting the number of times of error detection counted during communication when a control signal for stopping transmission of the serial data signal is sent to the transmission device 10.

  Next, with reference to FIGS. 2 and 3, a random error and a burst error that occur when a serial data signal is transmitted via the signal line 31 will be described.

  FIG. 2 is a diagram for explaining a random error caused by random noise in the signal line 31 of FIG. The upper part of FIG. 2 shows the serial data signal transmitted from the transmitter 10, and the lower part of FIG. 2 shows the serial data signal transmitted via the signal line 31 and received by the receiver 20. FIG. 2 shows a state in which a bit error has occurred in the serial data signal received by the receiving device 20 due to the influence of random noise on the signal line 31. In this state, random noise affects the serial data signal to be transmitted as a disturbance factor, and the receiving device 20 inverts some bits “0” and “1” of the serial data signal to invert the bit “1”. ”And“ 0 ”respectively. In the case of such a random error, the receiving device 20 can correct the error by increasing the redundancy of the error correction code. Therefore, it is effective to send a control signal instructing change of the error correction code from the receiving device 20 to the transmitting device 10.

  FIG. 3 is a diagram for explaining a burst error caused by burst noise in the signal line 31 of FIG. The serial data signal transmitted from the transmission apparatus 10 is shown in the upper part of FIG. 3, and the serial data signal transmitted through the signal line 31 and received by the reception apparatus 20 is shown in the lower part of FIG. FIG. 3 shows a state in which a burst error has occurred in the serial data signal received by the receiving device 20 due to the influence of burst noise on the signal line 31. In this state, burst noise affects the serial data signal to be transmitted as a disturbance factor, and the receiving apparatus 20 receives the bit string “010101110 ... 00101011” changed to “0111111111 ... 11111111”. Such a burst error may be caused by a sudden burst noise such as ESD (electrostatic discharge), or may occur in an environment having a transmission path quality in which an error is likely to occur. When a burst error is caused by sudden burst noise, the level of the received serial data signal is abnormal. Depending on the level of abnormal noise, the receiving device 20 cannot reproduce the clock signal.

  Next, an operation for determining whether the level of the serial data signal received by the deserializer circuit 21 is normal or abnormal will be described with reference to FIGS.

  FIG. 4 is a waveform diagram showing a normal serial data signal received by the receiving device 20 of FIG. The waveform of FIG. 4 has an amplitude that is not more than a predetermined threshold Th1 (FIG. 5) and not less than a predetermined threshold Th2 (FIG. 6) with respect to the center voltage of the serial data signal. It has Va1.

  On the other hand, FIGS. 5 to 7 show waveforms of serial data signals having abnormal levels. When these serial data signals are input for a certain period, the receiving device 20 cannot reproduce a normal clock signal.

  FIG. 5 is a waveform diagram showing a serial data signal having an abnormally large amplitude received by the receiving device 20 of FIG. The waveform in FIG. 5 has an amplitude Va2 larger than a predetermined threshold Th1 with respect to the center voltage of the serial data signal. When the serial data signal having an amplitude larger than the threshold value Th1 is continuously received for a certain period, the deserializer circuit 21 sends a signal indicating that the level of the received serial data signal is abnormal to the control circuit 26.

  FIG. 6 is a waveform diagram showing a serial data signal having an abnormally small amplitude received by the receiving device 20 of FIG. The waveform in FIG. 6 has an amplitude Va3 smaller than a predetermined threshold Th2 smaller than the threshold Th1 with respect to the center voltage of the serial data signal. When the serial data signal having an amplitude smaller than the threshold value Th2 is continuously received for a certain period, the deserializer circuit 21 sends a signal indicating that the level of the received serial data signal is abnormal to the control circuit 26. In this case, the serial data signal is considered to be substantially direct current.

  FIG. 7 is a waveform diagram showing a serial data signal having an abnormally large center voltage received by the receiving device 20 of FIG. In order to normally receive the serial data signal, the center voltage of the serial data signal is set to a predetermined upper threshold (for example, 1.0V) and a predetermined lower threshold (for example, 0.2V). ) Must be within the voltage range. The waveform in FIG. 6 has a center voltage of the serial data signal larger than the upper limit threshold (for example, 1.0 V) and has an amplitude Va4. When the deserializer circuit 21 continuously receives a serial data signal having a center voltage outside the voltage range between the upper threshold value and the lower threshold value for a certain period, the level of the received serial data signal is A signal indicating an abnormality is sent to the control circuit 26.

  The register 25 of the receiving device 20 stores in advance thresholds Th1 and Th2 of the amplitude of the serial data signal and upper and lower thresholds of the voltage range.

  Next, the operation of the serial data transmission system of FIG. 1 will be described with reference to FIG.

  FIG. 8 is a flowchart showing data reception processing executed by the control circuit 26 of the reception device 20 of FIG.

  In step S <b> 1, the control circuit 26 starts reception of the serial data signal by the receiving device 20. The receiving device 20 detects an error in the received serial data signal in the error detection circuit 22 after the reception of the serial data signal is started. In step S2, the control circuit 26 determines whether or not an error has been detected by the error detection circuit 22. If YES, the process proceeds to step S4, and if NO, the process proceeds to step S3. In step S3, the control circuit 26 continues to receive the serial data signal. If no error is detected by the error detection circuit 22, the transmission path quality is good, and communication using the currently set error correction code is continued.

  If an error is detected by the error detection circuit 22, the process proceeds to steps S4 to S6 for determining the transmission path quality. Here, as the transmission line quality, it is determined whether the level of the serial data signal has an abnormally large amplitude or an abnormally small amplitude, and the center voltage of the serial data signal is outside the predetermined voltage range. Determine if there is. In step S4, the control circuit 26 determines whether or not the amplitude of the received serial data signal is larger than the first threshold value Th1. If YES, the process proceeds to step S8. If NO, the process proceeds to step S5. move on. In step S5, the control circuit 26 determines whether or not the amplitude of the received serial data signal is smaller than the second threshold value Th2. If YES, the process proceeds to step S8. If NO, the process proceeds to step S6. move on. In step S6, the control circuit 26 determines whether or not the center voltage of the received serial data signal is outside the predetermined voltage range. If YES, the control circuit 26 proceeds to step S8, and if NO, step S7. Proceed to

  When Steps S4 to S6 are all NO, it is considered that a random error is caused on the signal line 31 by a slight disturbance factor such as random noise. Therefore, the error correction code is changed in order to perform data transmission more resistant to noise. In step S7, the control circuit 26 sends a control signal instructing change of the error correction code to the transmission apparatus 10, and proceeds to step S3. The control circuit 26 also sends a control signal instructing change of the error correction code to the error correction decoding circuit 24.

  When any of steps S4 to S6 is YES, it is considered that a burst error is caused by sudden burst noise such as ESD on the signal line 31. Therefore, the control circuit 26 of the reception device 20 does not instruct the transmission device 10 to change the error correction code, but instructs the transmission device 10 to stop transmission of the serial data signal. In step S8, the control circuit 26 stops error detection by the error detection circuit 22. In step S <b> 9, the control circuit 26 sends a control signal instructing to stop transmission of the serial data signal to the transmission device 10. At this time, the control circuit 26 stops the error detection by the error detection circuit 22 and resets the number of error detections counted during communication.

  Accordingly, the control circuit 26 of the receiving device 20 operates as follows.

  The control circuit 26 of the receiving device 20 detects when an error of the received serial data signal is detected by the error detection circuit 22, and when the amplitude of the received serial data signal is larger than the first threshold Th1, or When the amplitude of the received serial data signal is smaller than the second threshold value Th2, or when the center voltage of the received serial data signal is outside the predetermined voltage range, the serial data signal is received. Stop.

  The control circuit 26 of the receiving device 20 detects when an error of the received serial data signal is detected by the error detection circuit 22, and when the amplitude of the received serial data signal is larger than the first threshold Th1, or Stop transmission of the serial data signal when the amplitude of the received serial data signal is smaller than the second threshold Th2, or when the center voltage of the received serial data signal is outside the predetermined voltage range Is sent to the transmitter 10.

  The control circuit 26 of the receiving device 20 detects when an error of the received serial data signal is detected by the error detection circuit 22, and when the amplitude of the received serial data signal is equal to or less than the first threshold value Th1, and When the amplitude of the received serial data signal is greater than or equal to the second threshold Th2 and when the center voltage of the received serial data signal is within a predetermined voltage range, an instruction to change the error correction code is issued. A control signal is sent to the transmitter 10.

  The control circuit 14 of the transmission device 10 stops transmission of the serial data signal by the transmission device 10 when receiving a control signal for instructing stop of transmission of the serial data signal from the reception device 20. The control circuit 14 changes the error correction code used in the error correction coding circuit 11 when receiving a control signal instructing the change of the error correction code from the receiving device 20.

  For example, the control circuit 14 of the transmission device 10 resumes transmission of the serial data signal when a predetermined time elapses after receiving a control signal instructing to stop transmission of the serial data signal. At this time, the control circuit 14 may set the error correction code used immediately before stopping the transmission of the serial data signal in the error correction encoding circuit 11 again.

  As described above, when the error detection circuit 22 detects an error, the control circuit 26 of the receiving device 20 determines whether the error is caused by random noise or an unexpected burst based on the level of the received serial data signal. Determine if it is caused by noise. If the error is due to sudden burst noise, it is determined that the level of the received serial data signal is abnormal, and data transmission is stopped without changing the error correction code.

  According to the serial data transmission system 1 of FIG. 1, occurrence of a burst error can be reliably detected. Accordingly, it is possible to avoid the influence of burst errors due to sudden burst noise.

Second embodiment.
FIG. 9 is a block diagram showing a configuration of a serial data transmission system 1A according to the second embodiment of the present invention. The serial data transmission system 1 </ b> A includes a transmission device 10 </ b> A and a reception device 20 </ b> A connected to each other via a signal line 31, and an external control circuit 41. The transmitting apparatus 10A includes a differential receiver circuit 15 connected to the signal line 31 in addition to the components of the transmitting apparatus 10 of FIG. The receiving device 20A includes a differential driver circuit 27 connected to the signal line 31 in addition to the components of the receiving device 20 of FIG. The external control circuit 41 generates timing signals fsync and Igate and sends them to the transmission device 10A and the reception device 20A.

  The receiving device 20A receives a serial data signal from the transmitting device 10A via the common signal line 31, and transmits a control signal to the transmitting device 10A. The control circuit 26 of the receiving device 20A sends a control signal to the control circuit 14 of the transmitting device 10A via the differential driver circuit 27, the signal line 31, and the differential receiver circuit 15.

  FIG. 10 is a timing chart showing transmission of serial data signals and control signals in the serial data transmission system 1A of FIG. FIG. 10 shows a case where image data for one frame is transmitted from the transmitting apparatus 10A to the receiving apparatus 20A, for example. The timing signal fsync indicates the start of each frame. The timing signal Igate (gate signal) indicates a valid period during which a serial data signal can be transmitted from the transmission device 10A to the reception device 20A. In each frame, the serial data signal is not transmitted on the signal line 31 during the period from the transmission of the serial data signal to the start of the next frame. Therefore, this period is an effective period during which a control signal can be transmitted from the receiving apparatus 20A to the transmitting apparatus 10A.

  According to the serial data transmission system 1A of FIG. 9, since the signal line 31 is shared, no extra signal line is required to transmit a control signal from the receiving device 20A to the transmitting device 10A. Since the number of signal lines can be reduced as compared with the serial data transmission system 1 of FIG. 1, the degree of freedom in system design can be improved.

Third embodiment.
FIG. 11 is a block diagram showing a configuration of a serial data transmission system 1B according to the third embodiment of the present invention. The serial data transmission system 1B includes a transmission device 10B and a reception device 20B connected to each other via a signal line 31, and an external CPU 42 (processor). The transmission device 10B includes a control circuit 14B that communicates with the CPU 42 instead of the control circuit 14 of FIG. The receiving device 20B includes a control circuit 26B that communicates with the CPU 42 instead of the control circuit 26 of FIG.

  The receiving device 20B transmits a control signal to the transmitting device 10B via the external CPU 42. The control circuit 26B of the receiving device 20B sends an interrupt signal to the CPU 42 when instructing the control circuit 14B of the transmitting device 10B to stop transmission of the serial data signal or change the error correction code. The CPU 42 identifies the state of the receiving device 20B from the interrupt signal and sends a control signal to the control circuit 14B of the transmitting device 10B. The control circuit 14B of the transmission device 10B controls the operation of the transmission device 10B (stop and restart of transmission of the serial data signal or change of the error correction code) according to the control signal sent from the CPU 42.

  According to the serial data transmission system 1B of FIG. 11, the CPU 42 can recognize that burst noise has occurred on the signal line 31, for example, by managing the control signal.

Fourth embodiment.
FIG. 12 is a block diagram showing a configuration of a serial data transmission system 1C according to the fourth embodiment of the present invention. The serial data transmission system 1C includes a transmission device 10C and a reception device 20C connected to each other via signal lines 31 and 32. The transmitting apparatus 10C includes an interleaver circuit 16 provided between the error correction encoding circuit 11 and the 8B10B encoding circuit 12 in addition to the components of the transmitting apparatus 10 in FIG. The interleaver circuit 16 includes a memory 16m. The receiving device 20C includes a deinterleaver circuit 28 provided between the 10B8B decoding circuit 23 and the error correction decoding circuit 24 in addition to the components of the receiving device 20 of FIG. The deinterleaver circuit 28 includes a memory 28m.

  After adding an error correction code to the data signal, the interleaver circuit 16 interleaves the data signal on the memory 16m and sends the data signal to the 8B10B encoding circuit 12. The transmission device 10 transmits the interleaved serial data signal to the reception device 20. The deinterleaver circuit 28 deinterleaves the received serial data signal on the memory 28m after 10B8B decoding, and sends it to the error correction decoding circuit 24.

  FIG. 13 is a diagram showing data signal interleaving and deinterleaving in the serial data transmission system 1C of FIG. In interleaving, the order of symbols is changed when the original parallel data signal input by the transmitting apparatus 10C is converted into a serial data signal. The receiving device 20C restores the original order of the symbols after receiving the serial data signal. As a result, even if a burst error occurs on the signal line 31, the error is diffused after the original order of the symbols is restored by the receiving apparatus 20C, so that the error can be corrected by error correction coding. it can. In general, error correction using an error correction code is effective for random errors, but burst errors cannot be corrected. In the serial data transmission system 1C of FIG. 12, by interleaving the data signals, it is possible to correct a burst error to the extent that the level of the received serial data signal is not determined to be abnormal, and to improve noise resistance. It becomes possible.

  According to the serial data transmission system 1C of FIG. 12, by performing interleaving, not only a minor random error but also a minor burst error can be corrected, and noise resistance can be improved.

Fifth embodiment.
FIG. 14 is a block diagram showing a configuration of a serial data transmission system 1D according to the fifth embodiment of the present invention. The serial data transmission system 1D includes a transmission device 10 and a reception device 20 that are connected to each other via signal lines 31 and 32, and an external CPU 42. The voltage threshold values (threshold value Th1, threshold value Th2, and voltage range) set in the register of receiving device 20 may be variable. By setting the voltage threshold value in the register 25 by the CPU 42, an arbitrary voltage threshold value can be used. According to the serial data transmission system 1D of FIG. 14, it is possible to detect an abnormality in the level of the received serial data signal with an arbitrary accuracy in accordance with the transmission path quality.

Sixth embodiment.
FIG. 15 is a block diagram showing a configuration of a serial data transmission system 1E according to the sixth embodiment of the present invention. The serial data transmission system 1E includes a transmission device 10 and a reception device 20E connected to each other via signal lines 31 and 32. The receiving device 20E includes a control circuit 26E that determines voltage threshold values (threshold value Th1, threshold value Th2, and voltage range) set in the register 25 instead of the control circuit 26 of FIG.

  The deserializer circuit 21 determines the frequency at which the level of the received serial data signal is determined to be abnormal, and sends a signal indicating this frequency to the control circuit 26E. The error detection circuit 22 determines the frequency of detecting an error in the received serial data signal and sends a signal indicating this frequency to the control circuit 26E. When the frequency at which the level of the serial data signal is determined to be abnormal by the deserializer circuit 21 exceeds the first frequency threshold, the control circuit 26E determines the frequency at which the error detection circuit 22 has detected an error in the serial data signal. Compare with second frequency threshold. At this time, if the frequency at which the error of the serial data signal is detected by the error detection circuit 22 does not exceed the second frequency threshold, the voltage threshold set in the register 25 may be too low. Circuit 26E increases the voltage threshold. On the other hand, if the frequency at which the error detection circuit 22 detects an error in the serial data signal exceeds the second frequency threshold, it may have failed to detect an abnormality in the level of the received serial data signal. Therefore, the control circuit 26E decreases the voltage threshold value. The control circuit 26E sets the changed voltage threshold value in the register 25.

  As described above, the control circuit 26E of the reception device 20E has a frequency at which an error of the received serial data signal is detected by the error detection circuit 22, and an amplitude of the received serial data signal becomes larger than the first threshold value Th1. The first threshold based on whether the amplitude of the received serial data signal is smaller than the second threshold Th2 or the frequency at which the center voltage of the received serial data signal is outside the voltage range. A value Th1, a second threshold Th2, and a voltage range are determined.

  According to the serial data transmission system 1E of FIG. 15, the optimum information based on information during normal communication (the frequency at which the level of the serial data signal is determined to be abnormal and the frequency at which an error in the serial data signal is detected) is optimal. The voltage threshold can be set automatically. Therefore, even if an abnormality in the level of the serial data signal is detected due to noise, data transmission can actually be performed and transmission of the serial data signal can be prevented from being excessively stopped.

  Arbitrary electronic equipment provided with the serial data transmission system according to the first to sixth embodiments of the present invention, for example, a computer, a communication device (mobile phone, portable information terminal, etc.), an image processing device (projector, video conference) System, etc.) may be provided.

  A serial data receiving device, a serial data transmission system, and an electronic device according to an aspect of the present invention are characterized by having the following configuration.

The serial data receiving apparatus according to the first aspect of the present invention is:
In a serial data receiving device that receives a serial data signal from a serial data transmitting device, the serial data receiving device includes:
A level detection circuit for detecting the level of the received serial data signal;
An error detection circuit for detecting an error in the received serial data signal;
A control circuit for controlling the operation of the serial data receiving device based on the level and error of the received serial data signal,
The control circuit includes:
When an error of the received serial data signal is detected by the error detection circuit; and
When the amplitude of the received serial data signal is larger than a first threshold value, or when the amplitude of the received serial data signal is smaller than a second threshold value smaller than the first threshold value When small, or when the center voltage of the received serial data signal is outside a predetermined voltage range,
The reception of the serial data signal is stopped.

The serial data receiving device according to the second aspect of the present invention is the serial data receiving device according to the first aspect,
The control circuit includes:
When an error of the received serial data signal is detected by the error detection circuit; and
When the amplitude of the received serial data signal is greater than the first threshold, or when the amplitude of the received serial data signal is smaller than the second threshold, or the received serial When the center voltage of the data signal is outside the voltage range,
A first control signal for instructing to stop transmission of the serial data signal is sent to the serial data transmitting device.

The serial data receiving device according to the third aspect of the present invention is the serial data receiving device according to the first or second aspect,
The serial data transmission device transmits a serial data signal encoded by selectively using one of a plurality of error correction codes to the serial data reception device;
The control circuit includes:
When an error of the received serial data signal is detected by the error detection circuit; and
When the received serial data signal has an amplitude less than or equal to the first threshold and when the received serial data signal has an amplitude greater than or equal to the second threshold and the received serial data When the center voltage of the data signal is within the voltage range,
A second control signal for instructing the change of the error correction code is sent to the serial data transmitting device.

A serial data receiving device according to a fourth aspect of the present invention is the serial data receiving device according to the third aspect,
The serial data receiving device receives the serial data signal from the serial data transmitting device via a common signal line, and transmits the first and second control signals to the serial data transmitting device. And

A serial data receiving device according to a fifth aspect of the present invention is the serial data receiving device according to the third aspect,
The serial data receiving device transmits the first and second control signals to the serial data transmitting device via an external processor.

A serial data receiving device according to a sixth aspect of the present invention is the serial data receiving device according to one of the first to fifth aspects,
The serial data transmitting device transmits an interleaved serial data signal to the serial data receiving device;
The serial data receiving apparatus further includes a deinterleaver circuit that deinterleaves the received serial data signal.

A serial data receiving device according to a seventh aspect of the present invention is the serial data receiving device according to one of the first to sixth aspects,
The first threshold value, the second threshold value, and the voltage range are variable.

A serial data receiving device according to an eighth aspect of the present invention is the serial data receiving device according to the seventh aspect,
The control circuit includes:
The frequency of detecting errors in the received serial data signal by the error detection circuit;
Whether the amplitude of the received serial data signal is greater than the first threshold value, whether the amplitude of the received serial data signal is smaller than the second threshold value, or the received serial data signal On the basis of the frequency at which the center voltage is outside the voltage range,
The first threshold value, the second threshold value, and the voltage range are determined.

  A serial data transmission system according to a ninth aspect of the present invention includes the serial data transmission device and the serial data reception device according to one of the first to eighth aspects, which are connected to each other via a signal line. It is characterized by providing.

  An electronic apparatus according to a tenth aspect of the present invention includes the serial data transmission system according to the ninth aspect.

1, 1A to 1E ... serial data transmission system,
10, 10A to 10C ... transmitting device,
11 ... error correction coding circuit,
12 ... 8B10B encoding circuit,
13 ... Serializer circuit,
14, 14B ... control circuit,
15 ... Differential receiver circuit,
16 ... Interleaver circuit,
16m ... memory,
20, 20A to 20C, 20E ... receiving device,
21 ... deserializer circuit,
22 ... error detection circuit,
23 ... 10B8B decoding circuit,
24. Error correction decoding circuit,
25 ... registers,
26, 26B, 26E ... control circuit,
27: Differential driver circuit,
28 ... deinterleaver circuit,
28 ... Memory,
31, 32 ... signal lines,
41. External control circuit,
42 ... CPU.

JP 2011-0119188 A Japanese Patent No. 5239166

Claims (10)

In a serial data receiving device that receives a serial data signal from a serial data transmitting device, the serial data receiving device includes:
A level detection circuit for detecting the level of the received serial data signal;
An error detection circuit for detecting an error in the received serial data signal;
A control circuit for controlling the operation of the serial data receiving device based on the level and error of the received serial data signal,
The control circuit includes:
When an error of the received serial data signal is detected by the error detection circuit; and
When the amplitude of the received serial data signal is larger than a first threshold value, or when the amplitude of the received serial data signal is smaller than a second threshold value smaller than the first threshold value When small, or when the center voltage of the received serial data signal is outside a predetermined voltage range,
A serial data receiving apparatus, wherein reception of the serial data signal is stopped. The control circuit includes:
When an error of the received serial data signal is detected by the error detection circuit; and
When the amplitude of the received serial data signal is greater than the first threshold, or when the amplitude of the received serial data signal is smaller than the second threshold, or the received serial When the center voltage of the data signal is outside the voltage range,
2. The serial data receiving apparatus according to claim 1, wherein a first control signal instructing to stop transmission of the serial data signal is sent to the serial data transmitting apparatus. The serial data transmission device transmits a serial data signal encoded by selectively using one of a plurality of error correction codes to the serial data reception device;
The control circuit includes:
When an error of the received serial data signal is detected by the error detection circuit; and
When the received serial data signal has an amplitude less than or equal to the first threshold and when the received serial data signal has an amplitude greater than or equal to the second threshold and the received serial data When the center voltage of the data signal is within the voltage range,
3. The serial data receiving apparatus according to claim 1, wherein a second control signal instructing change of the error correction code is sent to the serial data transmitting apparatus.   The serial data receiving device receives the serial data signal from the serial data transmitting device via a common signal line, and transmits the first and second control signals to the serial data transmitting device. The serial data receiving device according to claim 3.   4. The serial data receiving apparatus according to claim 3, wherein the serial data receiving apparatus transmits the first and second control signals to the serial data transmitting apparatus via an external processor. The serial data transmitting device transmits an interleaved serial data signal to the serial data receiving device;
The serial data receiving device according to claim 1, further comprising a deinterleaver circuit that deinterleaves the received serial data signal.   The serial data receiving apparatus according to claim 1, wherein the first threshold value, the second threshold value, and the voltage range are variable. The control circuit includes:
The frequency of detecting errors in the received serial data signal by the error detection circuit;
Whether the amplitude of the received serial data signal is greater than the first threshold value, whether the amplitude of the received serial data signal is smaller than the second threshold value, or the received serial data signal On the basis of the frequency at which the center voltage is outside the voltage range,
8. The serial data receiving apparatus according to claim 7, wherein the first threshold value, the second threshold value, and the voltage range are determined.   A serial data transmission system comprising: the serial data transmission device and the serial data reception device according to claim 1 connected to each other via a signal line.   An electronic apparatus comprising the serial data transmission system according to claim 9.

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