JP2017005057A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a plurality of CMIS regions, which can inhibit threshold voltage variation caused by a movable ion to improve reliability.SOLUTION: A semiconductor device 1 includes: a semiconductor substrate 2 where a high-voltage side CMIS region 3 and a low-voltage side CMIS region are set; an interlayer insulation film 90 formed on the semiconductor substrate 2 so as to cover each CMIS region; and a plurality of interconnections 91 formed on the interlayer insulation film. The high-voltage side CMIS region 3 includes: a high-voltage side n-type MISFET 9 including a first gate electrode 13 which is formed on a first gate insulation film 12 and doped with an n-type impurity; and a high-voltage side p-type MISFET 10 including a second gate electrode 33 which is formed on a second gate insulation film 32 and doped with an n-type impurity. The low-voltage side CMIS region includes: a low-voltage side n-type MISFET including a third gate electrode doped with an n-type impurity; and a low-voltage side p-type MISFET including a fourth gate electrode doped with a p-type impurity.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device having a plurality of CMIS (Complementary Metal Insulator Semiconductor) regions.

  Patent Document 1 discloses a CMOS (Complementary Metal Oxide Semiconductor) semiconductor device. This semiconductor device includes a semiconductor substrate, an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a p-type MOSFET formed on the semiconductor substrate. The n-type MOSFET has an n-type gate electrode, and the p-type MOSFET has a p-type gate electrode.

JP 7-202010 A JP 2004-319631 A

  In a semiconductor device having a CMIS (Complementary Metal Insulator Semiconductor) region, a plurality of CMIS regions having different rated voltages may be set on a semiconductor substrate. In this case, the plurality of CMIS regions include a CMIS region having a relatively high rated voltage and a CMIS region having a relatively low rated voltage. The rated voltage is a voltage necessary for operating the CMIS region. Each CMIS region includes an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a p-type MISFET. An interlayer insulating film is formed on the semiconductor substrate so as to cover the n-type MISFET and the p-type MISFET, and a plurality of wirings for supplying power to the n-type MISFET and the p-type MISFET are formed on the interlayer insulating film.

  For example, as in Patent Document 1 and Patent Document 2, by forming an n-type MISFET including an n-type gate electrode and a p-type MISFET including a p-type gate electrode, the threshold voltage in the p-type MISFET can be reduced. Are known. However, in this configuration, ions of the metal material forming the wiring (positive ions such as metal ions) leak as movable ions, and there is a possibility that the characteristics of the p-type MISFET may fluctuate.

  More specifically, the movable ions leaking from the wiring reach the n-type gate electrode and the p-type gate electrode through the interlayer insulating film. In the n-type gate electrode, mobile ions are gettered (captured) by n-type impurities, but such a gettering effect cannot be expected in the p-type gate electrode. As a result, the movable ions reach the gate insulating film located immediately below the p-type gate electrode and are trapped. As a result, the threshold voltage in the p-type MISFET varies.

  Since the mobile ions increase as the rated voltage increases, in the CMIS region where the rated voltage is relatively low, there is a relatively small amount of mobile ions and the influence thereof tends to be small. However, in the CMIS region having a relatively high rated voltage, a relatively large amount of mobile ions exists, and thus tends to be easily affected. In particular, in a p-type MISFET in the CMIS region having a relatively high rated voltage, there is a possibility that the amount of variation in threshold voltage due to mobile ions will be greater than the amount of reduction in threshold voltage due to the adoption of a p-type gate electrode.

  In view of the above, an object of the present invention is to provide a semiconductor device that can improve the reliability by suppressing the fluctuation of the threshold voltage due to movable ions in a semiconductor device having a plurality of CMIS regions.

  In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a semiconductor substrate in which a high voltage side CMIS region having a relatively high rated voltage and a low voltage side CMIS region having a relatively low rated voltage are set. Including. Further, a semiconductor device is formed on the interlayer insulating film so as to cover the high-voltage side CMIS region and the low-voltage side CMIS region, and the high-voltage side CMIS region, A plurality of wirings for supplying power to the low-voltage side CMIS region. In this configuration, the high-voltage side CMIS region is formed on the semiconductor substrate with a first gate insulating film interposed therebetween, and includes a high-voltage side n-type MISFET including a first gate electrode doped with an n-type impurity, and a second gate. A high-voltage side p-type MISFET formed on the semiconductor substrate with an insulating film interposed therebetween and including a second gate electrode doped with an n-type impurity. On the other hand, the low-voltage side CMIS region has a low-voltage side n-type MISFET including a third gate electrode doped with an n-type impurity and a low-voltage side p-type MISFET including a fourth gate electrode doped with a p-type impurity. doing.

According to this configuration, the high voltage side CMIS region having a relatively high rated voltage and the low voltage side CMIS region having a relatively low rated voltage are set on the semiconductor substrate. The rated voltage of the low voltage side CMIS region is lower than the rated voltage of the high voltage side CMIS region. The rated voltage is a voltage necessary for operating the high-voltage side CMIS region and the low-voltage side CMIS region.
In this configuration, the high voltage side CMIS region includes a high voltage side n type MISFET including a first gate electrode doped with an n type impurity and a high voltage side p type MISFET including a second gate electrode doped with an n type impurity. Including a single gate structure. On the other hand, the low-voltage side CMIS region is a dual having a low-voltage side n-type MISFET including a third gate electrode doped with an n-type impurity and a low-voltage side p-type MISFET including a fourth gate electrode doped with a p-type impurity. Includes gate structure. That is, the semiconductor device has a hybrid gate structure including both a single gate structure and a dual gate structure.

  In the high-pressure side CMIS region, the mobile ions (cations such as metal ions) leaking from the wiring are the first gate electrode doped with the n-type impurity and the second doped with the n-type impurity through the interlayer insulating film. It reaches the gate electrode. Since the movable ions are gettered (captured) by the n-type impurities of the first gate electrode and the second gate electrode, it is possible to suppress the movable ions from reaching the first gate insulating film and the second gate insulating film. Thereby, it can suppress that a threshold voltage fluctuates in the high voltage side CMIS region. On the other hand, since the influence of mobile ions is small in the low-pressure side CMIS region, the threshold voltage can be reduced by the fourth gate electrode doped with the p-type impurity.

  According to this configuration, since the second gate electrode doped with the n-type impurity is formed in the high-voltage side p-type MISFET in the high-voltage side CMIS region, fluctuations in the threshold voltage due to movable ions can be suppressed. Since the fourth gate electrode doped with the p-type impurity is formed in the low-voltage p-type MISFET in the low-voltage CMIS region, the threshold voltage can be reduced. As a result, a semiconductor device that can improve reliability can be provided.

In the semiconductor device, the high-voltage side p-type MISFET is formed on the surface portion of the semiconductor substrate so as to be electrically connected to the second gate electrode, and is respectively doped with p-type impurities. The p-type source region and the p-type drain region may be included.
In the semiconductor device, the high voltage side CMIS region may have a rated voltage larger than 2.5V. The low voltage side CMIS region may have a rated voltage of 2.5 V or less.

In the semiconductor device, the first gate electrode and the second gate electrode may have a gate length of 0.35 μm or less. In the semiconductor device, the first gate electrode and the second gate electrode may have a gate length of 0.25 μm or less.
In the semiconductor device, the second gate electrode may have an n-type impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ or more and 1.0 × 10 ²² cm ⁻³ or less.

In the semiconductor device, the first gate electrode may include an n-type polysilicon gate electrode doped with an n-type impurity. The second gate electrode may include an n-type polysilicon gate electrode doped with an n-type impurity.
In the semiconductor device, the interlayer insulating film may contain SiO ₂ or SiN. For example, when the interlayer insulating film contains BPSG (Boron Phosphorus Silicon Glass) or PSG (Phosphorus Silicon Glass), it has phosphorus (P) which is an n-type impurity. (Cation) can be gettered (captured). However, when an interlayer insulating film containing BPSG or PSG is formed, it is necessary to heat the semiconductor substrate by a heat treatment step after film formation in order to diffuse impurities such as phosphorus (P). In this case, the impurity region formed in the semiconductor substrate may further diffuse from the target position and spread to other regions.

In the present invention, since mobile ions can be gettered (captured) by the first gate electrode and the second gate electrode doped with n-type impurities, an interlayer insulating film containing SiO ₂ or SiN can be formed instead of BPSG or PSG. . Thereby, heating of the semiconductor substrate due to the heat treatment process can be avoided, so that undesired diffusion of impurity regions formed in the semiconductor substrate can be suppressed. As a result, a semiconductor device that can further improve reliability can be provided. Further, since the heat treatment process can be omitted, the manufacturing process can be simplified.

Note that an interlayer insulating film containing BPSG or PSG may be formed by paying attention to the gettering (trapping) effect of mobile ions. In other words, in the semiconductor device, the interlayer insulating film may include one or more insulating materials selected from the group including SiO ₂ , SiN, BPSG, and PSG.
In the semiconductor device according to another aspect of the present invention, a plurality of CMIS regions including a high voltage side CMIS region having a rated voltage higher than 2.5V and a low voltage side CMIS region having a rated voltage of 2.5V or less are set. Includes a semiconductor substrate. Further, the semiconductor device includes an interlayer insulating film formed on the semiconductor substrate so as to cover the plurality of CMIS regions, and a plurality of semiconductor devices formed on the interlayer insulating film and supplying power to the plurality of CMIS regions. Including wiring. In this configuration, the high voltage side CMIS region is formed on the semiconductor substrate with a gate insulating film interposed therebetween, and has a high voltage side p type having an n type gate electrode doped with an n type impurity having a gate length of 0.35 μm or less. Includes MISFET. Meanwhile, the low-voltage side CMIS region includes a low-voltage side p-type MISFET having a p-type gate electrode doped with a p-type impurity having a gate length of 0.35 μm or less.

In a p-type MISFET, when a p-type gate electrode doped with a p-type impurity having a gate length of 0.35 μm or less is employed, a threshold voltage reduction effect can be expected when a voltage higher than 2.5 V is applied. There is a risk that the threshold voltage may fluctuate greatly due to mobile ions.
Therefore, in this configuration, an n-type gate electrode doped with an n-type impurity is employed in the high-voltage side p-type MISFET of the high-voltage side CMIS region having a rated voltage higher than 2.5 V among the plurality of CMIS regions. . As a result, the mobile ions leaking from the wiring are gettered (captured) by the n-type impurity of the n-type gate electrode, so that the mobile ions can be prevented from reaching the gate insulating film. Thereby, it can suppress that a threshold voltage fluctuates in the high voltage side CMIS region. On the other hand, since the influence of mobile ions is small in the low-pressure side CMIS region, the threshold voltage can be reduced by forming a p-type gate electrode doped with a p-type impurity.

  According to this configuration, since the n-type gate electrode doped with the n-type impurity is formed in the high-voltage side p-type MISFET in the high-voltage side CMIS region, fluctuations in threshold voltage due to movable ions can be suppressed. Since the p-type gate electrode doped with the p-type impurity is formed in the low-voltage side p-type MISFET in the low-voltage side CMIS region, the threshold voltage can be reduced. As a result, a semiconductor device that can improve reliability can be provided.

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 2 is a cross-sectional view taken along line II-II shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. FIG. 4 is a cross-sectional view for explaining the behavior of mobile ions. 5A is a cross-sectional view showing a manufacturing process of the high-pressure side CMIS region shown in FIG. FIG. 5B is a cross-sectional view showing a step subsequent to FIG. 5A. FIG. 5C is a cross-sectional view showing a step subsequent to FIG. 5B. FIG. 5D is a cross-sectional view showing a step subsequent to FIG. 5C. FIG. 5E is a cross-sectional view showing a step subsequent to FIG. 5D. FIG. 5F is a cross-sectional view showing a step subsequent to FIG. 5E. FIG. 5G is a cross-sectional view showing a step subsequent to FIG. 5F. FIG. 5H is a cross-sectional view showing a step subsequent to FIG. 5G. FIG. 5I is a cross-sectional view showing a step subsequent to FIG. 5H. FIG. 5J is a cross-sectional view showing a step subsequent to FIG. 5I. 6A is a cross-sectional view showing a manufacturing process of the low-pressure side CMIS region shown in FIG. FIG. 6B is a cross-sectional view showing a step subsequent to FIG. 6A. FIG. 6C is a cross-sectional view showing a step subsequent to FIG. 6B. FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6C. FIG. 6E is a cross-sectional view showing a step subsequent to FIG. 6D. FIG. 6F is a cross-sectional view showing a step subsequent to FIG. 6E. FIG. 6G is a cross-sectional view showing a step subsequent to FIG. 6F. 6H is a cross-sectional view showing a step subsequent to FIG. 6G. FIG. 6I is a cross-sectional view showing a step subsequent to FIG. 6H. FIG. 6J is a cross-sectional view showing a step subsequent to FIG. 6I.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention. 2 is a cross-sectional view taken along line II-II shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG.
Hereinafter, when an n-type impurity (n-type) is referred to, a pentavalent element (eg, phosphorus (P), arsenic (As), etc.) is included as a main impurity, and when a p-type impurity (p-type) is referred to, a trivalent element is included. It is assumed that an element (for example, boron (B), indium (In), gallium (Ga), etc.) is contained as a main impurity.

The semiconductor device 1 includes a semiconductor substrate 2 made of a p-type silicon substrate. A plurality of CMIS (Complementary Metal Insulator Semiconductor) regions are set on the semiconductor substrate 2. The plurality of CMIS regions include a high voltage side CMIS region 3 having a relatively high rated voltage and a low voltage side CMIS region 4 having a relatively low rated voltage.
More specifically, as shown in FIGS. 1 to 3, the semiconductor substrate 2 is formed with an element isolation portion 6 that partitions a region on the surface of the semiconductor substrate 2 into a plurality of active regions 5. The plurality of element isolation parts 6 include strip-like portions extending in stripes parallel to each other in a plan view (hereinafter simply referred to as “plan view”) viewed from the normal direction of the surface of the semiconductor substrate 2. In the present embodiment, the element isolation unit 6 includes STI (Shallow Trench Isolation) in which an insulator 8 is embedded in a plurality of trenches 7 formed in the semiconductor substrate 2. The insulator 8 may be, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN). In the present embodiment, the insulator 8 is made of silicon oxide.

  2 and 3, each trench 7 is formed in a tapered shape whose width gradually decreases from the opening end toward the bottom. The insulator 8 integrally includes a buried portion 8 a housed in the trench 7 and a projecting portion 8 b formed outside the trench 7 and projecting upward from the surface of the semiconductor substrate 2. The embedded portion 8a of the insulator 8 is formed in a tapered shape whose width is narrowed following the shape of the trench 7 in a cross-sectional view. That is, the embedded portion 8 a has a side surface that is inclined with respect to the surface of the semiconductor substrate 2.

The protruding portion 8 b of the insulator 8 is formed in a quadrangular shape that protrudes perpendicularly to the surface of the semiconductor substrate 2 in a cross-sectional view. The protruding portion 8 b has a top surface (flat surface) parallel to the surface of the semiconductor substrate 2 and a vertical side surface. The protrusion amount of the protrusion 8b is, for example, 0.05 μm or more and 0.1 μm or less with respect to the surface of the semiconductor substrate 2. The element isolation portion 6 may include a LOCOS film formed by a LOCOS (Local Oxidation of Silicon) method instead of or in addition to the STI. In the present embodiment, the high voltage side CMIS region 3 and the low voltage side CMIS region 4 are set in the stripe-shaped active region 5 partitioned into the plurality of element isolation parts 6. Hereinafter, after describing a specific configuration of the high-pressure side CMIS region 3, a specific configuration of the low-pressure side CMIS region 4 will be described.
<High pressure side CMIS area>
Referring to FIGS. 1 and 2, high voltage side CMIS region 3 includes a high voltage side n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) 9 and a high voltage side p type MISFET 10 which are separated from each other by element isolation unit 6. The rated voltage V _dd1n of the high-voltage side n-type MISFET 9 and the rated voltage V _dd1p of the high-voltage side p-type MISFET ₁₀ are both greater than 2.5V.

More specifically, the rated voltages V _dd1n and V _dd1p of the high-voltage side n-type MISFET 9 and the high-voltage side p-type MISFET ₁₀ are more than 3.0V and 100V or less. The rated voltages V _dd1n and V _dd1p are specifically voltages required to operate the high-voltage side n-type MISFET 9 and the high-voltage side p-type MISFET 10, and both are defined as drain-source voltages. Hereinafter, specific configurations of the high-voltage side n-type MISFET 9 and the high-voltage side p-type MISFET 10 will be described in order.
(1) High voltage side n-type MISFET
A p-type well 11 is formed on the surface portion of the semiconductor substrate 2 in the high-voltage side n-type MISFET 9 along the side of the element isolation portion 6. The boundary between the p-type well 11 and the semiconductor substrate 2 is in contact with the bottom of the element isolation portion 6. A first gate insulating film 12 is formed on the surface of the semiconductor substrate 2 so as to be in contact with the p-type well 11.

The first gate insulating film 12 is formed in a stripe shape in plan view. The first gate insulating film 12 has a thickness of not less than 100 mm and not more than 1500 mm, for example. The first gate insulating film 12 may be a SiO ₂ film. An n-type first gate electrode 13 doped with an n-type impurity is formed in a stripe shape in plan view so as to face the p-type well 11 with the first gate insulating film 12 interposed therebetween. More specifically, the first gate electrode 13 includes an n-type polysilicon gate electrode doped with an n-type impurity.

Referring to FIG. 1, the first gate electrode 13 has a gate length L1 of 0.35 μm or less, more specifically 0.25 μm or less. In this embodiment, the gate length L1 of the first gate electrode 13 is defined by the width in the direction orthogonal to the stripe direction of the first gate electrode 13. The first gate electrode 13 may have an n-type impurity concentration of, for example, 1.0 × 10 ²⁰ cm ⁻³ or more and 1.0 × 10 ²² cm ⁻³ or less. A silicide film 14 made of, for example, titanium silicide (TiSi ₂ ) is formed on the surface of the first gate electrode 13. Both side surfaces of the first gate electrode 13 are covered with sidewalls 15 made of an insulating material such as SiN.

  A first n-type source region 16 and a first n-type source contact region 17 are formed on the surface portion of the p-type well 11 on one side of the first gate electrode 13. The first n-type source region 16 and the first n-type source contact region 17 form a DDD (Double diffused Drain) structure. Note that an LDD (Lightly Doped Drain) structure may be formed by forming only the first n-type source region 16.

  The first n-type source region 16 is formed in a self-aligned manner with respect to the sidewall 15. The first n-type source region 16 may have the same n-type impurity concentration as the n-type impurity concentration of the first gate electrode 13. The first n-type source region 16 integrally includes a first n-type source offset region 18 formed in a self-aligned manner with respect to the first gate electrode 13. The n-type impurity concentration of the first n-type source offset region 18 is smaller than the n-type impurity concentration of the first n-type source region 16. The first n-type source contact region 17 is formed on the surface portion of the first n-type source region 16. A silicide film 19 made of, for example, titanium silicide is formed on the surface portions of the first n-type source region 16 and the first n-type source contact region 17.

  A first n-type drain region 20 and a first n-type drain contact region 21 are formed on the surface of the first gate electrode 13 on the other side of the p-type well 11 and spaced from the first n-type source region 16. . The first n-type drain region 20 and the first n-type drain contact region 21 form a DDD structure. Note that an LDD structure may be formed by forming only the first n-type drain region 20.

  The first n-type drain region 20 is formed in a self-aligned manner with respect to the sidewall 15. The first n-type drain region 20 may have the same n-type impurity concentration as the n-type impurity concentration of the first gate electrode 13. The first n-type drain region 20 integrally includes a first n-type drain offset region 22 formed in a self-aligned manner with respect to the first gate electrode 13. The n-type impurity concentration of the first n-type drain offset region 22 is smaller than the n-type impurity concentration of the first n-type drain region 20.

The first n-type drain contact region 21 is formed on the surface portion of the first n-type drain region 20. A silicide film 23 made of, for example, titanium silicide is formed on the surface portions of the first n-type drain region 20 and the first n-type drain contact region 21. A region between the first n-type source region 16 and the first n-type drain region 20 is a channel region 24 of the high-voltage side n-type MISFET 9.
(2) High voltage side p-type MISFET
An n-type well 31 is formed on the surface portion of the semiconductor substrate 2 in the high-voltage side p-type MISFET 10 along the side of the element isolation portion 6. The n-type well 31 is formed with the same depth as the p-type well 11 described above. The n-type impurity concentration of the n-type well 31 may be the same as the p-type impurity concentration of the p-type well 11. The boundary between the n-type well 31 and the semiconductor substrate 2 is in contact with the bottom of the element isolation portion 6. A second gate insulating film 32 is formed on the surface of the semiconductor substrate 2 so as to be in contact with the n-type well 31.

  The second gate insulating film 32 is formed in a stripe shape in plan view. The second gate insulating film 32 is formed of the same thickness and the same material as the first gate insulating film 12 described above. An n-type second gate electrode 33 doped with an n-type impurity is formed so as to face the n-type well 31 with the second gate insulating film 32 interposed therebetween. More specifically, the second gate electrode 33 includes an n-type polysilicon gate electrode doped with an n-type impurity.

Referring to FIG. 1, second gate electrode 33 has a gate length L2 of 0.35 μm or less, more specifically 0.25 μm or less. In the present embodiment, the gate length L2 of the second gate electrode 33 is defined by a width in a direction perpendicular to the stripe direction of the second gate electrode 33. The second gate electrode 33 may have an n-type impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ or more and 1.0 × 10 ²² cm ⁻³ or less, for example. A silicide film 34 made of, for example, titanium silicide is formed on the surface of the second gate electrode 33. Both side surfaces of the second gate electrode 33 are covered with sidewalls 35 made of an insulating material such as SiN.

A first p-type source region 36 and a first p-type source contact region 37 are formed on the surface portion of the n-type well 31 on one side of the second gate electrode 33. The first p-type source region 36 and the first p-type source contact region 37 form a DDD structure. Note that an LDD structure may be formed by forming only the first p-type source region 36.
The first p-type source region 36 is formed in a self-aligned manner with respect to the sidewall 35. The first p-type source region 36 integrally includes a first p-type source offset region 38 formed in a self-aligned manner with respect to the second gate electrode 33. The p-type impurity concentration of the first p-type source offset region 38 is smaller than the p-type impurity concentration of the first p-type source region 36. The first p-type source contact region 37 is formed on the surface portion of the first p-type source region 36. On the surface portions of the first p-type source region 36 and the first p-type source contact region 37, a silicide film 39 made of, for example, titanium silicide is formed.

  A first p-type drain region 40 and a first p-type drain contact region 41 are formed on the surface of the second gate electrode 33 on the other side of the n-type well 31 and spaced from the first p-type source region 36. . The first p-type drain region 40 and the first p-type drain contact region 41 form a DDD structure. Note that an LDD structure may be formed by forming only the first p-type drain region 40.

The first p-type drain region 40 is formed in a self-aligned manner with respect to the sidewall 35. The first p-type drain region 40 integrally includes a first p-type drain offset region 42 formed in a self-aligned manner with respect to the second gate electrode 33. The p-type impurity concentration of the first p-type drain offset region 42 is smaller than the p-type impurity concentration of the first p-type drain region 40. The first p-type drain contact region 41 is formed on the surface portion of the first p-type drain region 40. A silicide film 43 made of, for example, titanium silicide is formed on the surface portions of the first p-type drain region 40 and the first p-type drain contact region 41. A region between the first p-type source region 36 and the first p-type drain region 40 is a channel region 44 of the high-voltage side p-type MISFET 10.
<Low pressure side CMIS area>
Referring to FIGS. 1 and 3, low-voltage side CMIS region 4 includes a low-voltage n-type MISFET 49 and a low-voltage p-type MISFET 50 that are isolated from each other by element isolation unit 6. The rated voltage V _dd2n of the low-voltage side n-type MISFET 49 and the rated voltage V _dd2p of the low-voltage side p-type MISFET ₅₀ are both 2.5 V or less (rated voltages V _dd2n , V _dd2p > 0 V). The rated voltages V _dd2n and V _dd2p are specifically voltages required to operate the low-voltage side n-type MISFET 49 and the low-voltage side p-type MISFET 50, and both are defined as drain-source voltages. Hereinafter, specific configurations of the low-voltage side n-type MISFET 49 and the low-voltage side p-type MISFET 50 will be sequentially described.
(1) Low voltage side n-type MISFET
A p-type well 51 is formed on the surface portion of the semiconductor substrate 2 in the low-voltage side n-type MISFET 49 along the side of the element isolation portion 6. The p-type well 51 is formed with the same depth and the same p-type impurity concentration as the p-type well 11 described above. The boundary between the p-type well 51 and the semiconductor substrate 2 is in contact with the bottom of the element isolation portion 6. A third gate insulating film 52 is formed on the surface of the semiconductor substrate 2 so as to be in contact with the p-type well 51.

The third gate insulating film 52 is formed in a stripe shape in plan view. Third gate insulating film 52 has a thickness of not less than 100 mm and not more than 1500 mm, for example. The third gate insulating film 52 may be a SiO ₂ film. An n-type third gate electrode 53 doped with an n-type impurity is formed in a stripe shape in plan view so as to face the p-type well 51 with the third gate insulating film 52 interposed therebetween. More specifically, the third gate electrode 53 includes an n-type polysilicon gate electrode doped with an n-type impurity.

Referring to FIG. 1, the third gate electrode 53 has a gate length L3 of 0.35 μm or less, more specifically 0.25 μm or less. In the present embodiment, the gate length L3 of the third gate electrode 53 is defined by the width in the direction orthogonal to the stripe direction of the third gate electrode 53. Third gate electrode 53 may have an n-type impurity concentration of, for example, 1.0 × 10 ²⁰ cm ⁻³ or more and 1.0 × 10 ²² cm ⁻³ or less. A silicide film 54 made of, for example, titanium silicide is formed on the surface of the third gate electrode 53. Both side surfaces of the third gate electrode 53 are covered with sidewalls 55 made of an insulating material such as SiN.

A second n-type source region 56 and a second n-type source contact region 57 are formed on the surface portion of the p-type well 51 on one side of the third gate electrode 53. The second n-type source region 56 and the second n-type source contact region 57 form a DDD structure. Note that the LDD structure may be formed by forming only the second n-type source region 56.
The second n-type source region 56 is formed in a self-aligned manner with respect to the sidewall 55. The second n-type source region 56 may have the same n-type impurity concentration as the n-type impurity concentration of the third gate electrode 53. The second n-type source region 56 integrally includes a second n-type source offset region 58 formed in a self-aligned manner with respect to the third gate electrode 53. The n-type impurity concentration of the second n-type source offset region 58 is smaller than the n-type impurity concentration of the second n-type source region 56. The second n-type source contact region 57 is formed on the surface portion of the second n-type source region 56. On the surface portions of the second n-type source region 56 and the second n-type source contact region 57, a silicide film 59 made of, for example, titanium silicide is formed.

  A second n-type drain region 60 and a second n-type drain contact region 61 are formed on the surface of the p-type well 51 on the other side of the third gate electrode 53, spaced from the second n-type source region 56. . The second n-type drain region 60 and the second n-type drain contact region 61 form a DDD structure. Note that an LDD structure may be formed by forming only the second n-type drain region 60.

  The second n-type drain region 60 is formed in a self-aligned manner with respect to the sidewall 55. The second n-type drain region 60 may have the same n-type impurity concentration as the n-type impurity concentration of the third gate electrode 53. The second n-type drain region 60 integrally includes a second n-type drain offset region 62 formed in a self-aligned manner with respect to the third gate electrode 53. The n-type impurity concentration of the second n-type drain offset region 62 is smaller than the n-type impurity concentration of the second n-type drain region 60.

The second n-type drain contact region 61 is formed on the surface portion of the second n-type drain region 60. On the surface portions of the second n-type drain region 60 and the second n-type drain contact region 61, a silicide film 63 made of, for example, titanium silicide is formed. A region between the second n-type source region 56 and the second n-type drain region 60 is a channel region 64 of the low-voltage side n-type MISFET 49.
(2) Low voltage side p-type MISFET
An n-type well 71 is formed on the surface portion of the semiconductor substrate 2 in the low-voltage side p-type MISFET 50 along the side of the element isolation portion 6. The n-type well 71 is formed with the same depth and the same n-type impurity concentration as the n-type well 31 described above. The boundary between the n-type well 71 and the semiconductor substrate 2 is in contact with the bottom of the element isolation portion 6. A fourth gate insulating film 72 is formed on the surface of the semiconductor substrate 2 so as to be in contact with the n-type well 71.

  The fourth gate insulating film 72 is formed of the same thickness and the same material as the third gate insulating film 52 described above. A p-type fourth gate electrode 73 doped with a p-type impurity is formed in a stripe shape in plan view so as to face the n-type well 71 with the fourth gate insulating film 72 interposed therebetween. More specifically, the fourth gate electrode 73 includes a p-type polysilicon gate electrode doped with a p-type impurity.

Referring to FIG. 1, the fourth gate electrode 73 has a gate length L4 of 0.35 μm or less, more specifically 0.25 μm or less. In the present embodiment, the gate length L4 of the fourth gate electrode 73 is defined by the width in the direction orthogonal to the stripe direction of the fourth gate electrode 73. For example, fourth gate electrode 73 may have a p-type impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ or more and 1.0 × 10 ²² cm ⁻³ or less. On the surface of the fourth gate electrode 73, a silicide film 74 made of, for example, titanium silicide is formed. Both side surfaces of the fourth gate electrode 73 are covered with sidewalls 75 made of an insulating material such as SiN.

A second p-type source region 76 and a second p-type source contact region 77 are formed on the surface of the n-type well 71 on one side of the fourth gate electrode 73. The second p-type source region 76 and the second p-type source contact region 77 form a DDD structure. Note that an LDD structure may be formed by forming only the second p-type source region 76.
The second p-type source region 76 is formed in a self-aligned manner with respect to the sidewall 75. The second p-type source region 76 may have the same p-type impurity concentration as the p-type impurity concentration of the fourth gate electrode 73. The second p-type source region 76 integrally includes a second p-type source offset region 78 formed in a self-aligned manner with respect to the fourth gate electrode 73. The p-type impurity concentration of the second p-type source offset region 78 is smaller than the p-type impurity concentration of the second p-type source region 76. The second p-type source contact region 77 is formed on the surface portion of the second p-type source region 76. On the surface portions of the second p-type source region 76 and the second p-type source contact region 77, a silicide film 79 made of, for example, titanium silicide is formed.

  A second p-type drain region 80 and a second p-type drain contact region 81 are formed on the surface portion of the n-type well 71 on one side of the fourth gate electrode 73 so as to be spaced from the second p-type source region 76. The second p-type drain region 80 and the second p-type drain contact region 81 form a DDD structure. Note that an LDD structure may be formed by forming only the second p-type drain region 80.

  The second p-type drain region 80 is formed in a self-aligned manner with respect to the sidewall 75. The second p-type drain region 80 may have the same p-type impurity concentration as the p-type impurity concentration of the fourth gate electrode 73. The second p-type drain region 80 integrally includes a second p-type drain offset region 82 formed in a self-aligned manner with respect to the fourth gate electrode 73. The p-type impurity concentration of the second p-type drain offset region 82 is smaller than the p-type impurity concentration of the second p-type drain region 80.

  The second p-type drain contact region 81 is formed on the surface portion of the second p-type drain region 80. On the surface portions of the second p-type drain region 80 and the second p-type drain contact region 81, a silicide film 83 made of, for example, titanium silicide is formed. A region between the second p-type source region 76 and the second p-type drain region 80 is a channel region 84 of the low-voltage side p-type MISFET 50.

Referring to FIGS. 2 and 3, an interlayer insulating film 90 is formed on the surface of semiconductor substrate 2 so as to cover the entire surface of semiconductor substrate 2. In the present embodiment, the interlayer insulating film 90 includes SiO ₂ or SiN. The interlayer insulating film 90 may be formed of one insulating film or a stacked film of a plurality of insulating films. A plurality of wirings 91 for supplying power to the high-voltage side CMIS region 3 and the low-voltage side CMIS region 4 are formed on the interlayer insulating film 90.

  The plurality of wirings 91 include a conductive material such as aluminum. Each wiring 91 has a corresponding first gate electrode 13, first n-type source region 16, first n-type drain region 20, and second gate electrode 33 through a contact plug 92 formed through the interlayer insulating film 90. , First p-type source region 36, first p-type drain region 40, third gate electrode 53, second n-type source region 56, second n-type drain region 60, fourth gate electrode 73, second p-type source region 76 or second p It is electrically connected to the mold drain region 80. Each wiring 91 is formed in a region on the gate electrodes 13, 33, 53, 73 so as to cross the first gate electrode 13, the second gate electrode 33, the third gate electrode 53, and the fourth gate electrode 73. May be. A surface protection film 93 made of an insulating material such as SiN is formed on the interlayer insulating film 90 so as to cover the wiring 91.

FIG. 4 is a cross-sectional view for explaining the behavior of the movable ions 94. FIG. 4 corresponds to the cross-sectional view shown in FIG. In the following description, the rated voltages V _dd1n and V _dd1p (> 2.5 V) are applied to the high-voltage side n-type MISFET 9 and the high-voltage side p-type MISFET 10 in the high-voltage side CMIS region 3 and the low-voltage side CMIS region 4 Consider a case where rated voltages V _dd2n and V _dd2p (≦ 2.5 V) are applied to the wiring 91 corresponding to the side n-type MISFET 49 and the low-voltage side p-type MISFET 50. Note that FIG. 3 is referred to for the low pressure side CMIS region 4.

The semiconductor device 1 includes a relatively high rated voltage _{V Dd1n,} the high-pressure side CMIS region 3 of the _{V Dd1p,} relatively low rated voltage _{V Dd2n,} and a low-pressure side CMIS region 4 of the _{V dd2p.} The high voltage side CMIS region 3 includes a high voltage side n-type MISFET 9 including a first gate electrode 13 doped with an n-type impurity, and a high voltage side p-type MISFET 10 including a second gate electrode 33 doped with an n-type impurity. Includes single gate structure.

  The low-voltage side CMIS region 4 includes a low-voltage side n-type MISFET 49 including a third gate electrode 53 doped with an n-type impurity, and a low-voltage side p-type MISFET 50 including a fourth gate electrode 73 doped with a p-type impurity. Includes dual gate structure. That is, the semiconductor device 1 has a hybrid gate structure including both a single gate structure and a dual gate structure.

Referring to FIG. 4, when rated voltages V _dd1n and V _dd1p are applied to corresponding wirings 91 in high-voltage side CMIS region 3, ions leak from the metal material forming wiring 91 as movable ions 94. . In the present embodiment, the movable ions 94 include aluminum ions (cations). In the high voltage side CMIS region 3, the movable ions 94 reach the first gate electrode 13 of the high voltage side n-type MISFET 9 and the second gate electrode 33 of the high voltage side p type MISFET 10 via the interlayer insulating film 90.

The first gate electrode 13 and the second gate electrode 33 are doped with n-type impurities. Therefore, the movable ions 94 are gettered (captured) by the n-type impurities of the first gate electrode 13 and the second gate electrode 33. Thereby, it is possible to suppress the movable ions 94 from reaching the first gate insulating film 12 and the second gate insulating film 32. As a result, in the high voltage side CMIS region 3, the threshold voltage _Vth can be suppressed from fluctuating.

On the other hand, referring to FIG. 3, in the low-pressure side CMIS region 4, the movement of ions in the wiring 91 is suppressed by the relatively low rated voltages V _dd2n and V _dd2p . Therefore, in the low-pressure side CMIS region 4, the influence of the movable ions 94 is small, and the threshold voltage _Vth can be reduced by the fourth gate electrode 73 doped with the p-type impurity.
As described above, in the present embodiment, since the second gate electrode 33 doped with the n-type impurity is formed in the high voltage side CMIS region 3, fluctuations in the threshold voltage _Vth due to the movable ions 94 can be suppressed. In the low voltage side CMIS region 4, the fourth gate electrode 73 doped with the p-type impurity is formed, so that the threshold voltage _Vth can be reduced. As a result, the semiconductor device 1 that can improve the reliability can be provided.

In the present embodiment, the interlayer insulating film 90 includes SiO ₂ or SiN. For example, when the interlayer insulating film 90 contains BPSG (Boron Phosphorus Silicon Glass) or PSG (Phosphorus Silicon Glass), it has phosphorus (P) which is an n-type impurity. 94 can be gettered (captured). However, when the interlayer insulating film 90 containing BPSG or PSG is formed, it is necessary to heat the semiconductor substrate 2 by a heat treatment step after film formation in order to diffuse impurities such as phosphorus (P). In this case, the impurity region formed in the semiconductor substrate 2 may further diffuse from the target position and spread to other regions.

In this embodiment, since the movable ions 94 can be gettered (captured) by the first gate electrode 13 and the second gate electrode 33 doped with n-type impurities, interlayer insulation containing SiO ₂ or SiN instead of BPSG or PSG A film 90 can be formed. Thereby, since heating of the semiconductor substrate 2 by a heat treatment process can be avoided, undesired diffusion of the impurity region formed in the semiconductor substrate 2 can be suppressed. As a result, the semiconductor device 1 that can further improve the reliability can be provided. Further, since the heat treatment process can be omitted, the manufacturing process can be simplified.
<Manufacturing method>
5A to 5J are cross-sectional views showing an example of a manufacturing process of the high-pressure side CMIS region 3 shown in FIG. 6A to 6J are cross-sectional views showing an example of a manufacturing process of the low-pressure side CMIS region 4 shown in FIG. Hereinafter, the active region 5 in which the high-voltage side n-type MISFET 9 is formed is referred to as a high-voltage side n-type MISFET formation region 9a, and the active region 5 in which the high-voltage side p-type MISFET 10 is formed is referred to as a high-voltage side p-type MISFET formation region 10a. The active region 5 in which the low-voltage n-type MISFET 49 is formed is referred to as a low-voltage n-type MISFET formation region 49a, and the active region 5 in which the low-voltage p-type MISFET 50 is formed is referred to as a low-voltage p-type MISFET formation region 50a.

  5A and 6A, a thermal oxide film 100 is formed on the surface of semiconductor substrate 2 by, for example, a thermal oxidation method. Next, nitride film 101 is formed so as to cover the entire region of thermal oxide film 100 by, for example, a CDV (Chemical Vapor Deposition) method. Next, for example, by photolithography and etching, an opening 102 for exposing a region where the trench 7 is to be formed is selectively formed in the nitride film 101 and the thermal oxide film 100. Next, unnecessary portions of the semiconductor substrate 2 are removed by etching using the nitride film 101 and the thermal oxide film 100 as a mask. Thereby, the trench 7 is formed.

  Next, a thin liner oxide film (not shown) is formed on the side and bottom surfaces of the trench 7 by, for example, thermal oxidation. Next, an insulating film made of silicon oxide is formed so as to fill trench 7 and cover the entire area of nitride film 101 by, eg, CVD. Next, the insulating film is etched back, and the insulator 8 is embedded in the trench 7. As a result, the element isolation portion 6 that partitions the active region 5 (the high-voltage side n-type MISFET formation region 9a, the high-voltage side p-type MISFET formation region 10a, the low-voltage side n-type MISFET formation region 49a, and the low-voltage side p-type MISFET formation region 50a). It becomes.

  Next, as shown in FIGS. 5B and 6B, the nitride film 101 and the thermal oxide film 100 are sequentially removed by etching. When the thermal oxide film 100 is removed, the insulator 8 is removed by the thickness of the thermal oxide film 100. As a result, the insulator 8 that integrally includes the embedded portion 8 a housed in the trench 7 and the protruding portion 8 b that is formed outside the trench 7 and protrudes above the surface of the semiconductor substrate 2 is formed.

  Next, as shown in FIGS. 5C and 6C, the p-type well 11 and the p-type well 51, and the n-type well 31 and the n-type well 71 are formed. More specifically, an ion implantation mask (not shown) having an opening exposing the high-voltage side n-type MISFET formation region 9a and the low-voltage side n-type MISFET formation region 49a includes the high-voltage side p-type MISFET formation region 10a and the low-voltage side. It is formed on the surface of the semiconductor substrate 2 so as to cover the p-type MISFET formation region 50a. Then, the p-type impurity is doped into the semiconductor substrate 2 through the ion implantation mask, and the p-type well 11 and the p-type well 51 are simultaneously formed. Thereafter, the ion implantation mask is removed.

  Similarly, an ion implantation mask (not shown) having an opening for exposing the high-voltage side p-type MISFET formation region 10a and the low-voltage side p-type MISFET formation region 50a includes the high-voltage side n-type MISFET formation region 9a and the low-voltage side n-type MISFET. It is formed on the surface of semiconductor substrate 2 so as to cover formation region 49a. Then, the n-type impurity is doped into the semiconductor substrate 2 through the ion implantation mask, and the n-type well 31 and the n-type well 71 are formed simultaneously. Thereafter, the ion implantation mask is removed.

  Next, as shown in FIGS. 5D and 6D, a mask 104 having an opening 103 exposing the low-voltage side n-type MISFET formation region 49a and the low-voltage side p-type MISFET formation region 50a is formed into a high-voltage side n-type MISFET formation region 9a and It is selectively formed on the surface of the semiconductor substrate 2 so as to cover the high-voltage side p-type MISFET formation region 10a. Next, a thin thermal oxide film 105 is formed on the surface of the semiconductor substrate 2 by, for example, a thermal oxidation method.

  Next, the thermal oxide film 105 formed in the low-voltage side n-type MISFET formation region 49a and the low-voltage side p-type MISFET formation region 50a is removed by etching through the mask 104. Next, the thermal oxidation method is performed again, and thin thermal oxide films 106 are formed in the low-voltage side n-type MISFET formation region 49a and the low-voltage side p-type MISFET formation region 50a. Thus, the first gate insulating film 12, the second gate insulating film 32, the third gate insulating film 52, and the fourth gate insulating film 72 are formed. The first gate insulating film 12 and the second gate insulating film 32 are formed thicker than the third gate insulating film 52 and the fourth gate insulating film 72. Thereafter, the mask 104 is removed.

Next, as shown in FIGS. 5E and 6E, the semiconductor substrate 2 is covered so as to cover the first gate insulating film 12, the second gate insulating film 32, the third gate insulating film 52, and the fourth gate insulating film 72. A polysilicon film 107 is formed on the surface.
Next, as shown in FIGS. 5F and 6F, the polysilicon film 107, the first gate insulating film 12, the second gate insulating film 32, the third gate insulating film 52, and the fourth gate insulating are formed by, for example, photolithography and etching. Unnecessary portions of the film 72 are removed. Thereby, the polysilicon film 107 is patterned into a predetermined shape to be the first gate electrode 13, the second gate electrode 33, the third gate electrode 53, and the fourth gate electrode 73.

  Next, as shown in FIGS. 5G and 6G, an ion implantation mask 109 that selectively has an opening 108 for exposing the high-voltage side n-type MISFET formation region 9a is formed into a high-voltage side p-type MISFET formation region 10a, a low-voltage side n-type MISFET. It is formed on the surface of semiconductor substrate 2 so as to cover MISFET formation region 49a and low-voltage side p-type MISFET formation region 50a. Next, n-type impurities are doped into the surface portion of the p-type well 11 and the first gate electrode 13 through the ion implantation mask 109. As a result, the first n-type source offset region 18 and the first n-type drain offset region 22 are formed in a self-aligned manner with respect to the first gate electrode 13. Thereafter, the ion implantation mask 109 is removed.

  Next, as shown in FIGS. 5H and 6H, an ion implantation mask 111 having an opening 110 exposing the high-voltage side p-type MISFET formation region 10a is formed into a high-voltage side n-type MISFET formation region 9a, a low-voltage side n-type MISFET formation region. 49a and the low voltage side p-type MISFET formation region 50a are formed on the surface of the semiconductor substrate 2 so as to cover them. Next, a p-type impurity is doped into the surface portion of the n-type well 31 and the second gate electrode 33 through the ion implantation mask 111. Thereby, the first p-type source offset region 38 and the first p-type drain offset region 42 are formed in a self-aligned manner with respect to the second gate electrode 33. Thereafter, the ion implantation mask 111 is removed.

  A process similar to this process is also performed on the low-voltage n-type MISFET formation region 49a and the low-voltage p-type MISFET formation region 50a. More specifically, in the low-voltage side n-type MISFET formation region 49 a, the n-type impurity is doped into the surface portion of the p-type well 51 and the third gate electrode 53. As a result, the second n-type source offset region 58 and the second n-type drain offset region 62 are formed in a self-aligned manner with respect to the third gate electrode 53. Similarly, in the low-voltage side p-type MISFET formation region 50a, the p-type impurity is doped into the surface portion of the n-type well 71 and the fourth gate electrode 73. As a result, the second p-type source offset region 78 and the second p-type drain offset region 82 are formed in a self-aligned manner with respect to the fourth gate electrode 73.

Next, as shown in FIGS. 5I and 6I, after a nitride film (not shown) is formed on the semiconductor substrate 2 by, for example, the CVD method, the nitride film is selectively etched to form the first gate insulating film. 12, sidewalls 15, 35, 55, and 75 are formed on the respective side surfaces of the second gate insulating film 32, the third gate insulating film 52, and the fourth gate insulating film 72.
Next, an ion implantation having a region where the first p-type source region 36 and the first p-type drain region 40 are to be formed in the high-voltage side p-type MISFET formation region 10a and an opening 112 exposing the low-voltage side p-type MISFET formation region 50a. A mask 113 is formed on the surface of the semiconductor substrate 2. In the high-voltage side p-type MISFET formation region 10 a, the ion implantation mask 113 covers the second gate electrode 33 and the sidewall 35. Next, p-type impurities are doped into the semiconductor substrate 2 through the ion implantation mask 113.

  In the high voltage side p-type MISFET formation region 10 a, the p-type impurity is doped in the surface portion of the n-type well 31. As a result, the first p-type source region 36 and the first p-type drain region 40 are formed in a self-aligned manner with respect to the sidewall 35. On the other hand, in the low-voltage side p-type MISFET formation region 50 a, the p-type impurity is doped into the surface portion of the n-type well 71 and the fourth gate electrode 73. As a result, the second p-type source region 76 and the second p-type drain region 80 are formed in a self-aligned manner with respect to the sidewall 75. Thereafter, the ion implantation mask 113 is removed.

  A process similar to this process is also performed on the high-voltage side n-type MISFET formation region 9a and the low-voltage side n-type MISFET formation region 49a. More specifically, in the high-voltage side n-type MISFET formation region 9a, the n-type impurity is doped into the surface portion of the p-type well 11 and the first gate electrode 13. As a result, the first n-type source region 16 and the first n-type drain region 20 are formed in a self-aligned manner with respect to the sidewall 15. On the other hand, in the low-voltage side n-type MISFET formation region 49 a, n-type impurities are doped into the surface portion of the p-type well 51 and the third gate electrode 53. As a result, the second n-type source region 56 and the second n-type drain region 60 are formed in a self-aligned manner with respect to the sidewall 55.

  Next, as shown in FIGS. 5J and 6J, a titanium film 114 is formed so as to cover the entire surface of the semiconductor substrate 2. Next, the second gate electrode 33 of the high-voltage side p-type MISFET formation region 10a and the ion implantation mask 116 having the opening 115 exposing the high-voltage side n-type MISFET formation region 9a and the low-voltage side n-type MISFET formation region 49a are semiconductors. It is formed on the surface of the substrate 2. Next, n-type impurities enter the second gate electrode 33 of the high-voltage side p-type MISFET formation region 10a, the high-voltage side n-type MISFET formation region 9a, and the low-voltage side n-type MISFET formation region 49a through the ion implantation mask 116. Doped. Thus, the second gate electrode 33 doped with n-type impurities is formed in the high-voltage side p-type MISFET formation region 10a.

  Next, the first n-type source contact region 17, the first n-type drain contact region 21, the first p-type source contact region 37, the first p-type drain contact region 41, the second n-type source contact region 57, and the second n-type drain contact region 61 The second p-type source contact region 77 and the second p-type drain contact region 81 are formed by ion implantation. Next, the titanium film 114 is subjected to heat treatment, and silicide films 19, 23, 34, 39, 43, 54, 59, 63, 74, 79, 83 made of titanium silicide are formed in the corresponding portions. Thereafter, the titanium film 114 is removed. Then, the interlayer insulating film 90, the contact plug 92, the wiring 91, and the surface protective film 93 are formed in this order on the semiconductor substrate 2, and the semiconductor device 1 is manufactured.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above-described embodiment, the example in which the first gate electrode 13, the second gate electrode 33, and the third gate electrode 53 doped with n-type impurities are formed has been described. The n-type impurity concentrations of the first gate electrode 13, the second gate electrode 33, and the third gate electrode 53 may have different concentration profiles in the thickness direction toward the semiconductor substrate 2. The n-type impurity concentrations of the first gate electrode 13, the second gate electrode 33, and the third gate electrode 53 may be set so as to gradually decrease in the direction toward the semiconductor substrate 2, for example.

  In the above-described embodiment, the example in which the fourth gate electrode 73 doped with the p-type impurity is formed has been described. In this configuration, the p-type impurity concentration of the fourth gate electrode 73 may have a different concentration profile in the thickness direction toward the semiconductor substrate 2. The p-type impurity concentration of the fourth gate electrode 73 may be set so as to gradually decrease in the direction toward the semiconductor substrate 2, for example.

In the above-described embodiment, the example in which the interlayer insulating film 90 includes SiO ₂ or SiN has been described. However, the interlayer insulating film 90 containing BPSG or PSG may be formed by paying attention to the gettering (trapping) effect of the movable ions 94. That is, the interlayer insulating film 90 may include one or more insulating materials (insulating films) selected from the group including SiO ₂ , SiN, BPSG, and PSG. When the interlayer insulating film 90 includes a plurality of insulating materials (insulating films), the interlayer insulating film 90 may be a stacked film in which a plurality of insulating films selected from the above group are stacked.

  In the above-described embodiment, the semiconductor device 1 includes a memory region in which a non-volatile memory having a control gate and a floating gate is formed in addition to the high-voltage side CMIS region 3 and the low-voltage side CMIS region 4, BJT (Bipolar Junction Transistor) ) May be included, and various element formation regions such as a JFET region in which a JFET (Junction Field Effect Transistor) is formed may be included. In addition to the high voltage side CMIS region 3 and the low voltage side CMIS region 4, the semiconductor device 1 may include a passive element formation region in which a capacitor region, a resistance region, and the like are formed. Further, the semiconductor device 1 includes an LSI (Large Scale Integration), an SSI (Small Scale Integration), and an MSI by combining the high voltage side CMIS region 3 and the low voltage side CMIS region 4 with the element formation region and / or the passive element formation region. An integrated circuit such as (Medium Scale Integration), VLSI (Very Large Scale Integration), or ULSI (Ultra-Very Large Scale Integration) may be configured.

In the above-described embodiment, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 is reversed may be employed. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.
In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 High voltage | pressure side CMIS area | region 4 Low voltage | pressure side CMIS area | region 9 High voltage | pressure side n-type MISFET
10 High-voltage side p-type MISFET
12 First gate insulating film 13 First gate electrode 32 Second gate insulating film 33 Second gate electrode 36 First p-type source region 40 First p-type drain region 49 Low-voltage side n-type MISFET
50 Low voltage side p-type MISFET
53 Third gate electrode 73 Fourth gate electrode 90 Interlayer insulating film 91 Wiring 94 Movable ions L1 Gate length L2 Gate length

Claims (9)

A semiconductor substrate in which a high voltage side CMIS region having a relatively high rated voltage and a low voltage side CMIS region having a relatively low rated voltage are set;
An interlayer insulating film formed on the semiconductor substrate so as to cover the high-pressure side CMIS region and the low-pressure side CMIS region;
A plurality of wirings formed on the interlayer insulating film and supplying power to the high-voltage side CMIS region and the low-voltage side CMIS region;
The high pressure side CMIS region is:
A high-voltage n-type MISFET formed on the semiconductor substrate with a first gate insulating film interposed therebetween and including a first gate electrode doped with an n-type impurity;
A high-voltage side p-type MISFET including a second gate electrode formed on the semiconductor substrate with a second gate insulating film interposed therebetween and doped with an n-type impurity;
The low pressure side CMIS region is:
a low-voltage n-type MISFET including a third gate electrode doped with an n-type impurity;
A semiconductor device having a low-voltage side p-type MISFET including a fourth gate electrode doped with a p-type impurity. The high-voltage side p-type MISFET is
A p-type source region and a p-type drain region, which are formed on the surface portion of the semiconductor substrate so as to be electrically connected to the second gate electrode and spaced apart from each other, and are respectively doped with p-type impurities; The semiconductor device according to claim 1. The high voltage side CMIS region has a rated voltage greater than 2.5V,
The semiconductor device according to claim 1, wherein the low-voltage side CMIS region has a rated voltage of 2.5 V or less.   The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode have a gate length of 0.35 μm or less.   The semiconductor device according to claim 4, wherein the first gate electrode and the second gate electrode have a gate length of 0.25 μm or less. 6. The second gate electrode according to claim 1, wherein the second gate electrode has an n-type impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ or more and 1.0 × 10 ²² cm ⁻³ or less. Semiconductor device. The first gate electrode includes an n-type polysilicon gate electrode doped with an n-type impurity,
The semiconductor device according to claim 1, wherein the second gate electrode includes an n-type polysilicon gate electrode doped with an n-type impurity. The semiconductor device according to claim 1, wherein the interlayer insulating film includes SiO ₂ or SiN. A semiconductor substrate on which a plurality of CMIS regions including a high voltage side CMIS region having a rated voltage greater than 2.5 V and a low voltage side CMIS region having a rated voltage of 2.5 V or less are set;
An interlayer insulating film formed on the semiconductor substrate so as to cover the plurality of CMIS regions;
A plurality of wirings formed on the interlayer insulating film and supplying power to the plurality of CMIS regions;
The high pressure side CMIS region is:
A high-voltage side p-type MISFET having an n-type gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween and doped with an n-type impurity having a gate length of 0.35 μm or less;
The low pressure side CMIS region is:
A semiconductor device including a low-voltage p-type MISFET having a p-type gate electrode doped with a p-type impurity having a gate length of 0.35 μm or less.

Images