JP2017004997A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve heat dissipation of a semiconductor integrated circuit positioned at an intermediate part of a lamination layer on a semiconductor device formed by laminating a plurality of semiconductor integrated circuits.SOLUTION: The semiconductor device includes: a plurality of semiconductor integrated circuits 102, 103, 105 and 106 including a through conductor; a substrate 101 including a through conductor, on which the plurality of semiconductor integrated circuits are laminated; and a heat dissipation member 104, including the through conductor, laminated between at least part of the laminated semiconductor integrated circuits.SELECTED DRAWING: Figure 1

Description

  The present invention relates to three-dimensional mounting of semiconductor devices.

  In recent years, there has been an increasing demand for downsizing, high functionality, and power saving of electronic devices. In response to this request, in packaging of LSIs, a highly integrated semiconductor device is realized by forming a structure in which a plurality of semiconductor integrated circuits are three-dimensionally mounted using PoP (Package on Package) technology.

  Furthermore, in high-density three-dimensional packaging, the use of TSV (Through Silicon Via), which allows wiring to penetrate the semiconductor integrated circuit, achieves higher circuit integration, higher functionality, and lower power consumption. It became possible. For example, a PCB (Printed Circuit Board) of an electronic device can be miniaturized by three-dimensionally mounting a memory or other LSI on the LSI in the vertical direction. Further, the wiring length is shortened by the wiring penetrating the semiconductor integrated circuit, the signal speed can be improved and the parasitic capacitance can be reduced, and the power consumption can be reduced.

  On the other hand, in the three-dimensional mounting using TSV, the thermal resistance in the vertical direction becomes very low compared to the conventional mounting method due to the thinning of the semiconductor integrated circuit such as LSI. As a result, in the three-dimensional mounting in which the semiconductor integrated circuits are stacked vertically, the semiconductor integrated circuits stacked one above the other are easily affected by heat generation, and the semiconductor integrated circuits affected by the heat may malfunction. is there.

  Therefore, a technology is known in which a heat sink is arranged on the top of a three-dimensionally mounted package to improve heat dissipation, or a heat insulating material is arranged between semiconductor integrated circuits to suppress the influence of heat (see Patent Document 1). ).

  However, the technology of arranging a heat sink on the top of the package and the technology of arranging a heat insulating material between the semiconductor integrated circuits, when the semiconductor integrated circuit is further thinned, the heat of the semiconductor integrated circuit arranged in the middle part of the stack is sufficient. May not be spread. In other words, in the three-dimensional mounting in which a plurality of semiconductor integrated circuits are stacked, it is necessary to improve the heat dissipation of the semiconductor integrated circuit located in the middle of the stack and prevent malfunction of the semiconductor integrated circuit due to heat.

JP 2005-347390 A

  An object of the present invention is to improve heat dissipation of a semiconductor integrated circuit located in an intermediate portion of a stacked layer in a semiconductor device in which a plurality of semiconductor integrated circuits are stacked.

  The present invention has the following configuration as one means for achieving the above object.

  A semiconductor device according to the present invention includes a plurality of semiconductor integrated circuits including through conductors, a substrate including through conductors on which the plurality of semiconductor integrated circuits are stacked, a through conductor, and the stacked semiconductor integrated circuits. And a heat dissipating member laminated between at least a part.

  ADVANTAGE OF THE INVENTION According to this invention, the heat dissipation of the semiconductor integrated circuit located in the intermediate part of a lamination | stacking can be improved in the semiconductor device by which a several semiconductor integrated circuit is laminated | stacked.

FIG. 6 illustrates a configuration example of a semiconductor device according to an embodiment. The figure which shows an example which observed the interposer for thermal radiation from the heat-transfer layer side. 3A and 3B illustrate a heat dissipation path for heat generated in a semiconductor integrated circuit.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. In addition, an Example does not limit this invention concerning a claim, and all the combinations of the structure demonstrated in an Example are not necessarily essential for the solution means of this invention.

[Configuration of semiconductor device]
Hereinafter, an embodiment will be described by taking as an example a semiconductor device in which four semiconductor integrated circuits such as an LSI and a memory and an interposer (hereinafter referred to as a heat dissipation interposer) as a heat dissipation member are stacked. FIG. 1 shows a configuration example of the semiconductor device of the embodiment.

  The semiconductor device of the embodiment has a structure in which a module substrate 101, an LSI 102, a memory 103, a heat dissipating interposer 104, a memory 105, and a memory 106 are stacked in this order from the side connected to the PCB (hereinafter referred to as the lower side). In other words, the LSI 102 and the memory 103 are stacked on the module substrate 101, and the memory 105 and the memory 106 are further stacked with the heat dissipating interposer 104 interposed therebetween.

  The module substrate 101 is connected to the LSI 102 via vias 101a that are through conductors and module bumps 112 that are connection portions. Further, the module substrate 101 has a heat transfer layer 101b, and the heat transfer layer 101b is connected to the ground potential of the PCB through the via 101a and the module ball 111.

  The LSI 102, the memory 103, the heat dissipating interposer 104, the memory 105, and the memory 106 are connected to each other through TSVs 102a, 103a, 104a, 105a, and 106a that are their own through conductors, and micro bumps 113 that are connection portions. Is done. Note that other than the micro bumps 113 may be used for connection between devices as long as semiconductor integrated circuits having a TSV structure can be stacked and heat can be transferred.

  The heat dissipating interposer 104 has a base member 104b and a heat conductive layer disposed on at least one surface of the base member 104b. For efficient heat dissipation, it is desirable to dispose heat conductive layers on both sides of the base member 104b. The example of FIG. 1 is arranged on the heat transfer layer 104c disposed on the surface of the base member 104b and on the back surface of the base member 104b. A heat transfer layer 104d is shown. The heat transfer layers 104c and 104d are connected by a TSV 104a penetrating the base member 104a.

  The heat transfer layer 101b of the module substrate 101 and the heat transfer layers 104c and 104d of the heat dissipating interposer 104 may be formed of a material having good thermal conductivity. For example, a metal such as copper is preferably used. Further, the base member 104b of the heat dissipating interposer 104 may be an insulating material, but for example, silicon or the like is preferably used in the same manner as the substrate of the semiconductor integrated circuit.

[Interposer for heat dissipation]
FIG. 2 shows an example in which the heat dissipating interposer 104 is observed from the heat transfer layer 104c side. The heat transfer layer 104c is connected to the grounding TSV 104a indicated by black circles disposed on the inner and outer four sides of the heat dissipating interposer 104. On the other hand, the signal TSV 104a indicated by white circles arranged inside the heat dissipation interposer 104 is separated from the heat transfer layer 104c and is not connected to the heat transfer layer 104c. The same applies to the case where the heat dissipating interposer 104 is observed from the heat transfer layer 104d side. In FIG. 2, although the insulating region around the signal TSV 104a is shown as a rectangle, the insulating region may be circular.

  The area of the heat dissipating interposer 104 may be larger than the area of the semiconductor integrated circuit and smaller than the area of the module substrate 101, and is not particularly limited. For example, when the LSI and the memory are 9 mm square, the heat dissipating interposer 104 is 18 mm square, the module substrate 101 is 18 mm square, and the like. The memory 105 is stacked at the center of the heat dissipating interposer 104. In FIG. 2, the dashed-dotted rectangle indicates the position of the memory 105 stacked on the heat dissipating interposer 104.

[Heat dissipation path]
The thermal resistance of a semiconductor integrated circuit is generally small in the thickness direction of the semiconductor integrated circuit and large in the surface direction of the semiconductor integrated circuit. Accordingly, when heat cannot be released in the thickness direction, heat is trapped in the semiconductor integrated circuit, and the temperature of the semiconductor integrated circuit rises.

  A heat dissipation path of heat generated in the semiconductor integrated circuit will be described with reference to FIG. FIG. 3 shows main heat dissipation paths when the LSI 102, the memory 103, the memory 105, and the memory 106 operate simultaneously.

  The heat of the LSI 102 reaches the module substrate 101 mainly through the path of the module bump 112 → the via 101a → the heat transfer layer 101b because the memory 103 exists as a heat source above. The heat that has reached the module substrate 101 diffuses directly from the module substrate 101 to the surroundings and is transmitted to the PCB via the module ball 111.

  The heat of the memory 103 reaches the heat dissipating interposer 104 mainly through the path of the upper micro bump 113 → the heat transfer layer 104d because the LSI 102 exists as a heat source below. The heat reaching the heat dissipating interposer 104 is diffused directly from the heat dissipating interposer 104 to the surroundings.

  The heat of the memory 105 reaches the heat dissipating interposer 104 mainly through the path from the lower micro bump 113 to the heat transfer layer 104c because the memory 106 exists as a heat source above. The heat reaching the heat dissipating interposer 104 is diffused directly from the heat dissipating interposer 104 to the surroundings.

  The heat of the memory 106 is diffused directly from the upper surface of the memory 106 to the surroundings because the memory 105 exists as a heat source below. If necessary, a heat dissipating interposer equivalent to a heat sink or a heat dissipating interposer 104 (not shown) can be stacked on the upper surface (the uppermost part of the stack) of the memory 106 for heat dissipation.

● Effect of heat dissipation interposer When there is no heat dissipation interposer 104 between the memories 103 and 105 and all the semiconductor integrated circuits operate and generate heat, the memories 103 and 105 in which the heat sources (memory 106 and LSI102) exist above and below This heat will mainly diffuse from their sides to the surroundings. In this case, the heat dissipation path is in a plane direction in which the thermal resistance inside the memories 103 and 105 is relatively high, and heat dissipation is difficult. In addition, there is heat transfer from the upper and lower heat sources (memory 106 and LSI 102), and the temperature rise of the memories 103 and 105 arranged in the middle of the stack increases.

  As a result, the temperature rise of the semiconductor device is larger than when the heat dissipating interposer 104 is provided, and the difference in the temperature rise of each semiconductor integrated circuit is also increased. That is, the temperature rise of the memories 103 and 105 is larger than the temperature rise of the LSI 102 and the memory 106.

  The increase in the resistance value of the signal path is proportional to the temperature rise, and the higher the resistance value, the more difficult the current flows, so that the rise and fall of the signal is delayed. That is, if there is a temperature difference between the memories, the resistance value of the signal path is different, and a difference in signal rise time or fall time occurs between the memories, causing malfunction.

  On the other hand, in the semiconductor device of the embodiment, the heat of the memories 103 and 105 arranged in the intermediate portion of the stack can be diffused to the surroundings through the heat dissipating interposer 104. In this case, the heat dissipation path is in the thickness direction where the internal thermal resistance of the memories 103 and 105 is relatively low, and heat dissipation is easy. As a result, a temperature difference between the memories is suppressed, and a malfunction caused by a difference in signal rise time or a fall time can be prevented.

  In the above description, the configuration example in which four semiconductor integrated circuits and one heat dissipating interposer are stacked has been described. The heat dissipating interposer only needs to be stacked between at least some of the plurality of semiconductor integrated circuits in accordance with the amount of heat generated by each semiconductor integrated circuit. The number of semiconductor integrated circuits, the number of heat dissipating interposers, and the order of stacking There is no limit. Of course, a semiconductor integrated circuit that generates a large amount of heat may be sandwiched between two heat dissipating interposers, or two or more heat dissipating interposers may be stacked.

  As described above, in the three-dimensional mounting in which a plurality of semiconductor integrated circuits are stacked, the heat dissipation of the semiconductor integrated circuit located in the middle of the stack can be improved, and malfunction of the semiconductor integrated circuit due to heat can be prevented.

  101… module substrate, 102, 103, 105, 106… semiconductor integrated circuit, 104… heat dissipation interposer

Claims (7)

A plurality of semiconductor integrated circuits comprising through conductors;
A substrate including a through conductor, on which the plurality of semiconductor integrated circuits are stacked;
A semiconductor device comprising a through conductor and a heat dissipation member laminated between at least a part of the laminated semiconductor integrated circuits.   2. The semiconductor device according to claim 1, wherein the heat radiating member has a heat conductive layer connected to the through conductor on at least one surface thereof.   3. The semiconductor device according to claim 2, wherein the heat conductive layer of the heat radiating member is grounded.   4. The semiconductor device according to claim 1, wherein the heat dissipation member has an area that is equal to or smaller than an area of the substrate and larger than an area of the semiconductor integrated circuit.   5. The semiconductor device according to claim 1, wherein the substrate has a heat conductive layer connected to the through conductor.   6. The semiconductor device according to claim 5, wherein the heat conductive layer of the substrate is grounded.   7. The semiconductor device according to claim 1, further comprising a heat sink or the heat radiating member at an uppermost portion of the stack.

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