JP2016537726A - Vector processing engine with merging circuit between execution unit and vector data memory and associated method - Google Patents

Abstract

A vector processing engine (VPE) is disclosed that utilizes a merging circuit in the data flow path between the execution unit and the vector data memory to provide in-flight merging of output vector data stored in the vector data memory. Related vector processing instructions, systems, and methods are also disclosed. The merging circuit is provided in the data flow path between the execution unit in the VPE and the vector data memory. The merging circuit performs an in-flight vector processing operation while the output vector data sample set is being supplied from the execution unit to the vector data memory via the output data flow path to be stored. It is configured to merge the output vector data sample sets. The merged output vector data sample set is in a form merged into vector data memory without the need for further post-processing steps that may delay the next vector processing operation to be performed within the execution unit. Remembered. [Selection] Figure 31

Description

Related applications

  [0001] This application was filed on March 13, 2013 and is hereby incorporated by reference in its entirety, "VECTOR PROCESSING ENGINES HAVING PROGRAMMABLE DATA PATH CONFIGURATIONS FOR PROVIDING MULTITED ED Related to US patent application Ser. No. 13 / 798,641, entitled “VECTOR PROCESSORS, SYSTEMS, AND METHODS”, 123249.

  [0002] This application was filed on March 13, 2013, and is incorporated herein by reference in its entirety, "VECTOR PROCESSING CARRY-SAVE ACCUMULATORS EMPLOYING REDUNDANT CARRY-SAVE FORMAT TO REDUPRAND CARRY. Related to US patent application Ser. No. 13 / 798,618, entitled RELATED VECTOR PROCESSORS, SYSTEMS, AND METHODS, 123248.

  [0003] This application is filed on Nov. 15, 2013, which is incorporated herein by reference in its entirety, "VECTOR PROCESSING ENGINES (VPEs) EMPLOYING A TAPED-DELAY LINE (S) FOR PROVIDING PRECISION" FILTER VECTOR PROCESSING OPERATIONS WITH REDUCED SAMPLE RE-FETCHING AND POWER CONSUMPTION, AND RELATED VECTOR PROCESSOR SYSTEMS AND METHODS "

  [0004] This application is filed on November 15, 2013, and is incorporated herein by reference in its entirety, "VECTOR PROCESSING ENGINES (VPEs) EMPLOYING TAPPED-DELAY LINE (S) FOR PROVIDING PRECISION CORRELATION. / COVARIANCE VECTOR PROCESSING OPERATIONS WITH REDUCED SAMPLE RE-FETCHING AND POWER CONSUMPTION, AND RELATED VECTOR PROCESSOR SYSTEM 0, and US REFERENCE VECTOR / AND

  [0005] This application is filed on November 15, 2013 and is incorporated herein by reference in its entirety, "VECTOR PROCESSING ENGINES (VPEs) EMPLOYING FORMAT CONVERSION CIRCUITRY DATA FLOWOR BETWEME BETWEET AND EXECUTION UNITS TO PROVIDE IN-FLIGHT FORMAT-CONVERTING OF INPUT VECTOR DATA TO EXECUTION UNITS FOR VECTOR PROCESSING OPERATIONS, AND RELATIVES "Entitled 124365 also relates to U.S. Patent Application No. 14 / 082,088.

  [0006] This application was filed on November 15, 2013, and is hereby incorporated by reference in its entirety, "VECTOR PROCESSING ENGINES (VPEs) EMPLOYING REORDERING BETWEEN EXTECUENT EXTECUENT EXECT DATA MEMORY TO PROVIDE IN-FLIGHT REORDERING OF OUTPUT VECTOR DATA STORED TO VECTOR DATA MEMORY, AND RELATED VECTOR PROCESSOR SYSTEMS AND METHODS, US Patent No. 1244500 To.

  [0007] This application was filed on November 15, 2013, and is incorporated herein by reference in its entirety, "VECTOR PROCESSING ENGINES (VPEs) EMPLOYING DESPREADING CIRCUITRY IN DATA FLOW EVENT EXTECUENT EXECT DATA MEMORY TO PROVIDE IN-FLIGHT DESPREADING OF SPREAD-SPECTRUM SEQUENCES, AND RELATED VECTOR PROCESSING INSTRUCTIONS, SYSTEMS, AND METHODS, US Patent No. 124363U2 To do.

  [0008] The field of this disclosure relates to vector processors and related systems for processing vector operations and scalar operations, including single instruction multiple data (SIMD) processors and multiple instruction multiple data (MIMD) processors.

  [0009] Wireless computing systems are rapidly becoming one of the most popular technologies in the digital information domain. Advances in technology have made wireless communication devices smaller and more powerful. For example, wireless computing devices generally include small, lightweight, portable wireless phones that are easy for the user to carry, personal digital assistants (PDAs), and paging devices. More specifically, portable wireless phones, such as cellular phones and Internet Protocol (IP) phones, can communicate voice and data packets over a wireless network. In addition, many such wireless communication devices include other types of devices. For example, a wireless phone may include a digital still camera, a digital video camera, a digital recorder, and / or an audio file player. The wireless phone can also include a web interface that can be used to access the Internet. In addition, wireless communication devices are capable of high-speed wireless according to designed wireless communication technology standards (eg, code division multiple access (CDMA), wideband CDMA (WCDMA®), and long term evolution (LTE®)). May contain complex processing resources for processing communication data. As such, these wireless communication devices include significant computing capabilities.

  [0010] As wireless computing devices become smaller and more powerful, they become increasingly resource constrained. For example, the screen size, the amount of available memory and file system space, and the amount of input / output capability may be limited by the small size of the device. In addition, battery size, the amount of power supplied by the battery, and battery life are also limited. One way to increase the battery life of a device is to design a processor that consumes less power.

  [0011] In this regard, baseband processors, including vector processors, can be utilized for wireless communication devices. Vector processors have a vector architecture that provides high-level operations that operate on vectors, or arrays of data. Vector processing fetches a vector instruction once, as opposed to executing the vector instruction on one data set and then refetching and decoding the vector instruction for subsequent elements in the vector, It then involves executing the vector instruction multiple times across the array of data elements. This process allows a reduction in the energy required to execute the program because, among other factors, each vector instruction needs to be fetched fewer times. Since vector instructions operate on long vectors simultaneously over multiple clock periods, a high degree of parallelism can be achieved using simple ordered vector instruction dispatch.

  [0012] FIG. 1 illustrates an exemplary baseband processor 10 that may be utilized within a computing device, such as a wireless computing device. Baseband processor 10 includes a plurality of processing engines (PE) 12 each dedicated to providing function eigenvector processing for a particular application. In this example, six separate PEs 12 (0) to PE 12 (5) are provided in the baseband processor 10. PE12 (0) -PE12 (5) are each configured to provide vector processing for fixed X-bit wide vector data 14 supplied from shared memory 16 to PE12 (0) -PE12 (5). . For example, the vector data 14 may be 512 bits wide. Vector data 14 may be defined within vector data sample sets 18 (0) -18 (Y) (eg, 16-bit and 32-bit sample sets) of bit widths that are smaller multiples of X. In this way, PE12 (0) -PE12 (5) is a vector for a plurality of vector data sample sets 18 supplied in parallel to PE12 (0) -PE12 (5) to achieve a high degree of parallelism. Processing can be provided. Each PE 12 (0) -PE 12 (5) may include a vector register file (VR) for storing the results of vector instructions processed on the vector data 14.

  [0013] Each PE 12 (0) -PE 12 (5) in the baseband processor 10 of FIG. 1 is a specific dedicated circuit and hardware specifically designed to efficiently perform a specific type of fixed operation. Including. For example, the baseband processor 10 of FIG. 1 includes separate WCDMA PEs 12 (0), PE12 (1) and LTE PEs 12 (4), PE12 (5), which are different in WCDMA and LTE. This is because it involves special operations of type. Therefore, by providing separate WCDMA specific PE12 (0), PE12 (1) and LTE specific PE12 (4), PE12 (5), PE12 (0), PE12 (1), PE12 (4), PE12 ( Each of 5) can be designed to include special dedicated circuitry specific to frequently executed functions for WCDMA and LTE for high efficiency operations. This design is inefficient, but in contrast to a scalar processing engine that includes more general circuits and hardware designed to be flexible to support a larger number of unrelated operations. It is.

  [0014] Some wireless baseband operations require merging of data samples determined from previous processing operations. For example, it may be desirable to accumulate vector data samples with a wider variation than the execution unit data path. As another example, it may be desirable to provide dot product multiplication of output vector data samples from various execution units to provide merging of output vector data in vector processing operations. Vector data samples in these vector processing operations can include complex routing that provides a data path that intersects the vector data lane. However, parallelization in output vector data to be merged across different vector data lanes is difficult, which can increase complexity and reduce the efficiency of the vector processing engine (VPE). The vector processor may also include circuitry that performs post-processing merging of output vector data stored in the vector data memory from the execution unit. The post-processed output vector data samples stored in the vector data memory are fetched from the vector data memory, merged as necessary, and returned to the vector data memory for storage. However, this post-processing may delay the next vector processing operation of the VPE and cause underutilization of computer components in the execution unit.

  [0015] Embodiments disclosed herein include a merging circuit in a data flow path between an execution unit and a vector data memory to provide in-flight merging of output vector data stored in the vector data memory. Includes vector processing engine (VPE) to use. Related vector processing instructions, systems, and methods are also disclosed. The merging circuit is provided in the data flow path between the execution unit in the VPE and the vector data memory. The merging circuit performs an in-flight vector processing operation while the output vector data sample set is being supplied from the execution unit to the vector data memory via the output data flow path to be stored. It is configured to merge the output vector data sample sets. In-flight merging of output data sample sets means that the desired programmed output vector data samples in the output vector data sample set supplied by the execution unit are merged before being stored in the vector data memory. As a result, the output vector data sample set is stored in the vector data memory in the merged format. As a non-limiting example, merging output vector data may include adding an output vector data sample set that provides a merged output vector data sample set and an output scalar data sample set. As another non-limiting example, the merging of output vector data sample sets includes generating maximum output vector data and / or minimum output vector data between the compared output vector data sample sets from the execution unit. There is. The merged output vector data sample set is in a form merged into vector data memory without the need for further post-processing steps that may delay the next vector processing operation to be performed within the execution unit. Remembered.

  [0016] Thus, the efficiency of the data flow path within the VPE is not limited by merging of output vector data. When the output vector data sample set is to be stored in merged form in vector data memory, the next vector processing in the execution unit is limited only by computer resources, not data flow limitations. The VPE is also configured to provide a merged in-vector output vector data sample set within a desired destination location in the vector data memory without affecting the efficiency of the execution unit computer elements.

  [0017] In this regard, in one embodiment, a VPE configured to in-flight merge a resulting output vector data sample set generated by at least one execution unit that performs vector processing operations is provided. The The VPE comprises at least one vector data file. The vector data file is configured to provide an input vector data sample set fetched in at least one input data flow path for vector processing operations. The vector data file is also configured to receive at least one merged resulting output vector data sample set from at least one output data flow path to be stored. The VPE also comprises at least one execution unit provided in at least one input data flow path. The execution unit is configured to receive the input vector data sample set on at least one input data flow path. The execution unit is also configured to perform vector processing operations on the input vector data sample set to provide the resulting output vector data sample set on at least one output data flow path. The VPE also includes at least one merging circuit. The merging circuit is configured to receive the resulting output vector data sample set. The merging circuit also results in providing at least one merged resulting output vector data sample set without the resulting output vector data sample set being stored in at least one vector data file. It is configured to merge the resulting output vector data sample sets. The merging circuit is also configured to provide at least one merged resulting output vector data sample set on at least one output data flow path.

  [0018] In another embodiment, a VPE configured to in-flight merge a resulting output vector data sample set generated by at least one execution unit that performs vector processing operations is provided. The VPE comprises at least one vector data file means. The vector data file means comprises means for providing a set of input vector data samples fetched into at least one input data flow path means for vector processing operations. The vector data file means also comprises means for receiving at least one merged resulting output vector data sample set from at least one output data flow path means to be stored. The VPE also comprises at least one execution unit means provided in the at least one input data flow path means. The execution unit means comprises means for receiving an input vector data sample set on at least one input data flow path means. The execution unit means also comprises execution means for performing vector processing operations on the input vector data sample set to provide the resulting output vector data sample set on at least one input data flow path means. .

  [0019] Furthermore, the VPE also comprises at least one merging circuit means. The merging circuit means comprises means for receiving the resulting output vector data sample set on at least one input data flow path means. The merging circuit means also provides the at least one merged resulting output vector data sample set without the resulting output vector data sample set being stored in the at least one vector data file means. Merging means are provided for merging the resulting output vector data sample set with the code sequence vector data sample set. The merging circuit means also comprises means for providing at least one merged resulting output vector data sample set on the at least one output data flow path means.

  [0020] In another embodiment, a method is provided for in-flight merging a resulting output vector data sample set generated by at least one execution unit that performs vector processing operations. The method comprises providing an input vector data sample set fetched from at least one vector data file into at least one input data flow path for vector processing operations. The method also comprises receiving an input vector data sample set on at least one input data flow path in at least one execution unit provided in the at least one input data flow path. The method also comprises performing a vector processing operation on the input vector data sample set to provide a resulting output vector data sample set on at least one input data flow path. The method also results to provide at least one merged resulting output vector data sample set without the resulting output vector data sample set being stored in at least one vector data file. Merging output vector data sample sets. The method also comprises storing at least one merged resulting output vector data sample set from at least one output data flow path in at least one vector data file.

1 is a schematic diagram of an exemplary vector processor that includes multiple vector processing engines (VPEs), each dedicated to provide function-specific vector processing for a particular application. A common circuit and hardware provided within a VPE allows multiple modes to perform certain types of vector operations in a highly efficient manner for multiple applications or technologies without the need for separate VPE 1 is a schematic diagram of an exemplary baseband processor including a VPE having a programmable data path configuration as can be programmed with. FIG. FIG. 3 is a schematic diagram of a discrete finite impulse response (FIR) filter that may be provided in a filter vector processing operation supported by a VPE. Tapped to receive and provide a shifted input vector data sample set to be processed with filter coefficient data to provide recursive and power consumption reduced precision filter vector processing operations 1 is a schematic diagram of an example VPE that utilizes a delay line. FIG. 5 is a flowchart illustrating an example filter vector processing operation that may be performed in the VPE of FIG. 4 in accordance with an example filter vector instruction. FIG. 5 is a schematic diagram of filter tap coefficients stored in a register file in the VPE of FIG. 4. FIG. 5 is a schematic diagram of an exemplary input vector data sample set stored in a vector data file in the VPE of FIG. FIG. 5 is a schematic diagram illustrating an example tapped delay line and an optional shadow tapped delay line that may be provided in the VPE of FIG. FIG. 4 is a schematic diagram comprising a plurality of pipeline registers for receiving and supplying input vector data sample sets and shifted input vector data sample sets from a vector data memory to an execution unit during processing operations. Exemplary pipeline registers in data lanes, including intra-lane and inter-lane routing in pipeline registers for shifting input vector data samples in an input vector data sample set during a filter vector processing operation FIG. 8 is a schematic diagram illustrating more exemplary details of the tapped delay line of FIG. 7 showing details. FIG. 5 is a schematic diagram of an input vector data sample set initially stored on a primary tapped delay line in the VPE of FIG. 4 as part of a first filter tap execution of an exemplary 8-tap filter vector processing operation. The filter tap coefficients stored in the register file and the shadow taps in the VPE of FIG. 4 as part of the first filter tap execution of the exemplary 8-tap filter vector processing operation filter vector processing operation shown in FIG. 9A FIG. 3 is a schematic diagram of a shadow input vector data sample set initially stored in a delay line. Shifted input vector data samples stored in the primary tapped delay line and shadow tapped delay line in the VPE of FIG. 4 as part of the second filter tap execution of the exemplary 8-tap filter vector processing operation. The schematic of the filter tap coefficient memorize | stored in the set and a register file. Shifted input vector data samples stored in the primary tapped delay line and shadow tapped delay line in the VPE of FIG. 4 as part of the eighth filter tap execution of the exemplary 8-tap filter vector processing operation. The schematic of the filter tap coefficient memorize | stored in the set and a register file. FIG. 5 is a schematic diagram of the contents of an accumulator of execution units in the VPE of FIG. 4 after an exemplary 8-tap filter vector processing operation has been fully performed. Receive and supply to the execution unit a shifted input vector data sample set to be processed with sequence number data to provide precision correlation / covariance vector processing operations with reduced refetch and power consumption FIG. 3 is a schematic diagram of an example VPE that utilizes a tapped delay line for the purpose. Exemplary correlation / covariance vector processing that may be performed in parallel in the VPE of FIG. 11, in which interleaved on-time and late input vector data sample sets are fetched according to exemplary correlation / covariance vector processing operations The flowchart which shows operation | movement. Exemplary correlation / covariance vector processing that may be performed in parallel in the VPE of FIG. 11, in which interleaved on-time and late input vector data sample sets are fetched according to exemplary correlation / covariance vector processing operations The flowchart which shows operation | movement. 12 is a schematic diagram of a correlation / covariance input vector data sample set stored in a register file in the VPE of FIG. FIG. 12 is a schematic diagram illustrating an exemplary tapped delay line and an optional shadow tapped delay line that may be provided in the VPE of FIG. 11, wherein the exemplary tapped delay line is each a correlation performed by the VPE. / Comprising a plurality of pipeline registers for receiving and supplying the input vector data sample set and the shifted input vector data sample set from the vector data memory to the execution unit during the covariance vector processing operation Figure. FIG. 12 is a schematic diagram of an input vector data sample set from a vector data file first supplied to a primary tapped delay line in the VPE of FIG. 11 as part of a first processing stage of a correlation / covariance vector processing operation. FIG. 12 is a schematic diagram of a shadow input vector data sample set from a vector data file initially supplied to a shadow tapped delay line in the VPE of FIG. 11 as part of a first processing stage of a correlation / covariance vector processing operation. As part of the second processing stage of the correlation / covariance vector processing operation, the shifted input vector data sample set stored in the primary tapped delay line and shadow tapped delay line in the VPE of FIG. FIG. 4 is a schematic diagram of a shifted input vector data sample set stored in a register file. As part of the fourteenth processing stage of the correlation / covariance vector processing operation, the shifted input vector data sample set stored in the primary tapped delay line and shadow tapped delay line in the VPE of FIG. FIG. 4 is a schematic diagram of a shifted input vector data sample set stored in a register file. FIG. 12 is a schematic diagram of the contents of an execution unit accumulator in the VPE of FIG. 11 after an exemplary correlation / covariance vector processing operation has been fully performed. FIG. 4 is an exemplary vector data file illustrating a resulting set of filter output vector data samples stored separately in real and imaginary components of the resulting filter output vector data samples. FIG. 4 is an exemplary vector data file showing a resulting set of filter output vector data samples stored with their even and odd number of resulting filter output vector data samples stored separately. FIG. 5 is an illustration of an exemplary interleaved vector data sample of a vector data sample set stored in a VPE vector data file in a signed complex 16-bit format. FIG. 6 is an illustration of an exemplary interleaved vector data sample of a vector data sample set stored in a VPE vector data file in a signed complex 8-bit format. A vector data file without the input vector data sample set having to be refetched from the vector data file to provide a formatted input vector data sample set to at least one execution unit for performing vector processing operations FIG. 4 is a schematic diagram of an example VPE that utilizes a format conversion circuit configured to provide in-flight format conversion of an input vector data sample set in at least one input data flow path between and at least one execution unit. FIG. 20 is a flowchart illustrating an example in-flight format conversion of an input vector data sample set in at least one input data flow path between a vector data file and at least one execution unit that may be performed in the VPE of FIG. FIG. 20 is a schematic diagram of an exemplary format conversion circuit provided between the tapped delay line in the VPE of FIG. 19 and the execution unit, where the format conversion circuit is in the tapped delay line in the input data flow path to the execution unit. Schematic configured to provide in-flight format conversion of input vector data sample sets supplied by FIG. 20 illustrates an exemplary vector instruction data format that provides programming to the VPE of FIG. 19 to provide in-flight format conversion of input vector data sample sets within an input data flow path prior to receipt at an execution unit. In order to provide and store the rearranged resulting output data sample set, the resulting output vector data sample set is not stored in at least one vector data file, but at least one execution unit and at least one FIG. 4 is a schematic diagram of an example VPE that utilizes a reordering circuit configured to provide in-flight reordering of a resulting output vector data sample set in at least one output data flow path to and from a vector data file. An exemplary in-flight data set of output vector data sample sets in at least one output data flow path between the vector data file in the VPE of FIG. The flowchart which shows interleaving. Overview of an exemplary VPE that utilizes a reordering circuit in the output data flow path between the execution unit and the vector data file to provide in-flight reordering of the output vector data sample set stored in the vector data file. Figure. FIG. 26A is a diagram of an exemplary vector data sample sequence representing a communication signal. FIG. 26B is a diagram of an exemplary code division multiple access (CDMA) chip sequence. 26C is a diagram of the vector data sample sequence of FIG. 26A after being spread with the CDMA chip sequence of FIG. 26B. FIG. 26D is a diagram for despreading the spread vector data sample sequence of FIG. 26C with the CDMA chip sequence of FIG. 26B to restore the original vector data sample sequence of FIG. 26A. In order to provide and store the despread resulting output vector data sample set, the resulting output vector data sample set is not stored in at least one vector data file, but at least one execution unit and at least one FIG. 3 is a schematic diagram of an example VPE that utilizes a despreading circuit configured to provide despreading of a resulting set of output vector data samples in at least one output data flow path between two vector data files. Between at least one vector data file and at least one execution unit in the VPE of FIG. 27 to provide and store the resulting output vector data sample set despread in at least one vector data file 6 is a flowchart illustrating an exemplary despreading of the resulting output vector data sample set in at least one output data flow path. In the VPE of FIG. 27, providing despreading of the resulting output vector data sample set to provide and store the resulting output vector data sample set despread in at least one vector data file FIG. 3 is a schematic diagram of an exemplary despreading circuit in an output data flow path between at least one execution unit and at least one vector data file. FIG. 4 shows an exemplary vector data sample to be merged and a resulting vector data sample merged. In order to provide and store a merged resulting output vector data sample set, the resulting output vector data sample set is not stored in at least one vector data file, but at least one execution unit and at least one FIG. 6 is a schematic diagram of an example VPE that utilizes a merge circuit configured to provide merging of a resulting output vector data sample set in at least one output data flow path to and from a vector data file. At least one output data between the vector data file in the VPE of FIG. 31 and at least one execution unit to provide and store the resulting output vector data sample set merged into the vector data file. 6 is a flowchart illustrating exemplary additive merging of a resulting output vector data sample set in a flow path. The execution unit and vector data in the VPE of FIG. 31 that provides additive merging of the resulting output vector data sample set and storage of the resulting output vector data sample set merged into the vector data file. FIG. 4 is a schematic diagram of an exemplary merge circuit in an output data flow path to and from a file. Execution in the VPE of FIG. 31 that provides maximum / minimum merging of the resulting output vector data sample set and storage of the resulting output vector data sample set merged into the vector data file. FIG. 3 is a schematic diagram of an exemplary merge circuit in an output data flow path between a unit and a vector data file. FIG. 4 is a schematic diagram of exemplary vector processing stages that may be provided in a VPE, wherein some of the vector processing stages include exemplary vector processing blocks having a programmable data path configuration. 36 is a flow chart illustrating exemplary vector processing of multiplier and accumulator blocks, each having a programmable data path configuration and provided in various vector processing stages within the exemplary VPE of FIG. FIG. 36 is a more detailed schematic diagram of a plurality of multiplier blocks provided within the vector processing stage of the VPE of FIG. 35, wherein the plurality of multiplier blocks perform a plurality of modes for performing certain different types of vector multiplication operations. FIG. 2 is a schematic diagram in which a plurality of multiplier blocks each have a programmable data path configuration such that it can be programmed with FIG. 37 has a programmable data path configuration that can be programmed to provide multiplication operations for an 8 bit × 8 bit input vector data sample set and a 16 bit × 16 bit input vector data sample set. FIG. 2 is a schematic diagram of internal components of a multiplier block among a plurality of multiplier blocks of FIG. FIG. 39 is a generalized schematic diagram of a multiplier block and accumulator block in the VPE of FIG. 38, wherein the accumulator block uses a carry-over save format to reduce carry propagation. Schematic using an arithmetic structure. FIG. 40 is a detailed schematic diagram of exemplary internal components of the accumulator block of FIG. 39 provided within the VPE of FIG. 35, where the accumulator block uses a redundant carry save format to identify various different types. FIG. 6 is a schematic diagram of an accumulator block having a programmable data path configuration so that it can be programmed in multiple modes to perform a vector accumulation operation. An exemplary processor that can include a vector processor that can include the VPE disclosed herein to provide vector processing circuitry and vector processing operations in accordance with embodiments disclosed herein. The block diagram of a base system.

  [0073] Referring now to the drawings, several exemplary embodiments of the disclosure will be described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

  [0074] Embodiments disclosed herein include a merging circuit in a data flow path between an execution unit and a vector data memory to provide in-flight merging of output vector data stored in the vector data memory. It also includes a vector processing engine (VPE) to be used. Related vector processing instructions, systems, and methods are also disclosed. The merging circuit is provided in the data flow path between the execution unit in the VPE and the vector data memory. The merging circuit performs an in-flight vector processing operation while the output vector data sample set is being supplied from the execution unit to the vector data memory via the output data flow path to be stored. It is configured to merge the output vector data sample sets. In-flight merging of output data sample sets means that the desired programmed output vector data samples in the output vector data sample set supplied by the execution unit are merged before being stored in the vector data memory. As a result, the output vector data sample set is stored in the vector data memory in the merged format. As a non-limiting example, merging output vector data may include adding an output vector data sample set that provides a merged output vector data sample set and an output scalar data sample set. As another non-limiting example, the merging of output vector data sample sets includes generating maximum output vector data and / or minimum output vector data between the compared output vector data sample sets from the execution unit. There is. The merged output vector data sample set is in a form merged into vector data memory without the need for further post-processing steps that may delay the next vector processing operation to be performed within the execution unit. Remembered.

  [0075] Thus, the efficiency of the data flow path within the VPE is not limited by merging of output vector data. When the output vector data sample set is to be stored in merged form in vector data memory, the next vector processing in the execution unit is limited only by computer resources, not data flow limitations. The VPE is also configured to provide a merged in-vector output vector data sample set within a desired destination location in the vector data memory without affecting the efficiency of the execution unit computer elements.

  In this regard, FIG. 2 is a schematic diagram of a baseband processor 20 that includes an exemplary vector processing unit 22, also referred to as a vector processing engine (VPE) 22. As described in more detail below, VPE 22 provides execution unit 84 and other specific exemplary circuits and functions that provide vector processing operations, including the exemplary vector processing operations disclosed herein. Including. Baseband processor 20 and its VPE 22 may be provided in semiconductor die 24. In this embodiment, as described in more detail below, the baseband processor 20 includes a common VPE 22 that includes a programmable data path 26 that can be programmed to provide various programmable data path configurations. Including. In this way, the programmable data path 26 between the execution unit 84 in the VPE 22 and the vector data file 82 can be varied in various modes of operation without the need for a separate VPE 22 in the baseband processor 20. It can be programmed and reprogrammed to provide specific types of vector processing operations.

  [0077] Before describing the specific circuitry and vector processing operations configured to be provided by the VPE 22 in this disclosure for efficient processing beginning with FIG. 3, the components of the baseband processor 20 of FIG. Are listed first. Baseband processor 20 in this non-limiting example is a 512-bit vector processor. Baseband processor 20 includes components in addition to VPE 22 to support VPE 22 that provides vector processing within baseband processor 20. Baseband processor 20 includes a vector register, also known as vector data file 82, configured to receive and store vector data 30 from vector unit data memory (LMEM) 32. For example, vector data 30 is X bits wide and “X” is defined according to design choice (eg, 512 bits). Vector data 30 may be divided into vector data sample sets 34. As a non-limiting example, vector data 30 may be 256 bits wide and may comprise smaller vector data sample sets 34 (Y) -34 (0). Some vector data sample sets 34 (Y) -34 (0) may be 16 bits wide by way of example, and others are 32 bits wide other than vector data sample sets 34 (Y) -34 (0) obtain. The VPE 22 can provide vector processing for several selected vector data sample sets 34 (Y) -34 (0) that are fed in parallel to the VPE 22 to achieve a high degree of parallelism. . Vector data file 82 is also configured to store results generated when VPE 22 processes vector data 30. In some embodiments, the VPE 22 is configured not to store intermediate vector processing results in the vector data file 82 to reduce register writes to provide faster vector instruction execution time. This configuration is the opposite of a scalar instruction executed by a scalar processing engine that stores intermediate results in a register, such as a scalar processing digital signal processor (DSP).

  [0078] The baseband processor 20 of FIG. 2 is configured to condition the VPE 22 for use in conditional execution of vector instructions and to store updated conditions as a result of vector instruction execution. A condition register 36 is also included. The baseband processor 20 also includes an accumulation register 38, a global register file 40 including global registers, and an address register 42. The accumulation register 38 is configured to be used by the VPE 22 to store the accumulated result as a result of performing some special operations on the vector data 30. Global register file 40 is configured to store scalar operands for a number of vector instructions supported by VPE 22. The address register 42 retrieves the vector data 30 from the vector unit data memory 32, stores addresses addressable by vector load to store vector processing results in the vector unit data memory 32, and instructions supported by the VPE 22 Is configured to memorize.

  [0079] With continued reference to FIG. 2, the baseband processor 20 in this embodiment provides scalar processing (also referred to as an "integer unit") in the baseband processor 20 in addition to the vector processing provided by the VPE 22. A processor 44 is also included. It may be desirable to provide a central processing unit (CPU) configured to support both vector and scalar instruction operations based on the type of instruction executed for high efficiency operations. In this embodiment, scalar processor 44 is a 32-bit reduced instruction set computing (RISC) scalar processor, as a non-limiting example. Scalar processor 44 in this example includes an arithmetic logic unit (ALU) 46 to support scalar instruction processing. The baseband processor 20 fetches instructions from the program memory 50, decodes the fetched instructions, and based on the instruction type, fetches the fetched instructions to the scalar processor 44 or to the VPE 22 through the vector data path 53. Instruction dispatch circuit 48 is configured to be directed. Scalar processor 44 includes general purpose registers 54 that are used by scalar processor 44 when executing scalar instructions. An integer unit data memory (DMEM) 56 is included in the baseband processor 20 to supply data from the main memory to the general purpose register 54 for access by the scalar processor 44 for scalar instruction execution. The DMEM 56 may be a cache memory as a non-limiting example. Baseband processor 20 is a memory controller configured to receive a memory address from general register 54 when scalar processor 44 is executing a vector instruction that seeks access to main memory through memory controller data path 62. A memory controller 58 that includes a register 60 is also included.

  [0080] One type of special vector processing operation that may be desired to be supported by vector instruction processing by the VPE 22 is filtering. The filter operation calculates a quantized time domain representation of the superposition of the sampled input time function and a representation of the weighting function of the filter. Superposition in the time domain corresponds to multiplication in the frequency domain. In this way, the digital filter can be implemented in the VPE 22 with an extended sequence of multiplication and addition performed at evenly spaced sample intervals. For example, a discrete finite impulse response (FIR) filter may be implemented using a finite number (Y) of delay taps on the delay line with “Y” calculation filter coefficients to calculate the filter function.

  [0081] In this regard, FIG. 3 is a schematic diagram of an exemplary discrete FIR filter 64 that may be desired to be supported via filter vector processing operations in VPE 22 of FIG. Digitized input signal 66 (x [n]) passes through a delay structure called “filter delay taps” 68 (1) -68 (Y−1) and digitized input signal samples (x [0], x [1] ], ... x [n]). Filter delay taps 68 (1) -68 (Y-1) provide all the digitized input signal samples (ie, x [0]) to provide filter sample multiplicands 72 (0) -72 (Y-1). , X [1],... X [n]) are respectively multiplied by the filter coefficients (h [0] to h (Y−1)) (ie h (l) * x [n−1]). In order to shift the clocked digitized input signal samples (ie, x [0], x [1],... X [n]) into multipliers 70 (0) -70 (Y-1). To do. The filter sample multiplicands 72 (0) -72 (Y-1) are fed to an adder (ie, adder) 74 (1) to provide a resulting filtered output signal 76 (ie, y [n]). ) To 74 (Y-1). Thus, the discrete FIR filter 64 of FIG. 3 can be summarized as follows.

here,
n is the number of input signal samples,
x [n] is the digitized input signal 66;
y [n] is the resulting filtered output signal 76;
h (l) is a filter coefficient,
Y is the number of filter coefficients.
The filter coefficient h (l) can be a complex number. In one aspect, VPE 22 may receive filter coefficients (eg, from global register file 40). The VPE 22 can directly use the received filter coefficients to perform the FIR filter function, in which case the filter coefficient h (l) in the above equation can represent the received filter coefficients. Alternatively, the VPE 22 can calculate the complex conjugate of the received filter coefficients before using them to perform the FIR filter functions, in which case the filter coefficient h (l) in the above equation is , Which can represent the conjugate of the received filter coefficients.

[0082] The discrete FIR filter 64 of FIG. 3 may be rewritten as follows.
y [n] = x [n] * h0 + x [n-1] * h1 +. . . + X [n-7] * h7

  [0083] However, filtering operations such as the discrete FIR filter 64 of FIG. 3 may be difficult to parallelize in the vector processor due to the special data flow path provided in the vector processor. When an input vector data sample set to be filtered (eg, vectorized digitized input signal 66) is shifted between filter delay taps (eg, 68 (1) -68 (Y-1)), The input vector data sample set is refetched from the vector data file, thus increasing power consumption and reducing throughput. In order to minimize refetching of the input vector data sample set from the vector data file, the data flow path within the vector processor is filtered by a filter delay tap (e.g. 68 (1) -68) for efficient parallelization. (Y-1)) may be configured to provide as many multipliers (e.g., 70 (0) to 70 (Y-1)). However, other vector processing operations may require fewer multipliers, leading to inefficient scaling and underutilization of the multipliers in the data flow path. In order to provide scalability, if the number of multipliers is reduced to be less than the number of filter delay taps, the memory is used to obtain the same set of input vector data samples for the various phases of filtering. The parallelism is limited by requiring more refetches.

  [0084] In this regard, FIG. 4 is a schematic diagram of an exemplary VPE 22 (1) that may be provided as VPE 22 of FIG. As described in more detail below, the VPE 22 (1) of FIG. 4 is a precision filter vector processing operation within the VPE 22 (1) in which refetching of vector data samples is eliminated or reduced and power consumption is reduced. I will provide a. Precision filter vector processing operations require refetching of vector data samples, resulting in increased power consumption, compared to filter vector processing operations that require storage of intermediate results, provided in VPE 22 (1) Can be done. In order to eliminate or minimize refetching of input vector data samples from the vector data file to reduce power consumption and improve processing efficiency, the vector data files 82 (0) -82 (X ) And execution unit 84 (0) -84 (X) (also labeled “EU”) includes a tapped delay line 78 in the input data flow paths 80 (0) -80 (X). “X” +1 is the maximum number of parallel input data lanes provided in VPE 22 (1) for processing vector data samples in this example. The tapped delay line 78 is a subset or all of the input vector data samples 86 of the input vector data sample sets 86 (0) to 86 (X) from the corresponding subset or all of the vector data files 82 (0) to 82 (X). Is configured to receive input vector data sample sets 86 (0) -86 (X) on tapped delay line inputs 88 (0) -88 (X). Input vector data sample sets 86 (0) -86 (X) are 86 (0), 86 (1),. . . , And 86 (X), which is comprised of “X + 1” input vector data samples 86.

  [0085] With continued reference to FIG. 4, tapped delay line 78 is to be processed by execution units 84 (0) -84 (X) for filter vector processing operations, vector data files 82 (0) -82. The input vector data sample sets 86 (0) to 86 (X) fetched from (X) are stored. As described in more detail below with respect to FIGS. 6 and 7 below, tapped delay line 78 is input vector data sample set 86S (0) shifted to execution units 84 (0) -84 (X). Input vector data sample set 86 (0) for each filter delay tap (ie, filter stage) of the filter vector processing operation according to the filter vector instruction to be executed by VPE 22 (1) to supply ~ 86S (X). ) To 86 (X). All of the shifted input vector data samples 86S comprise the shifted input vector data sample sets 86S (0) -86S (X). The tapped delay line 78 provides input vector data samples 86S (0)-shifted to execution unit inputs 90 (0) -90 (X) of execution units 84 (0) -84 (X) during filter vector processing operations. 86S (X) is supplied. In this way, an intermediate filter result based on the operations performed on the shifted input vector data sample sets 86S (0) -86S (X) for the filter taps of the filter vector processing operation is VPE22 (1). During each processing stage of the filter vector processing operations performed by, there is no need to store, shift, and refetch from the vector data files 82 (0) -82 (X). In this way, the tapped delay line 78 can reduce power consumption and increase processing efficiency for the filter vector processing operation performed by the VPE 22 (1).

  [0086] A processing stage within VPE 22 (1), also referred to as a "vector processing stage", comprises a vector data path associated with circuitry designed to perform a particular task or operation. Vector processing operations may be performed by VPE 22 (1) at several different processing stages. Each processing stage may be executed over one or more clock cycles of VPE 22 (1). As a result, execution of vector processing operations in VPE 22 (1) may take many clock cycles to complete because each processing stage of the vector processing operations may consume one or more clock cycles each. It may take. For example, the processing stage may include fetching input vector data sample sets 86 (0) -86 (X) into the tapped delay line 78 in VPE 22 (1) of FIG. The vector processing stage in VPE 22 (1) may be pipelined.

  [0087] Execution units 84 (0) -84 (X) may include one or more pipeline stages that process fetched input vector data sample sets 86 (0) -86 (X). For example, one pipeline stage in execution units 84 (0) -84 (X) may include an accumulation stage comprised of accumulators configured to perform accumulation operations. As another example, another pipeline stage in execution units 84 (0) -84 (X) may include a multiplication stage comprised of multipliers configured to perform multiplication operations.

  [0088] With continued reference to FIG. 4, execution units 84 (0) -84 (X) receive filter coefficients 92 (0) -92 () stored in global register file 40 of FIG. 2 for filter vector processing operations. Y-1) receive filter coefficients 92, where “Y” may be equal to the number of filter coefficients for the filter vector processing operation. Execution units 84 (0) -84 (X) each during each processing stage of the vector filter processing operation to provide intermediate filter vector data output samples within execution units 84 (0) -84 (X). Received filter coefficients 92 (0), 90 (1),. . . 90 (Y-1) are shifted to shifted input vector data samples 86S (0) to 86S (X), 86S (0), 86S (1),. . . 86S (X) is configured to multiply. The intermediate filter vector data output sample set is accumulated in each of execution units 84 (0) -84 (X) (i.e., the previously accumulated filter output vector data samples are currently accumulated filter outputs. Added to vector data samples). Thus, the shifted input vector data samples 86S (0), 86S (1),. . . Provided by execution units 84 (0) -84 (X) on execution unit outputs 96 (0) -96 (X) on output data flow paths 98 (0) -98 (X), respectively, for each 86S (X). Resulting in the final resulting filter output vector data sample set 94 (0) -94 (X). The resulting filter output vector data sample sets 94 (0) -94 (X) are 94 (0), 94 (1),. . . , And 94 (X), consisting of “X + 1” resulting filter output vector data samples 94. Without having to store and shift the intermediate filter vector data output sample sets generated by execution units 84 (0) -84 (X), the resulting filter output vector data sample sets 94 (0) -94 (X) , Stored back into the respective vector data files 82 (0) -82 (X) for further use and / or processing by the VPE 22 (1).

  [0089] With continued reference to FIG. 4, the tapped delay line 78 is programmable to be controlled in accordance with the vector instruction being processed, as described in more detail below. When the filter vector instruction has not been processed, the tapped delay line 78 is connected to the input data flow path 80 () between the vector data files 82 (0) -82 (X) and the execution units 84 (0) -84 (X). 0) -80 (X) can be programmed. In this embodiment, tapped delay line 78 provides vector data file 82 (0) to provide input vector data sample sets 86S (0) -86S (X) shifted for each filter tap of the filter vector processing operation. ) -82 (X) is configured to load and shift the input vector data sample sets 86 (0) -86 (X) received from. Thus, the shifted input vector data sample sets 86S (0) -86S (X) are supplied to execution units 84 (0) -84 (X) for execution of filter taps of the filter vector processing operation. obtain. Without the tapped delay line 78, to supply again the intermediate input vector data sample set shifted to execution units 84 (0) -84 (X) for the next filter tap of the filter vector processing operation. A separate shifting process would need to be performed, thereby increasing the delay time and consuming additional power. In addition, during the filter vector processing operation, due to the refetch delay of the shifted input vector data sample sets 86S (0) -86S (X) from the vector data files 82 (0) -82 (X), The efficiency of the input data flow paths 80 (0) to 80 (X) and the output data flow paths 98 (0) to 98 (X) are limited.

  [0090] The shifted input vector data sample sets 86S (0) -86S (X) are provided by a tapped delay line 78 located in the execution units 84 (0) -84 (X). Vector processing in execution units 84 (0) -84 (X) is limited only by computer resources, not data flow limitations. This is done without having to wait until the shifted input vector data sample sets 86S (0) -86S (X) are fetched from the vector data files 82 (0) -82 (X). 84 (X) is continuously or substantially continuously busy receiving input vector data sample sets 86S (0) -86S (X) shifted to perform vector processing operations Means.

  [0091] In addition, the filter vector processing operations performed by VPE 22 (1) of FIG. This is because the output accumulation for the intermediate filtering stage in (X) need not be stored in vector data files 82 (0) -82 (X). Storage of the intermediate output vector data sample sets from execution units 84 (0) -84 (X) to vector data files 82 (0) -82 (X) may result in rounding. Thus, when the next intermediate output vector data sample set is fed to execution units 84 (0) -84 (X) for vector processing operations, any rounding errors are propagated and propagated during each multiplication phase of the vector processing operations. Is added. In contrast, in the VPE 22 (1) example of FIG. 4, the intermediate output vector data sample sets computed by execution units 84 (0) -84 (X) are vector data files 82 (0) -82 (X). Need not be memorized. Execution units 84 (0) -84 (X) may accumulate the previous intermediate output vector data sample set with the intermediate output vector data sample set for the next filter delay tap, which is tapped. Because delay line 78 provides input vector data sample sets 86S (0) -86S (X) shifted to execution units 84 (0) -84 (X) during vector processing operations to be processed. Yes, the result is accumulated with the previous vector data sample set for the previous filter delay tap.

  [0092] With continued reference to FIG. 4, the VPE 22 (1) in this embodiment is comprised of a plurality of vector data lanes (labeled VLANE0 100 (0) to VLANEX 100 (X)) for parallel processing. Is done. Each vector data lane 100 (0) -100 (X) includes a vector data file 82 and an execution unit 84 in this embodiment. Taking the vector data lane 100 (0) as an example, the vector data file 82 (0) therein is input data flow path 80 (0) as received by the execution unit 84 (0) for filter vector processing. ) Configured to provide input vector data samples 86 (0). As explained above, the tapped delay line 78 shifts the input vector data sample 86 (0) and executes the shifted input vector data sample 86S (0) for execution of the filter vector processing unit 84 ( 0) is provided in the input data flow path 80 (0). The vector data file 82 (0) is also transferred to the vector data file 82 (0) for the next vector processing operation as necessary or desired according to the current or next vector instruction to be processed by the VPE 22 (1). Receive the resulting filter output vector data sample 94 (0) supplied by execution unit 84 (0) as a result of filter vector processing from output data flow path 98 (0) to be returned and stored. Configured as follows.

  [0093] Any number of vector data lanes 100 (0) -100 (X) may be provided in VPE 22 (1) as needed. The number of vector data lanes 100 (0) -100 (X) provided in VPE 22 (1) provides parallel vector processing vs. further vector data lanes 100 (0) -100 (X) for efficiency purposes. May be based on additional circuit, space, and power consumption tradeoffs. As one non-limiting example, 16 vector data lanes 100 may be provided in the VPE 22 (1), and each vector data lane 100 is parallel to up to 512 bits of vector data in the VPE 22 (1). In order to provide processing, it has a 32-bit data width capability.

  [0094] Continuing to refer to FIG. 4, it is applicable to all vector data files 82 (0) -82 (X), but as an example the vector data file 82 (0) in the vector data lane 100 (0) In use, the vector data file 82 (0) allows one or more samples of the input vector data sample 86 (0) to be stored for vector processing. Depending on the programming of the input vector data sample 86 (0) according to the particular vector instruction being executed by the VPE 22 (1), the width of the input vector data sample 86 (0) is provided. The width of the input data flow path 80 (0) is determined by the number of clock cycles for a given vector instruction to provide input vector data samples 86 (0) of varying widths to the tapped delay line 78 and execution unit 84 (0). Programmable and reprogrammable for each vector instruction including In this way, the vector data lane 100 (0) is programmed and reprogrammed to provide varying width processing of the input vector data samples 86 (0), depending on the type of vector instruction being executed. Can be done.

  [0095] For example, the vector data file 82 (0) is 32 bits wide and may be capable of storing input vector data samples 86 that are also up to 32 bits wide. The input vector data sample 86 (0) may consume the entire width of the vector data file 82 (0) (eg, 32 bits) or with a smaller sample size than the width of the vector data file 82 (0). May be supplied. The size of the input vector data sample 86 (0) is used to program the configuration of the input data flow path 80 (0) for the size of the input vector data sample 86 (0) based on the vector instruction being executed by the VPE 22 (1). Can be configured on the basis. For example, input vector data sample 86 (0) may comprise two separate 16-bit vector data samples for one vector instruction. As another example, input vector data sample 86 (0) is the four 8-bit vector data in vector data file 82 (0) for another vector instruction, as opposed to one 32-bit vector data sample. May have a sample. In another example, input vector data sample 86 (0) may comprise one 32-bit vector data sample. The VPE 22 (1) also has various sizes of results supplied by the execution unit 84 (0) to the vector data file 82 (0) for each vector instruction and / or for each clock cycle of a given vector instruction. The output data flow path 98 (0) for the vector data file 82 (0) can be programmed and reprogrammed to receive the resulting filter output vector data sample 94 (0).

  [0096] Further details and features of VPE 22 (1) in FIG. 4 and shifted to execution units 84 (0) -84 (X) in input data flow paths 80 (0) -80 (X) in this embodiment. Further description of tapped delay line 78 for providing input vector data sample sets 86S (0) -86S (X) will now be described. In this regard, FIG. 5 is a flowchart illustrating an exemplary filter vector processing operation 102 that may be performed in VPE 22 (1) of FIG. 4 utilizing tapped delay line 78 in accordance with an exemplary filter vector instruction. With reference to the examples provided in FIGS. 6A-10, exemplary tasks performed in the filter vector processing operation 102 of FIG. 5 will be described.

[0097] Referring to FIG. 5, the input vector data sample sets 86 (0) -86 (X) to be processed in the filter vector processing operation 102 in accordance with the filter vector instructions include vector data for the filter vector processing operation 102. Fetched from files 82 (0) -82 (X) into input data flow paths 80 (0) -80 (X) (block 104). As described above with respect to VPE 22 (1) of FIG. 4, input vector data sample sets 86 (0) -86 (X) are derived from global register file 40 in execution units 84 (0) -84 (X). The received filter coefficients 92 (0) to 92 (Y-1) are multiplied. For example, FIG. 6A shows filter coefficients 92 (0) -92 (Y-1) (ie, h7-h0) in the global register file 40. FIG. In this example, there are eight filter coefficients 92 stored in the global register file 40 that provide eight filter taps in the filter vector processing operation 102 to be performed. Note that in this example, the filter vector processing operation 102 from the discrete FIR filter 64 equation of FIG. 3 described above is as follows.
y [n] = x [n] * h0 + x [n-1] * h1 +. . . + X [n-7] * h7

  [0098] FIG. 6B illustrates an exemplary stored in vector data files 82 (0) -82 (X) in VPE 22 (1) of FIG. 4 that represents the input signal to be filtered by the filter vector processing operation 102. Input vector data sample sets 86 (0) -86 (X) are shown. In this example, sample X0 is the oldest sample and sample X63 is the most recent sample. In other words, in this example, sample X63 occurs after sample X0 in time. Since each address of the vector data files 82 (0) to 82 (X) is 16 bits wide, the first input vector data sample set 86 (0) stored in the vector data files 82 (0) to 82 (X). ~ 86 (X) spans ADDRESS0 and ADDRESS1, as shown in FIG. 6B. This allows vector data files 82 (0) -82 (X) to support the 32-bit width capability of execution units 84 (0) -84 (X) in the example of VPE 22 (1) of FIG. It becomes possible to provide input vector data samples 86 of bit width. In this regard, a total of 64 total input vector data sample subsets (i.e., X0-X63) each comprising a total of 512 bits and 8 bits wide, comprising the first input vector data sample set 86 (0) -86 (X) Exists. Similarly, ADDRESS2 and ADDRESS3 store another second input vector data sample set 86 (0) -86 (X) stored in vector data files 82 (0) -82 (X). In this example of FIG. 6B, eight addresses (ADDRESS0-7) of each vector data file 82 (0) -82 (X) are shown, and 256 total input vector data samples 86 (ie, X0-X255). Note that this is not limiting.

  [0099] To provide a filter vector processing operation 102 according to programming of vector instructions, depending on the width of the input vector data sample sets 86 (0) -86 (X) involved in the filter vector processing operation 102, FIG. One, some, or all of the vector data lanes 100 (0) -100 (X) in VPE 22 (1) may be utilized. If the entire width of the vector data files 82 (0) -82 (X) is required, all vector data lanes 100 (0) -100 (X) may be utilized for the filter vector processing operation 102. Note that the filter vector processing operation 102 may only require a subset of the vector data lanes 100 (0) -100 (X) that may be utilized for the filter vector processing operation 102. This may be because the width of the input vector data sample set 86 (0) -86 (X) is smaller than the width of all vector data files 82 (0) -82 (X), where the filter vector It may be desirable to utilize additional vector data lanes 100 for other vector processing operations to be performed in parallel with processing operations 102. For the purpose of illustrating the current example, the input vector data sample set 86 (0) -86 (X) utilized in the filter vector processing operation 102 requires all vector data lanes 100 (0) -100 (X). Assume that.

  [00100] Referring back to FIG. 5, the fetched input vector data sample set 86 () is loaded into the tapped delay line 78 as the current input vector data sample set 86 (0) -86 (X). 0) -86 (X) are supplied from the vector data files 82 (0) -82 (X) to the input data flow paths 80 (0) -80 (X) (block 106). The input vector data sample sets 86 (0) -86 (X) are to be processed by the execution units 84 (0) -84 (X) for the filter vector processing operation 102. 86 (X) is loaded into the delay line 78 (0) with the primary tap. The input vector data sample sets 86 (0) -86 (X) loaded into the primary tapped delay line 78 (0) are not shifted due to the first filter tap operation of the filter vector processing operation 102. However, as described above and described in further detail below with respect to FIG. 7, the purpose of the tapped delay line 78 is to execute unit 84 (0) for the next filter tap operation of the filter vector processing operation 102. Providing a shift of the input vector data sample sets 86 (0) -86 (X) to provide input vector data sample sets 86S (0) -86S (X) shifted to .about.84 (X). is there. During each processing stage of the filter vector processing operation 102 performed by the execution units 84 (0) -84 (X), the input vector data sample set 86S (0) shifted to the execution units 84 (0) -84 (X). ) To 86S (X), the input vector data sample 86 is shifted in the primary tapped delay line 78 (0). In this way, the input vector data sample sets 86 (0) to 86 (X) are stored and shifted within the vector data files 82 (0) to 82 (X) for each filter tap operation of the filter vector processing operation 102. , And does not need to be refetched.

  [00101] If the optional shadow-tapped delay line 78 (1) is provided in the VPE 22 (1), the next input vector data sample sets 86N (0) -86N (X) are also stored in the vector data file 82 (0). ) -82 (X) can be loaded into the shadow tapped delay line 78 (1). As described in more detail below with respect to FIG. 7, the next input vector data sample set 86N (0) -86N (X) is the same as the shifted input vector data sample set 86S (0) -86S (X). To be at least partly shifted into the primary tapped delay line 78 (0) during the filter vector processing operation 102. In this way, the primary tapped delay line 78 (0) allows the next input vector data sample set 86N (0) -86N (X) to be executed for the filter vector processing operation 102 to be stored in the vector data file 82 ( If execution units 84 (0) -84 (X) had to wait from 0) -82 (X) to fetch into primary tapped delay line 78 (0), the delay incurred in some cases Without fetching, it is possible to have the shifted input vector data sample sets 86S (0) -86S (X) available during the filter vector processing operation 102.

  [00102] In this regard, FIG. 7 illustrates an exemplary tapped delay line 78 that may be provided within the VPE 22 (1) of FIG. In this embodiment, the tapped delay line 78 includes a shadow tapped delay line 78 (1) and a primary tapped delay line 78 (0). The primary tapped delay line 78 (0) in this example is comprised of a plurality of 8-bit primary pipeline registers 120 to allow the resolution of the input vector data sample 86 to drop to 8 bits long. The first input vector data sample sets 86 (0) -86 (X) processed by the execution units 84 (0) -84 (X) are used in the filter vector processing operation 102 as described with respect to FIG. 9A below. Due to the first filter tap, it is not shifted in this example. When execution units 84 (0) -84 (X) process the next filter tap for filter vector processing operation 102, input vector data sample set 86 (0) stored in primary tapped delay line 78 (0). ) To 86 (X), the input vector data samples 86 become the shifted input vector data sample sets 86S (0) to 86S (X), as shown by the arrows in FIG. Shifted in pipeline registers 120 (0) -120 (4X + 3). In this way, execution units 84 (0) -84 (X) do not need to store and shift input vector data sample sets 86 (0) -86 (X) and vector data files 82 (0)- Receiving shifted input vector data sample sets 86S (0) -86S (X) without refetching the input vector data sample sets 86S (0) -86S (X) shifted from 82 (X); By performing these filter vector processing operations 102, it is fully utilized.

  [00103] In this embodiment, primary pipeline registers 120 (0) -120 (4X + 3) are collectively the width of vector data files 82 (0) -82 (X) in FIG. In the example of a vector data file 82 (0) -82 (X) having a width of “X” equal to 15 and 512 bits, it provides a total width of 512 bits (ie, 64 registers × 8 bits each) Therefore, there are 64 total primary pipeline registers 120 (0) -120 (63), each 8 bits wide. Accordingly, in this example, the primary tapped delay line 78 (0) can store the entire width of one input vector data sample set 86 (0) -86 (X). In this example, by providing 8-bit wide primary pipeline registers 120 (0) to 120 (4X + 3), the input vector data sample sets 86 (0) to 86 (X) are converted into the primary pipeline registers 120 (0). ~ 120 (4X + 3) may be shifted down to an 8-bit vector data sample size for 8-bit filter vector processing operations. For example, if a larger input vector data sample 86 size, such as a 16-bit or 32-bit sample, is desired for the filter vector processing operation, the input vector data sample set 86 (0) -86 (X) Pipeline registers 120 (0) -120 (4X + 3) may be shifted by two primary pipeline registers 120 at a time.

  [00104] With continued reference to FIG. 7, a shadow tapped delay line 78 (1) is also provided within the tapped delay line 78. The shadow tapped delay line 78 (1) latches the next input vector data sample set 86N (0) -86N (X) from the vector data files 82 (0) -82 (X) for the next vector processing operation. Or it can be used to transport. As each filter tap for filter vector processing operation 102 is performed by execution units 84 (0) -84 (X), the next input from the next input vector data sample set 86N (0) -86N (X). Vector data sample 86N is shifted from shadow tapped delay line 78 (1) into primary tapped delay line 78 (0). The shadow tapped delay line 78 (1) also allows a plurality of 8-bit lengths to allow the resolution of the input vector data sample 86 to fall to 8-bit length, similar to the primary tapped delay line 78 (0). It consists of a shadow pipeline register 122. The shadow pipeline registers 122 (0) to 122 (4X + 3) provided in the delay line 78 (1) with shadow tap, such as the primary pipeline registers 120 (0) to 120 (4X + 3), are collectively shown in this example. Is the width of the vector data files 82 (0) to 82 (X), which is 512 bits. Therefore, the shadow pipeline registers 122 (0) -122 (4X + 3) of the delay line 78 (1) with shadow tap also store the entire width of one input vector data sample set 86 (0) -86 (X). Is possible. Therefore, in this embodiment, the number of shadow pipeline registers 122 (0) to 122 (4X + 3) included in the primary tapped delay line 78 (0) is a total of 16 in this example (ie, X = 15). This is four times the number of vector data lanes 100 (0) to 100 (X). Thus, the number of shadow pipeline registers 122 is also a total of 64 in this example for a total of 512 bits (ie, 64 registers × 8 bits each). As described above with respect to the primary tapped delay line 78 (0), in this example the next input vector data sample is provided by providing 8-bit wide shadow pipeline registers 122 (0) -122 (4X + 3). The sets 86N (0) -86N (X) may be shifted down to an 8-bit vector data sample size for 8-bit filter vector processing operations.

  [00105] FIG. 8 shows selected primary pipeline registers 120 and shadow pipeline registers 122 present in primary tapped delay line 78 (0) and shadow tapped delay line 78 (1) of FIG. FIG. FIG. 8 is provided to facilitate describing an example of shifting input vector data samples 86 between primary pipeline register 120 and shadow pipeline register 122. As explained above, the input vector data samples 86 are also primary in the primary tapped delay line 78 (0) and shadow tapped delay line 78 (1) and from the shadow tapped delay line 78 (1). It can be shifted to tapped delay line 78 (0). Pipeline registers 120 and 122 are each 8 bits wide in this example to allow shifting in 8-bit resolution when input vector data samples 86 are required. This is explained in more detail below. Primary tapped delay line 78 (0) and shadow tapped delay line 78 (1) are also 16-bit and 32-bit shifts in the resolution of input vector data samples 86, as will also be described in more detail below. Can be executed.

[00106] In this regard, FIG. 8 illustrates a primary pipeline register 120 (4X + 3) that forms a storage register for input vector data samples 86S (X) in the primary tapped delay line 78 (0) of FIG. , 120 (2X + 1), 120 (4X + 2), and 120 (2X). Primary pipeline registers 120 (4X + 3) and 120 (4X + 2) are registers B ₃₁ and B ₃₀ in the primary tapped delay line 78 (0) of FIG. 7, respectively. Primary pipeline registers 120 (2X + 1) and 120 (2X) are registers A ₃₁ and A ₃₀ in delay line 78 (0) with a primary tap in FIG. 7, respectively. As shown in FIG. 7, primary pipeline registers 120 (4X + 3) and 120 (4X + 2) for registers B ₃₁ and B ₃₀ are adjacent shadow pipeline registers in shadow tapped delay line 78 (1). An input vector data sample 86 shifted from 122 is configured to be received. Thus, in the example of FIG. 8, respectively, the shadow pipeline register 122 for register A _'0 and A' ₁ (0) and 122 (1), the primary pipeline register 120 for B ₃₁ and B ₃₀ ( 4X + 3) and 120 (4X + 2) are shown configured to shift the input vector data samples 86. Similarly, in the example of FIG. 8, primary pipeline registers 120 (2X + 3) and 120 (2X + 2) for registers B ₁ and B ₀ in primary tapped delay line 78 (0), respectively, are registered in register A _31. , And A ₃₀ are shown as being configured to shift input vector data samples 86 into adjacent primary pipeline registers 120 (2X + 1) and 120 (2X). An exemplary shift of input vector data samples 86 between these registers will now be described.

  [00107] With continued reference to FIG. 8, in the shift of FIG. 4 and the input vector data samples 86, a new set of input vector data samples 86 (0) -86 (X) from the vector data files 82 (0) -82 (X). In order to provide the flexibility to configure the primary pipeline register 120 and the shadow pipeline register 122 to load the input vector data sample selector to each of the primary pipeline register 120 and the shadow pipeline register 122. Associated. In this regard, the input vector data sample selector 124 (into the vector data loaded or shifted into the primary pipeline registers 120 (0) to 120 (4X + 3) in the primary tapped delay line 78 (0), respectively. 0) -124 (4X + 3) are provided. Input vector data sample selectors 126 (0) -126 for vector data loaded or shifted into shadow pipeline registers 122 (0) -122 (4X + 3) in delay line 78 (1) with shadow tap, respectively. (4X + 3) is provided. Input vector data sample selectors 124 (0) -124 (4X + 3) and input vector data sample selectors 126 (0) -126 (4X + 3) are each multiplexers in this example. As described in more detail below, the input vector data sample selectors 124 (0) -124 (4X + 3), 126 (0) -126 (4X + 3) are respectively primary pipeline registers 120 (0) -120. Data width shift control input 125 may be controlled to select input vector data to be loaded or shifted into (4X + 3) and shadow pipeline registers 122 (0) -122 (4X + 3).

[00108] In Figure 8, respectively, corresponding to the register _{B 31, B 30, A 31} , and A _30, respectively, the primary pipeline register 120 (4X + 3), 120 (4X + 2), 120 (2X + 1), 120 (2X Note that only the input vector data sample selectors 124 (4X + 3), 124 (4X + 2), 124 (2X + 1), 124 (2X) are shown. In FIG. 8, for pipeline registers 122 (1), 122 (0), 120 (2X + 3), 120 (2X + 2) respectively corresponding to registers A ′ ₁ , A ′ ₀ , B ₁ , and B ₀ . Thus, only the input vector data sample selectors 126 (1), 126 (0), 124 (2X + 3), 124 (2X + 2) are shown.

  [00109] Referring still to FIG. 8, for vector processing operations, if new input vector data is to be loaded into the primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1), The data width shift control input 125 is input to the input vector data sample selectors 124 (4X + 3), 124 (4X + 2), 124 (2X + 1), and 124 (2X), to the load data flow path 133 (4X + 3), 133 (4X + 2), and 133 ( 2X + 1), 133 (2X) may be selected by VPE 22 (1) of FIG. When the load data flow path 133 (4X + 3), 133 (4X + 2), 133 (2X + 1), 133 (2X) is selected, the input vector data from the vector data files 82 (0) to 82 (X) is transferred to the primary pipeline register 120 ( 4X + 3), 120 (4X + 2), 120 (2X + 1), 120 (2X). Loading input vector data from vector data files 82 (0) -82 (X) may be performed on a new or next vector instruction to be processed by VPE 22 (1) as an example. Similarly, data width shift control input 125 is also input to input vector data sample selectors 126 (1), 124 (2X + 3), 126 (0), 124 (2X + 2) to input data flow paths 135 (1), 133 (2X + 3). ), 135 (0), 133 (2X + 2) may be configured by VPE 22 (1) of FIG. When the load data flow path 135 (1), 133 (2X + 3), 135 (0), 133 (2X + 2) is selected, the input vector data from the vector data files 82 (0) to 82 (X) is stored in the pipeline register 122 (1 ), 120 (2X + 3), 124 (0), 120 (2X + 2).

  [00110] Continuing with FIG. 8, when the vector data stored in the primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1) needs to be shifted for vector processing operations. , The data width shift control input 125 is input to an input vector data sample selector 124 (4X + 3), 124 (4X + 2), 124 (2X + 1), 124 (2X) to an input data flow path 137 (4X + 3) for shifting vector data samples. ) 137 (4X + 2), 137 (2X + 1), 137 (2X) may be selected by VPE 22 (1) of FIG. Data width shift control input 125 also provides input vector data sample selectors 126 (1), 124 (2X + 3), 126 (0), 124 (2X + 2) to input data flow path 139 (1 ) 137 (2X + 3), 139 (0), and 137 (2X + 2). As shown therein, input vector data sample selectors 124 (4X + 3), 124 (4X + 2), 124 (2X + 1), 124 (2X) and input vector data sample selectors 126 (1), 124 (2X + 3) , 126 (0), 124 (2X + 2) each allow the vector data to be shifted to another register, respectively, output data flow path 141 (4X + 3), 141 (4X + 2), 141 (2X + 1), 141 (2X) and 143 (1), 141 (2X + 3), 143 (0), 124 (2X + 2). The output data flow path shown in FIG. 8 is a part of the output data flow paths 141 (0) to 141 (4X + 3) and 143 (0) to 143 (4X + 3), which are shown next as a whole. Input vector data sample selectors 124 (0) to 124 (4X + 3) in delay line 78 (0) with delay and input vector data sample selectors 126 (0) to 126 (4X + 3) in delay line 78 (1) with shadow tap. Included for).

[00111] As an example, during the shifting of 8-bit vector data, input vector data sample selectors 124 (4X + 3), 124 (4X + 2), 124 (2X + 1), 124 (2X) and input vector data sample selector 126 (1) , 124 (2X + 3), 126 (0), 124 (2X + 2) are input data flow paths 137 (4X + 3), 137 (4X + 2), 137 (2X + 1), 137 (2X), 139 (1), 137 (2X + 3), respectively. ) 139 (0), 137 (2X + 2). In this connection, by way of example, the vector data in primary pipeline register 120 (2X + 1) (ie, A ₃₁ ) is represented by primary pipeline register 120 (2X) (ie, A ₃₀ ) as shown in FIG. Shifted on the output data flow path 141 (2X + 1). The vector data in primary pipeline register 120 (4X + 3) (ie, B ₃₁ ) is output to primary pipeline register 120 (4X + 2) (ie, B ₃₀ ) as shown in FIG. 8, and output data flow path 141 (4X + 3). ) Shifted on. The vector data in shadow pipeline register 122 (0) (ie, A ′ ₀ ) is output to primary pipeline register 120 (4X + 3) (ie, B ₃₁ ) as shown in FIG. 0) shifted up. The vector data in the primary pipeline register 120 (2X + 3) (ie, B ₁ ) is output to the primary pipeline register 120 (4X + 2) (ie, B ₃₀ ) as shown in FIG. 8 in the output data flow path 141 (2X + 3). ) Shifted on. Shadow pipeline register 122 (1) (i.e., A _'1) vector data in, as shown in FIG. 8, the shadow pipeline register 122 (0) (i.e., A' ₀₎ output to the data flow path 143 (1) Shifted up. The vector data in primary pipeline register 120 (2X + 2) (ie, B ₀ ) is output to primary pipeline register 120 (2X + 1) (ie, A ₃₁ ) as shown in FIG. ) Shifted on.

[00112] Still referring to FIG. 8, during the shifting of 16-bit vector data, input vector data sample selectors 124 (4X + 3), 124 (4X + 2), 124 (2X + 1), 124 (2X) and input vector data sample selectors 126 (1), 124 (2X + 3), 126 (0), 124 (2X + 2) are input data flow paths 145 (4X + 3), 145 (4X + 2), 145 (2X + 1), 145 (2X), 147 (1), respectively. 145 (2X + 3), 147 (0), and 145 (2X + 2). In this context, by way of example, the vector data in primary pipeline register 120 (2X + 2) (ie, B ₀ ) is represented by primary pipeline register 120 (2X) (ie, A ₃₀ ) as shown in FIG. Shifted on the output data flow path 141 (2X + 2). The vector data in shadow pipeline register 122 (0) (ie, A ′ ₀ ) is transferred to primary pipeline register 120 (4X + 2) (ie, B ₃₀ ) as shown in FIG. 0) shifted up. The vector data in primary pipeline register 120 (2X + 3) (ie, B ₁ ) is output to primary pipeline register 120 (2X + 1) (ie, A ₃₁ ) as shown in FIG. 8, in output data flow path 141 (2X + 3). ) Shifted on. The vector data in the shadow pipeline register 122 (1) (ie, A ′ ₁ ) is transferred to the primary pipeline register 120 (4X + 3) (ie, B ₃₁ ) as shown in FIG. 1) Shifted up.

  [00113] When 32-bit vector data shift is desired in the primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1), the primary pipeline registers 120 (0) -120 (4X + 3) and the shadow pipeline Vector data stored in registers 122 (0) -122 (4X + 3) can be shifted in a shift operation of two 16-bit vector data, if necessary.

[00114] In Figure 7, the primary pipeline register 120 for register B ₃₁ and B ₃₀ (4X + 3) and 120 (4X + 2), as well as the primary pipeline register 120 for register A ₃₁ and A ₃₀ (2X + 1) and 120 Note that (2X) are logically related to each other for shifted input vector data samples 86S (X), but are not physically adjacent to each other as shown in FIG. This arrangement is due to the storage pattern of the input vector data sample sets 86 (0) -86 (X) in the vector data files 82 (0) -82 (X), as shown in FIG. 6B. Provided in the examples. Similarly, as shown in FIG. 6B, the input vector data sample sets 86 (0) -86 (X) stored in the vector data files 82 (0) -82 (X) straddle ADDRESS0 and ADDRESS1. It should be noted, however, that the disclosure herein is not limited to this storage pattern of input vector sample sets 86 (0) -86 (X) in vector data files 82 (0) -82 (X).

  [00115] Further, with respect to FIG. 8, tapped delay lines 78 (0), 78 (1) are programmable for tapped delay lines 78 (0), 78 (1) according to vector instructions to be executed. In the input data flow paths 80 (0) to 80 (X) between the vector data files 82 (0) to 82 (X) and the execution units 84 (0) to 84 (X) based on the various input data path configurations Can be configured to be selectively provided or not provided. For example, the vector instructions are not filter vector processing instructions and / or in some cases tapped delay lines 78 (0), 78 (1) to shift the input vector data sample sets 86 (0) -86 (X). Are not required, the tapped delay lines 78 (0), 78 (1) may be configured not to latch the input vector data sample sets 86 (0) -86 (X). The input vector data sample sets 86 (0) -86 (X) are bypassed from the primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1), respectively, so that each execution unit 84 (0). To 84 (X) may be supplied from the vector data files 82 (0) to 82 (X). This programmable data path configuration further provides a primary tapped delay line 78 (0) and a shadow tapped delay line 78 (1) in the input data flow paths 80 (0) -80 (X), or It becomes possible not to be provided. Primary tapped delay line 78 (0) and shadow tapped delay line 78 (1) are provided in the input data flow paths 80 (0) -80 (X) for each vector instruction as required, or It can be programmed not to be provided.

  [00116] FIG. 9A is loaded from the vector data files 82 (0) -82 (X) into the primary tapped delay line 78 (0) during the first clock cycle (CYCLE0) of the filter vector processing instruction. The input vector data sample sets 86 (0) to 86 (X) are shown. The primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1) are shown in simplified form from FIG. A global register file 40 is also shown. The first input vector data sample set 86 (0) -86 (X) is loaded into the primary tapped delay line 78 (0) as input vector data samples X0-X63. For example, the first input vector data sample set 86 (in the primary tapped delay line 78 (0) (and also in the shadow tapped delay line 78 (1), as will be described in more detail below)). Special vector instructions may be supported to load 0) -86 (X). This initial input vector data sample set 86 (0) -86 (X) was stored in ADDRESS0 and ADDRESS1 in vector data files 82 (0) -82 (X) as shown in FIG. 6B. Due to the storage pattern of vector data files 82 (0) -82 (X) in VPE 22 (1) of FIG. 4 for this example, in this example, X0, X1, X32, and X33 are the first inputs. Note that the vector data sample 86 (0) is formed. Other input vector data samples 86 are similarly formed as shown in FIG. 9A (eg, 86 (1), 86 (2),... 86 (X)). Other patterns may be provided to group input vector data samples 86 together to form input vector data sample sets 86 (0) -86 (X).

  [00117] FIG. 9B shows the next input vector data sample set 86N (0)-loaded into the shadow tapped delay line 78 (1) during the second clock cycle (CYCLE1) of the filter vector processing instruction. 86N (X) is shown. To set up the execution of the filtering operation, the first input vector data sample set 86 (0) -86 (X) from the vector data files 82 (0) -82 (X) is represented by the primary tapped delay line 78 (0 ) Is loaded into the shadow tapped delay line 78 (1). The next input vector data sample set 86N (0) -86N (X) is loaded. This next input vector data sample set 86N (0) -86N (X) is loaded into the delay line 78 (1) with shadow tap as input vector data samples X64-X127. This next input vector data sample set 86N (0) -86N (X) was stored in ADDRESS2 and ADDRESS3 in vector data files 82 (0) -82 (X) as shown in FIG. 6B. Due to the storage pattern of vector data files 82 (0) -82 (X) in VPE 22 (1) of FIG. 4 for this example, in this example, X64, X65, X96, and X97 are the first inputs. Note that the vector data sample 86 (0) is formed. Other patterns may be provided to group input vector data samples 86 together to form input vector data sample sets 86 (0) -86 (X). The first filter coefficient 92 (0) from global register file 40 is also in register ("C") to execution units 84 (0) -84 (X) of FIG. 9B for use in filter vector processing operation 102. Shown as provided.

  [00118] Referring back to FIG. 7, when the input vector data sample 86 is shifted within the primary tapped delay line 78 (0) during each processing stage of the filter vector processing operation 102, the shadow pipeline register 122 The next input vector data sample 86N stored in is also shifted in the shadow pipeline register 122 of the shadow tapped delay line 78 (1). The input vector data samples 86 stored in the first shadow pipeline register 122 (0) of FIG. 7 are stored in the last primary pipeline register 120 (4X + 3) of the primary tapped delay line 78 (0) during each shift. Shifted in. Thus, in this way, when the processing stage of filter vector processing operation 102 proceeds in execution units 84 (0) -84 (X), the next input initially stored in shadow tapped delay line 78 (1). At least a portion of the vector data sample sets 86N (0) -86N (X) is provided to the execution units 84 (0) -84 (X) for processing so that the primary tapped delay line 78 (0) Shifted in. The number of shifts depends in this example on the number of filter taps provided in the filter vector processing operation 102. Input vector data sample sets 86 (0) -86 () fetched from the vector data files 82 (0) -82 (X) into the primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1). If the number of input vector data samples 86 in X) is greater than the number of filter taps in the filter vector processing operation 102, the execution units 84 (0) -84 (X) may use any additional input vector data sample sets 86. The filter vector processing operation 102 can be performed without refetching (0) -86 (X) from the vector data files 82 (0) -82 (X). However, the number of filter taps in the filter vector processing operation 102 is fetched from the vector data files 82 (0) -82 (X) into the delay line 78 (0) with the primary tap and the delay line 78 (1) with the shadow tap. If the input vector data sample 86 is larger than the input vector data sample 86 in the input vector data sample set 86 (0) -86 (X), the additional input vector data sample set 86 (0) -86 as part of the filter vector processing operation 102. (X) may be fetched from the vector data files 82 (0) -82 (X). After the filter vector processing operation 102 is completed for the shifted input vector data sample sets 86S (0) -86S (X), an unprocessed input vector in the tapped delay lines 78 (0), 78 (1). If data sample 86S is present, execution units 84 (0) -84 (X) are then used as shifted input vector data sample sets 86S (0) -86S (X) for the next filter vector processing operation. The previous next input vector data sample set 86N (0) -86N (X) stored in the primary tapped delay line 78 (0) may be supplied.

  [00119] Another exemplary rationale for providing a shadow tapped delay line 78 (1) is as follows. If the current filter vector processing operation 102 requires more input vector data samples 86 than can be provided in the width of the vector data lanes 100 (0) -100 (X), the shadow tapped delay line 78 (1) Additional input vector data sample sets 86 (0) -86 (X) loaded therein are available to execution units 84 (0) -84 (X) during the filter vector processing operation 102 without delay. As the filter vector processing operation 102 proceeds through the currently shifted input vector data sample sets 86S (0) -86S (X), as described above, in the shadow tapped delay line 78 (1). The further next input vector data sample set 86N (0) -86N (X) loaded into is shifted into the primary tapped delay line 78 (0). Thus, in this way, the next input vector data sample sets 86N (0) -86N (X) for use in vector processing by the execution units 84 (0) -84 (X) are available without delay. . A single fetched input vector data sample set 86 (0) -86 (X) wide of vector data files 82 (0) -82 (X) is sufficient to perform the entire filter vector processing operation 102. Regardless of whether or not there is, execution units 84 (0)-84 (X) can continue to be fully utilized during the filter vector processing operation 102.

  [00120] The first input vector data sample set 86N (0) -86N (X) and the next input vector data sample set 86N (0) -86N (X) are respectively connected to the primary tapped delay line 78 (0) and After loading into the shadow tapped delay line 78 (1), the first input vector data sample set 86 (0) -86 (X) supplied to the primary tapped delay line 78 (0) is the filter vector. To be processed in the first processing stage of processing operation 102, it is supplied to each execution unit 84 (0) -84 (X) (block 108 of FIG. 5). After the first input vector data sample sets 86 (0) -86 (X) have been processed by execution units 84 (0) -84 (X), the first input vector data sample sets 86 (0) -86 (X) In the primary tapped delay line 78 (0) to become a shifted input vector data sample set 86S (0) -86S (X) to be processed by execution units 84 (0) -84 (X). Shifted by. As shown in VPE 22 (1) of FIG. 4, the shifted input vector data sample 86S (0) is provided to execution unit 84 (0), and the shifted input vector data sample 86S (1) is executed by the execution unit. 84 (1), and so on.

  [00121] Next, execution units 84 (0) -84 (X) perform a filter vector processing operation 102 (block 110 of FIG. 5). More specifically, execution units 84 (0) -84 (X), in this example, follow the operation: y [n] = x [n−7] * h7, the first set of input vector data samples in the first iteration. 86 (0) -86 (X) is multiplied by the current filter coefficient 92 (0), where x [n-7] is the resulting filter output vector data sample set 94 (0) -94 (X ) Is the first input vector data sample set 86 (0) -86 (X). In the next iteration of the filter vector processing operation 102 (block 110 of FIG. 5), the next shifted input vector data sample sets 86S (0) -86S (X) for the filter vector processing operation 102 are stored in the current filter. The coefficients 92 (1) to 92 (Y-1) are multiplied. Execution units 84 (0) -84 (X) provide the resulting filter output vector data sample set 94 (0) -94 (X) to provide a new previous filter output vector data sample set 94 (0) -94 (X). 94 (0) -94 (X) accumulates with the resulting filter output vector data sample sets 94 (0) -94 (X) before being calculated by execution units 84 (0) -84 (X) (Block 112 in FIG. 5). In the first processing stage of the filter vector processing operation 102, there is no previous resulting filter output vector data sample set.

  [00122] When all processing stages of the filter vector processing operation 102 are complete (block 114 in FIG. 5), the output data flow path 98 is supplied and stored in the vector data files 82 (0) -82 (X). The resulting filter output vector data sample set 94 (0) prior to accumulation as the resulting filter output vector data sample set 94 (0) -94 (X) in (0) -98 (X). ) To 94 (X) are supplied (block 116 in FIG. 5). If all processing stages of the filter vector processing operation 102 have not been completed (block 114 of FIG. 5), the filtered vector processing operation 102 receives the next shifted input vector data sample set 86S (0) -86S (X). To provide, samples stored in tapped delay lines 78 (0) and 78 (1) are shifted in tapped delay lines 78 (0), 78 (1) (block 118 in FIG. 5). The shifted input vector data sample sets 86S (0) -86S (X) are intermediate to be accumulated with the previous resulting filter output vector data sample sets until the filter vector processing operation 102 is complete. The result is then supplied to compute the resulting filter output vector data sample set. Shifting the input vector data samples 86 to provide input vector data sample sets 86S (0) -86S (X) shifted into tapped delay lines 78 (0), 78 (1) is shown in FIG. With respect to details above. The final accumulation of the intermediate results provided by the execution units 84 (0) -84 (X) to the filter vector processing operation 102 is performed as shown in FIG. 4 by execution units 84 (0) -84 (X ) As the resulting filter output vector data sample sets 94 (0) -94 (X).

  [00123] FIG. 9C is the next shifted input vector data sample set 86S (0) -86S (X) for the next filtering operation y [n] = x [n-6] * h6. 6 shows the contents of the tapped delay line 78 when the input vector data sample sets 86 (0) -86 (X) are shifted in the second processing stage of the filter vector processing operation 102. FIG. The shifted input vector data sample sets 86S (0) to 86S (X) in the primary tapped delay line 78 (0) are primary according to the shift width of the input vector data samples defined by the vector instruction being executed. Shifted in pipeline registers 120 (0) -120 (4X + 3). For example, as shown in FIG. 9C, sample X2 is shifted within shifted input vector data sample 86S (0). New shifted input vector data sample sets 86S (0) -86S (X) are sent to execution units 84 (0) -84 (X) for execution for the next filter tap of filter vector processing operation 102. Supplied. The filter coefficient 92 supplied to the execution units 84 (0) to 84 (X) is also the next filter coefficient 92 which is “h6” in this example.

  [00124] With continued reference to FIG. 5, the primary tapped delay line 78 (0) in the execution units 84 (0) -84 (X) to be multiplied by the next filter coefficient 92 (block 110 of FIG. 5). The process repeats by providing input vector data sample sets 86S (0) -86S (X) shifted from (block 108 in FIG. 5). The resulting filter output vector data sample sets 94 (0) -94 (X) are accumulated with the previous resulting filter output vector data sample sets 94 (0) -94 (X) (block of FIG. 5). 112). FIG. 9D shows the state of the input vector data sample 86 present in the tapped delay lines 78 (0), 78 (1) during the final processing stage of the exemplary filter vector processing operation 102. In this example shown in FIG. 9D, eight filter taps in the filter vector processing operation 102 due to the filter coefficients 92 “h7” to “h0” (ie, 92 (0) to 92 (Y−1)). (Y) was present. As shown in FIG. 9D, “h0” is the last filter coefficient 92 in the filter vector processing operation 102. The shifted input vector data sample sets 86S (0) -86S (X) have been shifted 7 times (one less than the number of filter taps), so that the last 8 for the filter vector processing operation 102 In the second processing stage, the input vector data sample X39 is stored in the shifted input vector data sample 86S (0) in the primary tapped delay line 78 (0).

  [00125] The example of the filter vector processing operation 102 described above utilizes each of the vector data lanes 100 (0) -100 (X) in the VPE 22 (1) to provide the filter vector processing operation 102, Note that it is not necessary. The filter vector processing operation 102 may only require a subset of the vector data lanes 100 (0) -100 (X) to be utilized for the filter vector processing operation 102. For example, the width of the input vector data sample sets 86 (0) -86 (X) may be smaller than the width of all vector data files 82 (0) -82 (X), where the filter vector processing operation 102 It is desirable to utilize additional vector data lanes 100 for other vector processing operations to be performed in parallel. In this scenario, the tapped delay lines 78 (0), 78 (1) of FIG. 7 will cause the shifted input vector data in the vector data lane 100 before reaching the last vector data lane 100 (X). As sample sets 86S (0) to 86S (X), the next input vector data sample sets 86N (0) to 86N (X) are transferred from the delay line with shadow tap 78 (1) to the delay line with primary tap 78 (0). It may need to be modified to shift.

  [00126] FIG. 10 illustrates that the exemplary eight tap filter vector processing stages in the above example are y [n] = x [n] * h0 + x [n-1] * h1 +. . . The contents of the accumulators in execution units 84 (0) -84 (X) in VPE 22 (1) of FIG. 4 after complete execution according to + x [n-7] * h7 (ie, the resulting FIG. 6 is a schematic diagram of a filter output vector data sample 94). In this example, each execution unit 84 (0) -84 (X) has four accumulators arranged in parallel for each of the vector data lanes 100 (0) -100 (X), so the accumulator Acc0 ~ Acc3 is shown in FIG. The accumulated resulting output vector data samples are then stored in the entire resulting filtered output vector data sample set 94 (0) -94 (X) to be stored for further analysis and / or processing. As such, vector data files 82 (0) -82 (X) may be supplied on output data flow paths 98 (0) -98 (X). If necessary, move the resulting row of filter output vector data sample sets 94 (0) -94 (X) from the vector data files 82 (0) -82 (X) to the vector unit data memory 32 of FIG. Therefore, special vector instructions may be supported by VPE 22 (1).

  [00127] Other types of vector processing operations other than the filter vector processing operation 102 are also the same or similar tapped delay lines as the tapped delay line 78 provided in the VPE 22 (1) of FIG. 4 described above. The processing efficiency in VPE by using 78 can be enjoyed. For example, another special vector processing operation that involves shifting the input vector data sample set 86 in the VPE is a correlation / covariance vector processing operation (referred to herein as a “correlation vector processing operation”). As an example, a direct spread spectrum code (DSSC) (ie, a chip sequence) for demodulating a user signal in a CDMA system to provide good separation between the user signal and other users' signals in a CDMA system It may be desirable to use vector processing to provide a correlation operation to choose. Signal separation is performed by correlating the received signal with a locally generated chip sequence of the desired user. If the signal matches the desired user's chip sequence, the correlation function is high and the CDMA system can extract the signal. If the desired user's chip sequence has little or no part in common with the signal, the correlation should be as close to zero as possible (thus removing the signal), which is called cross-correlation. If the chip sequence is correlated with the signal at any non-zero time offset, the correlation should be as close to zero as possible. This is called autocorrelation and is used to reject multipath interference.

  [00128] However, correlation operations may be difficult to parallelize in a vector processor due to the special data flow path provided in the vector processor. When the input vector data sample set representing the signal to be correlated is shifted between delay taps, the input vector data sample set is refetched from the vector data file, thus increasing power consumption and reducing throughput. In order to minimize refetching of input vector data sample sets from memory, the data flow path may be configured to provide as many multipliers as delay taps for efficient parallel processing. is there. However, other vector processing operations may require fewer multipliers, leading to inefficient scaling and underutilization of the multipliers in the data flow path. In order to provide scalability, if the number of multipliers is reduced to be less than the number of delay taps, the memory can be used to obtain the same set of input vector data samples for the various phases of the correlation process. The need for many refetches limits parallelism.

  [00129] In this regard, FIG. 11 is a schematic diagram of another exemplary VPE 22 (2) that may be provided as the VPE 22 of FIG. As described in more detail below, the VPE 22 (2) of FIG. 11 eliminates or reduces refetching of vector data samples, reducing power consumption, and the precision correlation vector processing operation in VPE 22 (2). Configured to provide. Precision correlation vector processing operations are provided at VPE22 (2) compared to correlation vector processing operations that require the storage of intermediate results, which requires refetching of vector data samples, resulting in increased power consumption. Can be done. In order to eliminate or minimize refetching of input vector data samples from the vector data file to reduce power consumption and improve processing efficiency, the tapped delay line 78 included in VPE 22 (1) of FIG. Input data flow path 80 (0) between vector data files 82 (0) -82 (X) in VPE 22 (2) and execution units 84 (0) -84 (X) (also labeled “EU”). ~ 80 (X). “X” +1 is the maximum number of parallel input data lanes provided in VPE 22 (2) for processing vector data samples in this example. As previously described above, tapped delay line 78 is used to input vector data sample sets 86 (0) -86 (X) from a corresponding subset or all of vector data files 82 (0) -82 (X). Are configured to receive the input vector data sample sets 86 (0) -86 (X) on the tapped delay line inputs 88 (0) -88 (X) as a subset or all of the input vector data samples 86. . All input vector data samples 86 comprise an input vector data sample set 86 (0) -86 (X). As described in more detail below, the input vector data sample sets 86 (0) -86 (X) from the vector data files 82 (0) -82 (X) are the resulting correlated output vector data sample sets. To provide 132 (0) -132 (X), the reference vector data sample sets 130 (0) -130 (X) and VPE 22 (2) are correlated. Reference vector data sample sets 130 (0) -130 (X) are 130 (0), 130 (1),. . . , And 130 (X), which are comprised of “X + 1” reference vector data samples 130. The resulting correlation output vector data sample sets 132 (0) -132 (X) are 132 (0), 132 (1),. . . , And 132 (X), consisting of “X + 1” resulting correlation output vector data samples 132.

  [00130] With continued reference to FIG. 11, the tapped delay line 78 provides a correlation to be performed by the VPE 22 (2) to provide a shifted input vector data sample set 86S (0) -86S (X). The input vector data sample sets 86 (0) to 86 (X) are shifted for each correlation delay tap (ie, correlation processing stage) of the correlation vector processing operation according to the vector instruction. All of the shifted input vector data samples 86S comprise the shifted input vector data sample sets 86S (0) -86S (X). Tapped delay line 78 is input vector data sample set 86S (0) shifted to execution unit inputs 90 (0) -90 (X) of execution units 84 (0) -84 (X) during correlation vector processing operations. Shift the input vector data sample sets 86 (0) -86 (X) to provide ~ 86S (X). In this way, the intermediate correlation results based on the operations performed on the shifted input vector data sample sets 86S (0) -86S (X) are obtained from each of the correlation vector processing operations performed by the VPE 22 (2). There is no need to store, shift, and refetch from the vector data files 82 (0) -82 (X) during the processing stage. Thus, the tapped delay line 78 can reduce power consumption and increase the processing efficiency for the correlation vector processing operation performed by the VPE 22 (2).

  [00131] With continued reference to FIG. 11, the execution units 84 (0) -84 (X) have the reference vector data sample set 130 (0) stored in the sequence number generator (SNG) 134 for correlation vector processing operations. ) To 130 (X), the reference vector data sample 130 is also received. Execution units 84 (0) -84 (X) use reference vector data sample sets 130 (0) -130 (X) as input vector data sample sets 86 (0) -86 (X) as part of the correlation vector processing operation. ) To be correlated. However, it should be noted that the sequence number generator (SNG) 134 can also be a register or other file. Since the correlation vector processing operation in this example is for CDMA correlation vector instructions, sequence number generator 134 is provided in this embodiment to provide reference vector data sample sets 130 (0) -130 (X). When the correlation between the reference vector data sample sets 130 (0) to 130 (X) and the input vector data sample sets 86 (0) to 86 (X) is high, the reference vector data sample sets 130 (0) to 130 ( X) is provided as a generated chip sequence for use in signal extraction from the input vector data sample sets 86 (0) -86 (X).

  [00132] For example, correlation vector processing operations for CDMA vector correlation instructions include on-time input vector data samples 86 in input vector data sample sets 86 (0) -86 (X) and input vector data sample sets 86 (0 ) -86 (X) may provide a correlation with later input vector data samples. For example, on-time input vector data samples 86 in input vector data sample sets 86 (0) -86 (X) are even-numbered input vector data samples 86 in input vector data sample sets 86 (0) -86 (X). (E.g., 86 (0), 86 (2), 86 (4),... 86 (X-1)). Subsequent input vector data samples 86 in input vector data sample sets 86 (0) -86 (X) are odd input vector data samples 86 in input vector data sample sets 86 (0) -86 (X) (eg, 86 (1), 86 (3), 86 (5),... 86 (X)). Alternatively, the on-time input vector data sample 86 can be an odd input vector data sample 86 and the late input vector data sample 86 can be an even input vector data sample 86. As a result of the correlation vector processing operation, the resulting correlation output vector data sample set 132 (0) -132 (X) for the on-time input vector data sample 86 and the late input vector data sample 86 are input to the signal extraction. It can be used to determine whether to use on-time input vector data samples from vector data sample sets 86 (0) -86 (X) or to use late input vector data samples. For example, the on-time correlation vector processing operation may be provided according to the following equation:

here,
n is the number of input signal samples,
x [n] is the digitized input signal 66;
y [n] is a reference signal,
l is the number of samples.

  [00133] The late correlation vector processing operation may be provided according to the following equation:

here,
n is the number of input signal samples,
x [n] is the digitized input signal 66;
y [n] is a reference signal,
l is the number of samples.
The reference signal y [n] (ie, the reference vector data sample) can be a complex number. In one aspect, VPE 22 (2) may receive a reference signal (eg, from sequence number generator 134). VPE 22 (2) may directly use the received reference signal to perform on-time correlation calculations and late correlation calculations, in which case the reference signal y [n] in the above equation is received. May represent a reference signal. Alternatively, VPE 22 (2) may calculate the complex conjugate of the received reference signal before using the reference signal to perform on-time correlation operations and late correlation operations, in which case The reference signal y [n] in the equation (1) may represent the conjugate of the received reference signal.

  [00134] With continued reference to FIG. 11, execution units 84 (0) -84 (X) each provide intermediate correlation output vector data samples in execution units 84 (0) -84 (X). During each processing stage of the correlation vector processing operation, the reference vector data sample sets 130 (0) to 130 (X) are shifted to the shifted input vector data sample sets 86S (0) to 86S (X). Vector data samples 86S (0), 86S (1),. . . 86S (X) is configured to multiply. The intermediate correlation output vector data sample set is accumulated in each of execution units 84 (0) -84 (X) (i.e., the previously accumulated correlation output vector data sample becomes the current correlation output vector data sample. Added). This allows each of the intermediate correlation output vector data sample sets generated by execution units 84 (0) -84 (X) to be used for further use and / or processing by VPE 22 (2) without having to store and shift. Input vector data sample sets 86 (0), 86 (1),... To be stored back to the vector data files 82 (0) -82 (X). . . For each 86 (X), supplied by execution units 84 (0) -84 (X) on execution unit outputs 96 (0) -96 (X) on output data flow paths 98 (0) -98 (X), respectively. Resulting in a final resulting correlation output vector data sample set 132 (0) -132 (X).

  [00135] Furthermore, it should be noted that the same components and architecture provided in VPE 22 (2) of FIG. 11 are provided in VPE 22 (1) of FIG. The sequence number generator 134 can supply filter coefficients 92 (0) -92 (Y-1) or reference vector data sample sets 130 (0) -130 (X) and other data to be processed. Addition and multiplexing are performed by the register file 40 and the multiplexer 136. Thus, VPE 22 (2) of FIG. 11 can provide both the filter vector processing operations described above and the correlation vector processing operations described herein and described in further detail below, under the control of multiplexer 136. . Multiplexer 136 may be controlled by a selector signal 138 that is controlled based on a vector instruction being executed by VPE 22 (2). For filter vector instructions, selector signal 138 provides filter coefficients 92 (0) -92 (Y-1) from global register file 40 to be supplied to execution units 84 (0) -84 (X). Can be configured as follows. In the case of a correlation vector instruction, the selector signal 138 receives the reference vector data sample sets 130 (0) -130 (X) from the sequence number generator 134 to be supplied to the execution units 84 (0) -84 (X). Can be configured to select.

  [00136] With continued reference to FIG. 11, tapped delay lines 78 (0), 78 (1) are programmable to be controlled in accordance with the vector instruction being processed, as described in more detail below. It is. If no correlated vector instructions or other instructions that do not utilize the tapped delay line 78 are being processed, the tapped delay line 78 is used by the vector data files 82 (0) -82 (X) and execution units 84 (0) -84. (X) may be programmed not to be included in the input data flow path 80 (0) -80 (X). In this embodiment, as previously described, two tapped delay lines 78, a primary tapped delay line 78 (0) and a shadow tapped delay line 78 (1) are provided, and a shadow tapped delay line 78 is provided. (1) is optional in this embodiment. As previously described, in the absence of the tapped delay line 78, a separate shifting process is used to provide the shifted intermediate input vector data sample set to execution units 84 (0) -84 (X) again. Need to be executed, which increases the delay time and consumes more power. Further, during the correlation vector processing operation, the refetch delay of the shifted input vector data sample sets 86S (0) to 86S (X) from the vector data files 82 (0) to 82 (X) causes the VPE 22 (2) to The efficiency of the input data flow paths 80 (0) to 80 (X) and the output data flow paths 98 (0) to 98 (X) is not limited. The shifted input vector data sample sets 86S (0) -86S (X) are provided by a tapped delay line 78 located in the execution units 84 (0) -84 (X). Vector processing in execution units 84 (0) -84 (X) is limited only by computer resources, not data flow limitations.

  [00137] Furthermore, the correlation vector processing operations performed by VPE 22 (2) of FIG. 11 may be made more precise by utilizing tapped delay line 78, which is performed by execution units 84 (0) -84. This is because the output accumulation for the intermediate correlation processing stage in (X) need not be stored in vector data files 82 (0) -82 (X). Storage of the intermediate vector data sample sets from execution units 84 (0) -84 (X) to vector data files 82 (0) -82 (X) can result in rounding. Thus, when the next intermediate vector data sample set is fed to execution units 84 (0) -84 (X) for vector processing operations, any rounding errors are propagated and added during each multiplication phase of the vector processing operations. Is done. In contrast, in the example of VPE 22 (2) of FIG. 11, the intermediate correlation output vector data sample sets calculated by execution units 84 (0) -84 (X) are vector data files 82 (0) -82 (X ) Need not be memorized. The previous intermediate correlation output vector data sample set may be accumulated with the intermediate correlation output vector data sample set for the next correlation output vector data sample set, which means that the tapped delay line 78 is to be processed. This is because, during the vector processing operation, the shifted input vector data sample sets 86S (0) -86S (X) are supplied to the execution units 84 (0) -84 (X), the result being the previous correlation output vector. Accumulated with the previous vector data sample set for the data sample set.

  [00138] The previous description of the components provided in VPE 22 (1) of FIG. 4 above is equally applicable to VPE 22 (2) of FIG. 11, and therefore will not be described again.

  [00139] Further details and features of VPE 22 (2) of FIG. 11 and shifted to execution units 84 (0) -84 (X) in input data flow paths 80 (0) -80 (X) in this embodiment. Further description of tapped delay line 78 for providing input vector data sample sets 86S (0) -86S (X) will now be described. In this regard, FIGS. 12A and 12B are flowcharts illustrating an exemplary correlation vector processing operation 140 that may be performed in VPE 22 (2) of FIG. 11 utilizing tapped delay line 78 in accordance with exemplary correlation vector instructions. is there. 12A and 12B may be performed in parallel in VPE 22 (2) of FIG. 11 where interleaved on-time and late input vector data sample sets are fetched according to exemplary correlation / covariance vector processing operations. 6 is a flowchart illustrating an exemplary correlation / covariance vector processing operation.

  [00140] With reference to the examples provided in FIGS. 13-17B, exemplary tasks performed in the correlation vector processing operation 140 of FIGS. 12A and 12B will be described. Referring to FIG. 12A, the input vector data sample sets 86 (0) -86 (X) to be processed in the correlation vector processing operation 140 according to the correlation vector instructions are transferred to the vector data file 82 ( 0) -82 (X) are fetched into the input data flow paths 80 (0) -80 (X) (block 142). As described above with respect to VPE 22 (2) of FIG. 11, the input vector data sample sets 86 (0) -86 (X) are converted into sequence number generators 134 in execution units 84 (0) -84 (X). Is multiplied by the reference vector data sample sets 130 (0) -130 (X) received from. For example, FIG. 13 shows reference vector data sample sets 130 (0) -130 (X) in sequence number generator 134. In this example, the 16 input vector data samples 86 (0), 86 (1),. . . 86 reference vector data samples 130 (0), 130 (1),... Stored in the global register file 40 to be correlated with 86 (15). . . 130 (15) exists. FIG. 6B, previously described above, shows an exemplary input vector data sample set 86 (0) -86 (X) stored in vector data files 82 (0) -82 (X), which It is also applicable in this example and is therefore not described here again.

  [00141] Vector instructions depending on the width of the input vector data sample sets 86 (0) -86 (X) and the reference vector data sample sets 130 (0) -130 (X) to be correlated in the correlation vector processing operation 140 One, some, or all of the vector data lanes 100 (0) -100 (X) in VPE 22 (2) of FIG. 11 may be utilized to provide a correlation vector processing operation 140 according to If the entire width of the vector data files 82 (0) -82 (X) is required, all vector data lanes 100 (0) -100 (X) may be utilized for the correlation vector processing operation 140. Note that correlation vector processing operation 140 may only require a subset of vector data lanes 100 (0) -100 (X) that may be utilized for correlation vector processing operation 140. This may be because the width of the input vector data sample set 86 (0) -86 (X) is smaller than the width of all vector data files 82 (0) -82 (X), where the correlation vector It may be desirable to utilize additional vector data lanes 100 for other vector processing operations that are to be performed in parallel with processing operations 140. For purposes of illustrating the current example, the input vector data sample sets 86 (0) -86 (X) and the reference vector data sample sets 130 (0) -130 (X) utilized in the correlation vector processing operation 140 are represented by VPE 22 Assume that all vector data lanes 100 (0) to 100 (X) in (2) are required.

  [00142] Referring back to FIG. 12A, fetch to be loaded into the tapped delay line 78 as a first input vector data sample set 86S (0) -86 (X) for the correlation vector processing operation 140. The input vector data sample sets 86 (0) to 86 (X) are supplied from the vector data files 82 (0) to 82 (X) to the input data flow paths 80 (0) to 80 (X) (block 144). ). The input vector data sample sets 86 (0) -86 (X) are to be processed by the execution units 84 (0) -84 (X) for the correlation vector processing operation 140. 86 (X) is loaded into the delay line 78 (0) with the primary tap. The input vector data sample sets 86 (0) -86 (X) loaded into the primary tapped delay line 78 (0) are not shifted due to the initial operation of the correlation vector processing operation 140. The next input vector data sample sets 86N (0) to 86N (X) are also processed by the execution units 84 (1) to 84 (X). Can be loaded into the delay line 78 (1) with shadow tap. As previously described above and described in further detail below, the purpose of tapped delay line 78 is to execute unit 84 (0) for the next correlation operation during operation of correlation vector processing operation 140. ) To provide input vector data sample sets 86 (0) to 86S (X) shifted to provide input vector data sample sets 86S (0) to 86S (X) shifted to 84 (X). It is. During each processing stage of the correlation vector processing operation 140 performed by execution units 84 (0) -84 (X), input vector data sample set 86S (shifted to execution units 84 (0) -84 (X). 0) to 86S (X), the input vector data samples 86 are shifted in the primary tapped delay line 78 (0). In this way, the input vector data sample sets 86 (0) to 86 (X) are stored and shifted in the vector data files 82 (0) to 82 (X) for each correlation calculation of the correlation vector processing operation 140. And does not need to be refetched.

  [00143] In this regard, FIG. 14 illustrates an exemplary tapped delay line 78 that may be provided within the VPE 22 (2) of FIG. In this embodiment, the tapped delay line 78 includes a shadow tapped delay line 78 (1) and a primary tapped delay line 78 (0). As previously described above, the primary tapped delay line 78 (0) in this example provides a plurality of 8-bit primary to allow the resolution of the input vector data sample 86 to drop to 8 bits long. It consists of a pipeline register 120. The first input vector data sample sets 86 (0) -86 (X) processed by execution units 84 (0) -84 (X) are shifted in this example for the first correlation operation of correlation vector processing operation 140. Not. When execution units 84 (0) -84 (X) process the next correlation operation for correlation vector processing operation 140, input vector data sample set 86 (0) stored in primary tapped delay line 78 (0). ) -86 (X), the input vector data samples 86 become the shifted input vector data sample sets 86S (0) -86S (X), as shown by the arrows in FIG. Shifted in line registers 120 (0) -120 (4X + 3). In this way, execution units 84 (0) -84 (X) store, shift, and store input vector data sample sets 86 (0) -86 (X) from vector data files 82 (0) -82 (X). And without having to refetch, it is fully utilized by receiving the shifted input vector data sample sets 86S (0) -86S (X) and performing their correlation vector processing operations 140.

  [00144] The number of shifts performed in primary tapped delay line 78 (0) and shadow tapped delay line 78 (1) for correlation vector processing operation 140 depends on the number of samples to be correlated. Input vector data sample sets 86 (0) -86 () fetched from the vector data files 82 (0) -82 (X) into the primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1). If the number of input vector data samples 86 in X) is greater than the number of correlation operations in the correlation vector processing operation 140, execution units 84 (0) -84 (X) may select any additional input vector data sample sets 86. Correlation vector processing operation 140 can be performed without refetching (0) -86 (X) from vector data files 82 (0) -82 (X). However, the number of correlation operations in correlation vector processing operation 140 is fetched from vector data files 82 (0) -82 (X) into primary tapped delay line 78 (0) and shadow tapped delay line 78 (1). If the input vector data sample set 86 (0) -86 (X) is greater than the number of input vector data samples 86, then as part of the correlation vector processing operation 140, a further input vector data sample set 86 (0) ~ 86 (X) may be fetched from the vector data files 82 (0) -82 (X).

  [00145] In this embodiment, primary pipeline registers 120 (0) -120 (4X + 3) are collectively the width of vector data files 82 (0) -82 (X). In the example of a vector data file 82 (0) -82 (X) having a width of “X” equal to 15 and 512 bits, it provides a total width of 512 bits (ie, 64 registers × 8 bits each) Therefore, there are 64 total primary pipeline registers 120 (0) -120 (63), each 8 bits wide. Accordingly, in this example, the primary tapped delay line 78 (0) can store the entire width of one input vector data sample set 86 (0) -86 (X). In this example, by providing 8-bit wide primary pipeline registers 120 (0) to 120 (4X + 3), the input vector data sample sets 86 (0) to 86 (X) are for 8-bit correlation vector processing operations. Can be shifted down to 8-bit vector data sample size. For example, if a larger input vector data sample 86 size, such as a 16-bit or 32-bit sample, is desired for the correlation vector processing operation 140, the input vector data sample set 86 (0) -86 (X) is the primary pipeline register. 120 (0) -120 (4X + 3) may be shifted by two primary pipeline registers 120 at a time.

  [00146] FIG. 15A illustrates that during the first clock cycle (CYCLE0) of the correlation vector processing instruction 140, from the vector data files 82 (0) -82 (X) into the primary tapped delay line 78 (0). The loaded input vector data sample sets 86 (0) -86 (X) are shown. The first input vector data sample set 86 (0) -86 (X) is loaded into the primary tapped delay line 78 (0) as input vector data samples X1-X32, but 64 input vector data samples are Supplied. Primary pipeline registers 120 (0) -120 (2X + 1) (see also FIG. 14) load on-time input vector data samples and late input vector data samples from input vector data sample sets 86 (0) -86 (X). Is done. For example, in the primary tapped delay line 78 (0) (and also in the shadow tapped delay line 78 (1), as will be described in more detail below), the input vector data sample set 86 ( Special vector instructions may be supported to load on-time input vector data samples and late input vector data samples from 0) to 86 (X). For example, primary pipeline registers 122 (0), 122 (1), 122 (2X + 2), and 122 (2X + 3) collectively include input vector data samples 86 (0). Primary pipeline registers 122 (0), 122 (1) include on-time input vector data samples 86OT (0) which are X (0) and X (1), where “OT” is “on-time”. "Means. Primary pipeline registers 122 (2X + 2) and 122 (2X + 3) include late input vector data samples 86L (0) which are X (1) and X (2), where “L” is “late”. means. The storage pattern of this input vector data sample 86 in the primary tapped delay line 78 (0) is repeated for the other primary pipeline registers 122 (2) -122 (2X + 1) and 122 (2X + 4) -122 (4X + 3). (See FIG. 14).

  [00147] Referring back to FIG. 14, a shadow tapped delay line 78 (1) is also provided in the tapped delay line 78. The shadow tapped delay line 78 (1) latches the next input vector data sample set 86N (0) -86N (X) from the vector data files 82 (0) -82 (X) for the next vector processing operation. Or it can be used to transport. Shadow tapped delay line 78 (1) also provides a plurality of 8-bit shadows to allow the resolution of the input vector data samples to fall to 8 bits long, similar to primary tapped delay line 78 (0). It consists of a pipeline register 122. The shadow pipeline register 122 is collectively the width of the vector data file 82 (0) -82 (X) which is 512 bits in this example, and as a result, the delay line 78 (1) with the shadow tap also has the primary tap. Like delay line 78 (0), it is possible to store the entire width of one input vector data sample set 86 (0) -86 (X). Accordingly, in this embodiment, the number of shadow pipeline registers 122 (0) to 122 (4X + 3) included in the primary tapped delay line 78 (0) is a total of 16, vector data lanes 100 (0) to 100 ( X) is four times the number, and in this example each vector data lane 100 (0) -100 (X) can support 32 bits each. Thus, the number of primary pipeline registers 120 is also a total of 64 in this example for a total of 512 bits (ie, 64 registers × 8 bits each).

  [00148] FIG. 15B illustrates the next input vector data sample set 86N (0) loaded into the shadow tapped delay line 78 (1) during the second clock cycle (CYCLE1) of the correlation vector processing instruction 140. ) To 86N (X). To set up the execution of the correlation vector processing operation 140, the first input vector data sample set 86 (0) -86 (X) from the vector data files 82 (0) -82 (X) is the primary tapped delay line 78. After being loaded into (0), the next input vector data sample set 86N (0) -86N (1) is loaded into the shadow tapped delay line 78 (1). The next set of input vector data samples 86N (0) to 86N (X) is input vector data samples X (32) to X (63) together with both the on-time input vector data sample 86OT and the subsequent input vector data sample 86L. Is loaded into the delay line 78 (1) with a shadow tap. In this example, X (32) and X (33) are on-time inputs of input vector data samples 86 (0), as in the storage pattern provided in the primary tapped delay line 78 (0) described above. Note that vector data sample 86OT is formed, and X (33) and X (34) form subsequent input vector data sample 86L of input vector data sample 86 (0). Other patterns may be provided to group input vector data samples 86 together to form input vector data sample sets 86 (0) -86 (X). From the reference vector data sample sets 130 (0) -130 (X) from the sequence number generator 134, the reference vector data samples 130 (ie, Y () correlated during the first processing stage of the correlation vector processing operation 140. 0) and Y (1)) are also provided in registers ("C") to execution units 84 (0) -84 (X) of FIG. 15B for use in correlation vector processing operation 140. Indicated.

  [00149] Referring back to FIG. 14, during each processing stage of the correlation vector processing operation 140, the input vector data samples 86 in the input vector data sample sets 86 (0) -86 (X) are delayed with a primary tap. When shifted in line 78 (0), the next input vector data sample 86N stored in shadow pipeline register 122 is also shifted in shadow pipeline register 122 of shadow tapped delay line 78 (1). . In this example, the input vector data samples 86 of the input vector data sample sets 86 (0) to 86 (X) are stored as an on-time version and a later version, so that the tapped delay line 78 (0) of FIG. The shift pattern provided between 78 (1) and the shift pattern provided between tapped delay lines 78 (0) and 78 (1) of FIG. 7 is different. As shown in FIG. 14, the on-time input vector data sample 86OT is transferred from the shadow pipeline register 122 (0) in the shadow tapped delay line 78 (1) to the primary tapped delay line 78 (0). Shifted to primary pipeline register 120 (2X + 1). Similarly, the late input vector data sample 86L is transferred from the shadow pipeline register 122 (2X + 2) in the shadow tap delay line 78 (1) to the primary pipeline register 120 (4X + 3) in the primary tap delay line 78 (0). Shifted to. In this way, when a shift of the input vector data sample 86 occurs during the correlation vector processing operation 140, the on-time input vector data sample 86OT and the later input vector data sample 86OT are tapped delay line 78 (0), Continue to be isolated from each other within 78 (1).

  [00150] The processing stage of correlation vector processing operation 140 proceeds in execution units 84 (0) -84 (X), and finally the next input vector initially stored in shadow-tapped delay line 78 (1). The entire data sample set 86N (0) -86N (X) is completely in the primary tapped delay line 78 (0) to be provided to the execution units 84 (0) -84 (X) for processing. Shifted to. Thus, after the correlation vector processing operation 140 is completed for the current input vector data sample set 86 (0) -86 (X), execution units 84 (0) -84 (X) are then required Otherwise, the previous next stored in the primary tapped delay line 78 (0) as the current input vector data sample set 86 (0) -86 (X) for the next correlation vector processing operation 140 without delay. Input vector data sample sets 86N (0) -86N (X).

  [00151] The first input vector data sample set 86 (0) -86 (X) and the next input vector data sample set 86N (0) -86N (X) are respectively the primary tapped delay line 78 (0) and After loading into the shadow tapped delay line 78 (1), the first input vector data sample set 86 (0) supplied in the primary tapped delay line 78 (0) as shown in FIG. 15B. ) -86 (X) are provided to respective execution units 84 (0) -84 (X) for processing in the first processing stage of the correlation vector processing operation 140 (block 146 of FIG. 12A). The first input vector data sample sets 86 (0) -86 (X) are the current input vector data sample sets 86 (0) -86 (X) being processed by execution units 84 (0) -84 (X). become. As shown in VPE 22 (2) of FIG. 11, the current input vector data sample 86 (0) is provided to execution unit 84 (0), and the current input vector data sample 86 (1) is provided to execution unit 84 (0). 1), and so on. At the current processing stage of correlation vector processing operation 140, reference vector data input samples 130 (0) -130 (X) to be correlated with input vector data sample sets 86 (0) -86 (X) are executed by execution unit 84 ( 0) to 84 (X) (block 148 in FIG. 12A).

  [00152] Next, execution units 84 (0) -84 (X) perform a correlation vector processing operation 140 (block 150 of FIG. 12A). More specifically, execution units 84 (0) -84 (X) are operated on: R (OT) [n] = y [0] * x [n] and late input for on-time input vector data sample 86OT. According to R (L) [n] = y [1] * x [1 + n] for the vector data sample 86L, the current input vector data sample set 86 (0) -86 (X) is obtained during the first processing stage. Multiply with reference vector data sample 130, where y [] is the designated reference vector data sample 130 and x [n] is the current input vector data sample set 86 (0) -86 (X). . The results of the correlation are the current on-time correlation output vector data sample set R (OT) [n] and the current late correlation output vector data sample set R (L) [n]. The execution units 84 (0) -84 (X) then provide each new, resulting correlation vector data sample set to provide a new previous input vector data sample set 86 (0) -86 (X). Are accumulated with the previous correlation vector data sample set calculated by execution units 84 (0) -84 (X) (block 152 of FIG. 12B). In the first processing stage of the correlation vector processing operation 140, the previous resulting correlation output vector data sample sets 132 (0) -132 (X) are not present. Thus, for the second next processing stage of the correlation vector processing operation 140, the first / current resulting correlation output vector data sample set 132 (0) -132 (X) is the previous input vector data sample set. It is only 86 (0) to 86 (X).

  [00153] When all processing stages of the correlation vector processing operation 140 are complete (block 154 of FIG. 12B), the output data flow path 98 is supplied and stored in the vector data files 82 (0) -82 (X). The resulting correlated output vector data sample set 132 (0) prior to accumulation as the resulting correlated output vector data sample set 132 (0) -132 (X) in (0) -98 (X). ) To 132 (X) are supplied (block 157 in FIG. 12B). If all processing stages of correlation vector processing operation 140 have not been completed (block 154 of FIG. 12A), they are shifted to provide shifted input vector data sample sets 86S (0) -86S (X). The input vector data sample sets 86S (0) -86S (X) are shifted within the tapped delay lines 78 (0), 78 (1) to the next location for the correlation vector processing operation 140 (FIG. 12B). Block 156). The shifted input vector data sample sets 86S (0) -86S (X) are accumulated with the previous resulting correlated output vector data sample sets 132 (0) -132 (X) as , To provide the resulting correlation output vector data sample sets 132 (0) -132 (X). Shifting the input vector data samples 86 within the tapped delay lines 78 (0), 78 (1) has been described above in detail with respect to FIG.

  [00154] FIG. 15C illustrates the next correlation operation 140, R (OT) [n] = y [2] * x [2 + n] for on-time input vector data sample 86SOT and late input vector data sample 86SL. Correlation vector processing operation 140 to become a new shifted input vector data sample set 86S (0) -86S (X) for R (L) [n] = y [3] * x [3 + n] The contents of the tapped delay line 78 when the input vector data sample sets 86 (0) -86 (X) are shifted in the second processing stage are shown. Input vector data sample sets 86 (0) to 86 (X) in the primary tapped delay line 78 (0) are shifted by two input vector data samples 86. For example, the input vector data sample 86OT (1) of FIG. 15B for x (2) and X (3) is then shifted into the input vector data sample 86S (0) of FIG. 15C. The shifted input vector data sample sets 86S (0) to 86S (X) become the current input vector data sample sets 86 (0) to 86 (X). The reference vector data samples 130 supplied to execution units 84 (0) -84 (X) are also reference vector data samples 130, which in this example are Y (2) and Y (3).

  [00155] With continued reference to FIG. 12B, run from primary tapped delay line 78 (0) (and from a portion of shadow tapped delay line 78 (1)) to be multiplied with the next reference vector data sample 130. By supplying the units 84 (0) -84 (X) with the next shifted input vector data sample sets 86S (0) -86S (X) (block 150 of FIG. 12A), the process repeats and the resulting correlation The output vector data sample sets 132 (0) -132 (X) are accumulated with the previous resulting correlated output vector data sample sets 132 (0) -132 (X) (block 152 of FIG. 12B). FIG. 15D shows the state of the input vector data sample 86 present in the tapped delay lines 78 (0), 78 (1) during the final processing stage of the exemplary correlation vector processing operation 140. FIG. In this example, as shown in FIG. 15D, the full data width of tapped delay line 78 was used for input vector data sample sets 86 (0) -86 (X), but on-time input vector data samples. There were 16 processing stages for the correlation vector processing operation 140 since it was divided between 86OT and the late input vector data sample 86L. As shown in FIG. 15D, Y (30) and Y (31) are the last reference vector data samples 130 (X) in the correlation vector processing operation 140, which in the example of FIG. 130 (15). The shifted input vector data sample sets 86S (0) -86S (X) are shifted 16 times (in this example, the width of the vector data lanes 100 (0) -100 (X)), resulting in correlation. In the last sixteenth processing stage for vector processing operation 140, input vector data samples X (30) and X (31) are shifted input vector data samples 86S (in primary tapped delay line 78 (0). 0).

  [00156] FIG. 16 illustrates execution units 84 (0) -84 (X) in VPE 22 (2) of FIG. 11 after the exemplary 16 correlation vector processing stages in the above example have been fully executed. FIG. 6 is a schematic diagram of the contents of the accumulators in (ie, the resulting correlation output vector data sample 132). The resulting correlation output vector data sample set is shown as 132 (0) -132 (X). In this example, each execution unit 84 (0) -84 (X) has four accumulators arranged in parallel for each of the vector data lanes 100 (0) -100 (X), so the accumulator Acc0 ~ Acc3 is shown in FIG. The resulting output vector data samples accumulated are as the entire resulting correlation output vector data sample set 132 (0) -132 (X) to be stored there for further analysis and / or processing. , Vector data files 82 (0) -82 (X) may be provided on output data flow paths 98 (0) -98 (X). If necessary, the rows of the resulting correlation output vector data sample sets 132 (0) -132 (X) are transferred from the vector data files 82 (0) -82 (X) to the vector unit data memory 32 (see FIG. 2). In order to move, special vector instructions may be supported by VPE 22 (2).

  [00157] An implementation comprising the resulting filter vector output data sample sets 94 (0) -94 (X) and the resulting correlation output vector data sample sets 132 (0) -132 (X), as described above. The resulting output vector data sample sets supplied by units 84 (0) -84 (X) are in different interleaved formats depending on vector instructions executed by the VPE, in vector data files 82 (0)- 82 (X) and 82 (31) can be stored back. In this example, “X” is equal to 31 to provide vector data files 82 (0) -82 (X) that are each 32 bits wide. For example, as shown in FIG. 17A, the resulting output vector data sample sets 158 (0) -158 (X), 158 (31) have their real (“q”) components and imaginary numbers (“i”). ) May be stored in vector data files 82 (0) -82 (X) separated by components. The resulting output vector data sample sets 158 (0) -158 (X) are 158 (0), 158 (1),. . . , And 158 (X), consisting of “X + 1” resulting output vector data samples 158. Efficiency, such as when the next vector instruction operates on the real and imaginary components of the resulting output vector data sample set 158 (0) -158 (X), 158 (31) as the input vector data sample set Storing the resulting output vector data sample sets 158 (0) -158 (X), 158 (31), separated by their real (“q”) and imaginary (“i”) components for purposes Can be more efficient. Alternatively, it may not be possible to store the resulting output vector data sample 158 in the vector data file 82, such as separating the resulting output vector data sample 158 into its real and imaginary components. . For example, if a 16-bit vector data sample is multiplied with another 16-bit vector data sample, the resulting vector data sample of 32 bits is provided. For example, the resulting output vector data sample 158 of 32 bits may be Y0 in FIG. 17A. The imaginary component Y0 of Y0. i158 (I) can be stored in ADDRESS “0” of the vector data file 82 (0), and the real component Y0. q158 (Q) may be stored in another ADDRESS such as ADDRESS “A”.

  [00158] The resulting output vector data sample sets 158 (0) -158 (X), 158 (31) of FIG. 17A are interleaved with the vector data file 82 (interleaved with even and odd resulting output vector data samples. 0) to 82 (X) and 82 (31). This is illustrated by the example in FIG. 17B. As shown in FIG. 17B, the resulting output vector data samples Y0-Y31 158 (0) -158 (X), 158 (31) are ADDRESS in the vector data files 82 (0) -82 (31). Stored in a format interleaved with even and odd vector data samples in "0" and ADDRESS "A". The resulting output vector data sample Y0 158 (0) is stored in ADDRESS “0” in the vector data file 82 (0). The resulting output vector data sample Y1 158 (1) is not stored in ADDRESS “0” in vector data file 82 (1), but is stored in ADDRESS “A” in vector data file 82 (0). The resulting output vector data sample Y2 158 (2) is stored in ADDRESS “0” in the vector data file 82 (1), and so on.

  [00159] Some wireless baseband operations require that data samples be formatted before being processed. For example, the resulting output vector data sample sets 158 (0) -158 (X) stored in vector data files 82 (0) -82 (X) in the interleaved format in FIGS. May need to be deinterleaved for a vector processing operation. For example, if the resulting output vector data samples 158 (0) -158 (X) represent a CDMA signal, the resulting output vector data samples 158 (0) -158 (X) are the even and odd phases of the signal. May need to be deinterleaved to separate them. The deinterleaved signal is locally received in a correlation processing operation, such as the exemplary correlation vector processing operation described above with respect to FIGS. 11-16, to determine whether the CDMA system can extract the signal. It may be correlated with the generated code or sequence number. Conventional programmable processors perform format conversion of data samples in multiple steps, which adds cycles, power consumption, and data flow complexity in vector data sample format conversion. The vector processor can preprocess the vector data samples to provide format conversion before the format converted vector data samples are provided to the execution unit. Format converted vector data samples are stored in vector data memory and refetched as part of a vector processing operation that requires data format conversion to be processed by the execution unit. However, this format preprocessing of vector data samples delays subsequent processing of the vector data samples that have been format converted by the execution unit, causing underutilization of computer components within the execution unit.

  [00160] The embodiments disclosed herein below provide for the conversion of interleaved vector data sample sets, such as the vector data sample sets shown in FIGS. 18A and 18B. For example, FIGS. 18A and 18B show vector data sample sets D (0) -D (X) stored in vector data files 82 (0) -82 (X) in various formats. FIG. 18A shows vector data sample sets D (0) -D (X) stored in signed complex (SC) 16-bit samples (SC16) and format interleaved with real and imaginary components. The 16-bit real component D (0) (Q) and imaginary component D (0) (I) of the 32-bit vector data sample D (0) are stored in the 32-bit vector data file 82 (0). The 16-bit real component D (X) (Q) and imaginary component D (X) (I) of the vector data sample D (X) are stored in the 32-bit vector data file 82 (X). FIG. 18B shows vector data sample sets D (0) -D (X) stored in SC 8-bit samples (SC8) and format interleaved with real and imaginary components. The 8-bit real component D (0) (1) (Q) and imaginary component D (0) (1) (I) of the 16-bit vector data sample D (0) (1) are stored in the vector data file 82 (0). Is remembered. The 8-bit real component D (0) (0) (Q) and imaginary component D (0) (0) (I) of the 16-bit vector data sample D (0) (0) are also converted into the 32-bit vector data file 82 ( 0). Similarly, the 8-bit real component D (X) (1) (Q) and the imaginary component D (X) (1) (I) of the 16-bit vector data sample D (X) (1) are a 32-bit vector data file. 82 (X). The 8-bit real component D (X) (0) (Q) and imaginary component D (X) (0) (I) of the 16-bit vector data sample D (X) (0) are also converted into the 32-bit vector data file 82 ( X).

  [00161] In this regard, FIG. 19 is a schematic diagram of another exemplary VPE 22 (3) that may be provided as the VPE 22 of FIG. As described in more detail below, VPE 22 (3) of FIG. 19 is for vector processing operations in VPE 22 (3) where refetching of vector data samples is eliminated or reduced, reducing power consumption. Is configured to provide in-flight format conversion (eg, deinterleaving) of the input vector data sample set supplied to the execution unit. In-flight format conversion of the input vector data sample set is stored in the vector data memory and refetched from it before the input vector data sample set retrieved from the vector data memory is supplied to the execution unit for execution. It means that the format is converted without having to be done. In order to eliminate or minimize refetching of input vector data samples from the vector data file to reduce power consumption and improve processing efficiency, the vector data files 82 (0) -82 (X) and execution unit 84 ( Format conversion circuits 159 (0) to 159 (X) are included in each of the vector data lanes 100 (0) to 100 (X) between 0) to 84 (X). As described in more detail below, execution units 84 (0) -84 (X) for vector processing operations that require deinterleaving of input vector data sample sets 86 (0) -86 (X). ) In the format conversion circuits 159 (0) to 159 (X) in the VPE 22 (3) to supply the input vector data sample sets 86F (0) to 86F (X) subjected to the format conversion to the vector data file 82. Input vector data sample sets 86 (0) -86 (X) from (0) -82 (X) are format converted (eg, deinterleaved). All of the format-converted input vector data samples 86F comprise the format-converted input vector data sample sets 86F (0) to 86F (X) in this example. “X” +1 is the maximum number of parallel input data lanes provided in the VPE 22 (3) for processing the input vector data samples 86 in this example.

  [00162] Thus, the format conversion of input vector data sample sets 86 (0) -86 (X) in VPE 22 (3) is pre-processed, stored, and vector data files 82 (0) -82 (X). No re-fetching is required, thereby reducing power consumption. Further, the format conversion of the input vector data sample sets 86 (0) to 86 (X) is performed by the format conversion of the input vector data sample sets 86 (0) to 86 (86) from the vector data files 82 (0) to 82 (X). Execution units 84 (0) -84 (X) are not delayed from performing vector processing operations because they do not require (X) preprocessing, storage, and refetching. Therefore, the efficiency of the data flow path in VPE 22 (3) is not limited by the format conversion pre-processing delay of input vector data sample sets 86 (0) -86 (X). Format converted (eg, deinterleaved) input vector data sample sets 86F (0) -86F (X) are provided to be localized to execution units 84 (0) -84 (X). Vector processing in execution units 84 (0) -84 (X) is limited only by computer resources, not data flow limitations.

  [00163] A primary tapped delay line 78 (0) and a shadow tapped delay line 78 (1) are shown in VPE 22 (3) of FIG. 19, but a tapped delay line in VPE 22 (3) of FIG. Note that inclusion is not necessary. In this example, as shown in FIG. 19, the format conversion circuits 159 (0) to 159 (X) can be included in an optional primary tapped delay line 78 (0). This arrangement is based on the input data flow paths 80 (0) -80 between the vector data files 82 (0) -82 (X) and the execution units 84 (0) -84 (X) in the VPE 22 (3) of FIG. Format conversion circuits 159 (0) to 159 (X) are provided in (X). The operation of primary tapped delay line 78 (0) has been described above with respect to VPE22 (1) and VPE22 (2). As previously described above, primary tapped delay line 78 (0) and shadow tapped delay line 78 (1) may be used for vector processing operations, and format converted input vector data samples. The sets 86F (0) to 86F (X) need to be supplied to the execution units 84 (0) to 84 (X), and the execution units 84 (0) to 84 (X) are also 86SF (0) to 86SF. Requires a format-converted and shifted input vector data sample set designated (X).

  [00164] Note that the same components and architecture provided in VPE 22 (3) of FIG. 19 are provided in VPE 22 (2) of FIG. The common components between the VPE 22 (3) of FIG. 19 and the VPE 22 (2) of FIG. 11 are shown in FIG. 19 together with the element numbers common to the components of FIG. 11 of the VPE 22 (2). The previous description and description of these common components for VPE 22 (2) in FIG. 11 above is also applicable to VPE 22 (3) in FIG. 19, and is therefore not described again here.

  [00165] Further details and features of VPE 22 (3) of FIG. 19 and format conversion to execution units 84 (0) -84 (X) in input data flow paths 80 (0) -80 (X) in this embodiment. Further description of the tapped delay line 78 for providing the input vector data sample sets 86F (0) -86F (X) will now be described. In this regard, FIG. 20 utilizes format conversion circuits 159 (0) -159 (X) in accordance with exemplary vector instructions requiring format conversion of input vector data sample sets 86 (0) -86 (X). 20 is a flowchart illustrating an exemplary deinterleaving format conversion vector processing operation 160 that may be performed at VPE 22 (3) of FIG.

  [00166] Referring to FIG. 20, input vector data sample sets 86 (0) -86 (X) for vector processing operations 160 according to vector instructions are input data from vector data files 82 (0) -82 (X). Fetched into flow paths 80 (0) -80 (X) (block 162). For example, the format conversion for the vector processing operation 160 may include an input vector data sample set 86 (0) -86 (X) from its interleaved state in the vector data file 82 (0) -82 (X): There may be a de-interleaving vector processing operation 160 that is de-interleaved into the de-interleaved input vector data sample sets 86F (0) -86F (X). Depending on the width of the input vector data sample sets 86 (0) -86 (X) to be formatted for vector processing operation 160, to provide a vector processing operation 160 according to the programming of vector instructions, FIG. One, some, or all of the vector data lanes 100 (0) -100 (X) in VPE 22 (3) may be utilized. If the entire width of the vector data files 82 (0) -82 (X) is required, all vector data lanes 100 (0) -100 (X) can be utilized for the vector processing operation 160. Vector processing operation 160 may only require a subset of vector data lanes 100 (0) -100 (X) that may be utilized for vector processing operation 160. This may be because the width of the input vector data sample set 86 (0) -86 (X) is less than the width of all vector data files 82 (0) -82 (X), where vector processing It may be desirable to utilize additional vector data lanes 100 for other vector processing operations to be performed in parallel with operation 160. For the purpose of describing the current example, input vector data sample sets 86 (0) -86 (X) that have been format converted to input vector data sample sets 86F (0) -86F (X) for vector processing operation 160 are provided. Assume that all the vector data lanes 100 (0) to 100 (X) in the VPE 22 (3) in FIG. 19 are required.

  [00167] With continued reference to FIG. 20, the fetched input vector data sample sets 86 (0) -86 (X) are converted into format conversion circuits 159 (0) -159 for format conversion in accordance with vector processing operation 160. Provided in the input data flow paths 80 (0) -80 (X) to (X) (block 164). As a non-limiting example, the current input vector data sample set 86 (0) -86 (X) is optionally supplied to execution units 84 (0) -84 (X) for vector processing operation 160. May be loaded into the primary tapped delay line 78 (0) as input vector data sample sets 86 (0) -86 (X) to be format converted. As previously described, the next input vector data sample set 86 (0) -86 (X) is possibly the next input vector to be processed by execution units 84 (0) -84 (X). Data sample sets 86N (0) -86N (X) may be loaded into the delay line 78 (1) with shadow tap. As previously described above, the purpose of the tapped delay line 78 is to execute units 84 (0) -84 during the operation of the vector processing operation 160 that operates on the shifted input vector data samples 86. Shifting the input vector data sample sets 86 (0) -86 (X) to the shifted input vector data sample sets 86S (0) -86S (X) to be supplied to (X). If the format-converted input vector data sample sets 86F (0) -86F (X) are also shifted within the tapped delay line 78 during the vector processing operation 160, the shifted and format-converted input vector data sample sets. Are designated as 86SF (0) to 86SF (X).

  [00168] With continued reference to FIG. 20, execution units 84 (0) -84 (X) then use the format-converted input vector data sample sets 86F (0) -86F (X) to generate a vector. A processing operation 160 may be performed (block 166). Execution units 84 (0) -84 (X) are configured to provide multiplication and / or accumulation using the formatted input vector data sample sets 86F (0) -86F (X). There is a case. When tapped delay line 78 is used to shift the input vector data sample sets 86F (0) -86F (X) that have been formatted during vector processing operation 160, execution units 84 (0) -84 ( X) can receive input vector data sample sets 86SF (0) -86SF (X) shifted and format converted during each processing stage of vector processing operation 160 until vector processing operation 160 is complete. (Block 168). When the vector processing operation 160 is complete, it is accompanied by a format converted input vector data sample set 86F (0) -86F (X), or a shifted and format converted input vector data sample set 86SF (0) -86SF (X) The resulting output vector data sample sets 172 (0) -172 (X) based on the vector processing operations are supplied to and stored in the vector data files 82 (0) -82 (X) so that the output data flow path 98 (0) to 98 (X) (block 170). The resulting output vector data sample sets 172 (0) -172 (X) are 172 (0), 172 (1),. . . , And 172 (X), consisting of “X + 1” resulting output vector data samples 172.

  [00169] FIG. 21 illustrates exemplary format conversion circuits 159 (0) -159 () that receive input vector data sample sets 86S (0) -86S (X) shifted from the primary tapped delay line 78 (0). It is the schematic of X). In this example, the format conversion circuits 159 (0) to 159 (X) are provided on the output of the primary tapped delay line 78 (0) in the input data flow paths 80 (0) to 80 (X). Exemplary format conversion circuits 159 (0) -159 (X) are described next.

  [00170] Exemplary format conversion circuits 159 (0) -159 (X) are described next. Exemplary details of the internal components of the format conversion circuit 159 (0) are provided in FIG. 21, which is also applicable to the format conversion circuits 159 (1) -159 (X). Taking the format conversion circuit 159 (0) of FIG. 21 as an example, the format conversion circuit 159 (0) in this example is the input vector data sample 86F (0) that has been subjected to the format conversion, or the shifted and format-converted, respectively. Input vectors from primary pipeline registers 120 (0), 120 (1), 120 (2X + 2), 120 (2X + 3) in vector data lane 100 (0) to provide input vector data samples 86SF (0) It is configured to provide deinterleaving and sign extention of data sample 86 (0) or shifted input vector data sample 86S (0). In this regard, in this example, four multiplexers 174 (3) -174 (0) are provided, which are arranged according to the assigned primary pipeline registers 120 (0) -120 (2X + 3), respectively. Each multiplexer 174 (3) -174 (0) receives a shifted input vector data sample 86S (in the assigned primary pipeline register 120 (0), 120 (1), 120 (2X + 2), 120 (2X + 3). 0) or shifted input vector data samples to be stored in the primary pipeline register 120 adjacent to the assigned primary pipeline register 120 (0), 120 (1), 120 (2X + 2), 120 (2X + 3) 86S (0) portion is selected.

  [00171] For example, primary pipeline registers 120 (0), 120 (1), 120 (2X + 2), 120 (2X + 3) are real numbers [15: 8], imaginary numbers [15: 8], and real numbers [7: 0]. , Store the input vector data sample 86S (0) interleaved and shifted in complex interleaved form as an imaginary number [7: 0], and the desired deinterleaved format is a real number according to the vector instruction to be executed For [15: 0] and imaginary [15: 0], the selection of multiplexers 174 (3) -174 (0) should be as follows. Multiplexer 174 (3) should select the portion of the shifted input vector data sample 86S stored in its assigned primary pipeline register 120 (0). However, multiplexer 174 (2) should select the portion of shifted input vector data sample 86S stored in primary pipeline register 120 (1). This is because the deinterleaved real part of the input vector data sample 86S (0) in adjacent input data flow paths 80 (0) (3), 80 (0) (2) (ie real [15: 0]) Should supply. Similarly, multiplexer 174 (0) should select the portion of shifted input vector data sample 86S stored in its assigned primary pipeline register 120 (2X + 3). However, multiplexer 174 (1) should select the portion of shifted input vector data sample 86S stored in primary pipeline register 120 (2X + 2). This is because the deinterleaved imaginary part of the shifted input vector data sample 86S (0) in the adjacent input data flow path 80 (0) (1), 80 (0) (0) (ie, imaginary [15: 0]) should be supplied. Multiplexers 176 (1), 176 (0) are not assigned non-adjacent primary pipeline registers 120 (0), 120 (1), 120 (2X + 2), 120 (2X + 3), as shown in FIG. ) Provides each multiplexer 174 (3) -174 (0) with the ability to select a portion of the shifted input vector data sample 86S (0).

  [00172] With continued reference to FIG. 21, format conversion circuits 159 (0) -159 (X) also sign extend the format-converted input vector data sample sets 86F (0) -86F (X). ). For example, if the format conversion of the input vector data sample sets 86 (0) to 86 (X) requires signed vector data samples converted from a small bit width to a large bit width, the format conversion circuits 159 (0) to 159 (X) may be configured to sign extend the deinterleaved vector data samples by extending the most significant bit as “0” for non-negative numbers and “F” for negative numbers. The format conversion circuits 159 (0) to 159 (X) indicate whether or not sign extension should be performed on the format-converted input vector data sample sets 86F (0) to 86F (X). May have a sign extension (SC) input 178 (0) -178 (X) set according to the vector instruction being executed. SC inputs 178 (0) -178 (X) perform sign extension according to the programmable data path configuration provided by SC inputs 178 (0) -178 (X) according to the vector instruction being processed, The signal may be supplied to sign extension circuits 180 (0) to 180 (X) provided in the format conversion circuits 159 (0) to 159 (X). SC inputs 178 (0) -178 (X) may be configured and reconfigured for each vector instruction to provide flexibility in vector processing by VPE 22 (3). For example, the programmable data paths in the format conversion circuits 159 (0) -159 (X) can be formatted as needed, making full use of the execution units 84 (0) -84 (X) if necessary. To provide the conversion, it can be configured by SC inputs 178 (0) -178 (X) that can be configured and reconfigured every clock cycle of the vector instruction and, if necessary, every clock cycle.

  [00173] However, as explained above, the format conversion circuits 159 (0) to 159 (X) need not be provided as part of the primary tapped delay line 78 (0). The primary tapped delay line 78 (0) and shadow tapped delay line 78 (1) are optional. The format conversion circuits 159 (0) to 159 (X) may receive the input vector data sample sets 86 (0) to 86 (X) directly from the vector data files 82 (0) to 82 (X). In this scenario, for example, referring to FIG. 21, the input vector data sample sets 86 (0) to 86 (X) are directly transferred from the vector register files 82 (0) to 82 (X) to the primary registers 120 (0) to 120 (4X + 3) may be loaded.

  [00174] Further, the format conversion circuits 159 (0) to 159 (X) output the primary tapped delay line 78 (0) to the format-converted input vector data sample sets 86 (0) to 86 (X). Note that although provided above, it is not necessary. The format conversion circuits 159 (0) to 159 (X) in FIG. 21 may be provided on the input side of the delay line 78 (0) with the primary tap and the delay line 78 (1) with the shadow tap. The input vector data sample sets 86 (0) to 86 (X) fetched from the vector data files 82 (0) to 82 (X) include a primary tapped delay line 78 (0) and a shadow tapped delay line 78 (1). The format is converted in the format conversion circuits 159 (0) to 159 (X) before being loaded into the. In this example, the input vector data sample sets 86 (0) to 86 (X) are format-converted input vector data sample sets in the primary tapped delay line 78 (0) and the shadow tapped delay line 78 (1). It should be stored as 86F (0) -86F (X) (or 86SF (0) -86SF (X) after shifting). The format converted input vector data sample set 86F (0) -86F (X) (or shifted 86SF (0) -86SF (X)) is then directly tapped for execution in vector processing operations. There is a possibility that the delay line 78 (0) may be directly supplied to the execution units 84 (0) to 84 (X).

  [00175] As explained above, the input data flow paths 80 (0) -80 (X) utilize the format conversion circuits 159 (0) -159 (X) according to the vector instructions to be executed, It can be programmed according to a programmable input data path configuration. In this regard, FIG. 22 illustrates an exemplary data format of the bits of the vector instruction that controls the shifting and format conversion programming of the input vector data sample set 86 (0) -86 (X) in VPE 22 (3) of FIG. It is the chart 182 which provides The data provided for the fields in chart 182 may be tapped with format conversion circuits 159 (0) -159 (X) and / or depending on whether those functions are required for the vector instruction to be processed. Programming is provided to VPE 22 (3) to control whether delay line 78 is included in input data flow paths 80 (0) -80 (X).

  [00176] In FIG. 22, for example, when using a signed complex 16-bit format (SC16) with a tapped delay line 78, to indicate whether a shift bias for arithmetic instructions is provided, a vector instruction or A bias field 184 (BIAS_SC16) is provided in bits [7: 0] of the vector programming. To indicate whether the first source data (ie, input vector data sample set 86 (0) -86 (X)) should be reduced (ie, deinterleaved) and converted from SC8 format to SC16 format. The first source data format conversion field 186 (DECIMATE_SRC1) is provided in bit [16] of the vector instruction or vector programming. To indicate whether the second source data (ie, input vector data sample set 86 (0) -86 (X)) should be reduced (ie, deinterleaved) and converted from SC8 format to SC16 format. The second source data format conversion field 188 (DECIMATE_SRC2) is provided in the bit [17] of the vector instruction or vector programming. Output source data (eg, the resulting output vector data sample sets 172 (0) -172 (X) in VPE 22 (3) of FIG. 19) are stored in vector data files 82 (0) -82 (X). When done, an output data format field 190 (DEST_FMT) is provided in bit [18] to indicate whether it should be stored in SC16 format or converted from SC16 format to SC8 format and reordered. As described above and in FIG. 17B, input source data (ie, along with even (eg, on-time) and odd (eg, late) samples, which may be particularly useful for CDMA-specific vector processing operations. Input vector data sample sets 86 (0) -86 (X)) and output data (eg, the resulting output vector data sample sets 172 (0) -172 (X) in VPE 22 (3) of FIG. 19) , A phase format field 192 (DECIMATE_PHASE) is provided in bit [19] to indicate whether it should be reduced (ie, deinterleaved).

  [00177] As explained above, execution units 84 (0) -84 (X) in VPE 22 perform vector processing on the input vector data samples, resulting in output data flow paths 98 (0) -98. (X) After supplying the resulting output vector data sample set above, the next vector processing operation may need to be performed on the resulting output vector data sample set. However, the resulting output vector data sample set may need to be reordered for the next vector processing operation. Thus, the resulting output vector data sample set obtained from the previous processing operation is stored in vector data files 82 (0) -82 (X), fetched for reordering, and vector data file 82 ( 0) -82 (X) must be re-stored in the sorted format. For example, as described above in FIGS. 17A and 17B, when the next processing operation is stored in vector data files 82 (0) -82 (X), the previously processed vector data samples May need to be interleaved.

  [00178] As another example, the following processing operation requires that previously processed vector data samples be de-interleaved when stored in vector data files 82 (0) -82 (X). There is a case. For example, in a CDMA processing operation, data samples representing a signal may need to be stored and interleaved according to the even (eg, on-time) and odd (eg, late) phases of the signal. To solve this problem, the vector processor can include circuitry that performs post-processing reordering of the output vector data from the execution unit after the output vector data is stored in the vector data memory. The post-processed output vector data samples stored in the vector data memory are fetched from the vector data memory, rearranged, returned to the vector data memory and stored. This post-processing delays subsequent processing of the reordered vector data samples by the execution unit, causing underutilization of computer components within the execution unit.

  [00179] In this regard, FIG. 23 is a schematic diagram of another exemplary VPE 22 (4) that may be provided as the VPE 22 of FIG. As described in more detail below, the VPE 22 (4) of FIG. 23 removes or reduces refetching of vector data samples, reducing power consumption, and the vector data file 82 ( 0) -82 (X), resulting output vector data sample sets 194 (0) -194 () supplied by execution units 84 (0) -84 (X) for vector processing operations. X) configured to provide in-flight reordering. The resulting output vector data sample sets 194 (0) -194 (X) are 194 (0), 194 (1),. . . , And 194 (X), consisting of “X + 1” resulting output vector data samples 194. For example, the reordering may include interleaving of the resulting output vector data sample sets 194 (0) -194 (X) before being stored in the vector data files 82 (0) -82 (X). is there.

  [00180] As shown in FIG. 23 and described in more detail below, the reordering circuits 196 (0) -196 (X) are located in each of the vector data lanes 100 (0) -100 (X). Are provided in output data flow paths 98 (0) to 98 (X) between the execution units 84 (0) to 84 (X) and the vector data files 82 (0) to 82 (X). The reordering circuits 196 (0) -196 (X) reorder the resulting output vector data sample sets 194R (0) -194R (X) in the output data flow paths 98 (0) -98 (X). As configured based on programming according to vector instructions to be executed to provide a reordering of the resulting output vector data sample sets 194 (0) -194 (X). The resulting in-flight reordering of output vector data sample sets 194 (0) -194 (X) in VPE 22 (4) of FIG. 23 is the result supplied by execution units 84 (0) -84 (X). The resulting output vector data sample sets 194 (0) -194 (X) are reordered before being stored in the vector data files 82 (0) -82 (X). It means that it is rearranged as 194R (0) to 194R (X). In this way, the resulting output vector data sample sets 194 (0) -194 (X) are rearranged as the resulting output vector data sample sets 194R (0) -194R (X). Are stored in the vector data files 82 (0) to 82 (X) in the format. As a non-limiting example, the resulting reordering of output vector data sample sets 194 (0) -194 (X) results in reordering into vector data files 82 (0) -82 (X). It may include interleaving or deinterleaving of the resulting output vector data sample sets 194 (0) -194 (X) to be stored as output vector data sample sets 194R (0) -194R (X).

  [00181] Thus, the resulting output vector data sample set 194 (0) by the reordering circuits 196 (0) -196 (X) provided in the output data flow paths 98 (0) -98 (X). ˜194 (X) are first stored in vector data files 82 (0) ˜82 (X), then fetched from the vector data files 82 (0) ˜82 (X), rearranged, and vector data file 82 There is no need to re-store in (0) -82 (X). The resulting output vector data sample sets 194 (0) -194 (X) are reordered before being stored in the vector data files 82 (0) -82 (X). In this way, the resulting output vector data sample sets 194 (0) -194 (X) can delay the next vector processing operation to be performed within execution units 84 (0) -84 (X). Stored in the rearranged format in the vector data files 82 (0) -82 (X) without the need for additional post-processing steps. Thus, the efficiency of the data flow path within VPE 22 (4) is not limited by the reordering of the resulting output vector data sample sets 194 (0) -194 (X). The next vector processing in execution units 84 (0) -84 (X) is that the resulting output vector data sample sets 194 (0) -194 (X) are arranged in vector data files 82 (0) -82 (X). When it is to be stored in the rearranged format as permuted resulting output vector data sample sets 194R (0) -194R (X), it is limited only by computer resources, not data flow limitations.

  [00182] In this example, VPE 22 (4) including reordering circuits 196 (0) -196 (X) also includes primary tapped delay line 78 (0) and / or shadow, as shown in FIG. A tapped delay line 78 (1) may optionally be included. The operation of tapped delay lines 78 (0), 78 (1) has been described above with respect to VPE 22 (1) and VPE 22 (2). As previously described above, tapped delay lines 78 (0), 78 (1) are shifted input vector data sample sets 86S to be supplied to execution units 84 (0) -84 (X). It may be used for vector processing operations that require (0) -86S (X). Similarly, it should be noted that common components provided in VPEs 22 (1) -22 (3) of FIGS. 4, 11, and 19 are provided in VPE 22 (4) of FIG. Common components are shown in VPE 22 (4) of FIG. 23 along with common element numbers. The previous description and description of these common components above for VPE 22 (1) -22 (3) is also applicable to VPE 22 (4) of FIG. 23 and is therefore not described again here.

  [00183] With continued reference to FIG. 23, more specifically, the reordering circuits 196 (0) -196 (X) receive reordering circuit inputs 198 () on the output data flow paths 98 (0) -98 (X). 0) -198 (X) is configured to receive the resulting output vector data sample sets 194 (0) -194 (X). Reordering circuits 196 (0) -196 (X) provide the resulting output vector data sample sets 194R (0) -194R (X) to provide the resulting output vector data sample sets 194R (0) -194R (X). 194 (0) to 194 (X) are rearranged. The reordering circuits 196 (0) -196 (X) are supplied to the vector data files 82 (0) -82 (X) for storage, so that the output data flow paths 98 (0) -98 (X) The resulting output vector data sample sets 194R (0) -194R (X) are arranged to be rearranged on the reordering circuit outputs 200 (0) -200 (X).

  [00184] The resulting output vector data sample set 194R (0) sorted into the vector data files 82 (0) -82 (X) in the output data flow paths 98 (0) -98 (X) in this embodiment. ) To 194R (X) for further details and further description of VPE 22 (4) of FIG. In this regard, FIG. 24 illustrates a reordering circuit 196 (0) -196 (X) according to an exemplary vector instruction that requires reordering of the resulting output vector data sample sets 194 (0) -194 (X). ) Using the vector processing operation 202 that may be performed in the VPE 22 (4) of FIG. 23, a flowchart illustrating an exemplary reordering of the resulting output vector data sample sets 194 (0) -194 (X). It is.

  [00185] Referring to FIGS. 23 and 24, input vector data sample sets 86 (0) -86 (X) to be processed in accordance with vector processing operations 202 according to vector instructions are converted to vector data files 82 (0) -82. Fetched from (X) and fed into input data flow paths 80 (0) -80 (X) (block 204 in FIG. 24). For example, vector processing operation 202 can include any vector processing operation required according to the vector instruction to be executed. Non-limiting examples including the above-described filter, correlation, and format conversion vector processing operations. Depending on the width of the input vector data sample set 86 (0) -86 (X) for the vector processing operation 202, the VPE 22 (4) in FIG. One, some, or all of the vector data lanes 100 (0) -100 (X) may be utilized. If the entire width of the vector data files 82 (0) -82 (X) is required, all vector data lanes 100 (0) -100 (X) may be utilized for the vector processing operation 202. Vector processing operation 202 may only require a subset of vector data lanes 100 (0) -100 (X). This may be because the width of the input vector data sample set 86 (0) -86 (X) is less than the width of all vector data files 82 (0) -82 (X), where vector processing It may be desirable to utilize additional vector data lanes 100 for other vector processing operations to be performed in parallel with operation 202.

  [00186] With continued reference to FIGS. 23 and 24, the input data flow path 80 where the fetched input vector data sample sets 86 (0) -86 (X) are in execution units 84 (0) -84 (X). (0) -80 (X) are received (block 206 in FIG. 24). Execution units 84 (0) -84 (X) perform vector processing on received input vector data sample sets 86 (0) -86 (X) according to vector processing operations 202 provided according to vector instructions. (Block 208 in FIG. 24). By way of non-limiting example, input vector data sample sets 86 (0) -86 (X) may be executed by execution unit 84 (0 ) -84 (X) as input vector data sample sets 86 (0) -86 (X) to be shifted during execution of vector processing operation 202 during each processing stage of vector processing operation 202 performed by primary May be loaded into tapped delay line 78 (0). As previously described, the next input vector data sample set 86N (0) -86N (X) is possibly the next input vector to be processed by execution units 84 (1) -84 (X). Data sample sets 86N (0) -86N (X) may be loaded into the delay line 78 (1) with shadow tap. As previously described above, the purpose of the tapped delay line 78 is to execute units 84 (0) -84 during operation of the vector processing operation 202 that operates on the shifted input vector data samples 86. Shifting the input vector data sample sets 86 (0) -86 (X) to the shifted input vector data sample sets 86S (0) -86S (X) to be supplied to (X).

  [00187] With continued reference to FIGS. 23 and 24, execution units 84 (0) -84 (X) may use input vector data sample sets 86 (0) -86 (X) to multiply and / or May be configured to provide accumulation. When tapped delay line 78 is used to shift input vector data sample sets 86F (0) -86F (X) that have been formatted during vector processing operation 202, execution units 84 (0) -84 ( X), as described above by example, the input vector data sample sets 86S (0) to 86S (X) shifted during each processing stage of the vector processing operation 202 until the vector processing operation 202 is completed. Can be received. Upon completion of the vector processing operation 202, based on the vector processing of the input vector data sample set 86 (0) -86 (X) or the shifted and format converted input vector data sample set 86S (0) -86S (X), The resulting output vector data sample sets 194 (0) -194 (X) are fed into output data flow paths 98 (0) -98 (X).

  [00188] With continued reference to FIGS. 23 and 24, before the resulting output vector data sample sets 194 (0) -194 (X) are stored in the vector data files 82 (0) -82 (X). The resulting output vector data sample sets 194 (0) -194 (X) are provided between the execution units 84 (0) -84 (X) and the vector data files 82 (0) -82 (X). The output data flow paths 98 (0) to 98 (X) are supplied to the rearrangement circuits 196 (0) to 196 (X). The reordering circuits 196 (0) -196 (X) transfer vector instructions to the vector data files 82 (0) -82 (X) according to the vector instructions being executed and as described in more detail below. When requesting reordering of the resulting output vector data sample sets 194 (0) -194 (X) to be stored, it can be programmed to be included in the output data flow paths 98 (0) -98 (X). is there. The resulting output vector data sample sets 194 (0) -194 (X) are not stored in the vector data files 82 (0) -82 (X), and the reordering circuits 196 (0) -196 (X) The resulting output vector data sample sets 194 (0) -194 (X) are reordered according to the reordering provided in programming according to the vector instruction being executed (block 210 of FIG. 24). In this way, the resulting output vector data sample sets 194 (0) -194 (X) will initially cause a delay in the execution units 84 (0) -84 (X), which is initially the vector data file 82 (0 ) -82 (X), re-fetched, rearranged in post-processing operations, and need not be stored in the rearranged format in vector data files 82 (0) -82 (X). The resulting output vector data sample sets 194 (0) -194 (X) are rearranged into vector data files 82 (0) -82 (X) without the need for post-reordering processing, resulting in It is stored as output vector data sample sets 194R (0) -194R (X) (block 212 in FIG. 24). For example, the resulting output vector data sample sets 194 (0) -194 (X) are provided in the format provided in FIGS. 18A and 18B before being reordered by the reordering circuits 196 (0) -196 (X). May appear in a format like

  [00189] Referring now to FIG. 25, an example of a reordering circuit 196 (0) -196 (X) will be described. For one instance of the reordering circuit 196 (0) provided within the vector data lane 100 (0) is provisioned, exemplary internal components of the reordering circuits 196 (0) -196 (X) Details are provided in FIG. 25, but it is also applicable to the reordering circuits 196 (1) -196 (X). Taking the reordering circuit 196 (0) in FIG. 25 as an example, the reordering circuit 196 (0) in this example provides a reordered resulting output vector data sample 194R (0): It is configured to reorder the resulting output vector data samples 194 (0) supplied by execution unit 84 (0) within output data flow path 98 (0) in vector data lane 100 (0). In this regard, four output vector data sample selectors 214 (3) -214 (0), provided in this example in the form of a multiplexer, are provided in this example, which are each 4 bits wide in this example. Are arranged according to the bit width of the execution unit output 96 (0), which is 96 (0) (3) -96 (0) (0). Each output vector data sample selector 214 (3) -214 (0) has a resulting output vector data sample 194 in the assigned execution unit output 96 (0) (3) -96 (0) (0). The resulting shifted output vector data sample 194 (0) from the execution unit output 96 adjacent to the portion of (0) or the assigned execution unit output 96 (0) (3) -96 (0) (0). Configured to select one of the parts.

  [00190] For example, execution unit outputs 96 (0) (3) -96 (0) (0) are 16-bit signed complex format, real [31:24], real [23:16], imaginary [15: 8], with the imaginary number [7: 0], providing the resulting output vector data sample 194 (0), where the desired reordered (eg, interleaved) format is real according to the vector instruction to be executed In the case of [31:24], imaginary number [23:16], real number [15: 8], imaginary number [7: 0], the selection of the output vector data sample selectors 214 (3) to 214 (0) is as follows. Should be. The output vector data sample selector 214 (3) provides the resulting output vector data sample 194 () from the execution unit output 96 (0) (3) to provide on the output data flow path 98 (0) (3). 0) (3) should be selected. However, the output vector data sample selector 214 (2) provides the resulting output vector data on the execution unit output 96 (0) (1) to provide on the output data flow path 98 (0) (2). The portion of sample 194 (0) (1) should be selected. This results in the rearranged resulting output vector data samples 194R (0) being rearranged and resulting output vector data samples 194R (0) (3), 194R (0) (2) as adjacent. The resulting shifted output vector data sample 194 (0) (ie real [31:24], imaginary [23:16]) in the output data flow path 98 (0) (3), 98 (0) (2) ) Should result in an interleaved real part. Similarly, output vector data sample selector 214 (0) provides the resulting output vector data from execution unit output 96 (0) (0) to provide in output data flow path 98 (0) (0). Sample 194 (0) (0) should be selected. However, the output vector data sample selector 214 (1) provides the resulting output vector data on the execution unit output 96 (0) (2) to provide on the output data flow path 98 (0) (1). Sample 194 (0) (2) should be selected. This results in rearranged output vector data samples 194R (0) being rearranged and resulting output vector data samples 194R (0) (1), 194R (0) (0) as adjacent. Resulting output vector data samples 194 (0) (2), 194 (0) (0) sorted and interleaved within output data flow paths 98 (0) (1), 98 (0) (0) ) (Ie real number [15: 8], imaginary number [7: 0]). Similarly, output vector data sample selectors 216 (1), 216 (0) provided in the form of a multiplexer, as shown in FIG. 25, are assigned non-adjacent execution unit outputs 96 (0) ( 3) to 96 (0) (0) provide the ability to select between the resulting output vector data samples 194 (0) (3) to 194 (0) (0).

  [00191] With continued reference to FIGS. 23 and 25, the reordering circuits 196 (0) -196 (X), depending on the vector instruction to be executed, result in output vector data sample sets 194 (0) -194. (X) may be provided as programmable to be configured or reconfigured so as not to be reordered. In this example, the rearrangement circuits 196 (0) to 196 (X) perform the output data flow path 98 (0) that flows directly to the rearrangement circuits 196 (0) to 196 (X) without any rearrangement operation formed. ) To 98 (X) may be programmed. Output source data (eg, resulting output vector data sample sets 194 (0) -194 (X) in VPE 22 (4) of FIG. 23) as previously described above and shown in FIG. Is stored in vector data files 82 (0) -82 (X) to indicate whether it should be stored in SC16 format or converted from SC16 format to SC8 format and reordered. As a typical example, bit [18] of a vector instruction may be provided with an output data format field 190 (DEST_FMT) in chart 182.

  [00192] In this regard, the programmable reordering data path configuration input 218 (0) of FIG. 25 is the resulting output vector data sample 194 (0) (3)-in the output data flow path 98 (0). The reordering circuit 196 (0) may be supplied to the reordering circuit 196 (0) to program the reordering circuit 196 (0) to reorder or not reorder 194 (0) (0). Programmable reordering data path configuration inputs 218 (1) -218 (X) (not shown) are the resulting output vector data sample sets in output data flow paths 98 (1) -98 (X), respectively. In order to program the rearrangement circuits 196 (1) to 196 (X) so as to rearrange or not rearrange 194 (1) to 194 (X), the rearrangement circuits 196 (1) to 196 (X ) As well. In this way, the reordering circuits 196 (0) -196 (X) provide the resulting output vector data sample sets 194 (0) -194 () if the vector instruction does not provide such processing to be executed. X) may be programmed not to reorder. Programmable reordering data path configuration inputs 218 (0) -218 (X) may be configured and reconfigured for each vector instruction to provide flexibility in vector processing by VPE 22 (4). For example, the programmable reordering data path configuration inputs 218 (0) -218 (X) can reorder as needed, making full use of execution units 84 (0) -84 (X) when necessary. As provided, it can be configured and reconfigured every clock cycle of the vector instruction and, if necessary, every clock cycle.

  [00193] Execution units 84 (0) -84 without requiring further post-processing steps that may delay the next vector processing operation to be performed in execution units 84 (0) -84 (X). Other vector processing operations may also be provided with in-flight processing of the resulting output vector data sample set from (X). For example, CDMA wireless baseband operation that requires despreading of the chip sequence according to a variable length spread signal data sequence may benefit from in-flight vector processing.

  [00194] For example, a data signal 220 that may be modulated using CDMA is shown in FIG. 26A. The data signal 220 has a period of 2T. As shown in FIG. 26A, the data signal 220 represents a data sequence 1010 in this example, where a high signal level represents a logic “1” and a low signal level represents a logic “0”. In CDMA modulation, the data signal 220 is extended by a chip sequence 222, such as the chip sequence 222 of FIG. 26B, which can be a pseudo-random code. In this example, the chip sequence 222 is one tenth of the period of the data signal 220 to provide a chip sequence 222 having a spreading factor or spreading factor of 10 chips for each sample of the data signal 220 in this example. Has a period that is In this example, to spread the data signal 220, the data signal 220 is exclusive ORed (ie, XOR) with the chip sequence 222 to provide a spread transmission data signal 224, as shown in FIG. 26C. ) Other data signals for other users transmitted with the same bandwidth along with the spread transmission data signal 224 are spread using another chip sequence and chip sequence 222 that are orthogonal to each other. In this way, when the original data signal 220 is to be reconstructed, the spread transmission data signal 224 is correlated with the sequence number as described above with respect to FIGS. If there is a high correlation between the sequence number and the spread transmitted data signal 224, as in the case of the chip sequence 222, the original data signal 220 is recovered using the chip sequence associated with the high correlation sequence number. obtain. The spread transmission data signal 224 is despread using a highly correlated chip sequence, which in this example is the chip sequence 222, to reconstruct the original data signal 220, like the reconstructed data signal 226 in FIG. 26D. .

  [00195] The despreading of the spread transmitted data signal 224 in FIG. 26C is similar to the correlation vector processing operation described above with respect to VPE 22 (2) of FIG. 11 to determine the highly correlated chip sequence, to determine the highly correlated chip sequence. As a dot product between and a potential chip sequence. The spread transmission data signal 224 is despread using a chip sequence 222 determined to be used to CDMA modulate the original data signal 220 to provide the recovered data signal 226 in FIG. 26D. obtain.

  [00196] In a vector processor that includes CDMA processing operations, the vector processor may include circuitry that performs despreading of the spread signal vector data sequence after being output from the execution unit and stored in the vector data memory. In this regard, the spread signal vector data sequence stored in the vector data memory is fetched from the vector data memory in a post-processing operation and despread using a correlation spread code sequence or chip sequence to recover the original data signal. Is done. The despread vector data sequence which is the original data sample before spreading is returned to the vector data memory and stored. This post-processing operation can delay the next vector operation process by the execution unit, causing underutilization of computer components in the execution unit. Furthermore, since the spread signal vector data sequence to be despread crosses different data flow paths from the execution unit, despreading of the spread signal vector sequence using the spread code sequence is difficult to parallelize.

  [00197] To address this issue, in the embodiments disclosed below, a VPE is provided that includes a despreading circuit provided in a data flow path between an execution unit in the VPE and a vector data memory. . The despreading circuit uses the output vector data samples from the in-flight execution unit while the output vector data sample set is fed from the execution unit to the vector data memory via the output data flow path, Configured to despread. In-flight despreading of the output vector data sample set means that the output vector data sample set supplied by the execution unit is despread before being stored in the vector data memory, so that the output vector data sample The set is stored in vector data memory in a despread format. The despread spread spectrum sequence (DSSS) is despread into the vector data memory without the need for further post-processing steps that may delay the next vector processing operation to be performed within the execution unit. Can be stored in different formats. Thus, the efficiency of the data flow path within the VPE may not be limited by despreading of the spread spectrum sequence. When the despread spread spectrum sequence is stored in the vector data memory, the next vector processing in the execution unit is limited only by computer resources, not data flow limitations.

  [00198] In this regard, FIG. 27 is a schematic diagram of another exemplary VPE 22 (5) that may be provided as the VPE 22 of FIG. As described in more detail below, VPE 22 (5) in FIG. 27 removes or reduces the refetching of vector data samples, reducing power consumption and reducing the vector data file 82 (V) in VPE 22 (5). 0) -82 (X), resulting output vector data sample set 228 (supplied by execution units 84 (0) -84 (X) with a code sequence for vector processing operations to be stored. 0) -228 (X) configured to provide in-flight despreading. The resulting output vector data sample sets 228 (0) -228 (X) are in this example 228 (0), 228 (1),. . . , And 228 (X), which are composed of output vector data samples 228 that result from “X + 1” inputs. The code sequence may be a spread spectrum CDMA chip sequence for CDMA despread vector processing operations as a non-limiting example. In VPE 22 (5) of FIG. 27, the resulting output vector data sample sets 228 (0) -228 (X) use code sequences before being stored in vector data files 82 (0) -82 (X). Can be despread.

  [00199] As shown in FIG. 27 and described in more detail below, the despreading circuit 230 includes an execution unit 84 (0)-in each of the vector data lanes 100 (0) -100 (X). 84 (X) and output data flow paths 98 (0) to 98 (X) between the vector data files 82 (0) to 82 (X). The despreading circuit 230 is supplied as reference vector data sample sets 130 (0) -130 (X) generated by the sequence number generator 134 as described above in FIGS. 11-16 with respect to the correlation vector processing operation. Configured based on programming according to the vector instructions to be executed to provide in-flight despreading of the resulting output vector data sample sets 228 (0) -228 (X) . The resulting despread output vector data sample sets 229 (0) -229 (Z) are provided by despreading circuit 230 in output data flow paths 98 (0) -98 (X). The resulting despread output vector data sample set 229 (0) -229 (Z) is 229 (0), 229 (1),. . . , And 229 (Z), consisting of “Z + 1” despread, resulting output vector data samples 229. The in-flight despreading of the resulting output vector data sample sets 228 (0) -228 (X) in VPE 22 (5) of FIG. 27 was provided by execution units 84 (0) -84 (X). The resulting output vector data sample sets 228 (0) -228 (X) are stored in the vector data files 82 (0) -82 (X) before the resulting vector data sample sets 228 (0) -228. In (X), it means despreading using a code sequence. In this way, the resulting output vector data sample sets 228 (0) -228 (X) are despread and despread as the resulting output vector data sample sets 229 (0) -229 (X). Are stored in the vector data files 82 (0) to 82 (X) in the same format.

  [00200] Thus, the resulting output vector data sample sets 228 (0) -228 (X) by the despreading circuit 230 provided in the output data flow paths 98 (0) -98 (X) Stored in vector data files 82 (0) -82 (X), then fetched from vector data files 82 (0) -82 (X), despread, and vector data files 82 (0) -82 (X) Need not be re-stored in despread form. The resulting output vector data sample sets 228 (0) -228 (X) are despread before being stored in the vector data files 82 (0) -82 (X). The resulting output vector data sample sets 229 (0) -229 (Z), despread in this way, are then used in the next vector processing operation to be performed in execution units 84 (0) -84 (X). Stored in vector data files 82 (0) -82 (X) without the need for further post-processing steps. Thus, the efficiency of the data flow path within VPE 22 (5) is not limited by the resulting despreading of output vector data sample sets 228 (0) -228 (X). The next vector processing in execution units 84 (0) -84 (X) causes the resulting output vector data sample sets 228 (0) -228 (X) to be reversed to vector data files 82 (0) -82 (X). When stored in despread form as a spread, resulting output vector data sample set 229 (0) -229 (Z), it is limited only by computer resources, not by data flow limitations.

  [00201] Further, a despreading circuit is provided in the output data flow paths 98 (0) -98 (X) between the execution units 84 (0) -84 (X) and the vector data files 82 (0) -82 (X). 230, the resulting output vector data sample sets 228 (0) -228 (X) are converted into vector data files 82 (0) -82 (X) and execution units 84 (0) -84 (X). There is no need to cross the vector data lane 100 in the input data flow path 80 (0) -80 (X) between the two. Providing a data flow path for despreading of input vector data samples 86 in input vector data sample sets 86 (0) -86 (X) between different vector data lanes 100 should increase routing complexity. is there. As a result, execution units 84 (0) -84 (X) may be underutilized while a despreading operation is being performed on input data flow paths 80 (0) -80 (X). Similarly, as described above, despreading of the resulting output vector data sample sets 228 (0) -228 (X) in the input data flow paths 80 (0) -80 (X) results. The output vector data sample sets 228 (0) -228 (X) should first be stored in the vector data files 82 (0) -82 (X) in VPE 22 (5) of FIG. , Thereby increasing power consumption when refetched and despread and / or delaying execution units 84 (0) -84 (X) that may be delayed while a despread operation is being performed. There is a risk of underuse.

  [00202] It is noted that the common components provided in VPEs 22 (1) -22 (4) of FIGS. 4, 11, 19, and 23 are provided in VPE 22 (5) of FIG. I want. Common components are shown in VPE 22 (5) of FIG. 27 along with common element numbers. The previous description and description of these common components above in VPE 22 (1) -22 (4) is also applicable to VPE 22 (5) in FIG. 27 and is therefore not described again here.

  [00203] Still referring to FIG. 27, more specifically, the despreading circuit 230 is on the despreading circuit inputs 232 (0) to 232 (X) on the output data flow paths 98 (0) to 98 (X). The resulting output vector data sample sets 228 (0) -228 (X) are configured to be received. The despreading circuit 230 provides the resulting output vector data sample sets 228 (0) -228 (X) to provide the despread resulting output vector data sample sets 229 (0) -229 (Z). ) Is despread. As will be described in more detail below, the number of despread resulting output vector data samples 229 is equal to the despread resulting output vector data sample set 229 (0) -229 (Z). In the figure, “Z + 1”. The number of despread resulting output vector data samples 229 in despread resulting output vector data sample sets 229 (0) -229 (Z) is the resulting output vector data sample set 228. Depends on the diffusion coefficient used to despread (0) -228 (X). The despreading circuit 230 is supplied to the vector data files 82 (0) -82 (X) for storage, so that the despreading circuit output 234 (0) in the output data flow paths 98 (0) -98 (X). 234 (X) is configured to provide a resulting output vector data sample set 229 (0) -229 (Z) that is despread onto 234 (X).

  [00204] The resulting output vector data sample set 229 (0) despread into the vector data files 82 (0) -82 (X) in the output data flow paths 98 (0) -98 (X) in this embodiment. ) To 229 (Z) for further details and further description of VPE 22 (5) of FIG. In this regard, FIG. 28 illustrates the VPE 22 of FIG. 27 utilizing the despreading circuit 230 in accordance with an exemplary vector instruction that requires despreading of the resulting output vector data sample sets 228 (0) -228 (X). FIG. 6 is a flowchart illustrating exemplary despreading of the resulting output vector data sample sets 228 (0) -228 (X) obtained from despreading vector processing operation 236 that may be performed in (5).

  [00205] Referring to FIGS. 27 and 28, an input vector data sample set 86 (0) -86 (X) to be processed according to a despread vector processing operation 236 according to a vector instruction is a vector data file 82 (0). To 82 (X) and fed into the input data flow paths 80 (0) to 80 (X) (block 238 of FIG. 28). Depending on the width of the resulting output vector data sample sets 228 (0) -228 (X) for the resulting despread vector processing operation 236, a despread vector processing operation 236 that follows programming of the vector instructions is provided. To that end, one, some, or all of the vector data lanes 100 (0) -100 (X) in VPE 22 (5) of FIG. 27 may be utilized. If the despread vector processing operation 236 requires performing despreading of all the resulting output vector data samples 228 in the resulting output vector data sample sets 228 (0) -228 (X), All vector data lanes 100 (0) -100 (X) in the output data flow paths 98 (0) -98 (X) from the execution units 84 (0) -84 (X) are used for the despread vector processing operation 236. Can be done. Alternatively, the despread vector processing operation 236 only requires despreading a subset of the resulting output vector data samples 228 in the resulting output vector data sample sets 228 (0) -228 (X). Thus, only the vector data lane 100 in the output data flow path 98 corresponding to a subset of the resulting output vector data samples 228 is required.

  [00206] With continued reference to FIGS. 27 and 28, the fetched input vector data sample set 86 before the despreading vector processing operation is performed by the despreading circuit 230 in VPE 22 (5) of FIG. (0) -86 (X) are received from input data flow paths 80 (0) -80 (X) in execution units 84 (0) -84 (X) (block 240 in FIG. 28). One or more vectors for input vector data sample sets 86 (0) -86 (X) received by execution units 84 (0) -84 (X) in accordance with vector processing operations provided in accordance with vector instructions. Processing operations are performed (block 242 of FIG. 28). For example, execution units 84 (0) -84 (X) may receive input vector data for performing vector processing operations to provide the resulting output vector data sample sets 228 (0) -228 (X). Sample sets 86 (0) -86 (X) and code sequences in reference vector data sample sets 130 (0) -130 (X) are used to provide multiplication and / or accumulation. For example, the resulting output vector data sample sets 228 (0) -228 (X) may be based on vector processing of the input vector data sample sets 86 (0) -86 (X) and the reference vector data sample set 130. (0) to 130 (X) are supplied into the output data flow paths 98 (0) to 98 (X) of the VPE 22 (5) in FIG.

  [00207] With continued reference to FIGS. 27 and 28, if it is desired to despread the resulting output vector data sample sets 228 (0) -228 (X), the despread vector processing operation 236 results in The resulting output vector data sample sets 228 (0) -228 (X) may be executed before being stored in the vector data files 82 (0) -82 (X). In this example, the resulting output vector data sample sets 228 (0) -228 (X) are associated with execution units 84 (0) -84 (X) and vector data file 82 (0) in VPE 22 (5) of FIG. ) To 82 (X) are supplied to the despreading circuit 230 provided in the output data flow paths 98 (0) to 98 (X). The despreading circuit 230 determines the resulting output vector data sample set 228 (0) -228 according to the vector instruction being executed and the vector instruction is to be stored in the vector data files 82 (0) -82 (X). When despreading (X) is required, the resulting output vector data sample sets 228 (0) -228 (X) are selectively despread within the output data flow paths 98 (0) -98 (X). Is programmable. The resulting output vector data sample sets 228 (0) -228 (X) are not stored in the vector data files 82 (0) -82 (X), and the despreading circuit 230 follows the vector instruction being executed. The resulting output vector data sample sets 228 (0) -228 (X) are despread according to despread programming (block 244 in FIG. 28).

  [00208] In this way, the resulting output vector data sample sets 228 (0) -228 (X) are initially vector data files resulting in delays in execution units 84 (0) -84 (X). Stored in 82 (0) -82 (X), refetched, despread in post-processing operation, and need not be stored in vector data file 82 (0) -82 (X) in despread format . The resulting output vector data sample sets 228 (0) -228 (X) are despread into the vector data files 82 (0) -82 (X) without requiring despreading post-processing, resulting in It is stored as output vector data sample sets 229 (0) -229 (Z) (block 246 in FIG. 28).

  [00209] FIG. 29 illustrates an output data flow path 98 (0) between execution units 84 (0) -84 (X) and vector data files 82 (0) -82 (X) in VPE 22 (5) of FIG. ) -98 (X) is a schematic diagram of an exemplary despreading circuit 230 that may be provided. The despreading circuit 230 despreads the resulting output vector data sample set 229 (0 ) ˜229 (Z) is configured to provide despreading of the resulting output vector data sample sets 228 (0) ˜228 (X). The resulting output vector data sample sets 228 (0) -228 (X) are supplied to the despreading circuit 230 from the execution unit outputs 96 (0) -96 (X) as shown in FIG. Since the spreading coefficients of the resulting output vector data sample sets 228 (0) -228 (X) may not be known, the reference vector data sample set 130 (0) generated by the sequence number generator 134 of FIG. ) To 130 (X), it may be desirable to despread the resulting output vector data sample sets 228 (0) to 228 (X) using various spreading factors with repetitive sequence numbers.

  [00210] For example, the resulting output vector data sample set 228 (0) -228 (X) includes 32 samples, and the resulting output vector data sample set 228 (0) -228 (X) as a whole. Is despread assuming a spreading factor of 4, the resulting output vector data sample sets 228 (0) -228 (X) are despread and then despread resulting output The vector data sample sets 229 (0) -229 (Z) should contain 8 despread samples (i.e. 32 samples / 4 spread coefficients). However, in this same example, if the entire resulting output vector data sample set 228 (0) -228 (X) is despread assuming a spreading factor of 8, the resulting output vector data sample set 228 ( After the despreading of 0) to 228 (X) is performed, the resulting output vector data sample set 229 (0) to 229 (Z) that has been despread has four despread samples (ie, 32 Sample / 8 diffusion coefficient).

  [00211] Thus, with continued reference to FIG. 29, the despreading circuit 230 despreads the resulting output vector data sample sets 228 (0) -228 (X) for different numbers of spreading factors. Configured as follows. The despreading circuit 230 in this embodiment is a despread resulting output vector data sample set 229 (0) -229 (Z) for various spreading factors in one vector processing operation / one vector instruction. ). In this regard, the despreading circuit 230 performs an addition coupled to the execution unit outputs 96 (0) -96 (X) to receive the resulting output vector data sample sets 228 (0) -228 (X). A container tree 248 is included. The adder tree 248 of the despreading circuit 230 has each sample of the resulting output vector data sample set 228 (0) -228 (X) within their respective vector data lanes 100 (0) -100 (X). 228 is configured to receive. A first adder tree level 248 (1) is provided in the adder tree 248. The first adder tree level 248 (1) adds so that the spreading factor of 4 can spread the samples 228 in the resulting output vector data sample sets 228 (0) -228 (X). Units 250 (0) to 250 (((X + 1) * 2) -1) and 250 (7). Latches 251 (0) -251 (X) are despread to latch the resulting output vector data sample sets 228 (0) -228 (X) from output data flow paths 98 (0) -98 (X). Provided in circuit 230.

  [00212] For example, each sample 228 in the resulting output vector data sample set 228 (0) -228 (X) is 32 bits wide and is two 16-bit complex vector data (ie, a first according to format I8Q8 Of the resulting output vector data samples 228 in the resulting output vector data sample sets 228 (0) to 228 (X), the second vector data according to format I8Q8). Four despread coefficients may be applied to despread the four vector data samples in into one despread, resulting output vector data sample. For example, as shown in FIG. 29, adder 250 (0) reverses the resulting output vector data samples 228 (0) and 228 (1) with a spreading factor of 4 for those samples. Configured to diffuse. Similarly, adder 250 (1) is configured to despread the resulting output vector data samples 228 (2) and 228 (3) by a spreading factor of 4 for those samples. The adders 250 (((X + 1) / 2) -1) and 250 (7) use despreading coefficients of 4, and despread vector data sample sets 252 (0) to 252 (((X + 1) / 2)- 1), 252 (7) is configured to despread the resulting output vector data sample sets 228 (X-1) and 228 (X) to provide 252 (7). Despread vector data sample sets 252 (0) -252 (((X + 1) / 2) -1) from the despread performed by adders 250 (((X + 1) / 2) -1), 250 (7) , 252 (7) is latched into latches 255 (0) -255 (((X + 1) / 2) -1), 255 (7).

  [00213] If the despread vector processing operation 236 requires despreading of the resulting output vector data sample set 228 (0) -228 (X) with a spreading factor of 4, it will be described in more detail below. Thus, the despread vector data sample sets 252 (0) -252 (((X + 1) / 2) -1), 252 (7) are despread and the resulting output vector data sample set 229 (0) ˜229 (Z), where “Z” is 7. However, if the despread vector processing operation 236 requires a higher spreading factor (eg, 8, 16, 32, 64, 128, 256), the despread vector data sample sets 252 (0) -252 (((X + 1) / 2) -1), 252 (7) is not supplied as despread, resulting output vector data sample sets 229 (0) -229 (Z). Despread vector data sample sets 252 (0) to 252 (((X + 1) / 2) -1), 252 (7) are adders 254 (0) to 254 (((X + 1) / 4) -1), To the second adder tree level 248 (2) to 254 (3). In this regard, adder 254 (0) provides despread vector data sample 252 (() to provide the resulting despread vector data sample 256 (0) with a spreading factor of 8 for those samples. 0) and 252 (1) are configured to perform despreading. Similarly, adder 254 (1) provides despread vector data sample 252 (2) to provide the resulting despread vector data sample 256 (1) with a spreading factor of 8 for those samples. And 252 (3) are configured to perform despreading. Adders 254 (((X + 1) / 4) -1), 254 (3) are the resulting despread vector data samples 256 (((X + 1) / 4) -1) 256 with 8 spreading factors. In order to supply (3), despread vector data sample sets 252 (((X + 1) / 4) -2), 252 (((X + 1) / 4) -1), 252 (3) are despread Configured to perform. Resulting despread vector data sample sets 256 (0) -256 (() from the despread performed by adders 254 (0) -254 (((X + 1) / 4) -1), 254 (3). (X + 1) / 4) -1), 256 (3) is latched into latches 257 (0) -257 (((X + 1) / 4) -1), 257 (3).

  [00214] With continued reference to FIG. 29, if the despread vector processing operation 236 requires despreading of the resulting output vector data sample sets 228 (0) -228 (X) with a spreading factor of 8, The despread vector data sample sets 256 (0) to 256 (((X + 1) / 4) -1), 256 (3) are despread, resulting output vectors, as described in more detail in Data sample sets 229 (0) -229 (Z) may be provided, where “Z” is three. However, if the despread vector processing operation 236 requires a spreading factor higher than 8 (eg, 16, 32, 64, 128, 256), the despread vector data sample sets 256 (0) to 256 (((X + 1) / 4) -1) 256 (3) is not supplied as the despread resulting output vector data sample set 229 (0) -229 (Z). Despread vector data sample sets 256 (0) to 256 (((X + 1) / 4) -1), 256 (3) are adders 258 (0) to 258 (((X + 1) / 8) -1), To the third adder tree level 248 (3) to 258 (1). In this regard, summer 258 (0) performs despreading on despread vector data samples 256 (0) and 256 (1) to provide 16 spreading factors for those samples. Configured as follows. Similarly, adder 258 (1) provides despread vector data sample sets 260 (0) -260 (((X + 1) / 8) -1), 260 (1) having 16 spreading factors. Despreading is configured to perform despreading vector data samples 256 (2) and 256 (3). Despread vector data sample sets 260 (0) -260 (((X + 1) /) from the despread performed by adders 258 (0) -258 (((X + 1) / 8) -1), 258 (1) 8) -1), 260 (1) are latched in latches 259 (0) -259 (((X + 1) / 8) -1), 259 (2).

  [00215] With continued reference to FIG. 29, if the despread vector processing operation 236 requires despreading of the resulting output vector data sample sets 228 (0) -228 (X) by 16 spreading factors, The despread vector data sample sets 260 (0) -260 (((X + 1) / 8) -1), 256 (1) are despread and the resulting output vector, as described in more detail in Data sample sets 229 (0) -229 (Z) may be provided, where “Z” is one. However, if the despread vector processing operation 236 requires a spreading factor higher than 16 (eg, 32, 64, 128, 256), the despread vector data sample sets 260 (0) -260 (((X + 1) / 8 ) -1), 260 (1) are not supplied as despread, resulting output vector data sample sets 229 (0) -229 (Z). The despread vector data sample sets 260 (0) -260 (((X + 1) / 8) -1), 260 (1) are supplied to a fourth adder tree level 248 (4) to adder 262. . In this regard, adder 262 performs despreading on despread vector data samples 260 (0) and 260 (1) to provide despread vector data samples 264 having 32 spreading factors. Configured. Despread vector data samples 264 from the despread performed by adder 262 are latched into latches 266 and 268.

  [00216] With continued reference to FIG. 29, if the despread vector processing operation 236 requires despreading of the resulting output vector data sample sets 228 (0) -228 (X) by 32 spreading factors, As described in more detail in, despread vector data sample 264 may be provided as a despread resulting output vector data sample 229. However, if the despread vector processing operation 236 requires a spreading factor higher than 32 (eg, 64, 128, 256), the despread vector data sample 264 is despread and the resulting output vector data sample set Not supplied as 229. The despread vector data sample 264 remains latched in the latch 268 without having to be stored in the vector data file 82. As described above, due to despreading using 32 spreading factors, another resulting output vector data sample set 228 (0) -228 (X) is latched 251 ( 0) to 251 (X). The resulting despread vector data sample 264 ′ is added by the adder 270 in the fifth adder tree 248 (5) to provide a despread vector data sample 272 having 64 spreading factors. It is added to the diffusion vector data sample 264. The selector 273 selects either the despread vector data sample 264 having 32 spread coefficients or the despread vector data sample 264 ′ having 64 spread coefficients as a despread vector data sample 272 to be latched in the latch 274. Controls whether it is latched. This same process of latching the additional resulting output vector data sample sets 228 (0) -228 (X) and despreading the additional resulting output vector data sample sets 228 (0) -228 (X) is necessary If so, it can be performed to achieve a diffusion coefficient greater than 64. The despread vector data sample 272 is finally latched into the latch 274 as the desired despread resulting output vector data sample 229 according to the desired spreading factor for the despread vector processing operation 236. Is done.

  [00217] With continued reference to FIG. 29, no matter what spreading factor is requested in the despread vector processing operation 236, the resulting despread output vector data sample sets 229 (0) -229 (Z) are: The vector data files 82 (0) to 82 (X) in FIG. 27 need to be stored. As will be described next, the despreading circuit 230 of FIG. 29 also produces a resulting output vector data sample set 229 (0) -229 (Z) that is despread. The resulting despread, resulting output vector data sample 229 is latched 276 (0) as a result of performing the despread vector processing operation 236 on the vector data sample sets 228 (0) -228 (X). Configured to load into ~ 276 (X). The despread resulting output vector data sample sets 229 (0) -229 (Z) can be supplied to vector data files 82 (0) -82 (X) for storage. In this way, vector data files 82 (0) -82 are stored to store the despread resulting output vector data sample sets 229 (0) -229 (Z) created by the despreading circuit 230. Only one write is required for (X). The adder trees 248 (1) to 248 (5) in the despreading circuit 230 of FIG. 29 can obtain the spreading coefficients 4, 8, 16, and 32 regardless of which spreading coefficient is required in the despreading vector processing operation 236. The resulting output vector data sample 229, despread for all, can be generated. Alternatively, adders in the adder tree that do not need to perform the despread vector processing operation 236 according to the desired spreading factor can be disabled or configured to add zeros. However, to determine which of these despread, resulting output vector data samples 229 are supplied to latches 276 (0) -276 (X) for storage, the following is described. As shown, selectors 278 (0) to 278 (((X + 1) / 4) -1) and 278 (3) are provided.

  [00218] Continuing with reference to FIG. 29 in this regard, the selector 278 (0) is based on the despread vector processing operation 236 being performed, respectively, with adders 250 (0), 254 (0), Resulting output vector data despread for spreading coefficients 4, 8, and 16 from 258 (0) and any of spreading coefficients 32, 64, 128, 256 from adders 262, 270 Sample 229 can be selected. Selector 278 (1) is based on the despreading vector processing operation 236 being performed, and spreading coefficients 4, 8, and, from adders 250 (1), 254 (1), and 258 (1), respectively. For 16, the resulting output vector data sample 229, despread, can be selected. Selector 278 (2) was despread for spreading coefficients 4 and 8 from adders 250 (2) and 254 (2), respectively, based on the despreading vector processing operation 236 being performed. The resulting output vector data sample 229 can be selected. Selector 278 (3) was despread for spreading coefficients 4 and 8 from adders 250 (3) and 254 (3), respectively, based on the despreading vector processing operation 236 being performed. The resulting output vector data sample 229 can be selected. Selector 278 (4) is despread for spreading coefficients 4 and 8 from adder trees 248 (1) and 248 (2), respectively, based on the despreading vector processing operation 236 being performed. Also, the resulting output vector data sample 229 can be selected. Since supplying a spreading factor of 8 can be fully satisfied by the selectors 278 (0) -278 (3), the selector is despread from the adders 250 (4) -250 (7). It is not provided to control the resulting output vector data sample 229.

  [00219] With continued reference to FIG. 29, selectors 278 (0) -278 (((X + 1) / 4) -1), 278 (3) and adders 250 (4) -250 (((X + 1)), respectively. / 2) -1), a series of data slicers 280 (0) -280 (((X + 1) / 2) to receive the resulting output vector data samples 229 selected and despread by 250 (7) -1) 280 (7) is provided. Data slicers 280 (0) -280 (((X + 1) / 2) -1), 280 (7) receive and despread the resulting output vector data samples 229 at a logic high level (eg, logic It is configured to select whether it is characterized as “1”) or as a logic low level (eg, logic “0”). The despread resulting output vector data sample 229 is then stored in the desired latch 276 in latches 276 (0) -276 (X) to be stored via connection to crossbar 282. Transferred. Crossbar 282 provides the flexibility to supply various latches 276 (0) -276 (X) with the resulting output vector data sample 229, which is despread according to despread vector processing operation 236. In this way, the resulting output vector data samples 229 that have been despread are stored in various iterations of the despread vector processing operation 236 before being stored in the vector data files 82 (0) -82 (X). In, it can be stacked into latches 276 (0) -276 (X). For example, the despread resulting output vector data sample sets 229 (0) -229 (Z) may be despread vector processing operations before being stored in the vector data files 82 (0) -82 (X). In various iterations of 236, it can be stacked into latches 276 (0) -276 (X). In this way, access to the vector data files 82 (0) -82 (X) to store the despread resulting output vector data sample sets 229 (0) -229 (Z) is operational. Can be minimized for efficiency.

  [00220] For example, as shown in FIG. 29, selectors 284 (0) -284 (X) coupled to crossbar 282 are in any of latches 276 (0) -276 (X). It can be controlled to store the despread resulting output vector data samples 229 from data slicer 280 (0). Selectors 284 (1), 284 (3), 284 (5), 284 (7), 284 (9), 284 (11), 284 (13), 284 (15) coupled to the crossbar 282 are Data slicer 280 (to be stored in latches 276 (1), 276 (3), 276 (5), 276 (7), 276 (9), 276 (11), 276 (13), and 276 (15) It can be controlled to store the despread resulting output vector data samples 229 from 1). Selectors 284 (2), 284 (6), 284 (10), 284 (14) coupled to crossbar 282 are latched 276 (2), 276 (6), 276 (10), and 276 (14). ) Can be controlled to store the despread resulting output vector data samples 229 from the data slicer 280 (2). Selectors 284 (3), 284 (7), 284 (11), 284 (15) coupled to crossbar 282 are latched 276 (3), 276 (7), 276 (11), and 276 (15). ) Can be controlled to store the despread resulting output vector data samples 229 from the data slicer 280 (3). Selectors 284 (4) and 284 (12) coupled to crossbar 282 are despread resulting output vector data from data slicer 280 (4) to latches 276 (4) and 276 (12). The sample 229 can be controlled to store. Selectors 284 (5) and 284 (13) coupled to crossbar 282 are despread resulting output vector data from data slicer 280 (5) to latches 276 (5) and 276 (13). The sample 229 can be controlled to store. Selectors 284 (6) and 284 (14) coupled to crossbar 282 are despread resulting output vector data from data slicer 280 (6) to latch 276 (6) or 276 (14). The sample 229 can be controlled to store. Selectors 284 (7) and 284 (15) coupled to crossbar 282 are despread resulting output vector data from data slicer 280 (7) to latch 276 (7) or 276 (15). The sample 229 can be controlled to store.

  [00221] With continued reference to FIG. 29, does the despreading circuit 230 perform a despreading operation on the resulting output vector data samples 228 (0) -228 (X) according to the vector instruction to be executed? Or may be programmed to be configured not to execute. In this regard, a despreading operation is performed on the resulting output vector data sample sets 228 (0) -228 (X), respectively, for storage in vector data files 82 (0) -82 (X). Or the despreading configuration input 286 of FIG. 29 is reversed to simply supply the resulting output vector data sample sets 228 (0) -228 (X) to the latches 276 (0) -276 (X). The diffusion circuit 230 can be provided. In this way, the despreading circuit 230 does not despread the resulting output vector data sample sets 228 (0) -228 (X) if the vector instruction does not provide such processing to be performed. Can be programmed. Despread configuration input 284 may be configured and reconfigured for each vector instruction to provide flexibility in vector processing by VPE 22 (5) of FIG. For example, the despreading configuration input 284 may use the execution units 84 (0) -84 (X) when necessary to provide despreading as needed, every vector instruction clock cycle, It can be configured and reconfigured every clock cycle if necessary.

  [00222] Some other wireless baseband operations require merging of data samples determined from previous processing operations for reasons other than despreading of the spread spectrum data sequence. For example, it may be desirable to accumulate vector data samples having a wider variation width than the data flow path for execution units 84 (0) -84 (X) provided by vector data lanes 100 (0) -100 (X). There is a case. As another example, it may be desirable to provide dot product multiplication of output vector data samples from various execution units 84 (0) -84 (X) to provide merging of output vector data in vector processing operations. There is. Vector data lanes 100 (0) -100 (X) in the VPE are inter-vector data paths for intersecting vector data lanes 100 (0) -100 (X) to provide merged vector processing operations. May include complex routing to provide. However, parallelization in output vector data to be merged across various vector data lanes is difficult, so this can increase complexity and reduce the efficiency of the VPE. The vector processor may include circuitry that performs post-processing merging of output vector data stored in the vector data memory from the execution unit. The post-processed output vector data samples stored in the vector data memory are fetched from the vector data memory, merged as necessary, and returned to the vector data memory for storage. However, this post-processing may delay the next vector processing operation of the VPE and cause underutilization of computer components in the execution unit.

  [00223] For example, two input vector data samples 290 (0), 290 (1) provided in the vector data files 82 (0), 82 (1) in the VPE described above are shown in FIG. It may be desirable to add these two input vector data samples 290 (0), 290 (1) together. In this example, the sum of the two input vector data samples 290 (0), 290 (1) is “0x11250314E”, which has a data width greater than either vector data lane 100 (0) or 100 (1). Have. Execution units 84 (0), 84 (1) provide carry logic between two execution units 84 (0), 84 (1) across vector data lanes 100 (0), 100 (1) Vector data between vector data lanes 100 (0), 100 (1) such that two input vector data samples 290 (0), 290 (1) can be performed together. A data flow path may be provided in the VPE 22 to provide routing. In order to provide a scalar result of merged vector data samples, the ability to cross all vector data lanes 100 (0) -100 (X) may be required, thereby increasing the complexity in the data flow path. May further increase. However, as explained above, this should add complexity in the data flow path, thereby increasing complexity and possibly reducing efficiency.

  [00224] To address this issue, the embodiments disclosed below include a VPE that includes a merging circuit provided in an output data flow path between an execution unit in the VPE and a vector data memory. The merging circuit outputs the output vector data samples from the output vector data sample set supplied by the in-flight execution unit while the output vector data sample set is supplied from the execution unit to the vector data memory via the output data flow path. Configured to merge. In-flight merging of output vector data samples means that the output vector data samples supplied by the execution unit can be merged before being stored in the vector data memory, so that the resulting output vector data sample set Are stored in the vector data memory in a merged format. The merged output vector data samples can be stored in the vector data file without the need for further post-processing steps that may delay the next vector processing operation to be performed in the execution unit. Therefore, the efficiency of the data flow path within the VPE is not limited by the vector data merging operation. When merged vector data samples are stored in vector data memory, the next vector processing in the execution unit is limited only by computer resources, not data flow limitations.

  [00225] In this regard, FIG. 31 is a schematic diagram of another exemplary VPE 22 (6) that may be provided as the VPE 22 of FIG. As described in more detail below, the VPE 22 (6) of FIG. 31 removes or reduces the refetching of vector data samples and reduces power consumption, thereby reducing the vector data file 82 (in VPE 22 (6). 0) -82 (X), resulting output vector data sample set 292 (supplied by execution units 84 (0) -84 (X) using a code sequence for vector processing operations. 0) to 292 (X) in-flight merging. The resulting output vector data sample sets 292 (0) -292 (X) are the resulting output vector data samples 292 (0),. . . , 292 (X). As a non-limiting example, a merge vector processing operation can add the resulting output vector data samples 292, determine a maximum vector data sample value among a plurality of resulting output vector data samples 292, or Determining a minimum vector data sample value among the plurality of resulting output vector data samples 292 may be included. In the VPE 22 (6) of FIG. 31, the resulting output vector data samples 292 in the resulting output vector data sample sets 292 (0) to 292 (X) are stored in vector data files 82 (0) to 82 ( X) can be merged before being stored.

  [00226] The merging circuit 294 is implemented to provide in-flight merging of the resulting output vector data samples 228 in the resulting output vector data sample sets 228 (0) -228 (X). Configured based on programming according to power vector instructions. The merged resulting output vector data samples 296 (0) -296 (Z) are provided by a merging circuit 294 in the output data flow path 98 (0) -98 (X). The “Z” in the resulting output vector data samples 296 (0) -296 (Z) that have been merged is merged into the merged resulting output vector data sample set 296 (0) -296 (Z). And the resulting number of output vector data samples 296. The merged resulting output vector data sample set 296 (0) -296 (Z) is 296 (0),. . . , And 296 (Z), resulting output vector data samples 296. The number of merged resulting output vector data samples 296 in the resulting output vector data sample sets 296 (0) -296 (Z) is equal to the resulting output vector data sample set 292 (0 ) To 292 (X). In-flight merging of the resulting output vector data samples 292 in VPE 22 (6) of FIG. 31 is provided by the resulting output vector data sample set 292 (0 ) -292 (X) means that the resulting output vector data samples 292 can be merged together before being stored in the vector data files 82 (0) -82 (X). In this way, the merged resulting output vector data samples 296 of the resulting output vector data sample sets 296 (0) -296 (Z) are merged into the resulting output vector. Data sample sets 296 (0) -296 (Z) can be stored in vector data files 82 (0) -82 (X) in merged form.

  [00227] Thus, the resulting output vector data sample sets 292 (0) -292 (X) by the merging circuit 294 provided in the output data flow paths 98 (0) -98 (X) It need not be stored in vector data files 82 (0) -82 (X) and then fetched from vector data files 82 (0) -82 (X). The desired output vector data sample 292 is merged and the resulting output vector data sample 292 is re-stored in the merged form in the vector data files 82 (0) -82 (X). The resulting output vector data samples 292 from the resulting output vector data sample sets 292 (0) -292 (X) are merged before being stored in the vector data files 82 (0) -82 (X). obtain. In this way, the merged resulting output vector data samples 296 from the resulting output vector data sample sets 296 (0) -296 (Z) are stored in execution units 84 (0) -84. Stored in vector data files 82 (0) -82 (X) without the need for further post-processing steps that may delay the next vector processing operation to be performed in (X). Thus, the efficiency of the data flow path in VPE 22 (6) is not limited by the resulting merging of output vector data samples 292. When the resulting output vector data samples 292 are stored in merged form in vector data files 82 (0) -82 (X), the next vector processing in execution units 84 (0) -84 (X) is: Limited by computer resources only, not data flow limitations.

  [00228] Further, the merging circuit 294 in the output data flow path 98 (0) -98 (X) between the execution units 84 (0) -84 (X) and the vector data files 82 (0) -82 (X). Resulting in output vector data sample sets 292 (0) -292 (X) between vector data files 82 (0) -82 (X) and execution units 84 (0) -84 (X). There is no need to cross the vector data lane 100 in the input data flow paths 80 (0) -80 (X) between. Providing a data flow path for merging of input vector data samples 86 in input vector data sample sets 86 (0) -86 (X) between different vector data lanes 100 should increase routing complexity. . As a result, execution units 84 (0) -84 (X) may be underutilized while merging operations are being performed in input data flow paths 80 (0) -80 (X). Similarly, the resulting output vectors from the resulting output vector data sample sets 292 (0) -292 (X) in the input data flow paths 80 (0) -80 (X) as described above. For merging data samples 292, the resulting output vector data sample sets 292 (0) -292 (X) are first stored in vector data files 82 (0) -82 (X) in VPE 22 (6) of FIG. Execution unit 84 (which may need to be done, thereby increasing power consumption when refetched and merged and / or delaying while merging operations are being performed) There is a risk of underuse of 0) to 84 (X).

  [00229] The common components provided in VPE 22 (1) -22 (5) of FIGS. 4, 11, 19, 23, and 27 are provided in VPE 22 (6) of FIG. Please keep in mind. The common component is shown in VPE 22 (6) of FIG. 31 together with the common element number. The previous description and description of these common components above in VPE 22 (1) -22 (5) is also applicable to VPE 22 (6) of FIG. 31, and is therefore not described again here.

  [00230] Continuing with reference to FIG. 31, more specifically, the merging circuit 294 is configured on the merging circuit inputs 300 (0) -300 (X) on the output data flow paths 98 (0) -98 (X): The resulting output vector data sample sets 292 (0) -292 (X) are configured to be received. Merging circuit 294 provides a merged, resulting output vector data sample set 296 (0) -296 (Z) from the resulting output vector data sample set 292 (0) -292 (X). Is configured to merge the resulting output vector data samples 292. “Z” in the resulting output vector data samples 296 (0) -296 (Z) that is merged results in the bit width of the merged resulting output vector data sample set 296 (0) -296 (Z). Represent. “Z” may be smaller than the bit width of the resulting output vector data sample set 292 (0) -292 (X) represented by “X” due to the merging operation. As described in more detail below, the number of merged resulting output vector data samples 296 in the resulting output vector data sample sets 296 (0) -296 (Z) “Z + 1”. Depends on the resulting output vector data samples 292 from the resulting output vector data sample sets 292 (0) -292 (X) to be merged together. The merging circuit 294 is supplied to the vector data files 82 (0) -82 (X) for storage, so that the merging circuit outputs 301 (0) -301 in the output data flow paths 98 (0) -98 (X). (X) is configured to provide the resulting output vector data sample sets 296 (0) -296 (Z) merged onto.

  [00231] The resulting output vector data sample set 296 (0) merged into the vector data files 82 (0) -82 (X) in the output data flow paths 98 (0) -98 (X) in this embodiment. Further details and a further description of the features of VPE 22 (6) of FIG. 31 to supply ˜296 (Z) will now be described. In this regard, FIG. 32 illustrates a vector processing operation 302 that may be performed in VPE 22 (6) of FIG. 31 utilizing merging circuit 294 according to an exemplary vector instruction that requires merging of the resulting output vector data sample 292. FIG. 6 is a flowchart illustrating exemplary merging of the resulting output vector data samples 292 of the resulting output vector data sample sets 292 (0) -292 (X) obtained from FIG.

  [00232] Referring to FIGS. 31 and 32, input vector data sample sets 86 (0) -86 (X) to be processed according to vector processing operations 302 according to vector instructions are converted to vector data files 82 (0) -82. (X) is fetched and supplied into the input data flow paths 80 (0) -80 (X) (block 304 of FIG. 32). Depending on the width of the input vector data sample set 86 (0) -86 (X) for the vector processing operation 302, within the VPE 22 (6) of FIG. One, some, or all of the vector data lanes 100 (0) -100 (X) may be utilized. If the entire width of the vector data files 82 (0) -82 (X) is required, all vector data lanes 100 (0) -100 (X) can be utilized for the vector processing operation 302. Vector processing operation 302 may only require a subset of vector data lanes 100 (0) -100 (X). This may be because the width of the input vector data sample set 86 (0) -86 (X) is less than the width of all vector data files 82 (0) -82 (X), where vector processing It may be desirable to utilize additional vector data lanes 100 for other vector processing operations to be performed in parallel with operation 302.

  [00233] With continued reference to FIGS. 31 and 32, the input data flow path 80 where the fetched input vector data sample sets 86 (0) -86 (X) are in execution units 84 (0) -84 (X). (0) -80 (X) are received (block 306 in FIG. 32). Execution units 84 (0) -84 (X) perform vector processing operations 302 on received input vector data sample sets 86 (0) -86 (X) according to vector processing operations 302 provided according to vector instructions. Perform (block 308 in FIG. 32). Execution units 84 (0) -84 (X) provide input vector data sample set 86 (0) for vector processing operation 302 to provide resulting output vector data sample sets 292 (0) -292 (X). ) -86 (X) can be used to provide multiplication and / or accumulation. When vector processing operation 302 is complete, the resulting output vector data sample sets 292 (0) -292 (X) based on vector processing operations 302 performed on input vector data sample sets 86 (0) -86 (X). ) Is supplied into the output data flow paths 98 (0) to 98 (X) of the VPE 22 (6) in FIG.

  [00234] With continued reference to FIGS. 31 and 32, before the resulting output vector data sample sets 292 (0) -292 (X) are stored in the vector data files 82 (0) -82 (X). The resulting output vector data sample sets 292 (0) -292 (X) are provided between the execution units 84 (0) -84 (X) and the vector data files 82 (0) -82 (X). The output data flow paths 98 (0) to 98 (X) are supplied to a merging circuit 294. The merging circuit 294 provides the resulting output that the vector instructions are to be stored in the vector data files 82 (0) -82 (X) according to the vector instructions being executed and as described in more detail below. Programmable to be included in the output data flow path 98 (0) -98 (X) when requesting merging of the resulting output vector data sample 292 from the vector data sample sets 292 (0) -292 (X) It is. Without the resulting output vector data sample sets 292 (0) -292 (X) being stored in the vector data files 82 (0) -82 (X), the merging circuit 294 follows the vector instruction being executed, The resulting output vector data samples 292 from the resulting output vector data sample sets 292 (0) -292 (X) are merged (block 310 of FIG. 32). In this way, the resulting output vector data sample sets 292 (0) -292 (X) will initially cause a delay in the execution units 84 (0) -84 (X), which is the first vector data file 82 (0 ) -82 (X), re-fetched, merged in post-processing operations, and need not be stored in the merged format in vector data files 82 (0) -82 (X). The resulting output vector data sample sets 292 (0) -292 (X) are merged into vector data files 82 (0) -82 (X) without requiring post-merging processing. Stored as data sample sets 296 (0) -296 (Z) (block 312 of FIG. 32).

  [00235] FIG. 33 illustrates an output data flow path 98 (0) between execution units 84 (0) -84 (X) and vector data files 82 (0) -82 (X) in VPE 22 (6) of FIG. ) -98 (X) is a schematic diagram of an exemplary merging circuit 294 that may be provided. The merging circuit 294 provides a merged, resulting output vector data sample set 296 (0) -296 (Z) of the resulting output vector data sample set 292 (0) -292 (X). Configured to provide merging. The resulting output vector data sample sets 292 (0) -292 (X) are supplied to the merging circuit 294 from the execution unit outputs 96 (0) -96 (X) as shown in FIG.

  [00236] With continued reference to FIG. 33, the merging circuit 294 is configured to merge the resulting output vector data sample sets 292 (0) -292 (X). The merging circuit 294 in this embodiment is configured to provide a merged resulting output vector data sample set 296 (0) -296 (Z). In this regard, the merging circuit 294 is an adder coupled to the execution unit outputs 96 (0) -96 (X) to receive the resulting output vector data sample sets 292 (0) -292 (X). A tree 318 is included. The adder tree 318 of the merging circuit 294 is responsible for each sample 292 of the resulting output vector data sample set 292 (0) -292 (X) within their respective vector data lanes 100 (0) -100 (X). Configured to receive. A first adder tree level 318 (1) is provided in the adder tree 318. The first adder tree level 318 (1) can merge the adjacent samples 292 in the resulting output vector data sample sets 292 (0) -292 (X) so that the merge circuit 320 (0). To 320 (((X + 1) / 2) -1), 320 (7). Latches 321 (0) -321 (X) are merging circuits to latch the resulting output vector data sample sets 292 (0) -292 (X) from output data flow paths 98 (0) -98 (X). 294 is provided.

  [00237] For example, each sample 292 in the resulting output vector data sample set 292 (0) -292 (X) is 32 bits wide and is two 16-bit complex vector data (ie, a first according to format I8Q8 Of the resulting output vector data samples 292 in the resulting output vector data sample sets 292 (0) -292 (X). A merging operation may be applied to merge the four vector data samples in into one merged resulting output vector data sample 296. For example, as shown in FIG. 33, adder 320 (0) is configured to merge the resulting output vector data samples 292 (0) and 292 (1). Similarly, adder 320 (1) is configured to merge the resulting output vector data samples 292 (2) and 292 (3) for those samples. The adders 320 (((X + 1) / 2) -1) and 320 (7) supply merge vector data sample sets 322 (0) to 322 (((X + 1) / 2) -1) and 322 (7). In order to do so, the resulting output vector data sample sets 292 (X-1) and 292 (X) are configured to be merged. Merge vector data sample sets 322 (0) -322 (((X + 1) / 2) -1), 322 from the merging performed by adders 320 (((X + 1) / 2) -1), 320 (7), 322 (7) is latched into latches 325 (0) -325 (((X + 1) / 2) -1), 325 (7).

  [00238] If the merge vector processing operation 302 requires merging of the resulting output vector data sample sets 292 (0) -292 (X), as described in more detail below, the merge vector data samples Sets 322 (0) -322 (((X + 1) / 2) -1), 322 (7) may be supplied as a merge, resulting output vector data sample set 296 (0) -296 (Z), Here, “Z” is 7. However, if the merge vector processing operation 302 requires merging of the resulting output vector data samples 292 that are not adjacent in the resulting output vector data sample sets 292 (0) -292 (X), then merge vector data samples Sets 322 (0) -322 (((X + 1) / 2) -1), 322 (7) are not supplied as merge, resulting output vector data sample sets 296 (0) -296 (Z). Merge vector data sample sets 322 (0) to 322 (((X + 1) / 2) -1) and 322 (7) are adders 324 (0) to 324 (((X + 1) / 4) -1), 324 To the second adder tree level 318 (2) to (3). In this regard, adder 324 (0) performs merging on merge vector data samples 322 (0) and 322 (1) to provide the resulting merge vector data samples 326 (0). Configured. Similarly, adder 324 (1) is configured to perform merging on merge vector data samples 322 (2) and 322 (3) to provide a resulting merge vector data sample 326 (1). Is done. Adders 324 (((X + 1) / 4) -1), 324 (3) provide the resulting merge vector data samples 326 (((X + 1) / 4) -1), 326 (3). The merge vector data samples 322 (((X + 1) / 4) -2), 322 (((X + 1) / 4) -1), and 322 (3) are configured to perform merging. Resulting merge vector data sample sets 326 (0) -326 (((X + 1) from the merging performed by adders 324 (0) -324 (((X + 1) / 4) -1), 324 (3) ) / 4) -1), 326 (3) are latched into latches 327 (0) -327 (((X + 1) / 4) -1), 327 (3).

  [00239] Still referring to FIG. 33, if the merge vector processing operation 302 requires merging of the resulting output vector data sample sets 292 (0) -292 (X) with a merge factor of 8, As described in detail, merge vector data sample sets 326 (0) -326 (((X + 1) / 4) -1), 326 (3) are merged and the resulting output vector data sample set 296 (0 ) To 296 (Z), where “Z” is 3. However, if merge vector processing operation 302 requires a merge factor higher than 8 (eg, 16, 32, 64, 128, 256), merge vector data sample sets 326 (0) -326 (((X + 1) / 4 ) -1), 326 (3) is not supplied as a merge, resulting output vector data sample set 296 (0) -296 (Z). Merge vector data sample sets 326 (0) to 326 (((X + 1) / 4) -1) and 326 (3) are adders 328 (0) to 328 (((X + 1) / 8) -1), 328 To the third adder tree level 318 (3) to (1). In this regard, adder 328 (0) performs merging on merge vector data samples 326 (0) and 326 (1) to provide 16 merge factors for those samples. Composed. Similarly, adder 328 (1) merges to provide merge vector data sample sets 330 (0) -330 (((X + 1) / 8) -1), 330 (1) having 16 merge coefficients. It is configured to perform merging on vector data samples 326 (2) and 326 (3). Merge vector data sample sets 330 (0) -330 (((X + 1) / 8) from merging performed by adders 328 (0) -328 (((X + 1) / 8) -1), 328 (1) -1) and 330 (1) are latched in latches 329 (0) to 329 (((X + 1) / 8) -1) and 329 (1).

  [00240] Still referring to FIG. 33, if the merge vector processing operation 302 requires merging of the resulting output vector data sample sets 292 (0) -292 (X) with 16 merge factors, As described in detail, merge vector data sample sets 330 (0) -330 (((X + 1) / 8) -1), 330 (1) are merged and the resulting output vector data sample set 296 (0 ) To 296 (Z), where “Z” is 1. However, if the merge vector processing operation 236 requires a merge factor higher than 16 (eg, 32, 64, 128, 256), the merge vector data sample sets 330 (0) -330 (((X + 1) / 8) − 1), 330 (1) are not supplied as a merge, resulting output vector data sample sets 296 (0) -296 (Z). Merge vector data sample sets 330 (0)-330 (((X + 1) / 8) −1), 330 (1) are supplied to a fourth adder tree level 318 (4) to adder 332. In this regard, adder 332 is configured to perform merging on merge vector data samples 330 (0) and 330 (1) to provide merge vector data samples 334 having 32 merge coefficients. The Merge vector data samples 334 from the merging performed by adder 332 are latched into latches 336 and 338.

  [00241] Still referring to FIG. 33, if the merge vector processing operation 302 requires merging of the resulting output vector data sample sets 292 (0) -292 (X) with 32 merge factors, As described in detail, merge vector data sample 334 may be provided as a merge, resulting output vector data sample 296. However, if the merge vector processing operation 302 requires a merge factor higher than 32 (eg, 64, 128, 256), the merge vector data sample 334 is not provided as a merge, resulting output vector data sample 296. The merge vector data sample 334 remains latched in the latch 338 without having to be stored in the vector data file 82. As described above, to be merged using 32 merge factors, another resulting output vector data sample set 292 (0) -292 (X) is latched 321 (0) over a further processing cycle. ) To 321 (X). The resulting merge vector data sample 334 ′ is added by the adder 340 in the fifth adder tree 318 (5) to provide a merge vector data sample 342 having 64 merge coefficients. Added to sample 334. The selector 343 controls whether a merge vector data sample 334 having 32 merge coefficients or a merge vector data sample 334 ′ having 64 merge coefficients is latched into the latch 344 as a merge vector data sample 342. To do. This same process of latching the additional resulting output vector data sample sets 292 (0) -292 (X) and merging the additional resulting output vector data sample sets 292 (0) -292 (X) is necessary If so, it can be performed to achieve a merge factor greater than 64. The merge vector data sample 342 is finally latched into the latch 344 as the desired merge, resulting output vector data sample 296, according to the desired merge factor for the merge vector processing operation 302.

  [00242] With continued reference to FIG. 33, no matter what merge coefficients are requested in the merge vector processing operation 302, the resulting output vector data sample sets 296 (0) -296 (Z) are merged into the vector data file 82. (0) to 82 (X) need to be stored. As will be explained next, the merging circuit 294 of FIG. 33 also merges the resulting output vector data sample sets 296 (0) -296 (Z) to form the resulting output vector data sample sets. The resulting merge, resulting in performing the merge vector processing operation 302 on 292 (0) -292 (X), and the resulting output vector data sample 296 in latches 346 (0) -346 (X) Configured to load. The merged, resulting output vector data sample sets 296 (0) -296 (Z) can be supplied to vector data files 82 (0) -82 (X) for storage. Thus, to store the merge created by merging circuit 294 and the resulting output vector data sample sets 296 (0) -296 (Z), vector data files 82 (0) -82 (X) Only one write is required for this. The adder trees 318 (1) -318 (5) in the merging circuit 294 of FIG. In contrast, merging and the resulting output vector data samples 296 can be generated. Alternatively, adders in the adder tree that do not need to perform the merge vector processing operation 302 according to the desired merge factor can be disabled or configured to add zeros. However, to determine which of these merges, the resulting output vector data samples 296, are supplied to latches 346 (0) -346 (X) for storage, as described next. , Selectors 348 (0) to 348 (((X + 1) / 4) -1), 348 (3) are provided.

  [00243] Continuing with reference to FIG. 33 in this regard, the selector 348 (0) is based on the merge vector processing operations 302 being performed, respectively, adders 320 (0), 324 (0), 328. Merge, select resulting merged output vector data sample 296 for any of merge factors 4, 8, and 16 from (0) and merge factors 32, 64, 128, 256 from adders 332, 340 can do. Selector 348 (1) determines merge factors 4, 8, and 16 from adders 320 (1), 324 (1), 328 (1), respectively, based on the merge vector processing operation 302 being performed. On the other hand, merging and the resulting output vector data sample 296 can be selected. Selector 348 (2) merges, resulting in merge coefficients 4 and 8, from adders 320 (2) and 324 (2), respectively, based on the merge vector processing operation 302 being performed. Output vector data samples 296 can be selected. Selector 348 (3) merges and results in merge factors 4 and 8 from adders 320 (3) and 324 (3), respectively, based on the merge vector processing operation 302 being performed. Output vector data samples 296 can be selected. Since supplying a merge factor of 8 can be fully satisfied by the selectors 348 (0) -348 (3), the selector is able to merge the results supplied from the adders 320 (4) -320 (7). Is not provided for controlling the resulting output vector data sample 296.

  [00244] With continued reference to FIG. 33, data slicers 350 (0) -350 (((X + 1) / 2) -1), 350 (7) provided for merge vector processing operations are bypassed, Alternatively, selectors 348 (0) to 348 (((X + 1) / 4) -1), 348 (3) and adders 320 (4) to 320 (((X + 1) / 2) -1), 320, respectively. The received merge selected by (7) may be configured not to perform data splicing on the resulting output vector data samples 296. The merged, resulting output vector data sample 296 is then transferred via a connection to the crossbar 352 to the desired latch 346 in latches 346 (0) -346 (X) for storage. . Crossbar 352 provides the flexibility to supply various latches 346 (0) -346 (X) to merge and the resulting output vector data samples 296 according to merge vector processing operation 302. In this way, the merged and resulting output vector data samples 296 are latched during various iterations of the merge vector processing operation 302 before being stored in the vector data files 82 (0) -82 (X). 346 (0) -346 (X). For example, the merged resulting output vector data sample sets 296 (0) -296 (Z) may be stored in the various merge vector processing operations 302 before being stored in the vector data files 82 (0) -82 (X). In iterations, they can be stacked into latches 346 (0) -346 (X). Thus, merging and accessing the resulting vector data files 82 (0) -82 (X) for storing the resulting output vector data sample sets 296 (0) -296 (Z) is for operational efficiency. Can be minimized.

  [00245] For example, as shown in FIG. 33, selectors 354 (0) -354 (X) coupled to crossbar 352 are in any of latches 346 (0) -346 (X). The merge from selector 348 (0) may be controlled to store the resulting output vector data samples 296. Selectors 354 (1), 354 (3), 354 (5), 354 (7), 354 (9), 354 (11), 354 (13), 354 (15) coupled to the crossbar 352 are A selector 348 (to be stored in latches 346 (1), 346 (3), 346 (5), 346 (7), 346 (9), 346 (11), 346 (13), and 346 (15). The merge from 1) may be controlled to store the resulting output vector data samples 296. Selectors 354 (2), 354 (6), 354 (10), 354 (14) coupled to the crossbar 352 include latches 346 (2), 346 (6), 346 (10), and 346 (14 ) May be controlled to store the merge from selector 348 (2) and the resulting output vector data samples 296. Selectors 354 (3), 354 (7), 354 (11), 354 (15) coupled to the crossbar 352 include latches 346 (3), 346 (7), 346 (11), and 346 (15 ) Can be controlled to store the merge from selector 348 (3) and the resulting output vector data samples 296. Selectors 354 (4) and 354 (12) coupled to crossbar 352 merge the latches 346 (4) and 346 (12) from adder 320 (4) into the resulting output vector data samples 296. It can be controlled to memorize. Selectors 354 (5) and 354 (13) coupled to crossbar 352 merge the latches 346 (5) and 346 (13) from adder 320 (5) into the resulting output vector data samples 296. It can be controlled to memorize. Selectors 354 (6) and 354 (14) coupled to crossbar 352 merge the latches 346 (6) or 346 (14) from adder 320 (6) into the resulting output vector data samples 296. It can be controlled to memorize. Selectors 354 (7) and 354 (15) coupled to crossbar 352 merge the latches 346 (7) or 346 (15) from adder 320 (7) and the resulting output vector data samples 296. It can be controlled to memorize.

  [00246] In the merging circuit 294 of FIG. 33, the adder causes the resulting output vector data samples 282 that are not adjacent in the resulting output vector data sample sets 292 (0) -292 (X) to be merged. Note that may be configured to enable. For example, if it is desired to merge the resulting output vector data sample 292 (0) with the resulting output vector data sample 292 (9), the additions in adder tree levels 318 (1) -318 (3) The instrument can be configured to simply pass the merge of the resulting output vector data sample 292 (0) with the resulting output vector data sample 292 (9) to the adder tree level 318 (4). There is sex. Adder 332 in adder tree level 318 (4) then provides the resulting output vector data sample 292 (0) to the resulting output vector data to provide merged output vector data samples 296. May merge with sample 292 (9).

  [00247] Merging circuits that provide other types of vector merging operations other than vector and / or scalar addition are also described in execution units 84 (0) -84 (X) and vector data files 82 (0) -82 (X). May be provided in the output data flow path 98 (0) to 98 (X) between and. For example, the merging circuit 294 of FIG. 33 may be configured to provide maximum or minimum vector and / or scalar merging operations. For example, adders in adder tree levels 318 (1) -318 (5) of adder tree 318 of FIG. 33 may be replaced with maximum or minimum functional circuits. In other words, the circuit passes either the larger or the smaller of the two resulting output vector data samples 292 from the resulting output vector data sample sets 292 (0) -292 (X). Should be selected. For example, two resulting output vector data samples 292 from the resulting output vector data sample sets 292 (0) -292 (X) are represented by the two input vector data samples 290 (0), 290 ( 1), if the merging circuit 294 is configured to select the largest vector data sample, the merging circuit 294 may be configured to select the vector data sample 290 (1). .

  [00248] In this regard, referring to FIG. 34, adders 320 (0) -320 (((X + 1) / 2) -1), 320 in the first adder tree level 318 (1) of FIG. (7) is replaced with the maximum or minimum merge selection adders 320 ′ (0) to 320 ′ (((X + 1) / 2) −1), 320 ′ (7) as shown in FIG. There is a possibility. The adders 324 (0) to 324 (((X + 1) / 4) -1), 324 (3) in the second adder tree level 318 (2) are maximum or The smallest selectors 324 ′ (0) to 324 ′ (((X + 1) / 4) −1) may be exchanged for 324 ′ (3). The adders 328 (0) to 328 (((X + 1) / 8) -1), 328 (1) in the third adder tree level 318 (3) are maximum or The smallest selectors 328 ′ (0) to 328 ′ (((X + 1) / 8) −1) and 328 ′ (1) may be exchanged. The adder 332 in the fourth adder tree level 318 (4) may be replaced with a maximum or minimum selector 332 'as shown in FIG. The adder 340 in the fifth adder tree level 318 (5) may be replaced with a maximum or minimum selector 340 'as shown in FIG. In the merging circuit 294 of FIG. 34, the adder is between the non-adjacent, resulting output vector data samples 292 in the resulting output vector data sample sets 292 (0) -292 (X) to be merged. May be configured to select the largest or smallest resulting output vector data sample 292. For example, if it is desired to maximum merge the resulting output vector data sample 292 (0) with the resulting output vector data sample 292 (9), the adder tree levels 318 (1) through 318 (3) The adder is simply configured to pass a merge of the resulting output vector data sample 292 (0) with the resulting output vector data sample 292 (9) to the adder tree level 318 (4). there is a possibility. The adder 332 ′ in adder tree level 318 (4) then provides the resulting output vector data sample 292 (0) to the resulting output vector to provide a merged output vector data sample 264. There is a possibility of maximal merging with data sample 292 (9).

  [00249] As described above, execution unit 84 in VPE 22 (1)-(6) is used to perform vector processing operations on input vector data sample sets 86 (0) -86 (X). (0) to 84 (X) are provided. Execution units 84 (0) -84 (X) provide execution modes 84 (0) -84 (X) using a common circuit and hardware for various vector processing operations. It also includes a programmable data path configuration that enables More exemplary details regarding the execution units 84 (0) -84 (X) and their programmable data path configurations for providing multiple modes of operation using common circuitry and hardware will now be described. .

  [00250] In this regard, FIG. 35 illustrates an exemplary execution unit that may be provided for each of the execution units 84 (0) -84 (X) in the VPEs 22 (1)-(6). A schematic diagram is shown. As shown in FIG. 35, and as described in more detail below in FIGS. 36-39, execution unit 84 may be configured with an exemplary vector processing block that may be configured with a programmable data path configuration. A plurality of exemplary vector pipeline stages 460. As will be described in more detail below, a programmable data path configuration provided within the vector processing block allows specific circuitry and hardware to receive vector data 30 received from the vector unit data memory 32 of FIG. Can be programmed and reprogrammed to support the execution of different specific vector processing operations.

  [00251] For example, some vector processing operations may typically require multiplication of vector data 30 followed by accumulation of the multiplied vector data results. Non-limiting examples of such vector processing include filtering operations, correlation operations, and radix-2 and radix-4 commonly used to perform fast Fourier transform (FFT) operations for wireless communication algorithms. A butterfly operation is included, where a series of parallel multiplications are provided followed by a series of parallel accumulations of the multiplication results. Similarly, as will be described in more detail below with respect to FIGS. 39 and 40, the execution unit 84 of FIG. 35 includes a carry save accumulator for providing a redundant carry save format in the carry save accumulator. There is also a fusion multiplier option with Providing a redundant carry save format in the carry save accumulator eliminates the need to provide a carry propagation path and a carry propagation add operation between each step of accumulation.

  [00252] In this connection, with further reference to FIG. 35, the M0 multiply vector pipeline stage 460 (1) of VPE 22 is first described. The M0 multiplication vector pipeline stage 460 (1) may include a plurality of vector processing blocks in the form of any desired number of multiplier blocks 462 (A) -462 (0), each having a programmable data path configuration. It is the 2nd vector pipeline stage containing. Multiplier blocks 462 (A) -462 (0) are provided for performing vector multiplication operations within execution unit 84. Multiple multiplier blocks 462 (A) -462 (0) provide M0 multiplication vector pipeline stage 460 () to provide multiplication of up to 12 multiplication vector data sample sets 34 (Y) -34 (0). 1) in parallel with each other. In this embodiment, “A” is equal to 3, which in this example means that the M0 multiplication vector pipeline stage 460 (1) includes four multiplier blocks 462 (3) -462 (0). Multiplier vector data sample sets 34 (Y) -34 (0) are the first vector pipeline stage 460 (0) in execution unit 84, and are provided in the input read (RR) vector pipeline stage. Are loaded into the execution unit 84 for vector processing into the latches 464 (Y) -464 (0). In this embodiment, there are twelve latches 464 (11) -464 (0) in the execution unit 84, which means that “Y” is equal to 11 in this embodiment. The latches 464 (11) to 464 (0) convert the multiplication vector data sample sets 34 (11) to 34 (0) fetched from the vector register (see the vector data file 28 in FIG. 2) into the vector data input sample set 466. (11) to 466 (0) are configured to be latched. In this example, each latch 464 (11) -464 (0) is 8 bits wide. The latches 464 (11) to 464 (0) respectively multiply the multiplication vector data input sample sets 466 (11) to 466 (0), respectively, and the vector data 30 having a total width of 96 bits (ie, 12 latches × 8 bits each). Configured to latch for.

  [00253] With continued reference to FIG. 35, a plurality of multiplier blocks 462 (3) -462 (0) are provided for the vector data input sample sets 466 (11) -466 (0) to provide vector multiplication operations. It is configured to be able to receive several combinations, where “Y” is equal to 11 in this example. Multiplier vector data input sample sets 466 (11) -466 (0) are provided in a plurality of input data paths A3-A0, B3-B0, and C3-C0 according to the design of execution unit 84. The vector data input sample sets 466 (3) to 466 (0) correspond to the input data paths C3 to C0 as shown in FIG. The vector data input sample sets 466 (7) to 466 (4) correspond to the input data paths B3 to B0 as shown in FIG. The vector data input sample sets 466 (11) to 466 (8) correspond to the input data paths A3 to A0 as shown in FIG. A plurality of multiplier blocks 462 (3) -462 (0) are respectively provided to an input data path A3 supplied to the plurality of multiplier blocks 462 (3) -462 (0) to provide vector multiplication operations. ~ Configured to process vector data input sample sets 466 (11) to 466 (0) received according to ~ A0, B3-B0, C3-C0.

  [00254] Programmable internal data path 467 (3) provided within multiplier blocks 462 (3) -462 (0) of FIG. 35, as described in more detail below with respect to FIGS. ˜467 (0) can be programmed to have various data path configurations. These various data path configurations depend on the specific input data paths A3-A0, B3-B0, C3-C0 supplied to each multiplier block 462 (3) -462 (0). ) To 462 (0) to provide various combinations and / or various bit length multiplications of a particular received vector data input sample set 466 (11) to 466 (0). In this regard, a plurality of multiplier blocks 462 (3) -462 (0) provides a vector result output comprising multiplication results obtained by multiplying together a particular combination of vector data input sample sets 466 (11) -466 (0). As sample sets, vector multiplication output sample sets 468 (3) to 468 (0) are supplied.

  [00255] For example, the programmable internal data paths 467 (3) -467 (0) of multiplier blocks 462 (3) -462 (0) are vectors in the instruction dispatch circuit 48 of the baseband processor 20 of FIG. It can be programmed according to the set value supplied from the instruction decoder. In this embodiment, there are four programmable internal data paths 467 (3) -467 (0) for multiplier blocks 462 (3) -462 (0). Vector instructions specify a particular type of operation to be performed by execution unit 84. Thus, execution unit 84 provides programmable internal data paths for multiplier blocks 462 (3) -462 (0) to provide various types of vector multiplication operations using the same common circuit in a highly efficient manner. 467 (3) -467 (0) may be programmed and reprogrammed. For example, execution unit 84 may use programmable internal data paths 467 (3) -467 (0) of multiplier blocks 462 (3) -462 (0) for vector instructions in the instruction pipeline in instruction dispatch circuit 48. According to the decoding, it can be programmed to configure and reconfigure every clock cycle for every vector instruction executed. Thus, if the M0 multiply vector pipeline stage 460 (1) in the execution unit 84 is configured to process the vector data input sample set 466 every clock cycle, the result is a multiplier block 462 (3). ˜462 (0) performs a vector multiplication operation every clock cycle in accordance with the decoding of the vector instruction in the instruction pipeline in the instruction dispatch circuit 48.

  [00256] Multiplier block 462 may be programmed to perform real and imaginary multiplication. With continued reference to FIG. 35, in one vector processing block data path configuration, multiplier block 462 may be configured to multiply two 8-bit vector data input sample sets 466 together. In one multiply block data path configuration, multiplier block 462 may be configured to multiply together two 16-bit vector data input sample sets 466, which are Formed from the first pair of 8-bit vector data input sample sets 466 multiplied by the second pair. This is shown in FIG. 38 and is described in more detail below. Again, by providing a programmable data path configuration within multiplier blocks 462 (3) -462 (0), multiplier blocks 462 (3) -462 (0) reduce the area within execution unit 84. , In some cases, configured and reconfigured to perform various types of multiplication operations to allow fewer execution units 84 to be provided in the baseband processor 20 to perform the desired vector processing operations. The flexibility is that it can be configured.

  [00257] Referring back to FIG. 35, the plurality of multiplier blocks 462 (3) -462 (0) includes vector multiply output sample sets 468 in programmable output data paths 470 (3) -470 (0). (3) -468 (0) are configured to be supplied to either the next vector processing stage 460 or the output processing stage. Vector multiply output sample sets 468 (3) -468 (0) are programmable outputs according to a programmed configuration based on vector instructions being executed by a plurality of multiplier blocks 462 (3) -462 (0). It is supplied in the data paths 470 (3) to 470 (0). In this example, vector multiplication output sample sets 468 (3) -468 (0) in programmable output data paths 470 (3) -470 (0) are used for accumulation, as described below. M1 accumulation vector pipeline stage 460 (2) is supplied. This particular design of execution unit 84 includes a plurality of multiplier blocks 462 (3) -462 (0) followed by special vector instructions that require multiplication of vector data input followed by accumulation of multiplication results. It is desirable to provide a supporting accumulator. For example, a radix-2 and radix-4 butterfly operation, commonly used to provide an FFT operation, includes a series of multiplication operations followed by accumulation of multiplication results. However, it should be noted that these combinations of vector processing blocks provided within execution unit 84 are exemplary and not limiting. A VPE with a programmable data path configuration may be configured to include one or any other number of vector processing stages with vector processing blocks. A vector processing block may be provided to perform any type of operation according to specific vector instructions designed to be supported by the design and execution unit.

  [00258] With continued reference to FIG. 35, in this embodiment, the vector multiplication output sample sets 468 (3) -468 (0) are in the next vector processing stage, which is the M1 accumulated vector processing stage 460 (2). The plurality of accumulator blocks 472 (3) to 472 (0) are provided. Each accumulator block in the plurality of accumulator blocks 472 (A) -472 (0) is represented by two accumulators 472 (X) (1) and 472 (X) (0) (ie, 472 ( 3) (1), 472 (3) (0), 472 (2) (1), 472 (2) (0), 472 (1) (1), 472 (1) (0), and 472 (0 ) (1), 472 (0) (0)). A plurality of accumulator blocks 472 (3) -472 (0) accumulate the results of the vector multiplication output sample sets 468 (3) -468 (0). As described in more detail below with respect to FIGS. 39 and 40, a plurality of accumulator blocks 472 (3) -472 (0) may be provided as carry save accumulators, where carry The product is essentially stored and not propagated during the accumulation process until the accumulation operation is complete. The plurality of accumulator blocks 472 (3) -472 (0) are shown in FIGS. 35 and 37 to provide a redundant carry save format in the plurality of accumulator blocks 472 (3) -472 (0). There is also an option to be merged with multiple multiplier blocks 462 (3) -462 (0). By providing a redundant carry save format in the plurality of accumulator blocks 472 (3) -472 (0), each step of accumulation in the plurality of accumulator blocks 472 (3) -472 (0). In the meantime, the need to provide a carry propagation path and a carry propagation addition operation can be eliminated. The M1 accumulated vector processing stage 460 (2) and its plurality of accumulator blocks 472 (3) -472 (0) are introduced next with reference to FIG.

  [00259] Referring to FIG. 35, a plurality of accumulator blocks 472 (3) -472 (0) in the M1 accumulated vector processing stage 460 (2) are connected to accumulator output sample sets 476 (3) -476. (0) (ie, 476 (3) (1), 476 (3) (0), 476 (2) (1), 476 (2) (0), 476 (1) (1), 476 (1) (0) and 476 (0) (1), 476 (0) (0)) in accordance with a programmable output data path configuration to supply either in the next vector processing stage 460 or output processing stage , Programmable output data paths 474 (3) -474 (0) (ie, 474 (3) (1), 474 (3) (0), 474 (2) (1), 474 (2) (0) 474 (1) (1), 474 (1) (0) , And 474 (0) (1), 474 (0) (0)) are configured to accumulate vector multiplication output sample sets 468 (3) -468 (0). In this example, accumulator output sample sets 476 (3) -476 (0) are supplied to an output processing stage, which is an ALU processing stage 460 (3). For example, as described in more detail below, accumulator output sample sets 476 (3) -476 (0) are also, by way of non-limiting example, scalar processor 44 within baseband processor 20 of FIG. It can be supplied to the ALU 46 within. For example, ALU 46 may take accumulator output sample sets 476 (3) -476 (0) according to special vector instructions executed by execution unit 84 for use in more general processing operations. is there.

  [00260] Referring back to FIG. 35, the programmable input data paths 478 (3) -78 (0) and / or the programmable internal data path 480 of the accumulator blocks 472 (3) -472 (0). (3) -480 (0) can be of various combinations and / or bit lengths supplied from multiplier blocks 462 (3) -462 (0) to accumulator blocks 472 (3) -472 (0). It can be programmed to be reconfigured to receive vector multiply output sample sets 468 (3) -468 (0). Each accumulator block 472 is composed of two accumulators 472 (X) (1), 472 (X) (0), so that the programmable input data paths 478 (A) -478 (0) are 478 (3) (1), 478 (3) (0), 478 (2) (1), 478 (2) (0), 478 (1) (1), 478 (1) (0), and It is shown in FIG. 35 as 478 (0) (1), 478 (0) (0). Similarly, the programmable internal data paths 480 (3) -480 (0) are 480 (3) (1), 480 (3) (0), 480 (2) (1), 480 (2) (0 ), 480 (1) (1), 480 (1) (0), 480 (0) (1), 480 (0) (0). Provide programmable input data paths 478 (3) -478 (0) and / or programmable internal data paths 480 (3) -480 (0) in accumulator blocks 472 (3) -472 (0). This is described in more detail below with respect to FIGS. 39 and 40. In this way, the programmable input data paths 478 (3) -478 (0) and / or the programmable internal data paths 480 (3) -480 () of the accumulator blocks 472 (3) -472 (0). 0), accumulator blocks 472 (3) -472 (0) are configured to generate accumulator output sample sets according to a programmed combination of accumulated vector multiplication output sample sets 468 (3) -468 (0). 476 (3) to 476 (0) can be supplied. Again, this causes accumulator blocks 472 (3) -472 (0) to reduce the area in execution unit 84 and possibly in baseband processor 20 to perform the desired vector processing operations. Of programmable input data paths 478 (3) -478 (0) and / or programmable internal data paths 480 (3) -480 (0) to allow fewer execution units 84 to be provided. Based on programming, the flexibility is provided that can be configured and reconfigured to perform various types of accumulation operations.

  [00261] For example, in certain accumulator mode configurations, the programmable input data path 478 and / or the programmable internal data path 480 of the two accumulator blocks 472 may include a single, It can be programmed to provide a 40-bit accumulator. In another accumulator mode configuration, the programmable input data path 478 and / or the programmable internal data path 480 of the two accumulator blocks 472 are, as a non-limiting example, a double 24-bit accumulator. Can be programmed to provide In another accumulator mode configuration, the programmable input data path 478 and / or the programmable internal data path 480 of the two accumulator blocks 472 may include a 16-bit carry save adder followed by a single 24 It can be programmed to provide a bit accumulator. Various particular combinations of multiplication and accumulation operations are also used in multiplier blocks 462 (3) -462 (0) and accumulator blocks 472 (3) -472 (0) (eg, 16 using 16-bit accumulation). According to the programming of bit imaginary multiplication and 32-bit imaginary multiplication with 16-bit accumulation) may be supported by execution unit 84.

  [00262] Programmable input data paths 478 (3) -478 (0) and / or programmable internal data paths 480 (3) -480 (0) of accumulator blocks 472 (3) -472 (0). Can be programmed according to the set value supplied from the vector instruction decoder in the instruction dispatch circuit 48 of the baseband processor 20 of FIG. Vector instructions specify a particular type of operation to be performed by execution unit 84. Accordingly, execution unit 84 may implement programmable input data paths 478 (3) -478 (0) and / or programmable internal data paths 480 (3)-of accumulator blocks 472 (3) -472 (0). 480 (0) may be configured to reprogram every vector instruction executed according to the decoding of the vector instruction in the instruction pipeline in instruction dispatch circuit 48. Vector instructions may be executed over one or more clock cycles of execution unit 84. Also, in this example, execution unit 84 has a programmable input data path 478 (3) -478 (0) and / or a programmable internal data path 480 for accumulator blocks 472 (3) -472 (0). (3) -480 (0) may be configured to reprogram every clock cycle of the vector instruction every clock cycle. Thus, for example, if a vector instruction executed by M1 accumulated vector processing stage 460 (2) in execution unit 84 processes vector multiply output sample sets 468 (3) -468 (0) every clock cycle, As a result, programmable input data paths 478 (3) -478 (0) and / or programmable internal data paths 480 (3) -480 (0) of accumulator blocks 472 (3) -472 (0). Can be reconfigured every clock cycle during execution of a vector instruction.

  [00263] FIG. 36 provides multiplier blocks 462 (A) -462 (0) and accumulator block 472 within execution unit 84 of FIGS. 2 and 35 to provide further explanation of exemplary vector processing. It is a flowchart which shows the exemplary vector processing of (A) (1) -472 (0) (0). Multiplier blocks 462 (A) through 462 (0) and accumulator blocks 472 (A) (1) through 472 (0) (0) each have a programmable data path configuration and are shown in FIGS. Are provided in various vector processing stages within the exemplary execution unit 84. For example, an FFT vector operation involves a multiplication operation followed by an accumulation operation.

  [00264] In this regard, with respect to FIG. 36, the vector processing is performed by a plurality of multiplication vectors of the width of the vector array in the input data paths in the plurality of input data paths A3-C0 in the input processing stage 460 (0). Receiving data sample sets 34 (Y) -34 (0) is received (block 501). The vector processing then receives the multiplication vector data sample sets 34 (Y) -34 (0) from the plurality of input data paths A3-C0 in the plurality of multiplier blocks 462 (A) -462 (0). (Block 503). Vector processing then outputs a plurality of multiply outputs based on a programmable data path configuration for multiplier blocks 462 (A) -462 (0) according to vector instructions executed by vector processing stage 460 (1). To provide multiplication vector result output sample sets 468 (A) -468 (0) in multiplication output data paths 470 (A) -470 (0) in data paths 470 (A) -470 (0), Multiplying the multiplication vector data sample sets 34 (Y) -34 (0) (block 505). The vector processing then outputs the multiplication vector result from the plurality of multiplication output data paths 470 (A) to 470 (0) in the plurality of accumulator blocks 472 (A) (1) to 472 (0) (0). Receiving sample sets 468 (A) -468 (0) (block 507). The vector processing is then programmable for the accumulator blocks 472 (A) (1) -472 (0) (0) according to the vector instructions executed by the second vector processing stage 460 (2). Input data path 478 (A) (1) -478 (0) (0), programmable internal data path 480 (A) (1) -480 (0) (0), and programmable output data path 474 ( A) Multiplication vector result output to provide accumulator output sample sets 476 (A) (1) -476 (0) (0) based on the configuration of (1) -474 (0) (0) The sample sets 468 (A) -468 (0) are accumulated together (block 509). Vector processing is then performed by accumulator output sample sets 476 (A) (1) -476 (0) (0) in programmable output data paths 474 (A) (1) -474 (0) (0). (Block 511). Vector processing then proceeds from accumulator blocks 472 (A) (1) -472 (0) (0) in output vector processing stage 460 (3) to accumulator output sample set 476 (A) (1)- Receiving 476 (0) (0) (block 513).

  [00265] Having described the exemplary execution unit 84 of FIG. 35 and the vector processing of FIG. 36 utilizing a vector processing block having a programmable data path configuration, the remainder of the description is shown in FIGS. More exemplary, non-limiting details of these vector processing blocks at 40 are described.

  [00266] In this regard, FIG. 37 is a more detailed schematic diagram of a plurality of multiplier blocks 462 (3) -462 (0) in the M0 multiplication vector processing stage 460 (1) of the execution unit 84 of FIG. is there. FIG. 38 is a schematic diagram of the internal components of the multiplier block 462 of FIG. As shown in FIG. 37, vector data input sample set 466 () received by multiplier blocks 462 (3) -462 (0) according to specific input data paths A3-A0, B3-B0, C3-C0. 11) to 466 (0) are shown. As will be described in more detail below with respect to FIG. 38, each of multiplier blocks 462 (3) -462 (0) in this example includes four 8-bit × 8-bit multipliers. Referring back to FIG. 37, each of the multiplier blocks 462 (3) -462 (0) in this example is to multiply the multiplicand input “A” with either the multiplicand input “B” or the multiplicand input “C”. Configured. The multiplicand inputs “A” and “B” or “C” that can be multiplied together in the multiplier block 462 are represented by which input data paths A3-A0, B3-B0, C3-C0 as shown in FIG. It is controlled depending on whether it is connected to the multiplier blocks 462 (3) to 462 (0). The multiplicand selector inputs 482 (3) -482 (0) are each selected to select which multiplicand input “B” or multiplicand input “C” is selected to be multiplied with the multiplicand input “A”. Input to each multiplier block 462 (3) -462 (0) to control programmable internal data paths 467 (3) -467 (0) in multiplier blocks 462 (3) -462 (0). Supplied as In this way, multiplier blocks 462 (3) -462 (0) allow their programmable internal data paths 467 (3) -467 (0) to provide various multiplication operations as needed. Provided with the ability to be reprogrammed.

  [00267] With continued reference to FIG. 37, using multiplier block 462 (3) as an example, input data paths A3 and A2 are connected to inputs AH and AL, respectively. The input AH represents the upper bit of the multiplicand input A, and AL means the lower bit of the input multiplicand input “A”. Input data paths B3 and B2 are connected to inputs BH and BL, respectively. The input BH represents the upper bits of the multiplicand input “B”, and AL represents the lower bits of the input multiplicand input “B”. Input data paths C3 and C2 are connected to inputs CI and CQ, respectively. Input CI represents the real bit portion of input multiplicand input “C” in this example. CQ represents the imaginary bit portion of the input multiplicand input “C” in this example. As described in more detail below with respect to FIG. 38, the multiplicand selector input 482 (3) is also, in this example, the programmable internal data path 467 (3) of the multiplier block 462 (3). Is configured to perform 8-bit multiplication on input “A” with either multiplicand input “B” or multiplicand input “C”, or multiplier block 462 (3) is 16 bits on multiplicand input “A”? Controls whether multiplication is performed with multiplicand input “B” or multiplicand input “C”.

  [00268] With continued reference to FIG. 37, multiplier blocks 462 (3) -462 (0) each multiply based on the configuration of their programmable internal data paths 467 (3) -467 (0). Vector multiplication output sample sets 468 (3) to 468 (0) are generated as vector output sample sets of the arithmetic carry "C" and the sum "S". As described in more detail below with respect to FIGS. 39 and 40, the carry “C” and the sum “S” of the vector multiplication output sample sets 468 (3) -468 (0) are merged and the carry “C” ”And the sum“ S ”to provide a redundant carry save format in the plurality of accumulator blocks 472 (3) to 472 (0), the plurality of accumulator blocks 472 (3) to 472 (0). Is supplied in redundant carry save format. As described in more detail below, a plurality of accumulator blocks 472 (3) -472 are provided by providing a redundant carry save format in the plurality of accumulator blocks 472 (3) -472 (0). During the accumulation operation performed by (0), the need to provide a carry propagation path and a carry propagation add operation can be eliminated.

  [00269] Vector multiplication output samples as a vector output sample set of carry "C" and sum "S" multiplication operations based on the configuration of their programmable internal data paths 467 (3) -467 (0) An example of multiplier blocks 462 (3) -462 (0) that generate sets 468 (3) -468 (0) is shown in FIG. For example, multiplier block 462 (3) generates carry C00 and sum S00 as a 32-bit value for 8-bit multiplication, and carries C01 and sum S01 as a 64-bit value for 16-bit multiplication. Configured to generate. The other multiplier blocks 462 (2) -462 (0) have the same capabilities in this example. In this regard, multiplier block 462 (2) generates carry C10 and sum S10 as a 32-bit value for 8-bit multiplication and carry C11 and sum S11 as a 64-bit value for 16-bit multiplication. And is configured to generate Multiplier block 462 (1) generates carry C20 and sum S20 as 32-bit values for 8-bit multiplication and generates carry C21 and sum S21 as 64-bit values for 16-bit multiplication. Configured as follows. Multiplier block 462 (0) generates carry C30 and sum S30 as 32-bit values for 8-bit multiplication and generates carry C31 and sum S31 as 64-bit values for 16-bit multiplication. Configured as follows.

  [00270] FIG. 38 is provided to describe more illustrative details of the programmable data path configuration provided within the multiplier block 462 of FIG. FIG. 38 illustrates the multiplication of FIG. 37 with a programmable data path configuration capable of multiplying an 8 bit × 8 bit vector data input sample set 466 and a 16 bit × 16 bit vector data input sample set 466. 3 is a schematic diagram of the internal components of the instrument block 462; In this regard, multiplier block 462 includes four 8 × 8 bit multipliers 484 (3) -484 (0) in this example. Any desired number of multipliers 484 may be provided. The first multiplier 484 (3) receives the 8-bit vector data input sample set 466A [H] (which is the upper bits of the input multiplicand input “A”), and receives the vector data input sample set 466A [H] as Of the 8-bit vector data input sample set 466B [H] (which is the upper bit of the input multiplicand input “B”) or the 8-bit vector data input sample set 466C [I] (which is the upper bit of the input multiplicand input “C”) Configured to multiply with either. Multiplexer 486 configured to select either 8-bit vector data input sample set 466B [H] or 8-bit vector data input sample set 466C [I] being supplied as a multiplicand to multiplier 484 (3) (3) is provided. Multiplexer 486 (3) is controlled by multiplicand selector input 482 [3], which in this embodiment is the upper bit in multiplicand selector input 482. In this way, multiplexer 486 (3) and multiplicand selector input 482 [3] received either 8-bit vector data input sample set 466B [H] or 8-bit vector data input sample set 466C [I]. A programmable internal data path 467 [0] configuration is provided for the multiplier 484 (3) to control whether the vector data input sample set 466A [H] is multiplied.

  [00271] With continued reference to FIG. 38, the other multipliers 484 (2) -484 (0) are also programmable internal data paths 467 similar to those provided for the first multiplier 484 (3). [2] to 467 [0] are included. Multiplier 484 (2) is an 8-bit vector data input sample set 466B [H] or an 8-bit vector to be multiplied with the 8-bit vector data input sample set 466A [L], which is the lower bits of the multiplicand input “A”. A programmable internal data path 467 [2] having a programmable configuration for providing any of the data input sample sets 466C [I] into the programmable internal data path 467 [1] is included. Selection is controlled by multiplexer 486 (2) in this embodiment according to multiplicand selector input 482 [2] in multiplicand selector input 482. Multiplier 484 (1) is an 8-bit vector data input sample set 466B [L] or multiplicand input that is a lower bit of multiplicand input “B” to be multiplied with 8-bit vector data input sample set 466A [H]. Programmable internal data path programmable to supply any of the 8-bit vector data input sample set 466C [Q], the lower bits of “C”, into the programmable internal data path 467 [1] 467 [1]. Selection is controlled by multiplexer 486 (1) in this embodiment according to multiplicand selector input 482 [1] in multiplicand selector input 482. Furthermore, the multiplier 484 (0) is to be multiplied by the 8-bit vector data input sample set 466A [L], and the 8-bit vector data input sample set 466B [L] or the 8-bit vector data input sample set 466C [Q]. Of the programmable internal data path 467 [0], which is programmable to be fed into the programmable internal data path 467 [0]. Selection is controlled in this embodiment by multiplexer 486 (0) according to multiplicand selector bit input 482 [0] in multiplier selector input 482.

  [00272] With continued reference to FIG. 38, as described above, the multipliers 484 (3) -484 (0) may be configured to perform various bit-length multiplication operations. In this regard, each multiplier 484 (3) -484 (0) includes a bit length multiplication mode input 488 (3) -488 (0), respectively. In this example, each multiplier 484 (3) -484 (0) has a programmable data path 490 (3) -490 (0), 491 and 492 (3) -492 (0) configuration, respectively. Depending on the input to be controlled, it can be programmed in 8 bit x 8 bit mode. Each multiplier 484 (3) -484 (0) also has an input that controls the configuration of programmable data paths 490 (3) -490 (0), 491, and 492 (3) -492 (0), respectively. Can be programmed to provide some of the larger bit multiplication operations, including 16 bit × 16 bit mode and 24 bit × 8 bit mode. For example, if each multiplier 484 (3) -484 (0) is configured in an 8-bit × 8-bit multiplication mode according to the configuration of programmable data paths 490 (3) -490 (0), multiple units as units Multipliers 484 (3)-484 (0) may be configured to include two individual 8-bit × 8-bit multipliers as part of multiplier block 462. When each multiplier 484 (3) -484 (0) is configured in a 16-bit × 16-bit multiplication mode according to the configuration of the programmable data path 491, a plurality of multipliers 484 (3) -484 ( 0) may be configured to comprise a single 16 bit × 16 bit multiplier as part of the multiplier block 462. When multipliers 484 (3) -484 (0) are configured in 24-bit × 8-bit multiplication mode according to the configuration of programmable data paths 492 (3) -492 (0), multiple multipliers as a unit 484 (3)-484 (0) may be configured with one 16-bit × 24-bit × 8-bit multiplier as part of the multiplier block 462.

  [00273] With continued reference to FIG. 38, the multipliers 484 (3) -484 (0) in this example are shown as configured in a 16-bit × 16-bit multiplication mode. A 16-bit input sum 494 (3), 494 (2) and an input carry 496 (3), 496 (2) are generated by each multiplier 484 (3), 484 (2), respectively. A 16-bit input sum 494 (1), 494 (0) and an input carry 496 (1), 496 (0) are generated by each multiplier 484 (1), 484 (0), respectively. The 16-bit input sums 494 (3), 494 (2) and the input carry 496 (3), 496 (2) are also combined with the input sums 494 (3) -494 (0) and the input carry 496 (3 ) To 496 (0) to the 24-bit 4: 2 compressor 515 along with the 16-bit sum inputs 494 (1), 494 (0) and the input carry 496 (1), 496 (0). Supplied. For the added input sums 494 (3) -494 (0) and input carry 496 (3) -496 (0), the programmable data path 491 is active and the input sums 494 (3) -494 (0) ) And input carry 496 (3) -496 (0), yielding a single sum 498 and a single carry 500 in 16 bit × 16 bit multiply mode. Programmable data path 491 is a first AND-based having a combined input sum 494 (3), 494 (2) as a 16-bit word to be fed to a 24-bit 4: 2 compressor 515. Gated by gate 502 (3) and as a 16-bit word by a second AND-based gate 502 (2) having combined input carry 496 (3), 496 (2). Programmable data path 491 is also a third AND base with input sums 494 (1), 494 (0) combined as a 16-bit word to be fed to 24-bit 4: 2 compressor 515. Gate 502 (1) and as a 16-bit word by a fourth AND-based gate 502 (0) with combined input carry 496 (1), 496 (0). When multiplier block 462 is configured in 16-bit × 16-bit multiplication mode or 24-bit × 8-bit multiplication mode, programmable output data path 470 [0] has a compressed 32-bit sum S0 and a 32-bit carry. A vector multiplication output sample set 468 [0] is supplied as the C0 partial product.

  [00274] When the multipliers 484 (3) -484 (0) in the multiplier block 462 are configured in an 8 bit x 8 bit multiplication mode, the programmable output data path 470 [1] configuration is not compressed. , 16-bit input sums 494 (3) -494 (0) and the corresponding 16-bit input carry 496 (3) -496 (0) as partial products. When the multipliers 484 (3) -484 (0) in the multiplier block 462 are configured in an 8 bit × 8 bit multiplication mode, the programmable output data path 470 [1] is 16-bit input without compression. Sums 494 (3) -494 (0) and corresponding 16-bit input carry 496 (3) -496 (0) as vector multiplication output sample set 468 [1] are provided. The vector multiplication output sample set 468 [0], 468 [1] depending on the multiplication mode of the multiplier block 462 is an accumulator block for accumulation of sum and carry products according to the vector instruction being executed. 472 (3) to 472 (0).

  [00275] Since the multiplier blocks 462 (3) -462 (0) of FIGS. 37 and 38 having a programmable data path configuration have been described, the accumulator block 472 configured in a redundant carry save format. The features of multiplier blocks 462 (3) -462 (0) in execution unit 84 to be merged with (3) -472 (0) are outlined below with respect to FIG.

  [00276] In this regard, FIG. 39 is a generalized schematic of the multiplier and accumulator blocks in the execution units 84 (0) -84 (X) described above, where accumulation is The generator block utilizes a carry save accumulator structure that utilizes a redundant carry save format to reduce carry propagation. As previously described and illustrated in FIG. 38, the multiplier block 462 multiplies the multiplicand inputs 466 [H] and 466 [L] to produce at least one input sum 494 and at least one input carry 496. Are provided in a programmable output data path 470 as a vector multiplication output sample set 468. At least one in vector multiply output sample set 468 in programmable output data path 470 to eliminate the need for a carry propagation path and carry propagation adder in accumulator block 472 for each accumulation step. One input sum 494 and at least one input carry 496 are fused to at least one accumulator block 472 in a redundant carry save format. In other words, the carry 496 in the vector multiply output sample set 468 is provided to the accumulator block 472 as a vector input carry 496 in a carry save format. In this way, the input sum 494 and input carry 496 in the vector multiply output sample set 468 can be provided to the compressor 508 of the accumulator block 472, which in this embodiment is a composite gate 4: 2 compressor. The compressor 508 is configured to accumulate the input sum 494 and the input carry 496 together with the previous accumulated vector output sum 512 and the previous shifted accumulated vector output carry 517, respectively. The previous shifted accumulation vector output carry 517 is essentially a stored carry accumulation during the accumulation operation.

  [00277] Thus, only a single final carry propagation adder is required to propagate the received input carry 496 to the input sum 494 as part of the accumulation generated by the accumulator block 472. Must be provided in the accumulator block 472. During each step of accumulation in accumulator block 472, the power consumption associated with performing carry propagation addition operations is reduced in this embodiment. Also, the gate delay associated with performing carry propagation addition operations during each step of accumulation in accumulator block 472 is also not in this embodiment.

  [00278] With continued reference to FIG. 39, the compressor 508 converts the input sum 494 and the input carry 496 in redundant form to the previous accumulated vector output sum 512 and the previous shifted accumulated vector output, respectively. It is configured to accumulate with carry 517. The shifted accumulated vector output carry 517 shifts the accumulated vector output carry 514 before the next accumulation of the next received input sum 494 and input carry 496 is performed by the compressor 508. Is generated by the accumulated vector output carry 514 generated by the compressor 508. The final shifted accumulated vector output carry 517 propagates the carry accumulation within the final shifted accumulated vector output carry 517 to produce the final accumulated vector output sum 512 as the final accumulated. Is added to the final accumulated vector output sum 512 by a single final carry propagation adder 519 provided in the accumulator block 472 for conversion to the complement representation of the generator output sample set 4762. The final accumulated vector output sum 512 is provided in the programmable output data path 474 as an accumulator output sample set 476 (see FIG. 35).

  [00279] Since FIG. 39 illustrating the fusion of multiplier block 462 with accumulator block 472 configured in a redundant carry save format has been described, more about accumulator blocks 472 (3) -472 (0). Exemplary details are outlined herein with respect to FIG. FIG. 40 is a detailed schematic diagram of exemplary internal components of accumulator block 472 provided within execution unit 84 of FIG. As previously described and described in more detail below, accumulator block 472 may include programmable input data paths 478 (3) -478 (0) and / or programmable internal data path 480 (3 ) -480 (0) so that accumulator block 472 can be programmed to act as a dedicated circuit designed to perform certain different types of vector accumulation operations. For example, accumulator block 472 may be programmed to provide a number of different accumulations and additions, including signed and unsigned accumulation operations. Programmable input data path 478 (3) -478 (0) and / or programmable internal data path 480 (3) in accumulator block 472 configured to provide various types of accumulation operations. ) To 480 (0) are disclosed. Accumulator block 472 also carries carry saves to provide redundant carry arithmetic to avoid or reduce carry propagation to provide fast accumulation operations using reduced combinatorial logic. The accumulators 472 [0] and 472 [1] are included.

  [00280] Exemplary internal components of accumulator block 472 are shown in FIG. As shown therein, the accumulator block 472 in this embodiment has a first input sum 494 [0] and a first input carry 496 [0] to be accumulated together. , A second input sum 494 [1] and a second input carry 496 [1] are configured to be received from multiplier block 462. With respect to FIG. 40, the input sums 494 [0], 494 [1] and the input carry 496 [0], 496 [1] are the vector input sums 494 [0], 494 [1] and the vector input carry 496 [0]. ] 496 [1]. As described above and shown in FIG. 39, the vector input sums 494 [0], 494 [1] and the vector input carry 496 [0], 496 [1] in this embodiment are each 16 bits in length. It is. The accumulator block 472 in this example is provided as two 24-bit carry save accumulator blocks 472 [0], 472 [1], where “[0]” is the carry save accumulator 472 [0]. Each contains similar components with a common element number, designated for use with “[1]” designated for carry save accumulator 472 [1]. The carry save accumulators 472 [0], 472 [1] may be configured to perform vector accumulation operations simultaneously.

  [00281] Referring to the carry save accumulator 472 [0] of FIG. 40, the vector input sum 494 [0] and the vector input carry 496 [0] are part of the programmable internal data path 480 [0]. This is an input in a multiplexer 504 (0) provided as a unit. According to input 521 (0) as an input to multiplexer 504 (0) for an accumulation operation requiring a negative vector input sum 494 [0] 'and a negative vector input carry 496 [0]'. Also provided is a negation circuit 506 (0), which may consist of an exclusive OR-based gate, that produces a negative vector input sum 494 [0] 'and a negative vector input carry 496 [0]'. Multiplexer 504 (0) generates vector input sum 494 [0] and vector input carry 496 to be supplied to compressor 508 (0) according to selector input 510 (0), generated as a result of vector instruction decoding. [0], or a negative vector input sum 494 [0] ′ and a negative vector input carry 496 [0] ′. In this regard, the programmable input data path 478 of the carry save accumulator 472 [0] according to the accumulation operation configured to be performed by the accumulator block 472 with the selector input 510 (0). [0] compresses either vector input sum 494 [0] and vector input carry 496 [0], or negative vector input sum 494 [0] 'and negative vector input carry 496 [0]' It can be programmed to feed to the device 508 (0).

  [00282] With continued reference to FIG. 40, the compressor 508 (0) of the carry save accumulator block 472 [0] in this embodiment is a composite gate 4: 2 compressor. In this regard, the compressor 508 (0) is configured to accumulate the sum and carry in a redundant carry save operation. The compressor 508 (0) has four inputs to the compressor 508 (0) as a current vector input sum 494 [0] and a vector input carry 496 [0], or a current negative vector input sum 494 [ 0] 'and negative vector input carry 496 [0]', the previous accumulated vector input sum 494 [0] and vector input carry 496 [0], or the accumulated negative vector input sum 494 [0] ′ and negative vector input carry 496 [0] ′ are configured to accumulate together. Compressor 508 (0) provides accumulator output in programmable output data path 474 [0] (see FIG. 35) to provide accumulator output sample sets 476 (3) -476 (0). As a sample set 476 [0], an accumulated vector output sum 512 (0) and an accumulated vector output carry 514 (0) are supplied. Accumulated vector output carry 514 (0) is performing an accumulation operation to provide a shifted accumulated vector output carry 517 (0) to control bit width growth during each accumulation step. Shifted by the bit shifter 516 (0). For example, bit shifter 516 (0) in this embodiment is a barrel shifter that is fused to compressor 508 (0) in a redundant carry save format. In this way, the shifted accumulated vector output carry 517 (0) is essentially the accumulated vector output sum 512 (0) during the accumulation operation performed by accumulator block 472 [0]. ) Stored without having to be propagated to. In this way, the power consumption and gate delay associated with performing carry propagation addition operations during each step of accumulation in accumulator block 472 [0] is not in this embodiment.

  [00283] Further subsequent vector input sum 494 [0] and vector input carry 496 [0], or negative vector input sum 494 [0] 'and negative vector input carry 496 [0]' The accumulated vector output sum 512 (0) and the current accumulated vector output carry 517 (0) may be accumulated. Vector input sum 494 [0] and vector input carry 496 [0], or negative vector input sum 494 [0] 'and negative vector input carry 496 [0]' are generated as a result of vector instruction decoding. Also selected by multiplexer 518 (0) as part of a programmable internal data path 480 [0] according to sum carry selector 520 (0). The current accumulated vector output sum 512 (0) and the current shifted accumulated vector output carry 517 (0) are stored in the carry save accumulator block 472 [0] by the updated accumulated vector output sum. To provide 512 (0) and accumulated vector output carry 514 (0), it can be provided as an input to compressor 508 (0). In this regard, the sum carry selector 520 (0) is configured such that the accumulator block 472 [0] programmable internal data path 480 [0] is executed by the accumulator block 472. According to the accumulation operation, the compressor 508 (0) can be programmed to supply a vector input sum 494 [0] and a vector input carry 496 [0]. Accumulated vector output sum 512 (0) and shifted accumulated vector output carry according to hold state input 526 (0) to control the operation timing of accumulation in carry save accumulator block 472 [0]. In order to hold the current state of 517 (0) in multiplexer 518 (0), hold gates 522 (0) and 524 (0) are also provided in this embodiment.

  [00284] With continued reference to FIG. 40, the accumulated vector output sum 512 (0) and shifted accumulated vector output carry 517 (0) of the carry save accumulator block 472 [0] and carry save. Accumulated vector output sum 512 (1) and shifted accumulated vector output carry 517 (1) of accumulator block 472 [1] are control gates 534 (0), 536 (0) and 534 ( 1) Gate controlled by 536 (1). Control gates 534 (0), 536 (0) and 534 (1), 536 (1) are fed back to compressors 508 (0), 508 (1), respectively, with accumulated vector output sums 512 (0) and Controls the shifted accumulated vector output carry 517 (0), the accumulated vector output sum 512 (1) and the shifted accumulated vector output carry 517 (1).

  [00285] In summary, the accumulator blocks 472 [0], 472 [1] of the accumulator block 472 of FIG. 40, the programmable input data paths 478 [0], 478 [1] and the programmable internal data. Passes 480 [0], 480 [1] allow accumulator block 472 to be configured in various modes. Accumulator block 472 may be configured to provide various accumulator operations according to specific vector processing instructions by the common accumulator circuit shown in FIG.

  [00286] A VPE according to the concepts and embodiments described herein may be provided within any processor-based device or may be integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, mobile phones, mobile phones, computers, portable computers, desktop computers, personal digital assistants ( PDA), monitor, computer monitor, television, tuner, radio, satellite radio, music player, digital music player, portable music player, digital video player, video player, digital video disc (DVD) player, and portable digital video player included.

  [00287] In this regard, FIG. 41 illustrates an example of a processor-based system 550. In this example, processor-based system 550 includes one or more processing units (PUs) 552 that each include one or more processors or cores 554. The PU 552 may be the baseband processor 20 of FIG. 2 as a non-limiting example. The processor 554 may be a vector processor such as the baseband processor 20 provided in FIG. 2 as a non-limiting example. In this regard, the processor 554 may include a VPE 556 that includes, but is not limited to, the execution unit 84 of FIG. The PU 552 may have a cache memory 558 coupled to the processor 554 for high speed access to temporarily stored data. The PU 552 is coupled to the system bus 560 and can interconnect the master and slave devices included in the processor-based system 550. As is well known, the PU 552 communicates with these other devices by exchanging address, control, and data information via the system bus 560. For example, PU 552 can communicate a bus transaction request to memory controller 562 as an example of a slave device. Although not shown in FIG. 41, multiple system buses 560 may be provided, where each system bus 560 comprises a different fabric.

  [00288] Other master and slave devices may be connected to the system bus 560. As shown in FIG. 41, these devices include, by way of example, a memory system 564, one or more input devices 566, one or more output devices 568, one or more network interface devices 570, And one or more display controllers 572 may be included. Memory system 564 may include memory 565 that is accessible by memory controller 562. Input device 566 can include any type of input device, including but not limited to input keys, switches, voice processors, and the like. The output device 568 can include any type of output device, including but not limited to audio, video, other visual indicators, and the like. Network interface device 570 may be any device configured to allow data exchange with network 574. The network 574 can be any type of network including, but not limited to, a wired or wireless network, a dedicated or public network, a local area network (LAN), a wide local area network (WLAN), and the Internet. . Network interface device 570 may be configured to support any type of communication protocol desired.

  [00289] PU 552 may also be configured to access display controller 572 via system bus 560 to control information sent to one or more displays 578. Display controller 572 sends information to be displayed via one or more video processors 580 to display 578, which processes the information to be displayed into a format suitable for display 578. Display 578 can include any type of display, including but not limited to a cathode ray tube (CRT), liquid crystal display (LCD), plasma display, and the like.

  [00290] The various exemplary logic blocks, modules, circuits, and algorithms described with the dual voltage domain memory buffer embodiments disclosed herein may be implemented as electronic hardware, memory or another computer readable. Those skilled in the art will further appreciate that they can be implemented as instructions stored on a medium and executed by a processor or other processing device, or as a combination of both. The arbiters, master devices, and slave devices described herein may be utilized by way of example in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this compatibility, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in a variety of ways for a particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

  [00291] Various exemplary logic blocks, modules, and circuits described with respect to the embodiments disclosed herein may be a processor, DSP, application specific integrated circuit (ASIC), FPGA, or other programmable logic device. May be implemented or implemented using discrete gates or transistors, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor is also implemented as a combination of computing devices, eg, a DSP and microprocessor combination, a plurality of microprocessors, one or more microprocessors associated with a DSP core, or any other such configuration. There is a case.

  [00292] The embodiments disclosed herein may be embodied in hardware and in instructions stored in hardware, eg, random access memory (RAM), flash memory, read-only memory. (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), register, hard disk, removable disk, CD-ROM, or any other known in the art In the form of a computer readable medium. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in the remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

  [00293] It should also be noted that the operational steps described in any of the exemplary embodiments herein have been described to provide examples and explanations. The described operations may be performed in a number of different sequences other than the illustrated sequence. Furthermore, the operations described in a single operation step may actually be performed in several different steps. Further, one or more of the operational steps described in the exemplary embodiments may be combined. It should be understood that the operational steps shown in the flowchart diagrams may be subject to many different modifications, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description are voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any of them May be represented by a combination.

  [00294] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. is there. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (27)

A vector processing engine (VPE) configured to in-flight merge a resulting output vector data sample set generated by at least one execution unit that performs vector processing operations;
Providing an input vector data sample set fetched in at least one input data flow path for vector processing operations;
Receiving at least one merged resulting output vector data sample set from at least one output data flow path to be stored; and at least one vector data file
Receiving the input vector data sample set on the at least one input data flow path;
Performing the vector processing operation on the input vector data sample set to provide a resulting output vector data sample set on the at least one output data flow path; At least one execution unit provided in the at least one input data flow path;
Receiving the resulting output vector data sample set;
The resulting output to provide at least one merged resulting output vector data sample set without the resulting output vector data sample set being stored in the at least one vector data file. Merging vector data sample sets;
VPE comprising: at least one merging circuit configured to provide the at least one merged resulting output vector data sample set on the at least one output data flow path. The at least one vector data file is
Providing the input vector data sample set of the width of the at least one vector data file in the at least one input data flow path for the vector processing operation;
Receiving the at least one merged resulting output vector data sample set of the width of the at least one vector data file from the at least one output data flow path to be stored. The VPE of claim 1. The at least one vector data file is
Providing the input vector data sample set on at least one vector data file output in the at least one input data flow path;
Receiving the at least one merged resulting output vector data sample set on at least one vector data file input in the at least one output data flow path; and
The at least one execution unit is
Receiving the input vector data sample set on at least one execution unit input in the at least one input data flow path;
Multiplying the input vector data sample set with a code sequence vector data sample set to provide the resulting output vector data sample set on at least one execution unit output in the at least one input data flow path; Configured to do
The at least one merging circuit comprises:
Receiving from the at least one execution unit the resulting output vector data sample set on at least one merging circuit input in the at least one input data flow path;
The method of claim 1, further comprising: providing the merged resulting output vector data sample set on at least one merging circuit output in the at least one output data flow path. VPE. The merging circuit outputs at least two resulting output vector data samples in the resulting output vector data sample set to provide the at least one merged resulting output vector data sample set. Consisting of at least one adder configured to merge;
The VPE of claim 1. The at least one adder is composed of a plurality of adders provided in an adder tree, and each of the plurality of adders results in a plurality of addition merges each having a different bit width. Configured to provide an output vector data sample set,
The VPE according to claim 4. The merging circuit has two vector results in the resulting output vector data sample set having a larger vector data value to provide the at least one merged resulting output vector data sample set. Consisting of at least one maximum vector data sample selector configured to maximum merge the resulting output vector data samples between the resulting output vector data samples.
The VPE of claim 1. The at least one maximum vector data sample selector is a plurality of maximum value data, each configured to provide a plurality of maximum merged resulting output vector data sample sets, each having a different bit width. Consists of sample selectors,
The VPE according to claim 6. The merging circuit has two, as a result, in the resulting output vector data sample set having smaller vector data values to provide the at least one merged resulting output vector data sample set. Consisting of at least one minimum vector data sample selector configured to minimally merge the resulting output vector data samples between the resulting output vector data samples;
The VPE of claim 1. The at least one minimum vector data sample selector is a plurality of minimum value data, each configured to provide a plurality of minimum merged resulting output vector data sample sets, each having a different bit width. Consists of sample selectors,
The VPE according to claim 8. The merging circuit further comprises a merge selector configured to select one of the at least one merged resulting output vector data sample set.
The VPE according to claim 4. The code sequence vector data sample set is composed of at least one CDMA chip code sequence;
The VPE of claim 1. The at least one merging circuit is configurable to be reconfigured based on a programmable merge data path configuration input to selectively merge the resulting output vector data sample set.
The VPE of claim 1. The at least one merging circuit is configured to selectively merge the resulting output vector data sample set every clock cycle of the VPE to be executed by the at least one execution unit. Further configured to be reconfigured based on the data path configuration input;
The VPE of claim 12. The at least one merging circuit is configured to selectively merge the resulting output vector data sample set on a next vector instruction to be executed by the at least one execution unit. Further configured to be reconfigured based on the path configuration input;
The VPE of claim 12. The at least one merging circuit further comprises a plurality of latches, and the at least one merging circuit is further configured to store the at least one merged resulting output vector data sample set in the plurality of latches. Composed,
The VPE of claim 1. The at least one merging circuit is further configured to store the at least one merged resulting output vector data sample set in a selected latch of the plurality of latches;
The VPE of claim 15. The at least one merging circuit further comprises a plurality of selectors corresponding to the plurality of latches, and the at least one merging circuit is merged with the selected latches in the plurality of latches. And configured to control a selector among the plurality of selectors to store the resulting output vector data sample set.
The VPE of claim 16. The at least one merging circuit provides the at least one merged resulting output vector data sample set in the at least one output data flow path for storage in the at least one vector data file. Previously configured to store the at least one merged resulting output vector data sample set in the plurality of latches;
The VPE of claim 17. The at least one execution unit is configured to process different bit widths of input vector data samples from the input vector data sample set based on a programmable input data flow path configuration for the at least one execution unit. Is configurable,
The VPE of claim 1. A vector processing engine (VPE) configured to in-flight merge a resulting output vector data sample set generated by at least one execution unit that performs vector processing operations;
Means for providing a set of input vector data samples fetched into at least one input data flow path means for vector processing operations;
Means for receiving at least one merged resulting output vector data sample set from at least one output data flow path means to be stored; and at least one vector data file means
Means for receiving the input vector data sample set on the at least one input data flow path means;
Execution means for performing the vector processing operation on the input vector data sample set to provide a resulting output vector data sample set on the at least one input data flow path means, At least one execution unit means provided in the at least one input data flow path means;
Means for receiving the resulting output vector data sample set;
The resulting output vector data sample set is generated to provide at least one merged resulting output vector data sample set without being stored in the at least one vector data file means. Merging means for merging an output vector data sample set with the code sequence vector data sample set;
A vector processing engine comprising: at least one merging circuit means comprising: means for providing the at least one merged resulting output vector data sample set on the at least one output data flow path means. VPE). A method for in-flight merging a resulting set of output vector data samples generated by at least one execution unit that performs vector processing operations, comprising:
Providing an input vector data sample set fetched from at least one vector data file into at least one input data flow path for vector processing operations;
Receiving the input vector data sample set on the at least one input data flow path in at least one execution unit provided in the at least one input data flow path;
Performing the vector processing operation on the input vector data sample set to provide a resulting output vector data sample set on the at least one input data flow path;
The resulting output to provide at least one merged resulting output vector data sample set without the resulting output vector data sample set being stored in the at least one vector data file. Merging vector data sample sets;
Storing the at least one merged resulting output vector data sample set from the at least one output data flow path in the at least one vector data file. The merging of the resulting output vector data sample sets occurs in the at least one adder to provide the at least one merged resulting output vector data sample set. Further comprising adding the merge samples in the output vector data sample set;
The method of claim 21. The at least one adder is comprised of a plurality of adders provided in an adder tree, each of the plurality of adders having a plurality of merged resulting outputs, each having a different bit width. Configured to supply a vector data sample set,
The method of claim 22. Selecting one of the plurality of resulting output vector data sample sets to provide as the at least one resulting output vector data sample set within the at least one output data flow path. Prepare
24. The method of claim 23. Receiving programmable merge data path configuration inputs; and
22. The method of claim 21, further comprising: selectively merging the resulting output vector data sample set based on the programmable merge data path configuration input. Further comprising selectively merging the resulting output vector data sample sets for each clock cycle of a VPE to be executed by the at least one execution unit;
26. The method of claim 25. Further comprising selectively merging the resulting output vector data sample sets for a next vector instruction to be executed by the at least one execution unit.
26. The method of claim 25.

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