JP2016537725A - 実行ユニットとベクトルデータメモリとの間のデータフローパスにおいて逆拡散回路を利用するベクトル処理エンジン、および関連する方法 - Google Patents
実行ユニットとベクトルデータメモリとの間のデータフローパスにおいて逆拡散回路を利用するベクトル処理エンジン、および関連する方法 Download PDFInfo
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- JP2016537725A JP2016537725A JP2016531024A JP2016531024A JP2016537725A JP 2016537725 A JP2016537725 A JP 2016537725A JP 2016531024 A JP2016531024 A JP 2016531024A JP 2016531024 A JP2016531024 A JP 2016531024A JP 2016537725 A JP2016537725 A JP 2016537725A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
- G06F9/38873—Iterative single instructions for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Computational Mathematics (AREA)
- Computer Hardware Design (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
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- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/082,067 | 2013-11-15 | ||
| US14/082,067 US20150143076A1 (en) | 2013-11-15 | 2013-11-15 | VECTOR PROCESSING ENGINES (VPEs) EMPLOYING DESPREADING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY TO PROVIDE IN-FLIGHT DESPREADING OF SPREAD-SPECTRUM SEQUENCES, AND RELATED VECTOR PROCESSING INSTRUCTIONS, SYSTEMS, AND METHODS |
| PCT/US2014/064677 WO2015073333A1 (en) | 2013-11-15 | 2014-11-07 | Vector processing engine employing despreading circuitry in data flow paths between execution units and vector data memory, and related method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016537725A true JP2016537725A (ja) | 2016-12-01 |
| JP2016537725A5 JP2016537725A5 (enExample) | 2017-11-30 |
Family
ID=52023612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016531024A Pending JP2016537725A (ja) | 2013-11-15 | 2014-11-07 | 実行ユニットとベクトルデータメモリとの間のデータフローパスにおいて逆拡散回路を利用するベクトル処理エンジン、および関連する方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20150143076A1 (enExample) |
| EP (1) | EP3069236A1 (enExample) |
| JP (1) | JP2016537725A (enExample) |
| KR (1) | KR20160085336A (enExample) |
| CN (1) | CN105723332A (enExample) |
| WO (1) | WO2015073333A1 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9495154B2 (en) | 2013-03-13 | 2016-11-15 | Qualcomm Incorporated | Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods |
| US9684509B2 (en) | 2013-11-15 | 2017-06-20 | Qualcomm Incorporated | Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, systems, and methods |
| US9619227B2 (en) | 2013-11-15 | 2017-04-11 | Qualcomm Incorporated | Vector processing engines (VPEs) employing tapped-delay line(s) for providing precision correlation / covariance vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods |
| US9977676B2 (en) | 2013-11-15 | 2018-05-22 | Qualcomm Incorporated | Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory, and related vector processor systems and methods |
| US9792118B2 (en) | 2013-11-15 | 2017-10-17 | Qualcomm Incorporated | Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods |
| US9880845B2 (en) | 2013-11-15 | 2018-01-30 | Qualcomm Incorporated | Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations, and related vector processor systems and methods |
| US9276778B2 (en) * | 2014-01-31 | 2016-03-01 | Qualcomm Incorporated | Instruction and method for fused rake-finger operation on a vector processor |
| US10108581B1 (en) | 2017-04-03 | 2018-10-23 | Google Llc | Vector reduction processor |
| US11277455B2 (en) | 2018-06-07 | 2022-03-15 | Mellanox Technologies, Ltd. | Streaming system |
| US20200106828A1 (en) * | 2018-10-02 | 2020-04-02 | Mellanox Technologies, Ltd. | Parallel Computation Network Device |
| US11625393B2 (en) | 2019-02-19 | 2023-04-11 | Mellanox Technologies, Ltd. | High performance computing system |
| EP3699770B1 (en) | 2019-02-25 | 2025-05-21 | Mellanox Technologies, Ltd. | Collective communication system and methods |
| US11750699B2 (en) | 2020-01-15 | 2023-09-05 | Mellanox Technologies, Ltd. | Small message aggregation |
| US11252027B2 (en) | 2020-01-23 | 2022-02-15 | Mellanox Technologies, Ltd. | Network element supporting flexible data reduction operations |
| US11876885B2 (en) | 2020-07-02 | 2024-01-16 | Mellanox Technologies, Ltd. | Clock queue with arming and/or self-arming features |
| US11556378B2 (en) | 2020-12-14 | 2023-01-17 | Mellanox Technologies, Ltd. | Offloading execution of a multi-task parameter-dependent operation to a network device |
| US12313774B2 (en) * | 2022-03-23 | 2025-05-27 | Nxp B.V. | Direction of arrival (DOA) estimation using circular convolutional network |
| US12309070B2 (en) | 2022-04-07 | 2025-05-20 | Nvidia Corporation | In-network message aggregation for efficient small message transport |
| US11922237B1 (en) | 2022-09-12 | 2024-03-05 | Mellanox Technologies, Ltd. | Single-step collective operations |
| US12489657B2 (en) | 2023-08-17 | 2025-12-02 | Mellanox Technologies, Ltd. | In-network compute operation spreading |
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| US6470000B1 (en) * | 1998-10-14 | 2002-10-22 | Agere Systems Guardian Corp. | Shared correlator system and method for direct-sequence CDMA demodulation |
| US20030014457A1 (en) * | 2001-07-13 | 2003-01-16 | Motorola, Inc. | Method and apparatus for vector processing |
| JP2004531135A (ja) * | 2001-05-09 | 2004-10-07 | クゥアルコム・インコーポレイテッド | Cdmaシステムにおけるチップレート処理のための方法および装置 |
| JP2005525005A (ja) * | 2002-01-07 | 2005-08-18 | クゥアルコム・インコーポレイテッド | Cdma及びgpsシステムのための多重初期サーチの方法 |
| JP2006080798A (ja) * | 2004-09-08 | 2006-03-23 | Univ Of Electro-Communications | 通信システム |
| JP2009505215A (ja) * | 2005-08-11 | 2009-02-05 | コアソニック アーベー | 複素ベクトル命令を実行するように構成されるクラスタードsimdマイクロ・アーキテクチャを含むプログラマブル・デジタル信号プロセッサ |
| JPWO2012111053A1 (ja) * | 2011-02-15 | 2014-07-03 | 日本電気株式会社 | 複素演算処理用コプロセッサ及びプロセッサシステム |
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| AU2466101A (en) * | 1999-12-30 | 2001-07-16 | Morphics Technology, Inc. | A configurable multimode despreader for spread spectrum applications |
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| JP4295428B2 (ja) * | 2000-12-06 | 2009-07-15 | 富士通マイクロエレクトロニクス株式会社 | Firフィルタ、firフィルタの制御方法、およびfirフィルタを有する半導体集積回路、firフィルタでフィルタリングされたデータを送信する通信システム |
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| TWI326189B (en) * | 2006-05-19 | 2010-06-11 | Novatek Microelectronics Corp | Method and apparatus for suppressing cross-color in a video display device |
| GB2464292A (en) * | 2008-10-08 | 2010-04-14 | Advanced Risc Mach Ltd | SIMD processor circuit for performing iterative SIMD multiply-accumulate operations |
-
2013
- 2013-11-15 US US14/082,067 patent/US20150143076A1/en not_active Abandoned
-
2014
- 2014-11-07 JP JP2016531024A patent/JP2016537725A/ja active Pending
- 2014-11-07 KR KR1020167015684A patent/KR20160085336A/ko not_active Withdrawn
- 2014-11-07 CN CN201480062437.6A patent/CN105723332A/zh active Pending
- 2014-11-07 WO PCT/US2014/064677 patent/WO2015073333A1/en not_active Ceased
- 2014-11-07 EP EP14812019.9A patent/EP3069236A1/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6470000B1 (en) * | 1998-10-14 | 2002-10-22 | Agere Systems Guardian Corp. | Shared correlator system and method for direct-sequence CDMA demodulation |
| JP2004531135A (ja) * | 2001-05-09 | 2004-10-07 | クゥアルコム・インコーポレイテッド | Cdmaシステムにおけるチップレート処理のための方法および装置 |
| US20030014457A1 (en) * | 2001-07-13 | 2003-01-16 | Motorola, Inc. | Method and apparatus for vector processing |
| JP2005525005A (ja) * | 2002-01-07 | 2005-08-18 | クゥアルコム・インコーポレイテッド | Cdma及びgpsシステムのための多重初期サーチの方法 |
| JP2006080798A (ja) * | 2004-09-08 | 2006-03-23 | Univ Of Electro-Communications | 通信システム |
| JP2009505215A (ja) * | 2005-08-11 | 2009-02-05 | コアソニック アーベー | 複素ベクトル命令を実行するように構成されるクラスタードsimdマイクロ・アーキテクチャを含むプログラマブル・デジタル信号プロセッサ |
| JPWO2012111053A1 (ja) * | 2011-02-15 | 2014-07-03 | 日本電気株式会社 | 複素演算処理用コプロセッサ及びプロセッサシステム |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2015073333A1 (en) | 2015-05-21 |
| CN105723332A (zh) | 2016-06-29 |
| EP3069236A1 (en) | 2016-09-21 |
| KR20160085336A (ko) | 2016-07-15 |
| US20150143076A1 (en) | 2015-05-21 |
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