JP2016224753A - Simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the relationship of the number of times of execution among a plurality of processing programs having a plurality of operation cycles, and to efficiently confirm the cooperation operation of the plurality of processing programs.SOLUTION: A simulation device 1 comprises: a plurality of processing programs 11a, 11b, etc. to each of which a processing priority is set and a processing cycle is set; a pseudo-time timer unit 22 counting integrated values; and a start control unit 21 controlling start timing of the plurality of processing programs 11a, 11b, etc., the start control unit 21 controls the to-be-started processing program to be started at timing at which the integrated value reaches a value corresponding to the processing cycle set to the to-be-started processing program in accordance with the priority, and the pseudo-timer unit 22 counts up the integrated value by the value corresponding to the processing cycle set to the to-be-started processing program at an opportunity of detection of the end of execution of the to-be-started processing program.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a simulation apparatus that tests a processing program executed in a control apparatus.

  Conventionally, a control device for monitoring equipment such as plant equipment and operation management of the equipment has been used. In such a control device, a processing program related to monitoring or operation management (also referred to as “logic”). Is running. When processing programs are newly installed in the control device or when the processing programs are upgraded, it is generally performed in advance to test whether these processing programs operate normally.

  For example, Patent Document 1 below discloses a simulator system that combines a control device or an emulator thereof and a plant model. The simulator system includes a control device and a model calculation device that simulates a control target model.

JP 2014-63391 A

  By the way, in the above conventional simulator system, the calculation cycle of the control device is set to a fixed cycle. For this reason, there is a possibility that the error in the calculation cycle varies depending on the accuracy of the clock of the simulator for the control device. Therefore, when a plurality of processing programs having a plurality of calculation cycles are tested at the same time, the relationship between the number of executions within a certain time may differ from that of the actual machine.

  Therefore, the present invention has been made in view of such a problem, and stabilizes the relationship of the number of times of execution between a plurality of processing programs having a plurality of operation cycles, thereby efficiently performing a cooperative operation of the plurality of processing programs. It is an object of the present invention to provide a simulation apparatus that can be confirmed.

  In order to solve the above-described problem, a simulation apparatus according to an aspect of the present invention is a simulation apparatus that tests a plurality of processing programs executed by a control apparatus. A plurality of processing programs set with a period, a pseudo time measuring means for counting an integrated value indicating pseudo time, and an activation control means for controlling the activation timing of the plurality of processing programs, the activation control means, The processing program to be activated among the plurality of processing programs is processed at the timing when the integrated value counted by the pseudo time measuring means reaches a value corresponding to the processing cycle set in the processing program to be activated. Control is performed according to the priority order set in the program, and the pseudo time measuring means Triggered by the completion of the execution of the processing program is detected, counts up the accumulated value by a value corresponding to the set processing cycle start target processing program.

  According to the simulation apparatus having such a configuration, the activation control unit sets in advance the timing at which the integrated value reaches a value corresponding to a preset processing cycle based on the integrated value counted by the pseudo time measuring unit. A plurality of processing programs are started according to the priorities set. Then, when the execution of the processing program to be activated ends, the integrated value is counted up by a value corresponding to the processing cycle of the processing program. As a result, the relationship of the number of executions between a plurality of processing programs within a predetermined time can be stabilized without being affected by the accuracy of the built-in clock. As a result, it is possible to efficiently confirm the cooperative operation of a plurality of processing programs.

  Each of the plurality of processing programs is set with a processing cycle that is an integral multiple of the shortest processing cycle, and the activation control means has reached the value corresponding to the processing cycle among the plurality of processing programs. A plurality of processing programs to be activated are selected, and the selected plurality of activation target processing programs are controlled to be activated in accordance with the priority order. It is also preferable to count up the integrated value by a value corresponding to the shortest processing cycle when the end of execution of the processing program is detected.

  By adopting such a configuration, the integrated value is counted up by the shortest processing cycle among the processing cycles of the plurality of processing programs, so that a plurality of processing programs within a predetermined time can be obtained by updating the minimum integrated value. The relationship of the number of executions can be stabilized. As a result, it is possible to confirm the execution of a stable processing program by minimizing the processing load of the simulation apparatus.

  In addition, it further comprises real-time time measuring means for measuring real time, and the pseudo-time time measuring means is configured to count up while referring to the real time timed by the real time time measuring means when counting up the integrated value. It is also suitable to insert a waiting time into the time.

  In this case, it is possible to perform a test in which the load of a plurality of processing programs is changed by appropriately adjusting the execution cycle of the processing program with respect to real time.

  Furthermore, it is also preferable that the pseudo time measuring means inserts a standby time so that the real time and the integrated value become values representing the same time. By providing such pseudo time measuring means, it is possible to perform a test assuming a real machine of a plurality of processing programs by appropriately adjusting the execution cycle of the processing program with respect to the real time.

  Furthermore, it is also preferable that the pseudo time measuring means insert the standby time so that the time indicated by the integrated value is a predetermined ratio with respect to the actual time. If such pseudo time measuring means is provided, it is possible to perform a test in which the load of a plurality of processing programs is variously changed by appropriately adjusting the execution cycle of the processing program with respect to the real time.

  Furthermore, a plurality of processing program groups each including a plurality of processing programs with priorities set independently of each other are provided, and the activation control means can control the activation timing for each of the plurality of processing program groups based on the integrated value. It is also suitable.

  By adopting such a configuration, it is possible to confirm the cooperative operation among a plurality of processing programs installed in a plurality of devices such as a control device and a control target device.

  It is also preferable to further include a processing program that simulates communication between processing programs of a plurality of processing program groups. In this case, a communication test between a plurality of processing programs mounted on a plurality of apparatuses can be performed together.

  According to the present invention, it is possible to stabilize the relationship of the number of executions between a plurality of processing programs having a plurality of calculation cycles, and to efficiently check the cooperative operation of the plurality of processing programs.

1 is a schematic configuration diagram of a simulation apparatus according to a preferred embodiment of the present invention. FIG. 2 is a ladder diagram illustrating an example of a processing program in FIG. 1. (A) is a timing chart showing the timing of calculation of the processing program whose activation is controlled by the control device of the actual machine, and (b) is the calculation of the processing program whose activation is controlled by the simulation apparatus of FIG. It is a timing chart figure which shows a timing. (A) is a timing chart showing the timing of calculation of the processing program whose activation is controlled by the control device of the actual machine, and (b) is the calculation of the processing program whose activation is controlled by the simulation apparatus of FIG. It is a timing chart figure which shows a timing. (A) is a timing chart showing the timing of calculation of the processing program whose activation is controlled by the control device of the actual machine, and (b) is the calculation of the processing program whose activation is controlled by the simulation apparatus of FIG. It is a timing chart figure which shows a timing. It is a flowchart which shows the procedure of starting control of the processing program by the simulation apparatus of FIG. (A) is a timing chart showing the timing of calculation of a processing program whose activation is controlled by a control device of an actual machine, and (b) is a processing program whose activation is controlled by the simulation apparatus 1 of the present embodiment. It is a timing chart figure which shows the timing of a calculation. (A) is a timing chart showing the timing of calculation of a processing program whose activation is controlled by a control device of an actual machine, and (b) to (d) are processes whose activation is controlled by a simulation device of a modified example. It is a timing chart figure which shows the timing of the calculation of a program. It is a flowchart which shows the procedure of starting control of the processing program by the simulation apparatus of a modification. It is a structure schematic diagram of the simulation apparatus concerning the modification of this invention. (A) is a timing chart showing the timing of calculation of a processing program group whose activation is controlled by a control device of a real machine, and (b) is a process whose activation is controlled by a simulation device based on real-time values. It is a timing chart figure which shows the timing of the calculation of a program group, (c) is a timing chart figure which shows the timing of the calculation of the processing program group by which starting was controlled by the simulation apparatus of this modification.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same or equivalent elements will be denoted by the same reference numerals, and redundant description will be omitted.

  FIG. 1 is a schematic configuration diagram of a simulation apparatus according to a preferred embodiment of the present invention. The simulation apparatus 1 shown in FIG. 1 is an apparatus for testing the operation of a processing program (also referred to as “logic”) installed in a control apparatus that monitors equipment such as plant equipment and manages the operation of equipment. Examples of the control device to be tested by the simulation apparatus 1 include a control device that controls the operation of the gas turbine of the power generation device, but the control device is not limited to this. The test target control device is configured by, for example, a PLC (programmable logic controller) or the like, and normally, logic that is activated at a plurality of priorities in a plurality of operation cycles is mounted.

  The simulation apparatus 1 is an information processing apparatus composed of a general-purpose computer typified by a personal computer, a server apparatus, and the like. Specifically, the simulation apparatus 1 physically includes one or a plurality of CPUs, a main storage device such as a RAM and a ROM, and a communication module that is a data transmission / reception device that transmits / receives data to / from an external device, The computer system includes an auxiliary storage device such as a semiconductor memory and a hard disk device, an input device such as a mouse, a touch panel, and a keyboard, and an output device such as a display and a speaker. Each function of the simulation apparatus 1 operates a communication module, an input device, and an output device under the control of the CPU by reading one or a plurality of predetermined computer software on hardware such as a CPU and a RAM. At the same time, it is realized by reading and writing data in the RAM and the auxiliary storage device.

  Next, the functional configuration of the simulation apparatus 1 will be described. As shown in FIG. 1, the simulation apparatus 1 functionally includes a plurality of processing programs 11a, 11b,..., A start control unit (start control unit) 21, a pseudo time timer unit (pseudo time count unit) 22, A time timer unit (real time measuring means) 23 and an integrated value storage unit 30 are provided. Hereinafter, functions of the respective functional units of the simulation apparatus 1 will be described in detail.

  The plurality of processing programs 11a, 11b,... Are processing programs to be tested by the simulation apparatus 1, and can be executed by the simulation apparatus 1 by being read into the simulation apparatus 1 in advance. FIG. 2 is a ladder diagram illustrating an example of a processing program read into the simulation apparatus 1. This processing program is a program for PLC, (1) confirming the contents of the input value “x2”, (2) confirming the contents of the output value “y70”, (3) the input value “x2” is “ON”, or If the output value “y70” is “on”, the output value “y70” is set to “on”. The processing of (1) to (3) is performed. The operation of repeating the processes (1) to (3) is incorporated. In each of the plurality of processing programs 11a, 11b,..., Calculation cycle information (for example, 40 msec) indicating a processing cycle and priority information indicating a mutual priority relationship between other processing programs. (For example, priority “1”) is preset.

  The pseudo time timer unit 22 counts an integrated value indicating the pseudo time. Specifically, the pseudo time timer unit 22 is triggered by the detection of the end of execution of the processing program activated by the activation control unit 21 among the plurality of processing programs 11a, 11b,. The integrated value is counted up by the value corresponding to the calculation cycle set in. More specifically, the pseudo time timer unit 22 is the shortest of the plurality of processing programs 11a, 11b,... When the end of execution of the processing program started by the start control unit 21 is detected. The integrated value is counted up by the value corresponding to the calculation cycle. Then, the pseudo time timer unit 22 stores the latest counted integrated value in the integrated value storage unit 30.

  The real time timer unit 23 is a time measuring means for measuring real time. For example, the real time timer unit 23 measures the real time using a clock included in an OS (Operating System) functioning in the simulation apparatus 1.

  The activation control unit 21 controls activation of a plurality of processing programs 11a, 11b,. That is, the activation control unit 21 refers to the integrated value counted by the pseudo time timer unit 22, and the activation target program whose integrated value corresponds to the calculation cycle is downloaded to the simulation apparatus 1. Select from a plurality of processing programs 11a, 11b,. Then, the activation control unit 21 controls the selected processing programs to be activated according to the order of priority set for them. At this time, the activation control unit 21 performs control so as to activate the processing program of the next priority immediately after the completion of the execution of one processing program without causing a plurality of processing programs to be executed in duplicate.

  Here, an example of the start control of the processing target test program by the start control unit 21 will be described with reference to FIGS. 3 to 5, (a) is a timing chart showing the calculation timing of the processing program whose activation is controlled by the actual control device, and (b) is activated by the simulation device 1 of the present embodiment. It is a timing chart figure which shows the timing of the calculation of the controlled processing program. In these examples, the calculation cycle “10 msec” and the priority “1” are set for the test target processing program “A”, and the calculation cycle “20 msec” for the test target processing program “B”. And the priority “2” is set, and the calculation cycle “40 msec” and the priority “3” are set for the processing program “C” to be tested. In this case, the processing periods “10 msec”, “20 msec”, and “40 msec”, which are integral multiples of the minimum calculation period “10 msec”, are set in the processing programs “A”, “B”, and “C”, respectively. Yes. In addition, an RTOS (Real Time Operating System) is mounted on the control device of the real machine, and a timer (RTOS timer) with higher accuracy than the real time timer unit 23 of the simulation apparatus 1 by the clock function of the RTOS. Is realized.

  As shown in FIG. 3A, in the actual machine, the activation of the processing programs “A”, “B”, and “C” is controlled using the RTOS timer with relatively high accuracy, so that the RTOS timer is “ The processing programs “A”, “B”, and “C” are started in order of priority at the timing of “0 msec”. Next, only the processing program “A” is started when the RTOS timer is “10 msec”, and then the processing programs “A” and “B” are started in order of priority when the RTOS timer is “20 msec”. The Furthermore, only the processing program “A” is started when the RTOS timer is “30 msec”. As described above, in the actual machine, a plurality of processing programs are executed in a predetermined time (for example, 40 msec) by starting a plurality of processing programs in a single task with a preset calculation cycle and priority while referring to the RTOS timer. The relationship of the number of executions between the programs “A”, “B”, and “C” is fixed. Specifically, the number of executions of the processing programs “A”, “B”, and “C” for 40 msec is set to 4, 2, and 1, respectively.

  On the other hand, as shown in FIG. 3B, in the simulation apparatus 1, a processing program in which the integrated value counted by the pseudo time timer unit 22 is the initial value “0 msec” and the integrated value corresponds to the calculation cycle. “A”, “B”, and “C” are selected as activation target processing programs, and the processing programs “A”, “B”, and “C” are activated in a single task according to the order of priority. At this time, when the end of execution of the processing program “C” having the lowest priority among the selected programs is detected, the integrated value is counted up by the value of the shortest calculation cycle “10 msec”. Updated to “10msec”. Next, only the processing program “A” corresponding to the calculation cycle of the integrated value “10 msec” at that time is selected as the processing program to be activated, and after the processing program “A” is activated, the processing program “A” When the end of execution is detected, the integrated value is counted up by the value of the shortest calculation cycle “10 msec” and updated to “20 msec”. Thereafter, similarly, the processing program “A”, “B” corresponding to the calculation cycle of the integrated value “20 msec” is selected as the processing program to be activated, and the processing programs “A”, “B” are activated in turn. After that, the integrated value is updated to “30 msec” when the end of execution of the processing program “B” is detected. Next, only the processing program “A” whose integrated value “30 msec” corresponds to the calculation cycle is selected as the processing program to be activated, and after the processing program “A” is activated, the processing program “A” is executed. When the end is detected, the integrated value is updated to “40 msec”.

  By such activation control by the activation control unit 21, the same relationship as the number of execution times during the actual time “40 msec” of the processing programs “A”, “B”, “C” in the real machine is obtained as a pseudo time timer unit. It can be set until 22 counts the integrated value “40 msec”. Specifically, in the simulation apparatus 1 as well, the number of executions of the processing programs “A”, “B”, and “C” while counting the integrated value “40 msec” is 4 times, 2 times, and 1 time, respectively. Can be set.

  FIG. 4A shows a case where execution of a plurality of processing programs competes in an actual machine. That is, at the timing when the RTOS timer is “10 msec”, the activation of the processing program “A” is controlled as in the case of FIG. On the other hand, since the processing program “C” is being activated at that time, the execution of the processing program “C” is interrupted and an interrupt for execution of the processing program “A” having a higher priority occurs. In other words, since the single task method is adopted in the actual machine, an interrupt according to the priority may occur depending on the execution time of the processing program.

  On the other hand, as shown in FIG. 4B, the simulation apparatus 1 cannot generate an interrupt process. This is because the processing program “A”, “B”, “C” to be activated is selected at the timing when the integrated value is “0 msec” and the activation is controlled, and then the processing program with the lowest priority “ This is because the integrated value is not counted up until the execution of C ″ is completed. Even in this case, the same relationship as the relationship of the number of executions of the processing programs “A”, “B”, and “C” in the actual machine can be set. Therefore, in the simulation apparatus 1, even when the accuracy of the clock is low and the calculation time cannot be managed accurately, the relationship between the number of executions can be faithfully reproduced.

  FIG. 5A shows a case where the execution of three processing programs in the actual machine competes simultaneously. At the timing when the RTOS timer is “30 msec”, the execution of the three processing programs “A”, “B”, and “C” is competing, but according to the priority, the execution of the processing program “A” has the highest priority, Next, after the processing program “B” is executed, the processing program “C” is started after the execution of the processing program “B” is completed. On the other hand, as shown in FIG. 5 (b), the interrupt processing is not generated in the simulation apparatus 1, but the same relationship as the number of execution times of the processing programs “A”, “B”, “C” in the actual machine. Can be set.

  Next, a procedure for starting control of the processing program by the simulation apparatus 1 will be described with reference to FIG. FIG. 6 is a flowchart illustrating a procedure for starting control of the processing program by the simulation apparatus 1.

  First, when a test of a plurality of processing programs is started by an instruction input from the outside to the simulation apparatus 1, the integrated value stored in the integrated value storage unit 30 is reset to the initial value “0 msec” (step S01). ). Thereafter, calculation cycles preset in the plurality of processing programs to be tested that have been downloaded are specified (step S02). At the same time, priorities set in advance for the plurality of processing programs to be tested are also specified (step S03).

  Subsequently, the current integrated value counted by the pseudo time timer unit 22 is referred to by the activation control unit 21 of the simulation apparatus 1 from the integrated value storage unit 30 (step S04). Next, the activation control unit 21 extracts a processing program whose integrated value has reached a value corresponding to the calculation cycle from among a plurality of processing programs as a processing program to be activated (step S05).

  Thereafter, the activation control unit 21 activates the extracted plurality of processing programs in a single task according to the order of priority (step S06). Then, the start control unit 21 detects the end of execution of all the extracted processing programs (step S07). Then, the integrated value is counted up by the shortest calculation cycle by the pseudo time timer unit 22 (step S08). Thereafter, it is determined whether or not the test termination condition is satisfied (for example, whether or not a predetermined integrated value has been reached) (step S09). If the condition is not satisfied (step S09; NO), the process returns to step S04. If the condition is satisfied (step S09; YES), the process is terminated.

  According to the simulation apparatus 1 described above, based on the integrated value counted by the pseudo time timer unit 22 by the activation control unit 21, the integrated value reaches a value corresponding to a preset processing cycle. A plurality of processing programs 11a, 11b,... Are started according to a preset priority order. Then, when execution of the processing programs 11a, 11b,... To be activated is completed, the integrated value is counted up by a value corresponding to the shortest processing cycle of the processing programs 11a, 11b,. As a result, the relationship of the number of executions between a plurality of processing programs within a predetermined time can be stabilized without being affected by the accuracy of the built-in clock. As a result, it is possible to efficiently confirm the cooperative operation of a plurality of processing programs.

  For example, the OS clock built in the general-purpose computer used as the simulation apparatus 1 may have low accuracy (for example, it has an error of 40 msec or more). Even in such a case, the simulation apparatus 1 sets the relationship of the number of execution times of a plurality of processing programs within a predetermined time (for example, 40 msec) in an actual machine while setting the execution order of these processing programs to a prescribed order. But you can keep it. As a result, it is possible to efficiently test the cooperative operation between a plurality of processing programs that mutually input and output data.

  Moreover, the pseudo time timer unit 22 counts up the integrated value by the shortest processing cycle among the processing cycles of the plurality of processing programs. As a result, the relationship of the number of executions between a plurality of processing programs within a predetermined time indicated by the integrated value can be stabilized by a minimum integrated value update process. As a result, it is possible to confirm the execution of a stable processing program by minimizing the processing load of the simulation apparatus 1.

  In addition, this invention is not limited to embodiment mentioned above.

  For example, the pseudo time timer unit 22 of the simulation apparatus 1 refers to the actual time counted by the real time timer unit 23 in the simulation apparatus 1 when counting up the integrated value, and the time until the count up is performed. You may insert a waiting time into

7 and 8 show an example of the start control of the processing target test program by the start control unit 21 in such a case. 7A is a timing chart showing the timing of calculation of the processing program whose activation is controlled by the control device of the actual machine, and FIG. 7B is a timing chart showing the activation controlled by the simulation apparatus 1 of the present modification. It is a timing chart figure which shows the timing of the calculation of the processed program. In the example of FIG. 7, the calculation time and priority similar to those in FIG. 3 are set. In this case, in the example shown in FIG. 3, a waiting time is inserted immediately before the integrated value is counted up to “120 msec”. That is, the pseudo time timer unit 22 refers to the real time value counted by the real time timer unit 23 when counting up the integrated value to “120 msec”, and until the real time value reaches “120 msec”, That is, after waiting for the waiting time Δt ₁ until the real time value becomes the same value as the updated integrated value, the integrated value is counted up to “120 msec”. In this way, the processing program can be repeatedly executed in the same time as the user's experience time.

Similarly, the pseudo time timer unit 22 may insert a waiting time so that the time indicated by the integrated value is a predetermined ratio with respect to the actual time in order to adjust the pace of the repeated execution of the processing program. . In FIG. 8, (a) is a timing chart showing the calculation timing of the processing program whose activation is controlled by the control device of the actual machine, and (b) to (d) are executed by the simulation apparatus 1 of the present modification. It is a timing chart figure which shows the timing of the calculation of the processing program by which start was controlled. In these examples, the calculation cycle “20 msec” and priority “1” are set for the processing program “A” to be tested, and the calculation cycle “40 msec” and priority are set for the processing program “B” to be tested. The degree “2” is set. In the example shown in FIG. 8B, the pseudo time timer unit 22 counts the time “120 msec” indicated by the accumulated value at the time when the accumulated value “120 msec” is counted up to the time “120 msec indicated by the actual time value. The waiting time Δt ₂ is inserted so as to be the same time as “”. Thereby, the repetition pace of the processing program can be matched with the real time. In the example shown in FIG. 8C, the pseudo time timer unit 22 counts the time “120 msec” indicated by the integrated value at the time when the integrated value “120 msec” is counted up to the time “60 msec indicated by the real time value. The waiting time Δt ₄ is inserted so as to be twice as long as “”. Thereby, the repetition pace of a processing program can be made faster than real time. In the example shown in FIG. 8D, the pseudo time timer unit 22 counts the time “120 msec” indicated by the integrated value “240 msec” when the integrated value “120 msec” is counted up. The waiting time Δt ₆ is inserted so as to be 0.5 times as long as “”. Thereby, the repetition pace of a processing program can be made slower than real time.

  FIG. 9 is a flowchart showing a procedure for starting control of a processing program by the simulation apparatus 1 according to the present modification. The processes in steps S102 to S107 and steps S109 to S110 in FIG. 9 are the same as the processes in steps S02 to S09 in FIG. In step S101, the integrated value is reset to the initial value “0 msec”, and at the same time, the real time value held by the real time timer unit 23 is also reset to the initial value “0 msec”. In step S108, the pseudo time timer unit 22 inserts the standby time while referring to the real time value counted by the real time timer unit 23 when the integrated value is counted up to a predetermined value (step S108). .

  According to the above modification, it is possible to perform a test in which the load of a plurality of processing programs is changed by appropriately adjusting the execution cycle of the processing program with respect to real time. In other words, it is possible to perform a test assuming that the processing program repetition pace is the same as that of the actual machine and that targets a plurality of processing programs, or the processing program repetition pace is set to a predetermined ratio with respect to the actual machine pace. Thus, it is possible to perform a test in which the loads of a plurality of processing programs are variously changed.

  As another modification of the present invention, a plurality of processing program groups having priorities set independently of each other may be processed. FIG. 10 shows the configuration of a simulation apparatus 1A according to a modification of the present invention. As described above, the simulation apparatus 1A includes the processing program group 11 including the processing programs 11a, 11b,... And the processing program group 12 including the processing programs 12a,. The activation control unit 21 of the simulation apparatus 1 </ b> A is configured to be able to control the activation timing for each of the two processing program groups 11 and 12 based on the integrated value counted by the pseudo time timer unit 22.

  FIG. 11 shows an example of the start control of the processing program group to be tested by the start control unit 21 in such a case. FIG. 11A shows the calculation of the processing program group whose start is controlled by the control device of the actual machine. It is a timing chart figure which shows a timing, (b) is a timing chart figure which shows the timing of the calculation of the processing program group by which starting was controlled by the simulation apparatus based on the real time value, (c) is this modification It is a timing chart figure which shows the timing of the calculation of the process program group by which the starting was controlled by the simulation apparatus 1A of the example. Here, one processing program group is configured by the processing programs “A” and “B”, and the other processing program group is configured by the processing program “C”. Further, the other processing program group includes a processing program “D” that simulates data communication processing between the processing program “C” and the processing program “A”. The processing program “D” is realized by, for example, data writing and reading operations with respect to the shared memory in the simulation apparatus 1A. In other words, the process of transmitting data from the apparatus is simulated by writing data to the shared memory, and the process of receiving data by the apparatus is simulated by reading data from the shared memory. The processing program “D” may be simulated by socket communication in the simulation apparatus 1A. One processing program group corresponds to, for example, a program group executed in the control device of the actual machine, and the other processing program group corresponds to, for example, a program group executed in the control target apparatus of the actual machine. Then, the calculation cycle “10 msec” and the priority “1” are set for the test target processing program “A”, and the calculation cycle “20 msec” and the priority “2” are set for the test target processing program “B”. Is set, the calculation cycle “60 msec” and the priority “3” are set for the processing program “B” to be tested, and the processing program “D” is set to start immediately after the processing program “C”. Has been.

  As shown in FIG. 11 (b), when a plurality of processing program groups are started based on real time values counted based on a built-in clock or the like, the clock accuracy is poor, so Deviation occurs in the execution timing. Therefore, even if it is going to test the process accompanied by communication, the cooperation operation | movement via communication between process programs cannot be reproduced. On the other hand, as shown in FIG. 11C, according to the simulation apparatus 1 </ b> A, by referring to the same integrated value in the start control of the processing program group, the execution timing shift between the processing program groups is reduced. Can be prevented. As a result, it is possible to check a cooperative operation among a plurality of processing programs mounted on a plurality of devices such as a control device and a control target device.

DESCRIPTION OF SYMBOLS 1, 1A Simulation apparatus 11, 12 Process program group 11a, 11b, 12a Process program 21 Start-up control part 22 Pseudo-time timer part 23 Real-time timer part 30 Integrated value storage part

Claims (7)

A simulation device for testing a plurality of processing programs executed by a control device,
A plurality of processing programs in which processing priorities are set and processing cycles are set for each,
Pseudo time counting means for counting an integrated value indicating pseudo time;
An activation control means for controlling the activation timing of the plurality of processing programs,
The activation control unit is a value corresponding to the processing cycle in which an integrated value counted by the pseudo time measuring unit is set as the activation target processing program among the plurality of processing programs. Control to start according to the priority set in the processing program to be started at the timing reached.
The pseudo time measuring means counts up the integrated value by a value corresponding to a processing cycle set in the processing program to be activated when the end of execution of the processing program to be activated is detected. ,
Simulation device. In the plurality of processing programs, the processing cycle that is an integral multiple of the shortest processing cycle is set, respectively.
The activation control means selects, as the activation target processing program, a plurality of the processing programs whose integrated value has reached a value corresponding to the processing cycle, and selects the plurality of activation target processes. Control the program to start according to the priorities,
The pseudo time measuring means counts the integrated value by a value corresponding to the shortest processing cycle when the end of execution of the processing programs to be activated selected by the activation control means is detected. Up,
The simulation apparatus according to claim 1. It further includes a real time timing means for measuring real time,
The pseudo time measuring means, when counting up the integrated value, inserts a waiting time into the time until the count up while referring to the real time timed by the real time time measuring means,
The simulation apparatus according to claim 1 or 2. The pseudo time measuring means inserts the waiting time so that the real time and the integrated value are values representing the same time.
The simulation apparatus according to claim 3. The pseudo time measuring means inserts the waiting time so that the time indicated by the integrated value is a predetermined ratio with respect to the actual time.
The simulation apparatus according to claim 3. A plurality of processing program groups each including the plurality of processing programs set with priorities independently of each other;
The activation control means can control activation timing for each of the plurality of processing program groups based on the integrated value.
The simulation apparatus according to any one of claims 1 to 5. A processing program for simulating communication between the processing programs of the plurality of processing programs;
The simulation apparatus according to claim 6.

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