JP2016219870A - Time synchronization controller, time synchronization control system, time synchronization control method, and time synchronization control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform time synchronization with high accuracy, when a specific device synchronizes the time information with other device, even if the time required for the processing performed by the specific device varies in accordance with the state of a system including the specific device.SOLUTION: A time synchronization controller 30 includes a storage section 31 for storing the current time information, outputted from a time output section 34, as second time information 310, upon receiving an input signal including first time information 400 received from an external device 40, and an update section 32 for updating the current time information outputted from the time output section 34, based on third time information 340, i.e., the current time information outputted from the time output section 34, when a signal processing section 33 performing predetermined signal processing for the input signal has finished the signal processing, the first time information 400, and the second time information 310 stored in the storage section 31.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a technique for synchronizing time information held by each of a plurality of devices.

  A system in which a plurality of electronic devices operate in cooperation operates in various fields. For example, an in-vehicle Top View camera system in the automobile field synthesizes video data displaying the surroundings of a car based on video data taken at the same time by cameras installed on the front, rear, left and right of the car. There is also a system in which a plurality of devices existing in different domains (communication networks) operate as one system by operating in cooperation. In such a system, it is necessary to synchronize the time information held by the electronic devices operating in cooperation with each other. Therefore, a technique for synchronizing the time information held by the plurality of electronic devices with high accuracy is expected.

  As an example of technology related to such technology, Patent Document 1 discloses a master device, a relay device connected to the master device by an optical fiber transmission line, and a relay device connected to the master device by an optical fiber transmission line. A time synchronization system including a master device and a slave device that performs time synchronization is disclosed. In this time synchronization system, the master device and the relay device each switch the light source wavelength to a plurality of different wavelengths and transmit each delay time measurement packet. The slave device uses a measurement result of the round trip delay time by each delay time measurement packet and information indicating a transmission speed or a refractive index at each wavelength, and a transmission path delay for correcting the time when the time is delivered from the master device. A time correction value is calculated.

  Further, Patent Document 2 discloses a communication system having a pair of termination devices connected to each other via a transmission line. This communication system uses a communication frame for delay measurement that is transmitted from one terminal device, which is a measurement subject, to the other terminal device, and a reply frame that is returned from the other terminal device in response to this frame. Thus, a delay measuring function for obtaining a frame delay between the both terminal devices is provided. In this communication system, an end device that is a measurement entity calculates a local clock ratio between both end devices based on a plurality of frame delay values that differ in the time required to transmit and receive a communication frame. A part.

  Patent Document 3 discloses a communication device including a measurement frame generation unit, a transmission time acquisition unit, and a correction unit. The measurement frame generation unit generates a measurement frame including a transmission time stamp to be used in delay measurement with a communication device that is a measurement target. The said transmission time acquisition part records the time when a measurement frame is transmitted to the communication apparatus which is a measuring object. The correction unit corrects a difference between the time recorded by the transmission time acquisition unit and the time recorded in the transmission time stamp.

JP 2014-106188 JP JP 2008-182549 A JP 2010-147806 JP

  IEEE (Institute of Electrical and Electronic Engineers) 802.1AS is one of the standards related to the technology for synchronizing time information held by each of a plurality of electronic devices. FIG. 6 illustrates an example of a delay time configuration for each step used by a general time synchronization process compliant with IEEE 802.1AS.

  In the system illustrated in FIG. 6, the slave device 50 and the master device 60 each have time information, and the slave device 50 synchronizes the time information with the master device 60. The master device 60 transmits to the slave device 50 a frame (hereinafter referred to as “AS frame”) including the time information held by the own device. A MAC (Media Access Control) processing unit 51 in the slave device performs MAC processing on the received AS frame. Here, the MAC process is a process for executing a communication protocol in a data link layer defined by an OSI (Open System Interconnection) reference model. The MAC processing unit 51 performs processing such as assembling frame data and confirming whether or not the frame is normal data as the MAC processing. When the received AS frame is normal, the MAC processing unit 51 inputs the AS frame to the time update processing unit 52.

  When the AS frame is input from the MAC processing unit 51, the time update processing unit 52 performs processing for synchronizing the time information held by the slave device 50 with the time information held by the master device 60. The time update processing unit 52 adds the signal propagation delay time, the MAC processing delay time, and the time update processing delay time shown in FIG. 6 to the value indicated by the time information held by the master device 60 included in the AS frame. Calculate the value. Then, the time update processing unit 52 updates the time information held by the slave device 50 to the calculated value.

  Here, the signal propagation delay time is a time required for a frame transmitted from the master device 60 to reach the slave device 50, such as a line length of a communication cable that connects the master device 60 and the slave device 50 so that communication is possible. It is a fixed value determined by. The time update processing delay time is a time required for the time update processing unit 52 to complete the time synchronization processing after the AS frame is input, and, like the signal propagation delay time, generally has a fixed value that hardly fluctuates. Value.

  On the other hand, the MAC processing delay time is a time required for the MAC processing unit 51 to complete the MAC processing for the AS frame after receiving the AS frame, and the value generally varies depending on the state of the system. It is a fluctuating value. That is, the MAC processing delay time varies depending on the traffic amount related to the frame, the MAC method (store and forward, cut-through, fragment free), or the like.

  In the system that performs the general time synchronization processing shown in FIG. 6, this MAC processing delay time is normally set to a predetermined fixed value. However, depending on the state of the system, the actual MAC processing delay time may deviate greatly from the fixed value. In this case, the accuracy with which the slave device 50 synchronizes the time information with the master device 60 is greatly reduced. With the techniques described in Patent Documents 1 to 3, it is difficult to solve this problem.

  The main object of the present invention is to provide a time synchronization control device or the like that solves this problem.

  When the time synchronization control device according to one aspect of the present invention receives an input signal including the first time information received from the external device, the time synchronization control device uses the current time information output from the time output means as the second time information. Storage means for storing the current time information output from the time output means when the signal processing means for performing predetermined signal processing on the input signal finishes the signal processing on the input signal. Update means for updating current time information output by the time output means based on the time information of the first time information and the second time information stored in the storage means. Prepare.

  In another aspect of achieving the above object, a time synchronization control method according to an aspect of the present invention provides a time output when an information processing device receives an input signal including first time information received from an external device. The current time information output from the means is stored in the storage means as second time information, and the signal processing means for performing predetermined signal processing on the input signal finishes the signal processing on the input signal. Based on the third time information that is the current time information output from the time output means, the first time information, and the second time information stored in the storage means, the time output The current time information output by the means is updated.

  Further, in a further aspect of achieving the above object, the time synchronization control program according to one aspect of the present invention outputs from the time output means when receiving the input signal including the first time information received from the external device. Storage processing for storing the current time information as second time information in the storage means, and when signal processing means for performing predetermined signal processing on the input signal finishes the signal processing on the input signal. Based on the third time information that is the current time information output from the time output means, the first time information, and the second time information stored in the storage means, the time output An update process for updating the current time information output by the means is implemented in the computer.

  Furthermore, the present invention can be realized by a computer-readable non-volatile recording medium in which such a time synchronization control program (computer program) is stored.

  In the present invention, when a specific device synchronizes time information with another device, even if the time required for the processing performed by the specific device varies depending on the state of the system including the specific device, It is possible to perform time synchronization processing with high accuracy.

It is a block diagram which shows the structure of the time synchronous control system 1 which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure of the memory | storage part 11 which concerns on 1st Embodiment of this invention. It is a flowchart (1/2) which shows operation | movement of the time synchronous control system 1 which concerns on 1st Embodiment of this invention. It is a flowchart (2/2) which shows operation | movement of the time synchronous control system 1 which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure of the time synchronous control apparatus 30 which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the information processing apparatus which can execute the time synchronous control program which implement | achieves the function with which the time synchronous control apparatus which concerns on each embodiment of this invention is provided. It is a figure which illustrates the structure of the delay time for every step in a general time synchronous process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram conceptually showing the structure of the time synchronization control system 1 according to the first embodiment. The time synchronization control system 1 according to the present embodiment includes a time synchronization control device 10 and an external device 20. The external device 20 provides time information (master clock information) held by itself as a master device in time synchronization processing to the time synchronization control device 10 that is a slave device. The time synchronization control device 10 synchronizes the time information with the external device 20 based on the master clock information provided from the external device 20.

  The external device 20 transmits various types of frames (signals) to the time synchronization control device 10. When the time synchronization control device 10 and the external device 20 perform time synchronization processing, the external device 20 transmits an AS frame, which is a frame including master clock information, to the time synchronization control device 10.

  The time synchronization control apparatus 10 includes a storage unit 11, an update unit 12, a MAC processing unit 13, and a time output unit 14. The update unit 12, the MAC processing unit 13, and the time output unit 14 may be electronic circuits or may be realized by a computer program and a processor that operates according to the computer program. The storage unit 11 is a non-volatile storage device such as an electronic memory or a magnetic disk. The storage unit 11 has a storage control function realized by an electronic circuit or a computer program and a processor that operates according to the computer program.

  The time output unit 14 is a clock (timer) and outputs the current time.

  The storage unit 11 stores a reception time stamp representing the current time output from the time output unit 14 at the timing when the time synchronization control device 10 receives a frame from the external device 20. The configuration of the storage unit 11 is illustrated in FIG.

  As illustrated in FIG. 2, the storage unit 11 is a ring buffer including n (n is an arbitrary integer greater than or equal to 1) entries 110-1 to 110-n, a write pointer 111, and a read pointer 112. . The entries 110-1 to 110-n are entries that can store a reception time stamp. The write pointer 111 indicates an entry that is a storage location of a reception time stamp, and stores any value from 1 to n. The read pointer 112 indicates an entry from which a reception time stamp is read, and stores one of values 1 to n.

  The storage unit 11 stores a reception time stamp in the entry 110-i (i is an integer from 1 to n) indicated by the write pointer 111 at the timing when the time synchronization control device 10 receives a frame from the external device 20. To do. After storing the reception time stamp in the entry 110-i, the storage unit 11 adds 1 to the write pointer 111. That is, in this case, the value of the write pointer 111 is “i + 1”. When “i = n”, the value of the write pointer 111 is returned to “1” by adding one.

  After storing the reception time stamp in the entry 110-i, the storage unit 11 is updated to “i + 1” when notified from the MAC processing unit 13 that the frame received from the external device 20 is not a normal frame. The value of the write pointer 111 is returned to “i”. When the storage unit 11 is notified from the MAC processing unit 13 that the MAC processing unit 13 is in a standby state in which there is no frame being MAC processed, the storage unit 11 sets the value of the write pointer 111 and the value of the read pointer 112. , Set (reset) to the same value (for example, “1”).

  After storing the reception time stamp in the entry 110-i, the storage unit 11 sets the value of the read pointer 112 to “1” when notified from the update unit 12 that the frame received from the external device 20 is not an AS frame. "to add. After storing the reception time stamp in the entry 110-i, the storage unit 11 sets the value of the read pointer 112 to “1” when the update unit 12 reads the reception time stamp from the entry indicated by the read pointer 112. "to add.

  The MAC processing unit 13 performs MAC processing on the frame received from the external device 20. The MAC processing unit 13 can accept a subsequent frame during the MAC processing of the frame, and can start the MAC processing for the subsequent frame. The MAC processing unit 51 performs, as MAC processing, processing for assembling data constituting a frame, processing for confirming whether or not the frame is a normal frame, and the like. The MAC processing unit 51 confirms whether there is any missing or excess data constituting the frame, and whether there is a CRC (Cyclic Redundancy Check) error or the like.

  When the received frame is normal, the MAC processing unit 13 inputs the MAC-processed frame to the updating unit 12. When the received frame is abnormal, the MAC processing unit 13 discards the frame and notifies the storage unit 11 that the frame is not a normal frame. The MAC processing unit 13 notifies the storage unit 11 that it is in a standby state when processing for all received frames is completed and a standby state in which there is no frame being subjected to MAC processing exists.

  The update unit 12 includes a frame determination unit 120 and a time synchronization processing unit 121. The frame determination unit 120 stores a frame determination reference (not shown) including frame configuration information representing the configuration content of the frame for each frame type. The frame determination unit 120 determines whether the frame input from the MAC processing unit 13 is an AS frame based on the frame determination criterion.

  When the frame input from the MAC processing unit 13 is not an AS frame, the frame determination unit 120 inputs the frame to a frame data processing unit outside the time synchronization control apparatus 10. The frame determination unit 120 notifies the storage unit 11 that the frame is not an AS frame.

  When the frame input from the MAC processing unit 13 is an AS frame, the frame determination unit 120 extracts master clock information from the AS frame, and inputs the extracted master clock information to the time synchronization processing unit 121.

  The time synchronization processing unit 121 acquires a MAC processing completion time stamp indicating the current time output from the time output unit 14 at the timing when the frame is input from the MAC processing unit 13. When the master clock information is input from the frame determination unit 120, the time synchronization processing unit 121 reads the reception time stamp from the entry indicated by the read pointer 112 in the storage unit 11.

  The time synchronization processing unit 121 calculates the MAC processing delay time by subtracting the obtained time stamp value at the time of reception from the obtained time stamp value at the time of completion of the MAC processing. This MAC processing delay time is the time required for the MAC processing unit 13 to perform the MAC processing on the received AS frame.

  The time synchronization processing unit 121 adds the value indicated by the master clock information input from the frame determination unit 120, the signal propagation delay time, and the time update processing delay time to the calculated MAC processing delay time. The synchronous control device 10 calculates a value (time) to be set in the own device as the current time. Here, the signal propagation time is the time required for the frame output from the external device 20 to reach the time synchronization control device 10, and is given in advance to the time synchronization processing unit 121 as a fixed value by a system administrator or the like. ing. The time update processing delay time is the time required for the update unit 12 to complete the time synchronization processing after the AS frame is input from the MAC processing unit 13, as with the signal propagation delay time. A fixed value is given to the time synchronization processing unit 121 in advance.

  The time synchronization processing unit 121 updates the current time output by the time output unit 14 to the current time calculated by the above-described processing.

  Next, the operation (processing) of the time synchronization control system 1 according to the present embodiment will be described in detail with reference to the flowcharts of FIGS. 3A and 3B.

  The time synchronization control device 10 receives a frame from the external device 20 (step S101). The storage unit 11 stores the current time output by the time output unit 14 at the time when the frame is received, in the entry 110-i indicated by the write pointer 111 as a reception time stamp, and adds “1” to the write pointer 111. (Step S102). The MAC processing unit 13 performs MAC processing on the received frame and determines whether or not it is a normal frame (step S103).

  If the received frame is not a normal frame (No in step S104), the MAC processing unit 13 discards the frame and notifies the storage unit 11 that the frame has been discarded (step S105). The storage unit 11 subtracts “1” from the write pointer 111 (step S106), and the entire process ends.

  When the received frame is a normal frame (Yes in step S104), the MAC processing unit 13 inputs the frame subjected to the MAC processing to the updating unit 12 (step S107). The time synchronization processing unit 121 obtains the current time output by the time output unit 14 at the timing when the frame is input as a time stamp when the MAC processing is completed (step S108).

  The frame determination unit 120 determines whether or not the frame is an AS frame (step S109). If the frame is not an AS frame (No in step S110), the frame determination unit 120 inputs the frame to an external frame data processing unit (step S111). The frame determination unit 120 notifies the storage unit 11 that the frame is not an AS frame (step S112). The storage unit 11 adds “1” to the read pointer 112 (step S113), and the entire process ends.

  When the frame is an AS frame (Yes in step S110), the frame determination unit 120 extracts master clock information from the AS frame and inputs the master clock information to the time synchronization processing unit 121 (step S114). . The time synchronization processing unit 121 reads a reception time stamp from the entry 110-i (step S115). The storage unit 11 adds “1” to the read pointer (step S116).

  The time synchronization processing unit 121 calculates the current time based on the master clock information, the reception time stamp, and the MAC processing completion time stamp (step S117). The time synchronization processing unit 121 updates the current time output by the time output unit 14 to the calculated current time (step S118), and the entire process ends.

  In the time synchronization control system 1 according to the present embodiment, when a specific device synchronizes time information with another device, the time required for processing performed by the specific device depends on the state of the system including the specific device. Even if it fluctuates, time synchronization processing can be performed with high accuracy. The reason is that the storage unit 11 stores the time when the master clock information is received from the external device 20 as a reception time stamp, and the update unit 12 is the time when the signal processing by the MAC processing unit 13 is completed. This is because the current time output by the time output unit 14 is updated based on a time stamp when a certain MAC process is completed, a reception time stamp stored in the storage unit 11, and a value indicated by the master clock information.

  For example, as in the case described in the column “Problems to be Solved by the Invention”, consider a case where the slave device synchronizes time information with the master device. In this case, the slave device normally updates the time information used by itself to a value obtained by adding a predetermined time to the value indicated by the master clock information output from the master device. This predetermined time includes a signal propagation delay time required until master clock information arrives from the master device to the slave device, and a processing delay time required until the slave device completes the time synchronization processing after receiving the master clock information. , Including. For example, in the case of the example shown in FIG. 6, the processing delay time includes a MAC processing delay time and a time update processing delay time.

  A system that performs general time synchronization processing normally sets a predetermined time to be added to a value indicated by master clock information when performing time synchronization processing to a predetermined fixed value. In the example shown in FIG. 6, the signal propagation delay time and the time update processing delay time are fixed values that hardly vary depending on the system state. On the other hand, the MAC processing delay time is a fluctuation value that varies depending on the state of the system. That is, the predetermined time added to the value indicated by the master clock information is a fluctuating value that varies depending on the state of the system. Therefore, depending on the state of the system, there is a possibility that the accuracy of synchronizing time information may be greatly reduced.

  On the other hand, according to the time synchronization control system 1 according to the present embodiment, the storage unit 11 stores the time when the master clock information is received from the external device 20 as a reception time stamp. The update unit 12 obtains a MAC process completion time stamp indicating the time when the signal processing by the MAC processing unit 13 is completed, and then subtracts the reception time stamp value from the MAC process completion time stamp value. To calculate a MAC processing delay time which is a variation value. The update unit 12 calculates the current time by adding the value indicated by the master clock information, the signal propagation delay time and the time update processing delay time, which are fixed values, to the calculated MAC processing delay time. The update unit 12 updates the time information output from the time output unit 14 to the calculated current time. Thereby, the time synchronization control system 1 according to the present embodiment can perform the time synchronization processing with high accuracy even when the time required for the time synchronization processing varies depending on the state of the system.

  Further, in the time synchronization control system 1 according to the present embodiment, the storage unit 11 is a ring buffer including a plurality of entries 110-1 to 110-n. When a plurality of master clock information are transmitted from the external device 20 in a short period of time, the time synchronization control device 10 can convert the subsequent master clock information into a plurality of times even if the time synchronization processing related to the preceding master clock information is not completed. The entry is stored in the storage unit 11. Thereby, the time synchronous control apparatus 10 can receive master clock information without delay. Then, the storage unit 11 resets the write pointer 111 and the read pointer 112 to the same value when the MAC processing unit 13 has entered the standby state in which the MAC processing related to all the master clock information received is completed. 110-1 to 110-n can be used effectively.

  In the time synchronization control system 1 according to the present embodiment, the time synchronization control device 10 calculates the MAC processing delay time by the MAC processing unit 13 as a variation value in the time synchronization processing, but the time synchronization control device 10 The processing delay time calculated as a variation value is not limited to the MAC processing delay time. The processing delay time calculated as the variation value by the time synchronization control apparatus 10 may be, for example, a delay time required for processing with an extended function with respect to MAC processing. The processing delay time calculated as the variation value by the time synchronization control apparatus 10 may be a delay time required for processing for executing a communication protocol in a layer other than the data link layer defined by the OSI reference model.

  In addition, when the time synchronization control apparatus 10 according to the present embodiment performs time synchronization processing by software, after storing the received AS frame in the built-in memory, the MAC processing and the program are executed by a CPU (Central Processing Unit). Perform time update processing. In this case, the processing time required for the time synchronization process varies more greatly than when the time synchronization process is performed by dedicated hardware due to the occurrence of contention with other processes related to the CPU and memory. Even in this case, the time synchronization control system 1 according to the present embodiment can calculate the delay time until the software completes the predetermined processing after receiving the AS frame, so the time synchronization processing can be performed with high accuracy. It can be performed.

<Second Embodiment>
FIG. 4 is a block diagram conceptually showing the structure of the time synchronization control apparatus 30 according to the second embodiment.

  The time synchronization control device 30 according to the present embodiment includes a storage unit 31 and an update unit 32.

  The storage unit 31 stores the current time information output from the time output unit 34 as the second time information 310 when receiving an input signal including the first time information 400 received from the external device 40.

  The update unit 32 performs a third time that is current time information output from the time output unit 34 when the signal processing unit 33 that performs predetermined signal processing on the input signal ends the signal processing on the input signal. Obtain information 340. Based on the third time information 340, the first time information 400, and the second time information 310 stored in the storage unit 31, the update unit 32 outputs the current time information output by the time output unit 34. Update.

  The time synchronization control device 30 according to the present embodiment, when a specific device synchronizes time information with another device, the time required for the processing performed by the specific device depends on the state of the system including the specific device. Even if it fluctuates, time synchronization processing can be performed with high accuracy. The reason is that the storage unit 31 stores the time when the first time information 400 is received from the external device 40 as the second time information 310, and the update unit 32 completes the signal processing by the signal processing unit 33. The time output unit 34 outputs based on the third time information 340 indicating the time when the operation is performed, the second time information 310 stored in the storage unit 31, and the value indicated by the first time information 400. This is because the current time information is updated.

<Hardware configuration example>
In each embodiment described above, the time synchronization control devices 10 and 30 shown in FIGS. 1 and 4 can be realized by a dedicated HW (HardWare) (electronic circuit). The time synchronization control devices 10 and 30 can also be realized by causing a general-purpose HW to execute a software program. An example of the hardware environment in this case will be described with reference to FIG.

  FIG. 5 is a diagram for exemplarily explaining the configuration of an information processing apparatus 900 (computer) that can execute a time synchronization control program that implements the functions of the time synchronization control apparatuses 10 and 30 according to the embodiments of the present invention. is there. 5 is a configuration of a computer (information processing apparatus) that can implement the time synchronization control apparatus 10 shown in FIG. 1 and the time synchronization control apparatus 30 shown in FIG. Represents a hardware environment that can implement each function.

The information processing apparatus 900 illustrated in FIG. 5 includes the following as constituent elements.
CPU (Central_Processing_Unit) 901,
ROM (Read_Only_Memory) 902,
RAM (Random_Access_Memory) 903,
-Hard disk (storage device) 904,
A communication interface 905 with an external device,
A reader / writer 908 capable of reading and writing data stored in a recording medium 907 such as a CD-ROM (Compact_Disc_Read_Only_Memory)
-I / O interface 909,
The information processing apparatus 900 is a general computer in which these configurations are connected via a bus 906 (communication line).

  The present invention described using the above-described embodiment as an example supplies a computer program capable of realizing the following functions to the information processing apparatus 900 illustrated in FIG. The function is the function of the time synchronization control devices 10 and 30 or the flowcharts (FIGS. 3A and 3B) in the block configuration diagrams (FIGS. 1 and 4) referred to in the description of the embodiment. The present invention is then achieved by reading the computer program into the hardware CPU 901 for interpretation and execution. The computer program supplied to the apparatus may be stored in a readable / writable volatile memory (RAM 903) or a nonvolatile storage device such as the hard disk 904.

  In the above case, a general procedure can be adopted as a method for supplying the computer program into the hardware. The procedure includes, for example, a method of installing in the apparatus via various recording media 907 such as a CD-ROM, a method of downloading from the outside via a communication line such as the Internet, and the like. In such a case, the present invention can be understood to be configured by a code constituting the computer program or a recording medium 907 in which the code is stored.

  The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Time synchronization control system 10 Time synchronization control apparatus 11 Memory | storage part 110-1 thru | or 110-n entry 111 Write pointer 112 Read pointer 12 Update part 120 Frame determination part 121 Time synchronization processing part 13 MAC processing part 14 Time output part 20 External apparatus 30 Time Synchronization Control Device 31 Storage Unit 310 Second Time Information 32 Update Unit 33 Signal Processing Unit 34 Time Output Unit 340 Third Time Information 40 External Device 400 First Time Information 50 Slave Device 51 MAC Processing Unit 52 Time Update Processing unit 60 Master device 900 Information processing device 901 CPU
902 ROM
903 RAM
904 Hard disk 905 Communication interface 906 Bus 907 Recording medium 908 Reader / writer 909 Input / output interface

Claims (10)

Storage means for storing current time information output from the time output means as second time information when an input signal including the first time information received from the external device is received;
Third time information, which is current time information output from the time output means when signal processing means for performing predetermined signal processing on the input signal ends the signal processing on the input signal, and the first Update means for updating current time information output by the time output means based on one time information and the second time information stored in the storage means;
A time synchronization control apparatus comprising: The updating means includes a value of a propagation delay time required for receiving the input signal after the input signal is transmitted from the external device, a value indicated by the third time information, and the second time information. Updating the current time information output by the time output means based on the difference between the value indicated by
The time synchronization control apparatus according to claim 1. The signal processing means;
The time output means;
The time synchronization control apparatus according to claim 1, further comprising: The storage means includes a plurality of entries capable of storing the second time information, and stores the second time information in any of the plurality of entries for the plurality of input signals.
The update means reads the second time information from the plurality of entries according to the order in which the second time information is written.
The time synchronous control apparatus as described in any one of Claims 1 thru | or 3. When the signal processing means is in a standby state where the input signal being processed does not exist, standby state information is input to the storage means,
When the standby state information is input from the signal processing unit, the storage unit includes a write pointer that indicates an entry that is a write destination and a read pointer that indicates an entry that is a read destination among the plurality of entries. , Set to the same value,
The time synchronous control apparatus according to claim 4. The signal processing means performs a process of determining whether or not data included in the input signal is normal as the predetermined signal processing.
The time synchronous control apparatus as described in any one of Claims 1 thru | or 5. The signal processing means performs processing in the data link layer in the OSI reference model.
The time synchronization control apparatus according to claim 6. A time synchronization control device according to any one of claims 1 to 7,
The external device;
A time synchronization control system comprising: Depending on the information processing device,
When the input signal including the first time information received from the external device is received, the current time information output from the time output means is stored in the storage means as the second time information,
Third time information, which is current time information output from the time output means when signal processing means for performing predetermined signal processing on the input signal ends the signal processing on the input signal, and the first Updating the current time information output by the time output means based on the one time information and the second time information stored in the storage means;
A time synchronization control method comprising: A storage process for storing the current time information output from the time output means in the storage means as second time information when an input signal including the first time information received from the external device is received;
Third time information, which is current time information output from the time output means when signal processing means for performing predetermined signal processing on the input signal ends the signal processing on the input signal, and the first An update process for updating the current time information output by the time output means based on the one time information and the second time information stored in the storage means;
A time synchronization control program for realizing the above in a computer.

Images