JP2016219678A - Electric field effect transistor and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric field effect transistor in which an odd mode oscillation is suppressed and an output synthesis efficiency is improved.SOLUTION: An electric field effect transistor 10 has a plurality of finger electrodes, a gate bus line 231, a gate terminal electrode 233, a drain terminal electrode 253, and a source terminal electrode 243. The finger electrode has two finger gate electrodes and a finger drain electrode and a finger source electrode provided so as to sandwich the finger gate electrode. The gate bus line 231 commonly bundles the finger gate electrode, the drain terminal electrode 253 commonly bundles finger drain electrode, and the source terminal electrode 243 commonly bundles the finger source electrode. The drain terminal electrode 253 and the gate bus line 231 are divided such that the combination of the cells bundled by the drain terminal electrode 253 and the combination of the cells bundled by the gate bus line 231 are different.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a field effect transistor and a semiconductor device.

  When increasing the output of a radar device or a communication device, using a field effect transistor in which a large number of cells are connected in parallel facilitates the configuration.

  In the configuration in which the input signal is distributed to each cell, amplified, and then the output signal is combined, multiple loops with different lengths are formed, so oscillation may occur at the frequency caused by the loop length. There is.

  For example, two amplifying elements connected in parallel constituting a loop operate in opposite phases with each other at a specific frequency, and when there is no appropriate load, an odd mode oscillation occurs and a stable amplifying operation becomes difficult. The loop in which odd mode oscillation is likely to occur varies for each product with different operating frequency, operating voltage, and output power. When odd mode oscillation occurs, the loop is specified, and the oscillation is suppressed by providing an isolation resistor in the loop. In particular, when a loop is formed on the field effect transistor and odd mode oscillation occurs in the loop, an isolation resistance is added to the field effect transistor or its value is changed.

Japanese Patent No. 5487082

  Provided are a field effect transistor and a semiconductor device that can be used in common in products having different operating frequencies, operating voltages, and output power, that are suppressed in odd mode oscillation, and that have improved output synthesis efficiency.

  The field effect transistor of the embodiment has a plurality of cells in parallel that control operating current by finger electrodes provided on a semiconductor stacked body. The field effect transistor includes a plurality of finger electrodes, a gate bus line, a gate terminal electrode, a drain terminal electrode, and a source terminal electrode. Each finger electrode has at least two finger gate electrodes, and a finger drain electrode and a finger source electrode provided so as to sandwich each finger gate electrode, and constitutes each cell. The gate bus line bundles a plurality of finger gate electrodes in common for each group. The gate terminal electrode is connected to the gate bus line. The drain terminal electrode bundles a plurality of finger drain electrodes in common for each group. The source terminal electrode bundles a plurality of finger source electrodes in common and is connected to a back surface conductive portion of the semiconductor stacked body through a via hole provided in the semiconductor stacked body. The drain terminal electrode and the gate bus line are divided so that the group (cell combination) bundled by the drain terminal electrode and the group (cell combination) bundled by the gate bus line are different.

1 is a schematic plan view of a semiconductor device according to a first embodiment. FIG. 2A is a configuration diagram of the semiconductor device according to the first embodiment, and FIG. 2B is an equivalent circuit diagram thereof. FIG. 3A is a schematic plan view of a unit cell of the field effect transistor, and FIG. 3B is a schematic cross-sectional view taken along the line AA. It is a schematic plan view of the semiconductor device concerning the 1st comparative example. It is a block diagram of the semiconductor device concerning the 1st comparative example. It is a model top view of the semiconductor device concerning the 2nd comparative example. It is a block diagram of the semiconductor device concerning the 2nd comparative example. FIG. 6 is a schematic plan view of a semiconductor device according to a second embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment.
FIG. 2A is a configuration diagram of the semiconductor device according to the first embodiment, and FIG. 2B is an equivalent circuit diagram thereof.
The semiconductor device 5 includes a field effect transistor 10, an input capacitor substrate 20, an output capacitor substrate 30, and bonding wires LI1 to LI8, LG1 to LG8, LD1 to LD8, and LO1 to LO8. The semiconductor device 5 may further include an input relay board 40 and an output relay board 50.

  In the field effect transistor 10, a plurality of cells for controlling the operating current are arranged in parallel by finger electrodes provided in the semiconductor stacked body. The input capacitor substrate 20 has a high dielectric material and an input conductive portion provided thereon. The output capacitor substrate 30 has a high dielectric material and an output conductive portion provided thereon.

FIG. 3A is a schematic plan view of a unit cell of the field effect transistor, and FIG. 3B is a schematic cross-sectional view taken along the line AA.
The unit cell M of the field effect transistor 10 includes a semiconductor stacked body 17 including the electron supply layer 14, the channel layer 12, and the substrate 10, and a finger electrode 213 provided on the semiconductor stacked body 17.

  Each finger electrode 213 includes at least two finger gate electrodes 230 and a finger drain electrode 250 and a finger source 240 electrode provided so as to sandwich each finger gate electrode 230.

  The unit cell of the field effect transistor 10 may further include a gate bus line 231. The gate bus line 231 bundles a plurality of finger gate electrodes 230 in common for each group. A gate bus line 231 is connected to the gate terminal electrode 233. The drain terminal electrode 253 connects a plurality of finger drain electrodes 250 in a bundle for each group.

  The source terminal electrode 243 bundles a plurality of finger source electrodes 240 in common for each group, and is connected to the back surface conductive portion 90 of the semiconductor stacked body 17 through a via hole 212 provided in the semiconductor stacked body 17.

  As shown in FIG. 3B, for example, the substrate 10 is made of SiC, the channel layer 12 is made of GaN, and the electron supply layer 14 is made of AlGaN. Further, the semiconductor stacked body 17 may include a source contact layer 215 and a drain contact layer 216.

  Such a field effect transistor can be called a HEMT (High Electron Mobility Transistor). GaN has a high saturation electron velocity and dielectric breakdown voltage, and can be used as a high-power amplifying element at frequencies above the microwave band.

  In the first embodiment, when one drain terminal electrode 253 bundles a plurality of finger drain electrodes of two cells, a combination of cells and when one gate bus line 231 bundles the finger gate electrodes 230 of two cells are combined. A slit for dividing the drain terminal electrode 253 and the gate bus line 231 is disposed so as to be different from the combination of the cells. In FIG. 1, a combination of cells bundled by the drain terminal electrode 253 includes a combination of two adjacent cells. Further, the combination of cells that bundle the gate bus lines 231 includes two adjacent combinations. The position of the slit S3 of the drain terminal electrode 253 and the position of the slit S1 of the gate bus line 231 are alternate (zigzag).

  For example, the gate bus line 231 bundles the finger gate electrodes 230 of the cells M1 and M2, the cells M3 and M4, the cells M5 and M6, the cells M7 and M8, respectively. On the other hand, the drain terminal electrode 253 bundles the finger drain electrodes 250 of the cell M1, the cell M2 and the cell M3, the cell M4 and the cell M5, the cell M6, the cell M7 and the cell M8, respectively. That is, since the positions of the slit S1 and the slit S3 are staggered, a loop is not formed on the field effect transistor 10 even though two cells are bundled on the field effect transistor 10.

FIG. 2A is a diagram for explaining in detail the configuration of the semiconductor device of the first embodiment, and FIG. 2B is an equivalent circuit diagram thereof.
Resistors R25, R26, and R27 are provided between the conductive regions 21 to 24 of the input capacitor substrate 20. The resistor R25 acts as an isolation resistor between the cells M1 and M2 and the cells M3 and M4 constituting the loop. The resistor R26 acts as an isolation resistor between the cells M1 to M4 and the cells M5 to M8 constituting the loop. The resistor R27 acts as an isolation resistor between the cells M5 and M6 constituting the loop and the cells M7 and M8. Further, resistors R31, R32, R33, and R34 are provided between the conductive regions 31 to 35 of the output capacitor substrate 30.

  The output relay substrate 50 has two conductive regions 51 and 52 divided by a slit S4 or the like. The resistor R51 is connected to the two conductive regions 51 and 52, respectively.

  Next, odd mode oscillation will be described. When cells are arranged in parallel for higher output, odd-mode oscillation may occur if the parallel cells are out of phase between the cells. For example, if the two cells are 180 degrees out of phase, the connection point between the two cells is equivalent to ground and the circuit outside the loop will not be visible as a load. That is, a loop may be formed between the two cells, which may cause undesirable oscillation at a specific frequency.

  In FIG. 2, LP1 to LP4 are considered as main loops. For example, the loop LP1 has the conductive region 41 of the input relay substrate 40 and the conductive region 253b of the drain terminal electrode 253 as connection points, and the conductive region 41 of the input relay substrate 40, the bonding wire LI2, and the conductive region 21 of the input capacitor substrate 20 are connected. , Bonding wire LG2, gate terminal electrode 233b, gate bus line 231a, cell M2, conductive region 253b of drain terminal electrode 253, cell M3, gate bus line 231b, gate terminal electrode 233c, bonding wire LG3, conductivity of input capacitor substrate 20 A region 22, a bonding wire LI3, and an input resistor R25 are included. In this case, odd mode oscillation is suppressed by the input resistor R25.

  The loop LP2 has the gate bus line 231a and the conductive region 51 of the output relay substrate 50 as connection points, and the gate bus line 231a, the cell M1, the bonding wire LD1, the conductive region 31 of the output capacitor substrate 30, the bonding wire LO1, It includes a conductive region 51 of the output relay substrate 50, a bonding wire LO2, a conductive region 32 of the output capacitor substrate 30, a bonding wire LD2, a resistor R31, and a cell M2. Similarly, a loop LP2 is formed between adjacent cells (M3 and M4, M5 and M6, and M7 and M8). In this case, the odd mode oscillation is suppressed by the resistors R31 connected to the conductive regions 31 and 32 of the output capacitor substrate 30, respectively.

  The loop LP3 has the conductive region 23 of the input capacitor substrate 20 and the conductive portion 52 of the output relay substrate 50 as connection points, and the conductive region 23, the conductive region 22, the bonding wire LG4, the cell M4, and the bonding wire LD4 of the input capacitor substrate 20. , Conductive region 33 of output capacitor substrate 30, bonding wire LO5, conductive portion 52 of output relay substrate 50, bonding wire LO6, conductive region 34 of output capacitor substrate 30, bonding wire LD7, cell M7, bonding wire LG7, input capacitor substrate 20 conductive regions 24 are included. In this case, the odd mode oscillation is further suppressed by the resistors R26, R27, and R33.

  The loop LP4 has the conductive region 41 of the input relay substrate 40 and the conductive portion 52 of the output relay substrate 50 as connection points, the conductive region 41 of the input relay substrate 40, the bonding wire LI5, the conductive region 23 of the input capacitor substrate 20, and the bonding. Wire LG5, cell M5, bonding wire LD5, conductive region 33 of output capacitor substrate 30, bonding wire LO5, conductive portion 52 of output relay substrate 50, bonding wire LO8, conductive region 35 of output capacitor substrate 30, bonding wire LD8, cell M8, the bonding wire LG8, the conductive region 24 of the input capacitor substrate 20, and the bonding wire LI8. In this case, the odd mode oscillation is further suppressed by the resistors R27, R33, and R34.

  It should be noted that odd mode oscillation can be effectively suppressed by connecting points (antinodes) where the voltage amplitude of standing wave oscillation of the odd mode oscillation is increased by resistors.

  When the semiconductor device 5 is disposed on a mounting member (not shown) and connected to the external terminal from the conductive regions 51 and 52 of the output relay substrate 50, another loop may occur. In this case, the odd mode is further suppressed by the resistor R51 connected to the conductive regions 51 and 52, respectively.

For example, the use of high dielectric material, such as a relative dielectric constant 140, as represented in FIG. 2 (b), the input capacitor C _I between the conductive region provided in the input capacitor substrate 20 and the ground is formed Then, the output capacitor _CO is formed between the conductive region provided on the output capacitor substrate 30 and the ground. Matching circuit on the input side can be configured by a bonding wire LG and consists T circuit between the bonding wires LI, an input capacitor C _I, and the gate terminal electrode 233 between the input relay board 40.

The output-side matching circuit can be constituted by a T-type circuit including a bonding wire LD between the drain terminal electrode 253, an output capacitance _CO, and a bonding wire LO between the output relay substrate 50.

FIG. 4 is a schematic plan view of the semiconductor device according to the first comparative example.
FIG. 5 is a configuration diagram of the semiconductor device according to the first comparative example.
The semiconductor device 105 includes a field effect transistor 110, an input capacitor substrate 120, an output capacitor substrate 130, bonding wires LI1 to LI8, LG1 to LG8, LD1 to LD8, and LO1 to LO4. The semiconductor device 105 may further include an input relay board 140 and an output relay board 150.

  In the field effect transistor 110, the gate bus line 331 is divided into eight for each of the cells MM1 to MM8, and only the gate finger electrodes of one cell are bundled. The eight divided gate bus lines 331 are connected by seven resistors R101 to R107, respectively. Further, the drain terminal electrode 353 is divided into eight for each of the cells MM1 to MM8, and only the drain finger electrodes of one cell are bundled, but no other cells are bundled on the field effect transistor 10. The loop LP11 including the cell MM1 and the cell MM2 is formed using the conductive regions 121 and 122 of the input capacitor substrate 120 and the conductive region of the output capacitor substrate 130 as connection points. In this case, the odd mode is further suppressed by the resistor R101 provided between the gate bus lines on the field effect transistor 10.

  The loop LP12 including the cells MM5 and MM8 is formed using the conductive region of the input capacitor substrate 120 and the conductive region of the output capacitor substrate 130 as connection points. In this case, the odd mode oscillation is suppressed by the resistor R106 provided between the gate bus lines on the field effect transistor 10. Since no cells are bundled on the field effect transistor 10, a composite loss occurs, and gain, output, and power added efficiency are reduced. In addition, since it is necessary to form an isolation resistance for each odd mode generated on the field effect transistor 10, the field effect transistor 10 must be created according to the frequency and loop of the generated odd mode oscillation.

FIG. 6 is a schematic plan view of a semiconductor device according to a second comparative example.
FIG. 7 is a configuration diagram of a semiconductor device according to a second comparative example.
The semiconductor device 105 includes a field effect transistor 110, an input capacitor substrate 120, an output capacitor substrate 130, and bonding wires. The semiconductor device 105 may further include an input relay board 140 and an output relay board 150.

  In the field effect transistor 110, the drain terminal electrode 353 is continuous. The loop LP15 includes two adjacent cells, and is formed using the conductive portion of the input capacitor substrate 120 and the drain terminal electrode 353 as a connection point. In this case, the odd mode oscillation is suppressed by the resistor R101 provided between the gate bus lines on the field effect transistor 10. Loop LP16 includes, for example, cell MM5 and cell MM8, and is formed using the conductive region of input capacitor substrate 120 and drain terminal electrode 353 as a connection point. In this case, the odd mode oscillation is suppressed by the resistor R106 provided between the gate bus lines on the field effect transistor 10. It is necessary to form an isolation resistor on the field effect transistor 10, and the field effect transistor 10 must be created according to the frequency and loop of the generated odd mode oscillation.

  On the other hand, in the semiconductor device according to the first embodiment shown in FIGS. 1 and 2, the isolation resistors R25 to R27 are formed on the circuit substrate outside the field effect transistor 10, and the isolation resistor is used as the field effect transistor. 10 is not built in, the field effect transistor can be used as a common component even when odd mode oscillation occurs.

FIG. 8 is a schematic plan view of a semiconductor device according to the second embodiment.
The semiconductor device 6 includes a semiconductor stacked body 17, a plurality of finger electrodes, gate bus lines 231a, 231b, 231c, and 231d, gate terminal electrodes 233a, 233b, 233c, 233d, 233e, 233f, 233g, and 233h, a drain Terminal electrodes 253a, 253b, 253c, 253d, 253e, source terminal electrodes (grounded via holes, not shown), resistors R31, R32, R33, R34, resistors R25, R26, R27, and input transmission line 540 And an output transmission line 560. The semiconductor device 6 according to the second embodiment can be called an MMIC (Microwave Monolythic Integrated Circuit) amplifier.

  The finger electrode has at least two finger gate electrodes, and a finger drain electrode and a finger source electrode provided so as to sandwich each finger gate electrode, and constitutes each cell.

  Gate terminal electrodes 233a to 233h are connected to the gate bus lines of cells M1 to M8, respectively. The gate bus lines of the cells M1 and M2 are short-circuited to form one gate bus line 231a, and a plurality of finger gate electrodes 230 of the cells M1 and M2 are bundled together as a group. Similarly, the gate bus lines 231b to 231d bundle the plurality of finger gate electrodes 230 in common for each group, and the drain terminal electrodes 253a to 253e bundle the plurality of finger drain electrodes 250 in common to each group.

  The source terminal electrode is connected to the back surface conductive portion of the semiconductor multilayer body through a via hole provided in the semiconductor multilayer body. The group (cell combination) bundled by the drain terminal electrode 253 is different from the group (cell combination) bundled by the gate bus line 231.

  The input transmission line 540 is connected to each of the gate terminal electrodes 233a to 233h and branches the input signal. In this figure, an input transmission line 540 includes transmission lines 545 and 546 that are bifurcated from the input terminal, transmission lines 541 and 542 that are bifurcated from the transmission line 545, and a transmission line 543 that is bifurcated from the transmission line 546. 544, and the like. For example, the transmission line 541 is further branched into two and connected to the gate terminal electrodes 233a and 233b of the cells M1 and M2. The electrical length is made equal from the input terminal to each cell.

  The output transmission line 560 is connected to each divided region of the drain terminal electrode 253 and synthesizes the output of the field effect transistor 10. The output transmission line 560 includes three stages of two composite transmission lines and is connected to the output terminal. The electrical length from each cell to the output terminal is made equal.

  The resistor R25 is connected to the gate terminal electrodes 233b and 233c, respectively. The resistor R26 is connected to the gate terminal electrodes 233d and 233e, respectively. The resistor R27 is connected between the gate terminal electrodes 233f and 233g, respectively.

  A plurality of loops are also formed in the MMIC in this embodiment, but the resistor R31 is connected between the drain terminal electrodes 253a and 253b. The (first) resistor R32 is connected between the drain terminal electrodes 253b and 253c. The resistor R34 is connected between the drain terminal electrodes 253d and 253e.

  In addition, at least one of the input transmission line 540 and the output transmission line 560 may include a quarter wavelength impedance converter. The quarter impedance converter operates as a matching circuit composed of distributed constants.

  In the field effect transistor 6, the channel formation region by the two-dimensional electron gas is left in a mesa shape and other regions are removed, or the outside of the field effect transistor 6 is used as an element isolation region by ion implantation.

  In the semiconductor device 6 according to the second embodiment, since two cells are connected at the cell end face, the imbalance between the cells is reduced, and the output synthesis efficiency can be increased.

  The field effect transistor and semiconductor device according to the present embodiment can be widely used in radar devices and communication devices.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  5, 6 Semiconductor device, 10 Field effect transistor, 17 Semiconductor stack, 20 Input capacitor substrate, 30 Output capacitor substrate, 540, 541, 542, 543, 544, 545, 546 Input transmission line, 560, 561, 562, 563 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574 output transmission line, 90 back surface conductive part, 212 via hole, 213 finger electrode, 230 finger gate electrode, 240 finger source electrode, 250 Finger drain electrode, 231 gate bus line, 233 gate terminal electrode, 243 source terminal electrode, 253 drain terminal electrode, S1, S2, S3, S4 slit, LI1-LI8 input bonding wire, LG1-LG8 gate bond Ding wire. LD1-LD8 drain bonding wire, LO1-LO8 output bonding wire, M1-M8 cell, R25-27 resistance, R31-34, R51 resistance

Claims (5)

A field effect transistor in which a plurality of cells for controlling operating current by finger electrodes provided on a semiconductor laminate are arranged in parallel,
A plurality of finger electrodes, each finger electrode having at least two finger gate electrodes, and a finger drain electrode and a finger source electrode provided so as to sandwich each finger gate electrode, and each cell Comprising a plurality of finger electrodes,
A gate bus line in which a plurality of finger gate electrodes are bundled in common for each group;
A gate terminal electrode connected to the gate bus line;
A drain terminal electrode in which a plurality of finger drain electrodes are bundled in common for each group;
A source terminal electrode bundled in common with a plurality of finger source electrodes, and connected to a back surface conductive portion of the semiconductor multilayer body through a via hole provided in the semiconductor multilayer body;
With
A field effect transistor, wherein the drain terminal electrode and the gate bus line are divided so that a combination of cells bundled by the drain terminal electrode and a combination of cells bundled by the gate bus line are different. The combination of cells bundled by the drain terminal electrode includes a combination of two adjacent cells,
The combination of cells that bundle the gate bus lines includes a combination of two adjacent cells,
The field effect transistor according to claim 1, wherein a division position of the drain terminal electrode and a division position of the gate bus line are alternate. A semiconductor device including a field effect transistor in which a plurality of cells for controlling operating current by finger electrodes are arranged in parallel,
A semiconductor laminate;
A plurality of finger electrodes provided on the semiconductor laminate, each finger electrode comprising at least two finger gate electrodes, a finger drain electrode and a finger source provided so as to sandwich each finger gate electrode A plurality of finger electrodes, each comprising a cell,
A plurality of gate bus lines in which a plurality of finger gate electrodes are bundled in common for each group;
A gate terminal electrode having a plurality of regions connected to each gate bus line;
A drain terminal electrode having a plurality of regions in which a plurality of finger drain electrodes are bundled in common for each group;
Through a conductive portion in a via hole provided in the semiconductor stacked body, a source terminal electrode connected to a back surface conductive portion of the semiconductor stacked body;
A resistor connecting two regions of the drain terminal electrode;
A resistor connecting two regions of the gate terminal electrode;
An input transmission line that branches an input signal and is connected to each region of the gate terminal electrode;
An output transmission line that is connected to each region of the drain terminal electrode and synthesizes the output of the field effect transistor;
With
A semiconductor device in which a combination of cells bundled by the drain terminal electrode and a combination of cells bundled by the gate terminal electrode are different. The combination of cells bundled by the drain terminal electrode includes a combination of two adjacent cells,
The combination of cells that bundle the gate bus lines includes a combination of two adjacent cells,
The semiconductor device according to claim 3, wherein a position where the drain terminal electrode is divided into the plurality of regions and a position where the gate terminal electrode is divided into the plurality of regions are alternate.   The semiconductor device according to claim 3 or 4, wherein at least one of the input transmission line and the output transmission line includes a quarter-wavelength impedance converter.