JP2016218670A - Semiconductor integrated circuit design assist device, semiconductor integrated circuit design assist method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently increase the bits of a cell to multi-bits in designing a semiconductor integrated circuit.SOLUTION: A semiconductor integrated circuit design assist device 1 performs circuit design on the basis of a circuit specification and generates circuit information (HDL), performs logic synthesis on the circuit information (HDL) using a cell library that includes the cell information of a semiconductor integrated circuit, and generates circuit information (NETLIST) which is logic circuit information that includes placement-wiring information on the placement of cells and wiring to cells. The semiconductor integrated circuit design assist device 1 executes the placement of cells and wiring to the cells on the basis of the placement-wiring information of the circuit information (NETLIST), refers to the cell library on the basis of the result of execution of the placement-wiring, and increases the bits of cells to turn the small-bit cells of the circuit information (NETLIST) into multi-bit cells.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit design support apparatus, a semiconductor integrated circuit design support method, and a program, and more particularly to a semiconductor integrated circuit design support apparatus, a semiconductor integrated circuit design support method, and a program that support the design of a semiconductor integrated circuit.

  Semiconductor integrated circuit design has been performed using a semiconductor integrated circuit design support apparatus, and the semiconductor integrated circuit design support apparatus generally includes a CAD (Computer Aided Design) tool which is a design tool. A computer is used. The semiconductor integrated circuit design support device is data indicating a connection state of a circuit to be a design support target by reading a file described in a hardware description language (HDL) by a CAD tool and performing logic synthesis. Generate a netlist.

  On the other hand, in recent years, with the increase in scale of semiconductor integrated circuits, a design method for reducing the power consumption of the semiconductor integrated circuits is demanded. One design technique for reducing the power consumption of a semiconductor integrated circuit is a design technique using a “multi-bit flip-flop” cell library in which a clock line circuit with large power consumption is shared.

  However, the conventional design method using a cell library of multi-bit flip-flops has an adverse effect of increasing the degree of congestion at the time of placement and routing, and selecting the optimal multi-bit flip-flop cells and selecting the optimal number of bits at the time of logic synthesis It was difficult.

  Conventionally, a plurality of unit cells that each perform a predetermined logic function are virtually wired at the time of logic synthesis by the logic synthesis unit, and a plurality of bit units are obtained by combining a part of the plurality of unit cells that are virtually wired. The multi-bit cell is generated, the arrangement processing unit arranges the plurality of unit cells and the plurality of multi-bit cells, and the control unit eliminates the virtual wiring congestion between the plurality of unit cells and the plurality of multi-bit cells. Thus, there is proposed a method for designing a semiconductor integrated circuit in which reconnection of virtual wiring is controlled, and a wiring processing unit performs main wiring between the plurality of unit cells and the plurality of multi-bit cells (see Patent Document 1). .

  That is, this prior art attempts to prevent wiring congestion when using multi-bit cells by changing the virtual wiring of multi-bit cells during placement and routing.

  However, in the prior art described in the above publication, since the virtual wiring of the multi-bit cell is changed at the time of placement and routing, it is difficult to select the optimal multi-bit cell at the time of logic synthesis and the optimal bit The number could not be determined and needed improvement.

  Therefore, an object of the present invention is to efficiently select a multi-bit cell having an optimum number of bits in the design of a semiconductor integrated circuit.

  To achieve the above object, a semiconductor integrated circuit design support apparatus according to claim 1 is a circuit including circuit design means for generating circuit information by performing circuit design based on circuit specifications, and a circuit including cell information of the semiconductor integrated circuit. Circuit-related information storage means for storing related information, and logic synthesis is performed on the circuit information using the circuit-related information to generate logic circuit information including cell placement and wiring placement / wiring information for the cell. A logic circuit information generating unit configured to perform placement and routing of the cell based on the placement and routing information of the logic circuit information, and refer to the circuit related information based on the placement and routing result. And a multi-bit arrangement / wiring unit that multi-bits the low-bit cell of the logic circuit information into a multi-bit cell.

  According to the present invention, it is possible to efficiently select a multi-bit cell having an optimum number of bits in designing a semiconductor integrated circuit.

1 is a block configuration diagram of a semiconductor integrated circuit design support apparatus to which an embodiment of the present invention is applied. The figure which shows an example of a cell library. The figure which shows an example of virtual 0 bit flip-flop and its circuit information. The figure which shows an example of a virtual 1 bit flip-flop and its circuit information. The figure which shows an example of virtual 2-bit flip-flop and its circuit information. The figure which shows an example of a virtual 4-bit flip-flop and its circuit information. The figure which shows an example of the information of a cell library. The functional block diagram of a semiconductor integrated circuit design support apparatus. The figure which shows an example of the circuit information (HDL) which a circuit design part produces | generates. The figure which shows an example of the circuit information (NETLIST) produced | generated from the circuit information (HDL) of FIG. The figure which shows an example of the circuit information (NETLIST) using the multibit flip flop produced | generated from the circuit information (HDL) of FIG. The figure which shows the circuit based on the circuit information (NETLIST) of FIG. FIG. 13 is a diagram showing a circuit using a multi-bit flip-flop based on the circuit information (NETLIST) in FIG. 12. Explanatory drawing of the wiring congestion degree in 1 bit flip-flop. Explanatory drawing of the wiring congestion degree in a multi-bit flip-flop. Explanatory drawing of arrangement | positioning of 1 bit flip-flop when the position of input / output is mutually separated relatively. Explanatory drawing of arrangement | positioning of 4 bit flip-flop when the position of input / output is comparatively separated mutually. Explanatory drawing of arrangement | positioning of 1 bit flip-flop when the position of input / output is mutually close. Explanatory drawing of arrangement | positioning of a 4-bit flip-flop when the position of input / output is mutually close. 5 is a flowchart showing semiconductor integrated circuit design support processing. Explanatory drawing of the logical equivalence of a multi-bit flip-flop and the multi-bit conversion method. Explanatory drawing of the logical equivalence of a multi-bit flip-flop and another multi-bit conversion method. The figure which shows the correspondence of the circuit information (NETLIST) using 1 bit flip flop, and the circuit information (NETLIST) using virtual 1 bit flip flop. Explanatory drawing of the multi-bit method from the circuit which has arrange | positioned the virtual flip-flop. Explanatory drawing of the multi-bit conversion method from the other circuit which has arrange | positioned the virtual flip-flop. Explanatory drawing of search range determination. Explanatory drawing of multi-bits of a virtual flip-flop and circuit information change. Explanatory drawing of the reconnection of the cell after multi-bit-ization. Explanatory drawing of the search of multi-bit conversion object when the input / output positions are close to each other. FIG. 30 is an explanatory diagram of increasing the number of bits in the case of FIG. 29.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 30 are diagrams showing an embodiment of a semiconductor integrated circuit design support apparatus, semiconductor integrated circuit design support method and program according to the present invention. FIG. 1 shows a semiconductor integrated circuit design support apparatus and semiconductor according to the present invention. 1 is a block configuration diagram of a semiconductor integrated circuit design support apparatus 1 to which an embodiment of an integrated circuit design support method and program is applied.

  In FIG. 1, a semiconductor integrated circuit design support apparatus 1 is constructed by mounting a program for executing a semiconductor integrated circuit design support method of the present invention on a computer having a normal hardware configuration and software configuration. The semiconductor integrated circuit design support device 1 of this embodiment is constructed by a single computer, but a plurality of computers, a mass storage device, and the like are connected via a network such as a LAN (Local Area Network) or the Internet. It may be constructed by doing.

  A semiconductor integrated circuit design support apparatus 1 includes a CPU (Central Processing Unit) 2, a ROM (Read Only Memory) 3, a RAM (Random Access Memory) 4, a nonvolatile memory 5, an input I / F (Input / Output) 6, and an output. An I / F 7 and an external I / F 8 are provided. In the semiconductor integrated circuit design support device 1, the above-described units are connected by a bus 9.

  An input device 11 such as a keyboard, a mouse, a stylus pen, and a touch panel is connected to the input I / F 6, and the input I / F 6 outputs various commands input from the input device 11 to the CPU 2.

  An output device 12 such as a display, a lamp, a speaker, and a printer is connected to the output I / F 7. The output I / F 7 is displayed on the output device 12 under the control of the CPU 2, blinking data, audio data, and recording data. Output data such as

  The external I / F 8 is connected to a network, an external storage device, and the like. The external I / F 8 performs communication under control of the CPU 2 by controlling protocols such as TCP / IP (Transmission Control Protocol / Internet Protocol) and SMTP (Simple Mail Transfer Protocol) / POP (Point Of Production). The external I / F 8 writes data to the external storage device and reads data from the external storage device under the control of the CPU 2.

  The ROM 3 stores a computer OS (Operating System), a basic program as the semiconductor integrated circuit design support apparatus 1, a program for executing the semiconductor integrated circuit design support method of the present invention, system data, and the like. The ROM 3 stores a placement and routing tool program and the like as a program that complements the program for executing the semiconductor integrated circuit design support method.

  The RAM 4 is used as a work memory for the CPU 2 and stores various data associated with execution of the semiconductor integrated circuit design support method.

  The CPU 2 uses the RAM 4 as a work memory based on a program in the ROM 3 to control each unit of the semiconductor integrated circuit design support apparatus 1 and executes basic processing as the semiconductor integrated circuit design support apparatus 1. Further, the CPU 2 executes the semiconductor integrated circuit design support method of the present invention based on the program of the semiconductor integrated circuit design support method in the ROM 3.

  The nonvolatile memory 5 is an NVRAM (Nonvolatile Random Access Memory), an SSD (Solid State Drive), a hard disk, or the like, and is a memory that retains stored contents even when the power of the semiconductor integrated circuit design support device 1 is OFF. .

  The nonvolatile memory 5 is, for example, a system setting value or a semiconductor integrated circuit design support device management method of the present invention as data that needs to be stored even when the power of the semiconductor integrated circuit design support device 1 is OFF. Various data to be used are stored under the control of the CPU 2. In particular, the nonvolatile memory 5 stores a cell library (circuit related information) CL as shown in FIG. The cell library CL includes information such as a 1-bit flip-flop DFF, a 2-bit flip-flop DFF2, and a 4-bit flip-flop DFF4. Further, the nonvolatile memory 5 includes a virtual 0-bit flip-flop cell VDFF0 generated from these 1-bit flip-flop DFF, 2-bit flip-flop DFF2, 4-bit flip-flop DFF4, etc. and its circuit information VkJ0, FIG. 4 virtual 1-bit flip-flop cell VDFF1 and its circuit information VkJ1, virtual 2-bit flip-flop cell VDFF2 and its circuit information Vkj2 as shown in FIG. 5, virtual 4-bit flip-flop VDFF4 and its circuit information as shown in FIG. Stores Vkj4 etc. Further, the nonvolatile memory 5 stores circuit information as shown in FIG. 7 as the cell library CL. That is, as shown in FIG. 7, the circuit information of the cell library CL includes cell names (BUF, DFF, DFF4, etc.), cell areas (areas: 1, 4, 14, etc.), power consumption values (2, 10). , 30 etc.) all of the information necessary for logic synthesis and placement and routing are included. For example, FIG. 7 shows that the size of the library cell named “BUF” is “1” and the power consumption value is “2”.

  The semiconductor integrated circuit design support apparatus 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), and a CD-RW (Compact Disc Rewritable). ), DVD (Digital Versatile Disk), USB (Universal Serial Bus) memory, SD (Secure Digital) card, MO (Magneto-Optical Disc), etc. A semiconductor integrated circuit design support method for efficiently selecting a multi-bit cell having an optimum number of bits in designing a semiconductor integrated circuit to be described later by reading a program for executing the circuit design support method and introducing the program into the ROM 3 or the nonvolatile memory 5 It is constructed as a semiconductor integrated circuit design support device that executes A program for executing this semiconductor integrated circuit design support method is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark), an object-oriented programming language, or the like. It can be stored in the recording medium and distributed.

  The semiconductor integrated circuit design support apparatus 1 is configured with the functional blocks shown in FIG. 8 by introducing a program for executing the semiconductor integrated circuit design support method. In other words, when the program is introduced, the semiconductor integrated circuit design support apparatus 1, as shown in FIG. 34 is built.

  The circuit design unit 31 is constructed by the CPU 2, the RAM 4, and the like. The circuit design unit 31 performs circuit design based on circuit specifications input from the input device 11 or circuit specifications stored in an external memory input via the external I / F 8 to generate circuit information. This circuit information is described in HDL (Hardware description language), and the time-dependent behavior and spatial structure of the semiconductor integrated circuit are described in a computer language described in characters. Therefore, the circuit design unit 31 functions as circuit design means.

  For example, the circuit design unit 31 generates circuit information (HDL) by HDL as shown in FIG. FIG. 9 shows circuit information using Verilog language as HDL, and the module name is declared “DUT” in the first line. The circuit information (HDL) in FIG. 9 is a statement in the second to fifth lines, has two input ports “CLK” and “IN”, one output port “OUT”, and a register “REG”. It is described to have It is described that these input / output ports and data types are all 4 bits. Further, the circuit information of FIG. 9 is a procedure assignment statement in the seventh to ninth lines, and a flip-flop in which the input signal “IN” is non-blocking assigned to the register type “REG” at the rising edge of “CLK”. It is described that. Furthermore, the circuit information in FIG. 9 describes that “REG” is assigned to the output port “OUT” by the continuation assignment statement on the eleventh line. That is, it is described that the “DUT” module is a module that latches the input signal “IN” at the rising edge of “CLK” and outputs it to “OUT”.

  The cell library storage unit 32 is constructed by the nonvolatile memory 5. The cell library storage unit 32 stores a cell library CL as shown in FIG. 2 as library information (circuit related information) of the semiconductor integrated circuit. As described above, the cell library CL includes information such as a 1-bit flip-flop DFF, a 2-bit flip-flop DFF2, and a 4-bit flip-flop DFF4. Therefore, the cell library storage unit 32 functions as cell library storage means.

  The logic circuit information generation unit 33 is constructed by the CPU 2, the RAM 4, and the like. The logic circuit information generation unit 33 uses the library information (cell library CL) in the cell library storage unit 32 to perform logic synthesis on the circuit information generated by the circuit design unit 31 to thereby arrange the cell arrangement and the cell. Circuit information (NETLIST), which is logic circuit information including layout and wiring information such as wiring, is generated. In the following description, the logic circuit information is appropriately referred to as circuit information (NETLIST).

  Specifically, the logic circuit information generation unit 33 generates, for example, a virtual 0-bit flip-flop cell VDFF0 as shown in FIG. 3A, and circuit information (NETLIST) of the virtual 0-bit flip-flop cell VDFF0 at this time Is as shown in FIG. In the virtual 0-bit flip-flop cell VDFF0 shown in FIG. 3A, the flip-flop of the cell library CL is not instantiated (materialized) inside the module. The virtual 0-bit flip-flop cell VDFF0 module has a 4-bit input and output. Since the virtual 0-bit flip-flop cell VDFF0 in FIG. 3A has 0 bits, all input ports are floating and all outputs are fixed at “0” (ground).

  Further, the logic circuit information generation unit 33 generates a virtual 1-bit flip-flop cell VDFF1 as shown in FIG. 4A, and the circuit information (NETLIST) of the virtual 2-bit flip-flop VDFF1 at this time is shown in FIG. It becomes like b). In the virtual 1-bit flip-flop cell VDFF1 shown in FIG. 4A, the 1-bit flip-flop DFF of the cell library CL is instantiated inside the module, but the virtual 1-bit flip-flop cell VDFF1 has a 4-bit input. And have an output. Since the virtual 1-bit flip-flop cell VDFF1 in FIG. 4A is 1 bit, the unused input port is floating, and the unused output is fixed at “0” (ground). Has been.

  Further, the logic circuit information generation unit 33 generates the virtual 2-bit flip-flop cell VDFF2 as shown in FIG. 5A, and the circuit information (NETLIST) of the virtual 2-bit flip-flop VDFF2 at this time is shown in FIG. It becomes like b). In the virtual 2-bit flip-flop cell VDFF2 shown in FIG. 5A, the 2-bit flip-flop DFF2 of the cell library CL is instantiated inside the module, but the virtual 2-bit flip-flop cell VDFF1 has a 4-bit input. And have an output. Since the virtual 2-bit flip-flop cell VDFF2 in FIG. 5A is 2 bits, the unused input port is floating, and the unused output is fixed at “0” (ground). Has been.

  The logic circuit information generation unit 33 generates a virtual 4-bit flip-flop cell VDFF4 as shown in FIG. 6A, and the circuit information (NETLIST) of the virtual 4-bit flip-flop VDFF4 at this time is shown in FIG. It becomes like b). In the virtual 4-bit flip-flop cell VDFF4 shown in FIG. 6A, the 4-bit flip-flop DFF4 of the cell library CL is instantiated inside the module, and the virtual 4-bit flip-flop DFF4 module has a 4-bit input. Have output. Now, since the virtual 4-bit flip-flop cell VDFF4 of FIG. 6A is 4 bits, there is no input port floating and there is no output fixed to “0”.

  The virtual flip-flop cells VDFF0, VDFF1, VDFF2, and VDFF4 have port usage information. In the virtual 0-bit flip-flop cell VDFF0, the default port usage information is D [0], D [1], D [2 ], All D [3] ports are not used. In the virtual 1-bit flip-flop cell VDFF1, the D [0] port is used as default port usage information, and other ports are not used. In the virtual 2-bit flip-flop cell VDFF2, the default port usage information uses the D [0] and D [1] ports and does not use other ports. Further, in the virtual 4-bit flip-flop cell VDFF4, the default port usage information uses all ports D [0], D [1], D [2], and D [3].

  The logic circuit information generation unit 33 temporarily stores the virtual flip-flop cells VDFF0, VDFF1, VDFF2, and VDFF4 generated as described above in the nonvolatile memory 5 or the like.

  Note that the logic circuit information generation unit 33 performs logic synthesis on the circuit information (HDL) shown in FIG. 9 using the 1-bit flip-flop cell DFF, for example, as shown in FIG. Generate information (NETLIST). In the circuit information (NETLIST) in FIG. 10, the procedure assignment statements in the seventh to ninth lines of the circuit information (HDL) in FIG. 2 are mapped to “DFF” of the 1-bit flip-flop, and the continuation in the eleventh line. The assignment statement is mapped to “BUF” which is a 1-bit buffer cell. Since “DFF” and “BUF” are 1-bit library cells, the circuit information (NETLIST) in FIG. 10 uses four DFF cells and four BUF cells in order to realize 4-bit substitution.

  Further, the logic circuit information generation unit 33 generates circuit information (NETLIST) using a multi-bit flip-flop (4-bit flip-flop DFF4) as shown in FIG. 11 from the circuit information (HDL) shown in FIG. . In the semiconductor integrated circuit design support device 1 of the present embodiment, for further multi-biting, the multi-bit placement / wiring unit 34 (to be described later) actually performs placement / wiring, and after verifying the result, the multi-bit placement is performed. Do. In FIG. 11, the procedure assignment statement in the 7th to 9th lines of the circuit information (HDL) in FIG. 9 is mapped to “DFF4” of the 4-bit flip-flop, and the continuation assignment statement in the 11th line is a 1-bit buffer cell. Mapping to "BUF". Since “DFF4” can implement 4-bit procedure substitution in one cell, one “DFF4” and four “BUF” are used.

  The multi-bit arrangement / wiring unit 34 is constructed by the CPU 2, the RAM 4, and the like. The multi-bit arrangement and wiring unit 34 performs cell arrangement and wiring to the cell based on the arrangement and wiring information of the circuit information (NETLIST) that is the logic circuit information. Further, the multi-bit placement and routing unit 34 refers to the library information in the cell library storage unit 32 based on the result of the placement and routing that has been performed, and increases the number of small bit cells (small bit flip-flops) in the circuit information (NETLIST). The number of bits is changed to a bit cell (multi-bit flip-flop). Therefore, the multi-bit arrangement / wiring unit 34 functions as multi-bit arrangement / wiring means.

  For example, the multi-bit placement and routing unit 34 performs wiring based on the placement and routing information of the circuit information (NETLIST) shown in FIG. 10 and generates a circuit diagram as shown in FIG. FIG. 12 is a circuit diagram using four DFF cells and BUF cells since “DFF” and “BUF” are 1-bit library cells as shown in FIG.

  Further, as shown in FIG. 13, the multi-bit arrangement / wiring unit 34 is based on circuit information (NETLIST) using a multi-bit flip-flop, for example, the 4-bit flip-flop DFF4 shown in FIG. Place and route. FIG. 13 is a circuit diagram using one DFF cell (DFF4) and four BUF cells because “DFF4” is a 4-bit library cell and “BUF” is a 1-bit library cell as shown in FIG. ing.

  As will be described later, the multi-bit arrangement / wiring unit 34 determines the arrangement by changing the connection with the multi-bit flip-flop based on the cell arrangement information in the multi-bit flip-flop. After that, the number of stages of the multi-bit flip-flop is determined.

  In addition, when the logic circuit information generation unit 33 generates a virtual flip-flop library of circuit information (HDL) as circuit information (NETLIST) that is logic circuit information, the multi-bit placement and routing unit 34 generates a virtual flip-flop library. Increase the number of flip-flops.

  Further, the multi-bit arrangement / wiring unit 34 may include a search unit (search means) (not shown) that searches the arrangement information for the presence / absence of cells in a predetermined peripheral range of the flip-flop. In this case, the multi-bit placement and routing unit 34 determines whether or not the flip-flop is multi-bit based on the search result of the search unit and multi-bits. This search unit and multi-biting based on the search will be described later.

  Next, the operation of this embodiment will be described. The semiconductor integrated circuit design support apparatus 1 of the present embodiment efficiently selects a multi-bit cell having an optimum number of bits in designing a semiconductor integrated circuit.

  In the semiconductor integrated circuit design support device 1, when a circuit specification is input, the circuit design unit 31 generates circuit information (HDL) as shown in FIG. 9, for example. Next, in the semiconductor integrated circuit design support device 1, the logic circuit information generation unit 33 refers to the cell library storage unit 32 to generate circuit information (NETLIST) as shown in FIG. 10. At this time, the multi-bit placement and routing unit 34 generally constructs a circuit using the 1-bit flip-flop shown in FIG.

  In the circuit information (NETLIST) shown in FIG. 10, the size of the entire circuit is (DFF size × 4) + (BUF size × 4), which is “20”. In the circuit information (NETLIST) shown in FIG. 10, the power consumption value of the entire circuit is (DFF power consumption value × 4) + (BUF power consumption value × 4), which is “48”.

  On the other hand, when circuit information (NETLIST) using the multi-bit flip-flop shown in FIG. 11 is obtained as a result of logic synthesis, the size of the entire circuit is (DFF4 size × 1) + (BUF size) X4), which is “18”. In this case, the power consumption value of the entire circuit is (DFF4 power consumption value × 1) + (BUF power consumption value × 4), which is “38”.

  That is, in the case of the above example, even if the circuit information (NETLIST) obtained as a result of using the cell library is logically equivalent, a 4-bit “DFF” is obtained from the circuit of FIG. Using one “DFF4” reduces the overall circuit size and power consumption. Therefore, in general, using a multi-bit flip-flop library cell saves area and consumes less power.

  However, in designing a semiconductor integrated circuit, it is necessary to consider the degree of wiring congestion.

  For example, in the case where the multi-bit layout and wiring unit 34 performs circuit layout and wiring using the circuit information (NETLIST) using the 1-bit flip-flop DFF as illustrated in FIG. 10, as illustrated in FIG. In general, library cells are arranged so that the wiring of the data line is the shortest. That is, the cell arrangement as shown in FIG. In this case, the multi-bit arrangement / wiring unit 34 has an input port (IN [0] to IN [3] and CLK) and an output port (OUT [0] to OUT [3]) that are in the shape of a semiconductor integrated circuit or a semiconductor. Since the position is fixed by the restriction of the board on which the integrated circuit is installed, the arrangement positions of the library cells of “DFF” and “BUF” are adjusted so that the wiring of the data line becomes the shortest. That is, since “DFF” and “BUF” are 1-bit cell libraries, they have a high degree of freedom and can be arranged at the most ideal positions.

  In FIG. 14A, the number of wirings intersecting with a broken-line circle indicating a certain range centered on “DFF” arranged is only three: a clock, an input data signal, and an output data signal.

  Therefore, as shown in FIG. 14B, as a result of the ideal circuit arrangement, the shortest possible wiring is possible, as is the case with the wiring 0, and there is a margin between other wirings. Can do.

  However, using the circuit information (NETLIST) using the 4-bit flip-flop DFF4 as shown in FIG. 11, the multi-bit arrangement / wiring unit 34 arranges the circuit, and the circuit information is shown in FIG. 15 (a). It is assumed that such an arrangement has been made.

  In FIG. 15A, since one “DFF4” is a cell library of 4-bit flip-flops, “DFF4” is arranged around the center in order to have the shortest wiring. The “BUF” cell library has a high degree of freedom as in FIG.

  In FIG. 15A, the number of wirings intersecting with a broken-line circle indicating a certain range centered on “DFF4” is 9 clocks, input data signals × 4, and output data signals × 4. . Therefore, as compared with the circuit of FIG. 14 in which four “DFFs” are arranged, it can be seen that wiring is concentrated and wiring congestion is likely to occur.

  In FIG. 15B, the wiring 2 can be the shortest wiring, but the wiring 0 ′ has a longer wiring length than the wiring 0 of FIG. 14B. Further, in the circuit of FIG. 15, since all the wirings from IN [0] to IN [3] are connected to the “DFF4” library cell, the wirings around “DFF4” are dense.

  In other words, the use of a 4-bit flip-flop DFF4 library cell has the advantage of reducing the size and power consumption, but the wiring length becomes longer, the wiring around the 4-bit flip-flop library cell becomes dense, etc. Depending on the situation of other wiring, wiring congestion may occur.

  Further, the input / output positions may differ depending on the semiconductor integrated circuit. In such a case, the arrangement of the flip-flops differs depending on the input / output positions.

  For example, FIG. 16 shows the arrangement and wiring of four 1-bit flip-flops DFF when the input / output positions are relatively far apart. In FIG. 16, the 1-bit flip-flop DFF is arranged at the position where the wiring from the input (IN [*]) to the output (OUT [*]) is the shortest for each bit. The distance from the DFF is also set at a certain distance.

  Therefore, the wiring around the DFF cell is also distributed, and the wiring crossing the broken-line circle in FIG. 16 is the DFF control signal (CLK), data input, and output.

  On the other hand, even in the case of a semiconductor integrated circuit having the same relatively distant input / output position, when one 4-bit flip-flop DFF4 is arranged, the result is as shown in FIG. That is, as shown in FIG. 17, since there is a connection from all inputs to one 4-bit flip-flop DFF4, the wiring length between bits is greatly different wherever the 4-bit flip-flop DFF4 is arranged. In FIG. 17, there is a large difference between the wiring length from IN [0] to “DFF4” and the wiring length from IN [2] to “DFF4”, and the wiring length is similarly different on the output side. Further, as shown in FIG. 17, the wiring is concentrated on the cells of the 4-bit flip-flop DFF4, and the wiring crossing the broken-line circle is the control signal (CLK) and data input × 4 of the 4-bit flip-flop DFF4. , Output × 4, 9 in total.

  Accordingly, in the arrangement and wiring situation of FIG. 17, the total wiring length becomes longer and the wiring around “DFF4” becomes denser than the arrangement and wiring situation of FIG.

  Next, FIG. 18 is a diagram showing the arrangement and wiring of the 1-bit flip-flop DFF when the input / output positions are relatively close to each other. In the case of FIG. 18, when the input / output positions are very close, the arrangement of the 1-bit flip-flop DFF has the shortest wiring from the input (IN [*]) to the output (OUT [*]) for each bit. Therefore, the 1-bit flip-flop DFF is also arranged at a very close position. Therefore, as shown in FIG. 18, the wiring intersecting with the broken-line circle is the wiring around the four “DFFs” arranged nearby, and the input of the control signal CLK and the data of the four 1-bit flip-flops DFF. The output is 9 in total.

  FIG. 19 is a diagram showing the arrangement and wiring of the 4-bit flip-flop DFF4 when the input / output positions are relatively close to each other. In the case of FIG. 19, when the input / output positions are very close, the arrangement of the 4-bit flip-flop DFF4 has the shortest wiring from the input (IN [*]) to the output (OUT [*]) for each bit. Placed in position. Accordingly, as shown in FIG. 19, the number of wirings around the 4-bit flip-flop DFF4 is nine in total with the input of the control signal CLK and four data and the four outputs.

  That is, when the input / output positions are very close, the wiring length may slightly increase as compared with the case where the 1-bit flip-flop DFF is arranged, but the number of wirings around the cell does not change. Therefore, even if the four 1-bit flip-flops DFF are changed to the 4-bit flip-flops DFF4, the influence on the wiring congestion is extremely small. As a result, when the input / output positions are very close, converting four 1-bit flip-flops DFF to 4-bit flip-flops has the same risk of wiring congestion, and can realize area saving and power saving.

  As described above, if the influence on the wiring congestion (the number of surrounding wiring lines) is almost the same as that of the 1-bit flip-flop, the design of a semiconductor integrated circuit advantageous for power consumption can be realized by increasing the number of bits. . Also, as shown in FIGS. 16 to 19, it cannot be accurately determined whether or not multi-biting is effective unless arrangement is performed.

  Therefore, in the semiconductor integrated circuit design support apparatus 1 of this embodiment, the logic circuit information generation unit 33 uses the cell library CL of the cell library storage unit 32 based on the circuit information (HDL) generated by the circuit design unit 31. Circuit information (NETLIST). Then, the multi-bit placement and routing unit 34 actually constructs a semiconductor integrated circuit based on the circuit information (NETLIST), and multi-bits by performing multi-bit evaluation of the flip-flop of this semiconductor integrated circuit. Determine whether or not. That is, in the semiconductor integrated circuit design support device 1, in the multi-bit flip-flop, the multi-bit layout / wiring unit 34 connects to the multi-bit flip-flop based on the cell layout information in the multi-bit flip-flop. After changing and determining the arrangement, the number of stages of the multi-bit flip-flop is determined.

  Further, the multi-bit arrangement / wiring unit 34 multi-bits the flip-flop based on the number of wirings of the flip-flop.

  Furthermore, in the semiconductor integrated circuit design support device 1, the logic circuit information generation unit 33 generates a virtual flip-flop library as circuit information (NETLIST) which is logic circuit information, and the multi-bit arrangement and wiring unit 34 The number of flip-flops in the flip-flop library is increased.

  The multi-bit arrangement / wiring unit 34 includes a search unit that searches the arrangement information for the presence / absence of cells in a predetermined peripheral range of the flip-flop. Based on the search result of the search unit, whether or not the multi-bit arrangement of the flip-flop is appropriate To determine the number of bits.

  Therefore, in the semiconductor integrated circuit design support apparatus 1 of this embodiment, as shown in FIG. 20, the CPU 2 executes the semiconductor integrated circuit design support processing based on the program for executing the semiconductor integrated circuit design support method in the ROM 3. .

  That is, in the semiconductor integrated circuit design support apparatus 1, when the circuit specification to be designed is input to the circuit design unit 31, the circuit design unit 31 generates circuit information (HDL) (step S101).

  Next, the logic circuit information generation unit 33 generates circuit information (NETLIST) using the circuit information (HDL) generated by the circuit design unit 31 and the cell library CL of the cell library storage unit 32 (step S102).

  The logic circuit information generation unit 33, as circuit information (NETLIST), corresponds to circuit information (HDL), for example, circuit information of a circuit including three 1-bit flip-flops DFF as shown in FIG. NETLIST). Further, the logic circuit information generation unit 33 is a circuit circuit including four 1-bit flip-flops DFF as shown in FIG. 22A according to the circuit information (HDL) as circuit information (NETLIST). Generate information (NETLIST).

  Furthermore, the logic circuit information generation unit 33 generates a circuit information (NETLIST) using a 1-bit flip-flop DFF as shown in FIG. 23A in accordance with the circuit information (HDL), for example. Circuit information (NETLIST) using the virtual 1-bit flip-flop VDFF1 as shown in FIG. 23 (b) may be generated. That is, in FIG. 23, the 1-bit flip-flop DFF in FIG. 23A is replaced with the virtual 1-bit flip-flop VDFF in FIG. The virtual 1-bit flip-flop VDFF is logically equivalent before and after the replacement because the 1-bit flip-flop DFF is instantiated inside.

  Next, in the semiconductor integrated circuit design support device 1, the multi-bit arrangement and wiring unit 34 first performs an arrangement and wiring process for configuring the semiconductor integrated circuit based on the logic circuit information circuit information (NETLIST) (step S 103). .

  When the virtual 1-bit flip-flop VDFF is used, the multi-bit arrangement / wiring unit 34 uses, for example, an arrangement / wiring process that configures circuits as shown in FIGS. 24 and 25 based on the logic circuit information circuit information (NETLIST). I do.

  When the multi-bit placement and routing unit 34 performs placement and routing, the multi-bit placement and routing unit 34 searches for a predetermined range around each cell and determines whether another cell exists (step S104). The multi-bit arrangement / wiring unit 34 performs the presence / absence of other cells using, for example, a known arrangement / wiring tool.

  The search range searched by the multi-bit arrangement and wiring unit 34 is, for example, a distance (double arrow) from the center of the virtual flip-flop (U_ff0) serving as a search reference, as shown in FIG. The simplest method for determining the search distance is the cell library CL. That is, since the size of the cell included in the cell library CL differs for each design process and library vendor, the multi-bit arrangement and routing unit 34 sets the search range to an appropriate value for each cell library CL.

  Further, the multi-bit arrangement / wiring unit 34 may change the search range depending on the cell arrangement density. In this case, the multi-bit arrangement and wiring unit 34 calculates the arrangement density based on the cell arrangement information. That is, it is known that there is generally a positive correlation between the arrangement density and the wiring congestion degree, and a state where the arrangement density is high is not a desirable state as the wiring congestion degree. Therefore, since the total number of areas is reduced by increasing the number of bits, and it is estimated that a good result for wiring congestion can be obtained if the arrangement density is lowered, it is effective to widen the search range. Further, the arrangement density can be calculated for the entire chip. For example, a method in which the vertical and horizontal sides of the chip are divided into four parts, divided into 16 areas, and the respective arrangement densities are calculated. The search range may be changed according to each area. That is, the number of bits can be controlled by changing the search range.

  The multi-bit arrangement and wiring unit 34 performs the search process as described above. In the case of FIG. 24, there is another virtual flip-flop in the search range (the range indicated by the dashed circle in FIG. 24). do not do.

  Therefore, in the case of FIG. 24, the multi-bit layout / wiring unit 34 determines that there is no cell nearby (NO in step S104), and performs the semiconductor integrated circuit design support process without performing multi-bit conversion. Exit.

  Further, the multi-bit arrangement / wiring unit 34 performs the search process as described above. In the case of FIG. 25, first, the range of the broken line is searched based on the cell U_ff0, U_ff1 is found, and U_ff1 is determined. A search is performed on the basis, and U_ff0 is found. Therefore, the multi-bit arrangement / wiring unit 34 sets U_ff1 and U_ff0 as multi-bit conversion targets. Similarly, the multi-bit arrangement / wiring unit 34 searches for U_ff2 and U_ff3 and sets it as a multi-bit target. However, the multi-bit arrangement / wiring unit 34 cannot find U_ff1 and U_ff2 in the search, and excludes U_ff1 and U_ff2 from multi-bit conversion targets.

  If the multi-bit placement and routing unit 34 finds that there is a cell nearby in the search (YES in step S104), it performs multi-bit processing (step S105).

  In this multi-bit processing, the multi-bit arrangement / wiring unit 34 determines a multi-bit target cell from the search result, determines a reference cell, and sets other cells as reference cells. Combined with cells, multi-bit.

  For example, in the case of FIG. 25, the multi-bit arrangement / wiring unit 34 multi-bits as shown in FIGS. 27 (a) and 27 (b). That is, in the case of FIG. 25, U_ff0 and U_ff1, U_ff2 and U_ff3 are multi-bit conversion targets. Therefore, the multi-bit arrangement / wiring unit 34 uses either U_ff0 or U_ff1 as the multi-bit reference cell from the arrangement information. The multi-bit arrangement / wiring unit 34 determines the reference cell from information such as surrounding arrangement density and wiring density, for example. Generally, since a 2-bit flip-flop has a larger cell size than a 1-bit flip-flop cell, the one having a lower arrangement density or wiring density is selected as a reference cell. As shown in FIG. 27, the multi-bit arrangement / wiring unit 34 uses U_ff0 and U_ff2 as reference cells.

  Next, the multi-bit arrangement / wiring unit 34 checks whether the two selected flip-flops can be multi-bit. The condition that enables multi-biting is that the control signals are the same as described above. In FIG. 27, both U_ff0 and U_ff1 have no reset, no enable, and the clock is connected with the same signal “CLK”, so that multiple bits are possible.

  Therefore, the multi-bit arrangement and wiring unit 34 changes the data signal of U_ff1 to U_ff0 which is the reference cell. Specifically, the multi-bit placement and routing unit 34 connects the signal IN [1] connected to the D0 port of U_ff1 to the D1 port of U_ff0 and the signal n [connected to the Q0 port of U_ff1. 1] is connected to the Q1 port of U_ff0. At this time, as shown in FIG. 27A, the multi-bit placement and routing unit 34 gives information that the D1 port is used to the port usage information of U_ff0, and the D0 port is added to the port usage information of U_ff1. Give information that it is no longer used. When the circuit information (NETLIST) is changed as shown in FIG. 27A to change the wiring connection, the connection shown in FIG. 27B is obtained.

  Next, the multi-bit arrangement and wiring unit 34 changes the cell. That is, referring to the port usage information of U_ff0, it can be seen that two ports D [0] and D [1] are used. Therefore, the multi-bit arrangement and wiring unit 34 changes U_ff0 from VDFF1 in FIG. 25 to VDFF2 cell as shown in FIG.

  Also, referring to the port usage information of U_ff1, it can be seen that not all ports are used. Therefore, the multi-bit arrangement and wiring unit 34 changes U_ff1 from VDFF1 in FIG. 25 to VDFF0 as shown in FIG.

  Then, the multi-bit arrangement / wiring unit 34 changes U_ff2 and U_ff3 to VDFF2 and VDFF0 in the same manner as U_ff0 and U_ff1.

  That is, the multi-bit arrangement / wiring unit 34 finally determines the number of bits only by confirming the use state of the virtual flip-flop port, and without changing the arrangement position, multi-bit conversion is performed. Execute.

  Next, when the multi-bit arrangement / wiring unit 34 changes the connection due to the multi-biting, the arrangement / wiring is performed again as shown in FIG. 28. When the wiring is completed, unnecessary cells are deleted. Then, confirm the change of the bit number of the cell.

  That is, the multi-bit arrangement / wiring unit 34 deletes the circuit information of VDFF0 which is no longer necessary as shown in FIG. 28A, and the cells and wiring by the remaining VDFF2 as shown in FIG. Connect.

  In this case, when the wiring is completed, the multi-bit arrangement / wiring unit 34 deletes VDFF0 and confirms the change in the number of bits of the cell. If the wiring is not completed, the multi-bit arrangement / wiring unit 34 Stop collecting the bits of the virtual flip-flop and restore the original VDFF1 wiring.

  Note that the semiconductor integrated circuit design support apparatus 1 of this embodiment determines a replacement reference cell and leaves VDFF0 scheduled to be finally deleted. Therefore, the original placement and routing information can be retained as much as possible. In particular, the clock wiring of the flip-flop has the most advantageous timing in the state where the clock tree is stretched most ideally after the initial placement and routing, and minimizes the influence on the timing due to the increase in the number of bits. be able to.

  In addition, as shown in FIG. 29, when the input / output positions are close, the multi-bit arrangement / wiring unit 34 searches for all the adjacent cells when all the adjacent cells are found. set to target.

  The multi-bit arrangement / wiring unit 34 indicates that the adjacent virtual 1-bit flip-flop VDFF1 exists in the search range of all the virtual 1-bit flip-flops VDFF1, as indicated by a broken-line circle in FIG. locate. That is, the multi-bit arrangement / wiring unit 34 first finds U_ff1 as a result of searching for a dotted circle range based on U_ff0, and then finds U_ff0 and U_ff2 as a result of searching based on U_ff1. The multi-bit placement and routing unit 34 further finds U_ff1 and U_ff3 as a result of performing a search based on U_ff2, and finally finds U_ff2 as a result of performing a search based on U_ff3.

  Therefore, the multi-bit arrangement / wiring unit 34 sets all U_ff0, U_ff1, U_ff2, and U_ff3 as multi-bit objects.

  Then, when all the cells are to be multi-bited, the multi-bit arrangement / wiring unit 34 multi-bits by a method of adding a new cell as shown in FIG.

  That is, the multi-bit arrangement / wiring unit 34 first checks whether the selected four flip-flops U_ff0, U_ff1, U_ff2, and U_ff3 can be multi-bit. The multi-bit arrangement / wiring unit 34 determines whether or not this multi-bit arrangement is possible as described above. That is, the multi-bit arrangement / wiring unit 34 is required to have the same control signal under the condition that multi-biting is possible. In the case of FIG. 29, all of U_ff0, U_ff1, U_ff2, and U_ff3 are not reset. Because no clock is enabled and the clock is connected with the same signal “CLK”, it is determined that the number of bits can be increased.

  Since U_ff0 to U_ff3 are 1-bit virtual flip-flops VDFF1, the total number of bits of flip-flops capable of multi-biting is “4”.

  In the semiconductor integrated circuit design support device 1 of the present embodiment, the virtual flip-flop library cell has 1 bit, 2 bits, and 4 bits, as shown in FIGS. VDFF4 is adopted and added as U_ff4 as shown in FIG.

  When the cells are added as described above, the multi-bit arrangement / wiring unit 34 connects the control signals. First, the multi-bit arrangement and wiring unit 34 connects the same signal as the signal connected to the control signal ports U_ff0 to U_ff3 to the control signal port (CK port) of U_ff4.

  Next, the multi-bit arrangement / wiring unit 34 changes the connection of the data signal. That is, the multi-bit arrangement and wiring unit 34 connects the signal IN [0] connected to the D0 port of U_ff0 to the D0 port of U_ff4, and the signal n [0] connected to the Q0 port of U_ff0 to U_ff4. Connect to the Q0 port. The multi-bit placement and routing unit 34 connects the signal IN [1] connected to the D0 port of U_ff1 to the D1 port of U_ff4, and the signal n [1] connected to the Q0 port of U_ff1 to Q1 of U_ff4 Connect to the port. Further, the multi-bit arrangement / wiring unit 34 connects the signal IN [2] connected to the D0 port of U_ff2 to the D2 port of U_ff4 and the signal n [2] connected to the Q0 port of U_ff2 to U_ff4 Connect to the Q2 port. Further, the multi-bit placement and routing unit 34 connects the signal IN [3] connected to the D0 port of U_ff3 to the D3 port of U_ff4, and the signal n [3] connected to the Q0 port of U_ff3 to U_ff4 Connect to the Q3 port.

  Finally, the multi-bit arrangement / wiring unit 34 deletes the virtual flip-flop VDFF1 from U_ff0 to U_ff3 that is the connection source, and changes the circuit information (NETLIST) in FIG.

  When the circuit information (NETLIST) is changed, the multi-bit arrangement / wiring unit 34 performs layout / wiring based on the circuit information (NETLIST) to generate a circuit as shown in FIG.

  As described above, the semiconductor integrated circuit design support apparatus 1 according to the present embodiment includes a circuit design unit (circuit design means) 31 that performs circuit design based on circuit specifications and generates circuit information (HDL), and a semiconductor integrated circuit. A cell library storage unit (circuit related information storage means) 32 for storing a cell library (circuit related information) CL including cell information, and logic synthesis is performed on the circuit information (HDL) using the cell library CL. A logic circuit information generating unit (logic circuit information generating means) 33 for generating circuit information (NETLIST) which is logic circuit information including cell arrangement and wiring arrangement / wiring information for the cells; and the circuit information (NETLIST) Based on the placement and routing information, the placement of the cells and the routing for the cells are performed, and the circuit information (NETLIST) is referred to the cell library CL based on the placement and routing results. It includes multiple bits placement and routing unit for multiple bits to low bit cell to the multi-bit cells and (multi-bit placement and routing section) 34, a.

  Therefore, in designing a semiconductor integrated circuit, a cell is mapped by using a cell library CL to perform logic synthesis on circuit information (HDL) generated from a circuit specification, and multi-bit based on the placement and routing information of the cell. Can be As a result, a multi-bit cell having the optimum number of bits can be efficiently selected.

  Further, the semiconductor integrated circuit design support apparatus 1 of this embodiment includes a circuit design processing step for generating circuit information (HDL) by performing circuit design based on circuit specifications, and a cell library storage unit (circuit related information storage means). 32 performs logic synthesis on the circuit information (HDL) using the cell library (circuit related information) CL including the cell information of the semiconductor integrated circuit stored in the cell 32, and arranges and arranges the cell and the wiring of the cell. A logic circuit information generation processing step for generating circuit information (NETLIST), which is logic circuit information including the circuit information, and placement and routing of the cells based on the placement and routing information of the circuit information (NETLIST) The multi-bit arrangement arrangement arrangement which refers to the cell library CL based on the execution result of the arrangement wiring and multi-bits the small bit cells of the circuit information (NETLIST) into multi-bit cells. A processing step, executing a semiconductor integrated circuit design support method has.

  Therefore, in designing a semiconductor integrated circuit, a cell is mapped by using a cell library CL to perform logic synthesis on circuit information (HDL) generated from a circuit specification, and multi-bit based on the placement and routing information of the cell. Can be As a result, a multi-bit cell having the optimum number of bits can be efficiently selected.

  Further, the semiconductor integrated circuit design support apparatus 1 of the present embodiment includes a circuit design process for generating circuit information (HDL) by performing circuit design based on the circuit specifications, and a cell library storage unit (circuit related information storage). Means) Using the cell library (circuit related information) CL including the cell information of the semiconductor integrated circuit stored in 32, the logic synthesis is performed on the circuit information (HDL), and the cell arrangement and the wiring arrangement for the cell are performed. Logic circuit information generation processing for generating circuit information (NETLIST), which is logic circuit information including wiring information, and placement of the cells and wiring to the cells based on the placement and routing information of the circuit information (NETLIST) A multi-bit arrangement that multi-bits a small bit cell of the circuit information (NETLIST) into a multi-bit cell by referring to the cell library CL based on the result of the placement and routing Are equipped with a program for executing the line process, the.

  Therefore, in designing a semiconductor integrated circuit, a cell is mapped by using a cell library CL to perform logic synthesis on circuit information (HDL) generated from a circuit specification, and multi-bit based on the placement and routing information of the cell. Can be As a result, a multi-bit cell having the optimum number of bits can be efficiently selected.

  Further, in the semiconductor integrated circuit design support device 1 of the present embodiment, the multi-bit arrangement and wiring unit 34 changes the connection to the multi-bit cell based on the arrangement and wiring information of the multi-bit cell and determines the arrangement. Later, the number of stages of the multi-bit cell is determined.

  Therefore, the number of bits can be increased in consideration of the wiring density, and a multi-bit cell having a more optimal number of bits can be efficiently selected.

  Furthermore, in the semiconductor integrated circuit design support device 1 of the present embodiment, the multi-bit placement and routing unit 34 multi-bits the cell based on the number of wirings of the cell.

  Therefore, the number of bits can be increased in consideration of the wiring density, and a multi-bit cell having a more optimal number of bits can be efficiently selected.

  Further, in the semiconductor integrated circuit design support device 1 of the present embodiment, the logic circuit information generation unit 33 generates circuit information (NETLIST) of virtual cells based on the circuit information (HDL), and the multi-bit arrangement The wiring unit 34 multi-bits the virtual cell.

  Therefore, it is possible to efficiently increase the number of bits using a virtual cell, and it is possible to more efficiently select a multi-bit cell having a more optimal number of bits.

  Furthermore, in the semiconductor integrated circuit design support device 1 of the present embodiment, the multi-bit layout and wiring unit 34 searches for the presence / absence of cells and the number of wirings in the predetermined peripheral range for each cell from the layout and wiring information ( Search means), and based on the search result of the search unit, the suitability of the cell for multi-biting is determined to perform multi-biting.

  Therefore, a cell in a more appropriate range can be multi-bited by searching, and a cell range to be multi-bit can be controlled by changing the search range. As a result, it is possible to efficiently select a multi-bit cell having a more optimal number of bits.

  In the semiconductor integrated circuit design support apparatus 1 of this embodiment, the cell is a flip-flop.

  Therefore, in designing a semiconductor integrated circuit using a flip-flop as a cell, the cell information is generated by logically synthesizing the circuit information (HDL) generated from the circuit specification using the cell library CL, and the cell is arranged. The number of bits can be increased based on the wiring information. As a result, a multi-bit cell having the optimum number of bits can be efficiently selected.

  In the above embodiment, the flip-flop has been described as the cell, but the cell is not limited to the flip-flop.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

1 Semiconductor Integrated Circuit Design Support Device 2 CPU
3 ROM
4 RAM
5 Nonvolatile memory 6 Input I / F
7 Output I / F
8 External I / F
9 Bus 11 Input device 12 Output device 31 Circuit design unit 32 Cell library storage unit 33 Logic circuit information generation unit 34 Multi-bit placement and routing unit CL Cell library
DFF 1-bit flip-flop
DFF2 2-bit flip-flop
DFF4 4-bit flip-flop
Circuit information of VkJ0, VkJ1, Vkj2, Vkj4
VDFF0 Virtual 0-bit flip-flop cell
VDFF1 Virtual 1-bit flip-flop cell
VDFF2 Virtual 2-bit flip-flop cell
VDFF4 Virtual 4-bit flip-flop cell

JP 2008-204171 A

Claims (8)

Circuit design means for performing circuit design based on circuit specifications to generate circuit information;
Circuit related information storage means for storing circuit related information including cell information of the semiconductor integrated circuit;
Logic circuit information generating means for performing logic synthesis on the circuit information using the circuit-related information and generating logic circuit information including cell arrangement and wiring arrangement wiring information for the cell;
Based on the placement and routing information of the logic circuit information, the placement and routing of the cells is performed, and the circuit related information is referred to based on the placement and routing results, and the small bit cell of the logic circuit information Multi-bit arrangement and wiring means for multi-biting into a multi-bit cell;
A semiconductor integrated circuit design support apparatus comprising: The multi-bit arrangement and routing means is:
2. The semiconductor integrated circuit design support device according to claim 1, wherein the connection to the multi-bit cell is changed based on the placement and routing information of the multi-bit cell, and the number of stages of the multi-bit cell is determined after the placement is determined. . The multi-bit arrangement and routing means is:
3. The semiconductor integrated circuit design support apparatus according to claim 1, wherein the number of bits of the cell is increased based on the number of wirings of the cell. The logic circuit information generating means includes
Generating virtual circuit logic circuit information based on the circuit information;
The multi-bit arrangement and routing means is:
4. The semiconductor integrated circuit design support apparatus according to claim 1, wherein the virtual cell is multi-bited. The multi-bit arrangement and routing means is:
Search means for searching for the presence / absence of cells and the number of wires in a predetermined peripheral range for each cell from the placement and routing information,
5. The semiconductor integrated circuit design according to claim 1, wherein multi-bit conversion is performed by determining whether or not multi-bit conversion of the cell is appropriate based on a search result of the search means. Support device. The semiconductor integrated circuit design support device includes:
6. The semiconductor integrated circuit design support apparatus according to claim 1, wherein the cell is a flip-flop. A circuit design processing step for generating circuit information by performing circuit design based on the circuit specifications;
Logic circuit including circuit arrangement information and arrangement information of wiring for cells by performing logic synthesis on the circuit information using circuit related information including cell information of semiconductor integrated circuit stored in circuit related information storage means A logic circuit information generation processing step for generating information;
Based on the placement and routing information of the logic circuit information, the placement and routing of the cells is performed, and the circuit related information is referred to based on the placement and routing results, and the small bit cell of the logic circuit information A multi-bit placement and routing process step for multi-biting a multi-bit cell,
A method for supporting the design of a semiconductor integrated circuit, comprising: On the computer,
Circuit design processing for generating circuit information by performing circuit design based on circuit specifications;
Logic circuit including circuit arrangement information and arrangement information of wiring for cells by performing logic synthesis on the circuit information using circuit related information including cell information of semiconductor integrated circuit stored in circuit related information storage means Logic circuit information generation processing for generating information;
Based on the placement and routing information of the logic circuit information, the placement and routing of the cells is performed, and the circuit related information is referred to based on the placement and routing results, and the small bit cell of the logic circuit information Multi-bit arrangement and wiring processing that multi-bits into multi-bit cells,
A program characterized by having executed.

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