JP2016212524A - Memory controller and method for controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a command two cycle mode cannot continuously transmit a two cycle command since two clocks are required to transmit one command as a countermeasure to a CA parity error due to a pattern sensitive bit error when a memory controller transmits a command to a DRAM, and accordingly, DRAM access performance may be reduced when the command two cycle mode is always used.SOLUTION: A method for controlling a memory controller comprises: transmitting a command including an address, a parity bit and a chip select to a memory; holding the transmitted command; holding an error pattern when transmitting the command; and controlling the transmission cycle number of a next command to be transmitted so as to be changed when a transmission pattern consisting of at least a part of the next command to be transmitted and at least a part of a command transmitted and held before the command fits into the error pattern.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a memory controller, and more particularly to a memory controller that retransmits a command when the memory cannot receive the command correctly.

  When the DRAM receives a chip selection signal (hereinafter also referred to as “CS”) from the memory controller, the DRAM decodes the received command signal and address signal in the same clock cycle. Then, the DRAM interprets the type of the decoded command and executes operations such as a memory cell that holds data to be processed and a mode register that stores the operation mode of the DRAM.

  In recent years, DDR4 SDRAM has appeared as a DRAM standard. Transmission / reception of commands of the DDR4 SDRAM is performed in synchronization with a clock of 800 MHz to 1.6 GHz. DDR4 SDRAM is faster than conventional DRAM. Therefore, the DDR4 SDRAM (hereinafter also referred to simply as “DRAM” or “memory device”) verifies whether the address including RAS, CAS, and WE, the bank group, the bank address, and the activation command signal are correctly received. A function called CA (Command Address) parity is supported. The memory controller transmits a parity bit to the DRAM simultaneously with transmitting CS. The DRAM verifies the parity bit for the received command address. When the DRAM detects a CA parity error (hereinafter also simply referred to as “parity error” or “error”), the DRAM notifies the memory controller that an error has occurred. (See Non-Patent Document 1)

  The number of cycles before the CA parity error occurs is not known whether the command has been executed, and the number of cycles after the CA parity error has not been executed. When a CA parity error occurs, the memory controller needs to re-send to the DRAM commands that may have been sent from the memory controller to the DRAM in several cycles before and after the CA parity error occurred, but may not have been executed on the DRAM.

  In order to realize command retransmission, for example, a command holding circuit (same as “retransmission buffer”) for storing a command issued to the DRAM for a certain period of time may be provided in the memory controller. The command holding circuit (retransmission buffer) stores not only commands but also addresses and parity bits.

  When a CA parity error occurs and a command in the command holding circuit (retransmission buffer) is retransmitted, normal command issuance is waited, and the response time of memory access becomes longer.

  When a command is retransmitted, the use efficiency of the memory access data bus is reduced, and the response time of the memory access is increased. In order not to deteriorate the access performance of the DRAM, it is necessary for the memory controller to control the CA parity error as much as possible.

  One of the causes of CA parity errors is signal degradation on the transmission line between the memory controller and the DRAM. It is known that the signal decay increases when the logic level changes after the same logic level continues. When signal degradation occurs, the transmitted signal is different from the signal that was supposed to be transmitted. An error in signal transmission caused by such a cause is called a pattern sensitivity bit error.

  As a technique for preventing a pattern sensitivity bit error, there is a technique for correcting a signal decrease after a logic level changes. In this technique, the signal level after the logic level is changed is higher than the signal level when the logic level continues (see Patent Document 1). This technique is called pre-emphasis, and when this technique is adopted, a dedicated output buffer circuit is required.

On the other hand, there is a technique called command two-cycle issuance that relaxes the timing constraints of memory controller command issuance. (See Patent Document 2)
FIG. 1 is a diagram for explaining a command two-cycle issue technique. Hereinafter, the command transmission method at timing T1 is referred to as a normal mode, and the command transmission method for transmitting commands, addresses, and parity bits from timing T5 to T6 for a period of 2 cycles is referred to as a command 2 cycle mode.

  In command 2-cycle mode, signals other than CS are sent continuously in the first and second cycles, and CS is sent in the second cycle when the signal level other than CS is stable, so stable command issuance is possible. It is. For this reason, the command two-cycle issue technique is also effective as a technique for preventing pattern sensitivity bit errors.

JP2011-239467A JP-A-2005-346502

JEDEC STANDARD DDR4 SDRAM JESD79-4A specification standard

  However, since the command 2-cycle mode requires two clocks to transmit one command, it cannot issue a command for two consecutive cycles. For example, the “active” command of another DRAM block cannot be issued in the next cycle of the “read” command of one DRAM block. Further, if the command is sent in the command 2 cycle mode, the command issuance is delayed by one cycle. Therefore, if the command 2 cycle mode is always used so that a pattern sensitivity bit error does not occur, the DRAM access performance may be lowered.

  The present invention has been made in view of the above problems. That is, an object of the present invention is to provide a memory controller that reduces the occurrence of pattern sensitivity bit errors, which is one of the causes of CA parity errors, while suppressing a decrease in DRAM access performance. Moreover, it aims at providing the method.

  The memory controller according to the present invention has the following configuration. That is, a transmitting unit that transmits a command including an address, a parity bit, and a chip select to a memory, a first holding unit that holds a command transmitted by the transmitting unit, and a second holding that holds an error pattern in the transmission of the command And a transmission pattern comprising: at least a part of a command to be transmitted next by the transmission unit; and at least a part of the command transmitted by the transmission unit and held in the first holding unit before the command. Control means for controlling the transmission means so as to change the number of transmission cycles of the next command to be transmitted when the error pattern held in the second holding means applies.

  According to the present invention, it is possible to reduce the occurrence of an error pattern of pattern sensitivity bit errors.

Waveform diagram of command 2 cycle mode, which is the conventional technology Schematic configuration example of the memory controller in the first embodiment Timing waveform diagram according to the first embodiment The figure explaining the error pattern holding | maintenance in 2nd Embodiment Timing waveform diagram in error pattern A in the second embodiment Timing waveform diagram in error pattern B in the second embodiment Schematic configuration example of a memory controller in the third embodiment The figure explaining operation | movement of the memory controller in 3rd Embodiment. Schematic configuration example of a memory controller in the fourth embodiment The figure explaining operation | movement of the memory controller in 4th Embodiment. Schematic configuration example of a memory controller in the fifth embodiment The figure explaining operation | movement of the memory controller in 5th Embodiment.

[First Embodiment]
FIG. 2 is a schematic configuration example of the memory controller 100 according to the first embodiment. The memory controller 100 is connected to a DRAM 900 (DDR4 SDRAM). The memory controller 100 transmits a DRAM command including CS (chip selection signal called chip select), command, address, and parity bit to the DRAM 900. The DRAM command includes RAS #, CAS #, and WE. Hereinafter, “transmission” and “issue” are used interchangeably.

  The parity bit of CA (Command Address) parity will be described. There are a signal line indicating a command and a signal line indicating an address, and the memory controller generates a parity bit depending on whether the number of bits that are High is odd or even. Then, the parity bit is added to the command and address and sent. The parity bit is used as a check bit on the DRAM 900 side.

  The DRAM 900 generates a parity bit from the number of High bits of the received command signal and address signal. Then, a parity check is performed to compare with the parity bit sent from the memory controller. If the comparison results are different, it is a CA parity error. When detecting the CA parity error, the DRAM 900 notifies the memory controller 100 of the occurrence of the CA parity error after a predetermined time.

  When the memory controller 100 receives the memory access request, the memory controller 100 converts the received memory access request into a DRAM command and stores it in the command queue 300.

  The command Queue 300 also stores DRAM commands other than DRAM memory refresh requests and memory access requests for executing calibration.

  The command issuing circuit 201 receives a DRAM command from the command queue 300, controls the transmission timing of the DRAM command, and transmits it to the DRAM 900. The DRAM command transmission interval is determined by the DRAM specification. For example, the “active command and read command have a time interval defined by a parameter tRCD”.

  The DRAM command holding circuit 203 holds the DRAM command transmitted to the DRAM 900 for a predetermined time. When a CA parity error occurs, the DRAM command is retransmitted and retained. After a certain time has elapsed, the DRAM command is discarded. The DRAM command holding circuit 203 only needs to have a capacity capable of holding DRAM commands for an execution time during which the DRAM 900 executes a parity check using a parity bit. The DRAM command holding circuit 203 holds the signal level transmitted to the DRAM as it is even while the command issuing circuit 201 does not send the DRAM command.

  When the occurrence of a CA parity error is notified from the DRAM 900, the error pattern holding circuit 204 refers to the DRAM command stored in the DRAM command holding circuit 203. The error pattern holding circuit 204 holds the DRAM command in which the CA parity error has occurred as an error pattern. In the following embodiments, this error pattern is a pattern sensitivity bit error pattern.

  The command 2 cycle mode request circuit 400 receives an error pattern from the error pattern holding circuit 204. In addition, a DRAM command issue status is received from the DRAM command holding circuit 203. Then, when the information of the next issued DRAM command is received from the command issuing circuit 201 and the next issued DRAM command is transmitted in the normal mode, the command issuing circuit 201 receives the command 2 when it matches the error pattern. Notify the cycle mode request. That is, when the transmission pattern composed of the signal level of the next DRAM command to be issued and the signal level of the immediately preceding DRAM command matches the error pattern held in the error pattern holding circuit 204, the command issuance is performed. The command 201 is notified of the command 2 cycle mode request.

  When the command issuing circuit 201 does not receive the command 2 cycle mode request from the command 2 cycle mode request circuit 400, the command issuing circuit 201 issues a DRAM command in the normal mode. When a command 2 cycle mode request is received, the number of transmission cycles other than chip select is changed, and a DRAM command is issued in the command 2 cycle mode. In this way, the command 2 cycle mode request circuit 400 controls the command issue circuit 201.

  FIG. 3 is an example of operation waveforms of the memory controller 100 in the first embodiment. CS and error are LOW active signals. The memory controller 100 sets the command, address, and parity bit to 0 in a cycle in which no DRAM command is transmitted. Here, if the memory controller 100 does not receive a CA parity error within three cycles after the DRAM 900 receives the DRAM command, it is assumed that the DRAM command has been correctly received by the DRAM.

  Since the DRAM 900 receives the command A at the timing T1 and the memory controller 100 has not received the CA parity error by the timing T4, it indicates that no CA parity error has occurred in the reception of the command A by the DRAM. .

  Since the DRAM receives the command B at timing T4 and the memory controller receives a CA parity error at timing T7, the memory controller 100 detects that a CA parity error has occurred when receiving the command B in the DRAM 900. To do.

  Along with the detection of the CA parity error, the memory controller 100 generates an error pattern. In the case of this operation waveform, since the command, address, and parity bit are 0 for the two-cycle period at timings T2 and T3 before issuing command B, the error pattern “issue of command B after 2 consecutive cycles of 0” Is generated. Thus, the error pattern is “issue of command X after the same signal continues for N cycles or more”. This error pattern is held in the error pattern holding circuit 204.

  The DRAM 900 receives the command C at timing T9. Since the command C command issuance does not match the error pattern held in the error pattern holding circuit 204, the DRAM command is issued in the normal mode.

  At the timing T9 cycle, the DRAM command to be issued next is transferred to the command issuing circuit 201, and the command 2-cycle mode request circuit 400 recognizes that the command to be issued next is the command B. Next, the DRAM command holding circuit 203 stores the fact that 0 is continued in the command, address, and parity bit during the two-cycle period of timing T10 and T11. Depending on the specifications of the DRAM, the DRAM command issuance interval needs to be 3 cycles or more.

  The command 2-cycle mode request circuit 400 receives from the DRAM command holding circuit 203 that the command, address, and parity bit are 0 for two cycles at timings T10 and T11. Since the command 2 cycle mode request circuit 400 has already recognized that the next command is the command B, the error pattern held in the error pattern holding circuit 204 and the transmission pattern including the DRAM command to be sent next are sent. Find a match. The command 2 cycle mode request circuit 400 notifies the command 2 cycle mode request at timing T12.

  The memory controller 100 issues a command B other than the chip select in the command 2-cycle mode at the timing T12 and T13 cycles. The chip select is issued at timing T13 in the second cycle.

  As described above, in the present embodiment, when a CA parity error is received from the DRAM 900, the DRAM command over a plurality of cycles is held in the error pattern holding circuit 204 as an error pattern. When a similar transmission pattern occurs, the command 2 cycle mode request circuit 400 of the memory controller 100 issues a DRAM command in the command 2 cycle mode to suppress the occurrence of a CA parity error. The command 2-cycle mode request circuit 400 may issue a DRAM command continuously for two cycles or more. In that case, the chip select is issued after the second cycle. In other words, the command two-cycle mode request circuit 400 can be rephrased as issuing a DRAM command other than chip select continuously for at least two cycles from at least one cycle before chip select.

  In the present embodiment, the memory controller that generates an error pattern and holds it in the error pattern holding circuit 204 when a CA parity error is received from the DRAM 900 has been described. In the error pattern holding circuit 204, an error pattern may be directly written and held in advance by register access or the like.

[Second Embodiment]
In the second embodiment, a memory controller that generates an error pattern focusing on the state of each bit that is a part of a command, an address, and a parity bit will be described.

  Since the circuit configuration example in the present embodiment is the same as that in the first embodiment, description thereof is omitted. The difference from the first embodiment is an error pattern held in the error pattern holding circuit 204.

  FIG. 4 is a diagram for explaining error pattern generation in the second embodiment. The memory controller 100 issues a command A at timing T5, a command B at timing T8, and a command C at timing T11. In this embodiment, the memory controller 100 keeps the command, address, and parity bit at the values when the previous DRAM command is issued until the next DRAM command is issued, and does not return to the 0 level.

  At timing T12, the memory controller 100 receives a CA parity error from the DRAM 900, and detects that a CA parity error has occurred in the command C at timing T11. The command B issued at the timing T8 is normally received by the DRAM 900 because the CA parity error is not notified by the timing T11 after the elapse of 3 cycles.

  In order to simplify the description, it is assumed that the command, address, and parity bits are composed of 6 bits from bit 0 to bit 5 in this operation waveform. For example, command 3 bits, address 2 bits, parity bit 1 bit.

  In the case of this operation waveform, the signal level of bit 1 and bit 3 does not change from the issue of command A to the issue of command C. Bit 0, bit 2, and bit 4 invert the signal level in order to issue command C, and the signal level before being inverted is continuous for three cycles from timing T8 to timing T10. Bit 5 also inverts the signal to issue command C, and the signal level before inversion is continuous for 6 cycles from timing T4 to timing T10.

The cause of the pattern sensitivity bit error is signal decrease when the logic level changes after the same logic level continues. The error pattern in the second embodiment is an error pattern holding circuit 204 as in the following two examples. Hold on.
-Error pattern A Change in signal level after bit 5 is 6 cycles or more and signal level is continuous-Error pattern B Change in signal level after 6 cycles or more and signal level is continuous Note that "3 or more cycles, signal level "Change in signal level after continuation" is not included in the error pattern example because no CA parity error has occurred in the reception of the command B by the DRAM 900.

  FIG. 5 is an example of operation waveforms of the memory controller 100 to which the error pattern A in the second embodiment is applied. When issuing the command C at the timing T11, the memory controller 100 detects that the bit 5 is 0 for 6 consecutive cycles in the previous cycle, and issues the command C in the command 2 cycle mode. Note that the commands A and B are not issued in the command 2-cycle mode because the commands are changed simultaneously with CS. Since CS is issued in the next cycle after changing command C, command C is issued in the command 2 cycle mode.

  The command 2-cycle mode request circuit 400 receives information from the command issuing circuit 201, the error pattern holding circuit 204, and the DRAM command holding circuit 203. As a result, the command 2 cycle mode request circuit 400 matches the error pattern held in the error pattern holding circuit 204 with the transmission pattern including the next DRAM command, so that the CA parity error caused by the pattern sensitivity bit error occurs. It is judged that it is likely to cause. And that error is prevented. Specifically, it is possible to prevent a CA parity error from occurring on the DRAM 900 side when the memory controller 100 issues a command C at timing T11.

  On the other hand, when the command D is issued at the timing T14, in the bit 3, the 9-cycle signal level is inverted after continuous, but if it does not match the error pattern held in the error pattern holding circuit 204, the command 2 cycle mode The request circuit 400 determines. Therefore, the command 2 cycle mode request circuit 400 does not request the command 2 cycle mode, and the command issuing circuit 201 issues a DRAM command in the normal mode.

  FIG. 6 is an operation waveform example of the memory controller 100 to which the error pattern B in the second embodiment is applied. When issuing the command C at the timing T11, the memory controller 100 detects that the bit 5 is 0 for 6 consecutive cycles, and issues the command C in the command 2 cycle mode. Further, when issuing the command D at the timing T14, the memory controller 100 detects that the bit 3 is 1 continuously for 6 cycles or more and issues the command D in the command 2 cycle mode. As a result, it is possible to prevent a CA parity error from occurring on the DRAM 900 side when the memory controller 100 issues the command C.

  In the present embodiment, it has been described that the memory controller 100 generates an error pattern by paying attention to the continuation of the signal level of each bit. In addition to the continuation of the same signal level, the signal level itself may be included in the error pattern condition. Referring to the operation waveform example of FIG. 4, the error pattern A is “bit 5 changes to“ 1 ”after“ 0 ”continues for 6 cycles or more”, and the error pattern B is “6 cycles or more,“ 0 ”. "Change to" 1 "after" "continues."

  As described above, in this embodiment, when the memory controller 100 receives a CA parity error from the DRAM 900, the error pattern is held in the error pattern holding circuit 204 from the state of each bit of the issued DRAM command. When a similar pattern occurs, the command 2 cycle mode request circuit of the memory controller 100 issues a DRAM command in the command 2 cycle mode to suppress the occurrence of a CA parity error.

  In this embodiment, the memory controller 100 that generates an error pattern and stores the error pattern in the error pattern holding circuit 204 when a CA parity error is received from the DRAM 900 has been described. The error pattern may be directly written and held in advance in the error pattern holding circuit 204 by register access or the like.

[Third Embodiment]
FIG. 7 is a schematic configuration example of the memory controller 100 according to the third embodiment. The memory controller 100 is connected to a DRAM 900 (DDR4 SDRAM), and transmits a DRAM command including CS, a command, an address, and a parity bit to the DRAM 900. Similar to the first embodiment, the DRAM 900 performs a parity check of the DRAM command, and when a CA parity error is detected, notifies the memory controller 100 of the occurrence of the CA parity error after a predetermined time.

  When the memory controller 100 receives the memory access request, the memory controller 100 converts the received memory access request into a DRAM command and stores it in the command queue 300.

  The command Queue 300 also stores DRAM commands other than DRAM memory refresh requests and memory access requests for executing calibration.

  The command issuing circuit 201 receives a DRAM command from the command Queue 300, controls the transmission timing of the DRAM command, and transmits the DRAM command to the selection circuit 601.

  When receiving the DRAM command from the command issuing circuit 201, the selection circuit 601 transmits the received DRAM command to the DRAM 900, and when not receiving the DRAM command from the command issuing circuit 201, the selection pattern 601 receives the toggle pattern Is transmitted to the DRAM 900.

  The DRAM command holding circuit 203 holds the DRAM command transmitted to the DRAM 900 for a predetermined time. When a CA parity error occurs, the DRAM command is retransmitted and retained. After a certain time has elapsed, the DRAM command is discarded. The DRAM command holding circuit 203 only needs to have a capacity capable of holding DRAM commands for an execution time during which the DRAM 900 executes a parity check using a parity bit. The DRAM command holding circuit 203 holds the signal level transmitted to the DRAM as it is even while the command issuing circuit 201 does not send the DRAM command.

  When the occurrence of a CA parity error is notified from the DRAM 900, the error pattern holding circuit 204 refers to the DRAM command stored in the DRAM command holding circuit 203. Then, the error pattern holding circuit 204 generates and holds an error pattern from the issued pattern including the DRAM command in which the CA parity error has occurred. This error pattern is a pattern sensitivity bit error pattern.

  The toggle generation circuit 600 receives the error pattern from the error pattern holding circuit 204, and generates a toggle pattern that toggles the command, address, and parity bit so that the next issued DRAM command does not match the error pattern.

  FIG. 8 is an example of operation waveforms of the memory controller in the third embodiment. Since the DRAM receives the command A at the timing T0 and the memory controller does not receive the CA parity error by the timing T4, the CA parity error does not occur when the command A is received by the DRAM. Since the DRAM receives the command B at timing T5 and the memory controller receives a CA parity error at timing T8, the memory controller detects that a CA parity error has occurred when receiving the command B in the DRAM.

  With the detection of the CA parity error, the memory controller generates an error pattern. In the case of this operation waveform, since the command, address, and parity bit are 0 during the 4-cycle period of timing T1, T2, T3, and T4 before command B, an error pattern of “continuation of signal level of 4 cycles or more” is generated. Is done.

  After timing T8, the toggle generation circuit 600 generates a toggle signal that toggles the command and address signals every two cycles. In this embodiment, the generation of toggle signals in which the command, address, and parity bits are all 0 bits and all 1 bits at intervals of two cycles continues, but it is only necessary to control so that the signal level of each bit is not continuous. There is no need to change to the same signal level at the timing.

  If the signal is toggled every two cycles, the continuation of the same signal level is a maximum of three cycles. Prevents signal levels from continuing for more than 4 cycles. The same signal level continues for a maximum of three cycles because the output of the same signal level in the two consecutive cycles of the toggle generation circuit 600 and the command output at the same signal level as the toggle generation circuit 600 of the command issuing circuit 201 are continuous. Occurs when

  The selection circuit 601 selects the DRAM command generated by the command issuance circuit 201 when the DRAM command is input from the command issuance circuit 201, and selects the DRAM command generated by the toggle generation circuit 600 otherwise. .

  In FIG. 8, the memory controller 100 issues a command C at timing T13. In a period other than the timing T13, the memory controller 100 transmits the command generated by the toggle generation circuit 600.

  As described above, in this embodiment, when a CA parity error is received from the DRAM 900, the number of cycles in which the signal level continues before the error is held as an error pattern. Then, the command signal is toggled by the toggle generation circuit so that a similar pattern does not occur, thereby suppressing the recurrence of the CA parity error.

  In this embodiment, when a CA parity error is received from the DRAM, an error pattern is generated and the error pattern holding circuit 204 has been described with respect to the holding memory controller. The error pattern may be directly written and held in advance in the error pattern holding circuit 204 by register access or the like.

  In the present embodiment, the embodiment has been described in which the error pattern is held and the toggle cycle of the command, address, and parity bit is made as long as possible under the condition that the CA parity error does not occur. As a simpler implementation method, for example, if a toggle generation circuit that toggles commands, addresses, and parity bits in a short cycle such as one cycle is configured, the recurrence of CA parity errors can be suppressed without using an error pattern holding circuit. Is possible.

[Fourth Embodiment]
FIG. 9 is a schematic configuration example of the memory controller 100 according to the fourth embodiment. The difference from the circuit configuration example of the third embodiment is that the toggle generation circuit 600 confirms the issued DRAM command using the DRAM command holding circuit 203. A toggle signal is generated only when a DRAM command is stored in the command queue 300 or the command issuing circuit 201 and an error pattern occurs.

  FIG. 10 is an example of operation waveforms of the memory controller in the fourth embodiment.

  Since the DRAM receives the command A at the timing T0 and the memory controller does not receive the CA parity error by the timing T4, the CA parity error does not occur when the command A is received by the DRAM.

  Since the DRAM receives the command B at timing T5 and the memory controller receives a CA parity error at timing T8, the memory controller detects that a CA parity error has occurred when receiving the command B in the DRAM.

  With the detection of the CA parity error, the memory controller generates an error pattern.

  In the case of this operation waveform, since the command, address, and parity bit are 0 during the 4-cycle period of timing T1, T2, T3, and T4 before command B, an error pattern of “continuation of signal level of 4 cycles or more” is generated. Is done.

  The memory controller receives the memory access request at timing T11, and the DRAM command is stored in the command queue 300. The toggle generation circuit 600 inputs the issued DRAM command information from the DRAM command holding circuit 203, confirms that the issued DRAM command is 0 in the four cycles from timing T8 to T11, and sends it to the error pattern holding circuit 204. Detects a match with the stored error pattern.

  The toggle generation circuit 600 starts toggling the command, address, and parity bit at timing T11. The command issuing circuit 201 receives a DRAM command from the command queue 300 at timing T12. Since the command C is issued at the timing T13 and the command queue 300 and the command issuing circuit 201 become empty, the command, address, and parity bit are not toggled at the timing T13. Unlike the third embodiment, the signal level 1 is continuously output from the toggle generation circuit 600 after the timing T13.

  As described above, in the present embodiment, when a CA parity error is received from the DRAM, the number of cycles in which the signal level continues before the error is held in the error pattern holding circuit 204 as an error pattern. Then, the command signal is toggled by the toggle generation circuit 600 so that the same error pattern does not occur only during the period from the issue of the next DRAM command to the completion of the issue of the DRAM command. As a result, while the occurrence of the CA parity error is suppressed, the signal toggle during the period when there is no memory access to the DRAM 900 is suppressed.

  In this embodiment, the memory controller that generates an error pattern and stores it in the error pattern holding circuit 204 when a CA parity error is received from the DRAM has been described. The error pattern may be directly written and held in advance in the error pattern holding circuit 204 by register access or the like.

  Further, as in the third embodiment, for example, if a toggle generation circuit that toggles commands, addresses, and parity bits at a short cycle such as one cycle is configured, a CA parity error can be detected without using an error pattern holding circuit. It is possible to suppress recurrence.

[Fifth Embodiment]
FIG. 11 is a schematic configuration example of the memory controller 100 according to the fifth embodiment. The difference from the first embodiment is that a training circuit 500 is added.

  In the present embodiment, the training circuit 500 generates a training pattern. In order to know how long a signal level continues to issue a DRAM command and a CA parity error is likely to occur, a training pattern is generated in which the command issue interval is sequentially increased. The training pattern is composed of DRAM commands. When receiving a DRAM command from the command issuing circuit 201, the selection circuit 602 transmits the received DRAM command to the DRAM 900 (DDR4 SDRAM). When receiving a DRAM command from the training circuit 500, the selection circuit 602 transmits the received DRAM command to the DRAM 900. To do.

  FIG. 12 is a diagram for explaining operation waveforms generated by the training circuit in the present embodiment. The memory controller 100 sets the command, address, and parity bit to 0 in a cycle in which no DRAM command is transmitted.

  The memory controller 100 issues a DRAM command at timings T2, T4, T7, T11, and T16 while sequentially increasing the number of cycles of the command issue interval, and sets the command, address, and parity bit to 1 at that time.

  When receiving a CA parity error notification from the DRAM at timing T14, the error pattern holding circuit 204 recognizes that a CA parity error has occurred by issuing a DRAM command at timing T11. Since the DRAM command at the timing T11 is changed after the command, address, and parity bit have been continued for 3 cycles, an error pattern “issue command after signal level is continuous for 3 cycles or more” is an error pattern holding circuit. 204.

  The training pattern issuance operation by the training circuit 500 is performed before the memory controller starts issuing a DRAM command for a memory access request.

  As described above, in this embodiment, the training pattern issuance operation is performed before the memory access is started, thereby suppressing the occurrence of a CA parity error when the DRAM command is issued due to the memory access request.

  In this embodiment, the configuration example in which the training circuit is added to the configuration example of the memory controller in the first embodiment has been described. However, the training circuit is added to the configuration example of the memory controller in the second to fourth embodiments. Thus, the same effect as in the present embodiment can be obtained.

  The operation waveform generated by the training circuit in the present embodiment is an example, and may be a training waveform in which the command, address, and parity bit are changed by one bit. Further, when adding a training circuit to the memory controller of the second to fourth embodiments, it is preferable to generate a training pattern so as to efficiently acquire an error pattern used in each embodiment.

DESCRIPTION OF SYMBOLS 100 Memory controller 201 Command issuing circuit 203 DRAM command holding circuit 204 Error pattern holding circuit 300 Command Queue
400 Command 2-cycle mode request circuit 900 DRAM

Claims (18)

A transmission means for transmitting a command including an address, a parity bit, and a chip select to the memory;
First holding means for holding a command transmitted by the transmitting means;
Second holding means for holding an error pattern in transmission of the command;
A transmission pattern comprising at least a part of a command to be transmitted next by the transmission unit and at least a part of a command transmitted by the transmission unit and held in the first holding unit before the command is 2. A memory controller comprising: control means for controlling the transmission means so as to change the number of transmission cycles of the next command to be transmitted when the error pattern held in the holding means applies. The control means transmits the command to be transmitted next to other than the chip select continuously for two cycles or more, and transmits the chip select to the transmission means to transmit the chip select after the second cycle of the command to be transmitted next. Request,
The memory controller according to claim 1, wherein the transmission unit transmits the command to the memory as requested by the control unit. The control means requests the transmitting means to continuously transmit at least one cycle before the chip select from the next command to be transmitted continuously for at least two cycles.
The memory controller according to claim 1, wherein the transmission unit transmits the command to the memory as requested by the control unit.   4. The memory controller according to claim 1, wherein the control means is a request circuit that requests transmission of a command in two cycles.   5. The memory controller according to claim 1, wherein the first holding unit holds the command for a predetermined time and discards the command after the predetermined time elapses.   When the first holding unit is notified from the memory that an error has occurred in receiving the command transmitted by the transmitting unit in the memory, the first holding unit stores the command held in the first holding unit in the memory. The memory controller according to any one of claims 1 to 5, wherein the memory controller is retransmitted at a later time.   7. The first holding unit has a capacity capable of holding a command transmitted by the transmission unit for a time during which the memory performs a parity check using the parity bit. 2. The memory controller according to item 1.   When the second holding unit is notified from the memory that an error has occurred in receiving the command transmitted by the transmitting unit, the transmitting unit transmits the command and the command before the command. 8. The memory controller according to claim 1, wherein a transmission pattern included in a command held in the first holding unit is held as the error pattern.   The memory controller according to claim 1, wherein the error pattern held in the second holding unit is a pattern sensitivity bit error.   2. The error pattern held in the second holding means is a pattern showing a change in a signal after the same signal continues for N cycles or more for any bit included in the command. 10. The memory controller according to any one of 1 to 9.   The memory controller according to claim 1, wherein an error pattern is held in advance in the second holding unit.   The memory controller according to claim 1, wherein the memory controller is connected to the memory.   The memory controller according to claim 1, wherein the memory is a DRAM.   A training circuit for generating the error pattern, wherein the training circuit generates a pattern indicating a change in the signal after the same signal continues for N cycles or more as a training pattern, and the second holding unit includes: The memory controller according to any one of claims 1 to 13, wherein when the memory notifies that an error has occurred in reception, the training pattern generated by the training circuit is held as an error pattern. . Issuing means for issuing a command including an address, a parity bit, and a chip select;
A pattern holding means for holding, as an error pattern, a pattern indicating a change in signal after the same signal continues for N cycles or more with respect to an issuance pattern of a signal of any bit included in the command;
(N-2) generating means for generating a toggle pattern that changes every cycle;
During the period when the command and the toggle pattern are received and the issuing means does not issue the command, the toggle pattern generated by the generating means is selected and transmitted to the memory, and the issuing means issues the command. And a selection means for selecting the command and transmitting it to the memory during the period. Command holding means for holding the command transmitted to the memory;
The generating means generates a signal having the same pattern of any bit signal included in the command issued by the issuing means and held in the command holding means before the next command issued by the issuing means for N cycles or more. If it is continuous, a toggle pattern is generated in the cycle before the next command to be issued,
The memory controller according to claim 15, wherein the selection unit selects a toggle pattern generated by the generation unit between the same continuous signal for N cycles or more and the next command to be issued.   The method of controlling a memory controller according to claim 1.   The method for controlling a memory controller according to claim 15.

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