JP2016208460A - Booster circuit and solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a booster circuit capable of improving stability of a step-up voltage.SOLUTION: The present invention comprises: a charge pump circuit PM1 performing a step-up operation; a capacitance C1 for holding a divided voltage VB1 obtained by dividing a step-up voltage BS1 output from the charge pump circuit PM1; and a comparator A1 operating the charge pump circuit PM1 on the basis of a comparison result between the divided voltage VB1 held in the capacitance C1 and a reference voltage VA1.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a booster circuit and a solid-state imaging device.

  In a booster circuit, a boosted voltage is dropped through a resistor, and the dropped voltage is compared with a reference voltage. When the drop voltage becomes lower than the reference voltage, the boosted voltage is kept constant by operating the charge pump circuit.

JP 2007-151100 A

  An object of one embodiment of the present invention is to provide a booster circuit and a solid-state imaging device capable of improving the stability of a boosted voltage.

  According to one embodiment of the present invention, a charge pump circuit, a capacitor, and a comparator are provided. The charge pump circuit performs a boosting operation. The capacitor holds the divided voltage obtained by dividing the boosted voltage output from the charge pump circuit. The comparator operates the charge pump circuit based on a comparison result between the divided voltage held in the capacitor and a reference voltage.

FIG. 1 is a block diagram illustrating a configuration example of the booster circuit according to the first embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the second embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG. FIG. 4 is a circuit diagram showing a schematic configuration example of the column ADC circuit of FIG. FIG. 5 is a timing chart showing voltage waveforms of the respective units during the pixel readout operation of the solid-state imaging device of FIG. FIG. 6 is a block diagram illustrating a configuration example of the booster circuit according to the third embodiment. FIG. 7 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the fourth embodiment is applied.

  Hereinafter, a booster circuit and a solid-state imaging device according to embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of the booster circuit according to the first embodiment.
In FIG. 1, the booster circuit includes a reference voltage generation circuit VF1, a comparator A1, a charge pump circuit PM1, a capacitor C1, and a sampling circuit SE1. The sampling circuit SE1 is provided with a variable resistor R1, a resistor R2, and switches W1 to W3. The reference voltage generation circuit VF1 is connected to the non-inverting input terminal of the comparator A1. A capacitor C1 is connected between the output terminal of the charge pump circuit PM1 and the inverting input terminal of the comparator A1. A parasitic capacitance C2 is added to the inverting input terminal of the comparator A1. An external capacitor C3 may be added to the output terminal of the charge pump circuit PM1 in order to stabilize the boosted voltage BS1 of the charge pump circuit PM1. The output DET of the comparator A1 is input to the control terminal of the charge pump circuit PM1, and the clock CLK is input to the clock terminal of the charge pump circuit PM1. The variable resistor R1 and the resistor R2 are connected in series with each other. One end of the resistor series circuit is connected to one end of the capacitor C1 through the switch W1, and the other end of the resistor series circuit is connected to the other end of the capacitor C1 through the switch W3. The other end of the resistor series circuit is grounded via the switch W2. The switches W1 to W3 are turned on / off according to the switching signal SP.

In the sampling period, the switches W1 to W3 are turned on. At this time, the output terminal of the charge pump circuit PM1 is grounded through a resistor series circuit of the variable resistor R1 and the resistor R2, and this resistor series circuit is connected in parallel to the capacitor C1. The boosted voltage BS1 output from the charge pump circuit PM1 is divided by a resistor series circuit including a variable resistor R1 and a resistor R2, and the divided voltage VB1 at that time is held in the capacitor C1.
In the hold period, the switches W1 to W3 are turned off. At this time, the resistor series circuit of the variable resistor R1 and the resistor R2 is disconnected from the capacitor C1. The boosted voltage BS1 output from the charge pump circuit PM1 is divided by the capacitor C1, and the divided voltage VB1 at that time is input to the comparator A1. The reference voltage VA1 generated by the reference voltage generation circuit VF1 is input to the comparator A1. The reference voltage VA1 can be set to about 1V, for example. The boost voltage BS1 can be set to, for example, 3.8 V or higher. When the divided voltage VB1 falls below the reference voltage VA1, the output DET of the comparator A1 rises. At this time, when the clock CLK is supplied to the charge pump circuit PM1, the charge pump circuit PM1 is driven, and the boosting operation of the boosted voltage BS1 is performed. As a result of the boost operation of the boost voltage BS1, when the divided voltage VB1 exceeds the reference voltage VA1, the output DET of the comparator A1 falls and the drive of the charge pump circuit PM1 is stopped.
Here, in the hold period, it is possible to prevent current from flowing from the output terminal of the charge pump circuit PM1 to the resistor series circuit of the variable resistor R1 and the resistor R2. Therefore, it is possible to prevent the boosted voltage BS1 from being lowered due to the feedback of the boosted voltage BS1, and to improve the boosting efficiency.
In the hold period, the variable resistor R1 and the resistor R2 can be removed from the feedback system of the boosted voltage BS1. For this reason, the signal delay due to the RC component can be reduced when the boosted voltage BS1 is fed back, and the overshoot and undershoot of the boosted voltage BS1 can be reduced.

(Second Embodiment)
FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the second embodiment.
In FIG. 2, the pixel array unit 1 is provided in the solid-state imaging device. In the pixel array unit 1, pixels PC that accumulate photoelectrically converted charges are arranged in a matrix in m (m is a positive integer) rows × n (n is a positive integer) columns in the row direction RD and the column direction CD. Has been. In the pixel array unit 1, a horizontal control line Hlin for performing readout control of the pixel PC is provided in the row direction RD, and a vertical signal line Vlin for transmitting a signal read from the pixel PC is provided in the column direction CD. Is provided.

  Further, in the solid-state imaging device, a source follower operation is performed between the pixel PC to be read out and the vertical scanning circuit 2 that scans the pixel PC in the vertical direction and the pixel PC, so that the pixel PC is connected to the vertical signal line Vlin for each column. A load circuit 3 for reading out pixel signals, a column ADC circuit 4 for detecting signal components of each pixel PC for each column by CDS (correlated double sampling), a horizontal scanning circuit 5 for scanning the pixel PC to be read out in a horizontal direction, A reference voltage generation circuit 6 that outputs a reference voltage VREF to the column ADC circuit 4, a timing control circuit 7 that controls the timing of reading and storage of each pixel PC, and a drive voltage DV that drives the pixel PC when the pixel PC is driven are output. A drive voltage generation circuit 8 is provided. The horizontal scanning circuit 5 can use a horizontal register. A ramp wave can be used as the reference voltage VREF. The drive voltage generation circuit 8 is provided with a booster circuit 8A that generates the drive voltage DV. The configuration of FIG. 1 can be used for the booster circuit 8A.

  Then, the pixel PC is scanned in the vertical direction by the vertical scanning circuit 2, whereby the pixel PC is selected in the row direction RD, and the drive voltage DV generated by the drive voltage generation circuit 8 is supplied to the pixel PC. . Then, the load follower 3 performs a source follower operation with the pixel PC, whereby the pixel signal read from the pixel PC is transmitted via the vertical signal line Vlin and sent to the column ADC circuit 4. . In the reference voltage generation circuit 6, a ramp wave is set as the reference voltage VREF and sent to the column ADC circuit 4. Then, the column ADC circuit 4 performs a clock counting operation until the signal level read from the pixel PC and the reset level coincide with the ramp wave level, and the difference between the signal level and the reset level at that time is taken. Thus, the signal component of each pixel PC is detected for each column by the CDS, and is serially output as the output signal S1.

FIG. 3 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG.
In FIG. 3, each pixel PC is provided with a photodiode PD, a row selection transistor Ta, an amplification transistor Tb, a reset transistor Tr, and a readout transistor Td. In addition, a floating diffusion FD is formed as a detection node at a connection point between the amplification transistor Tb, the reset transistor Tr, and the read transistor Td.

  In the pixel PC, the source of the readout transistor Td is connected to the photodiode PD, and the readout signal ΦD is input to the gate of the readout transistor Td. The source of the reset transistor Tr is connected to the drain of the read transistor Td, the reset signal ΦR is input to the gate of the reset transistor Tr, and the drain of the reset transistor Tr is connected to the power supply potential VDD. The row selection signal ΦA is input to the gate of the row selection transistor Ta, and the drain of the row selection transistor Ta is connected to the power supply potential VDD. The source of the amplification transistor Tb is connected to the vertical signal line Vlin, the gate of the amplification transistor Tb is connected to the drain of the read transistor Td, and the drain of the amplification transistor Tb is connected to the source of the row selection transistor Ta. Yes. 2 can transmit the readout signal ΦD, the reset signal ΦR, and the row selection signal ΦA to the pixel PC for each row. In the load circuit 3 of FIG. 2, a constant current source GA is provided for each column, and the constant current source GA is connected to the vertical signal line Vlin. Note that the drive voltage DV can be used as a pulse voltage for the row selection signal ΦA, the read signal ΦD, and the reset signal ΦR. The horizontal control line Hlin can be provided with a horizontal control line HlinA that transmits a row selection signal ΦA, a horizontal control line HlinD that transmits a read signal ΦD, and a horizontal control line HlinR that transmits a reset signal ΦR.

FIG. 4 is a circuit diagram showing a schematic configuration example of the column ADC circuit 4 of FIG.
In FIG. 4, vertical signal lines Vlin1 to Vlin12 are provided for each column, and pixels PC1 to PC12 are connected to the vertical signal lines Vlin1 to Vlin12. The load circuit 3 is provided with transistors T0 to T12, and the transistors T1 to T12 are connected in series to the vertical signal lines Vlin1 to Vlin12. Each of the transistors T1 to T12 is connected to the transistor T0 in a current mirror, so that a constant current source GA is configured for each column. The column ADC circuit 4 is provided with comparators E1 to E12, counters N1 to N12, capacitors P1 to P12, and switches WD1 to WD12. The reference voltage VREF is input to the non-inverting input terminals of the comparators E1 to E12, and the inverting input terminals of the comparators E1 to E12 are connected to the vertical signal lines Vlin1 to Vlin12 via the capacitors P1 to P12, respectively. The output terminals of the comparators E1 to E12 are connected to the counters N1 to N12. Switches WD1 to WD12 are connected between the inverting input terminals and output terminals of the comparators E1 to E12.

FIG. 5 is a timing chart showing voltage waveforms of the respective units during the pixel readout operation of the solid-state imaging device of FIG.
In FIG. 5, in the sampling period ES, the switches W1 to W3 are turned on according to the switching signal SP. The boosted voltage BS1 output from the charge pump circuit PM1 is divided by a resistor series circuit including a variable resistor R1 and a resistor R2, and the divided voltage VB1 at that time is held in the capacitor C1. At this time, when the row selection signal ΦA is at a low level, the row selection transistor Ta is turned off and the source follower operation is not performed, so that no signal is output to the vertical signal line Vlin. Then, when the read signal ΦD and the reset signal ΦR become high level, the read transistor Td is turned on, and the charge accumulated in the photodiode PD is discharged to the floating diffusion FD. Then, it is discharged to the power supply potential VDD via the reset transistor Tr.

After the charge accumulated in the photodiode PD is discharged to the power supply potential VDD, when the read signal ΦD becomes a low level, accumulation of effective signal charges is started in the photodiode PD.
In the hold period EH, the switches W1 to W3 are turned off according to the switching signal SP. Note that the hold period EH can include the AD conversion period of the column ADC circuit 4. Then, based on the comparison result between the divided voltage VB1 held in the capacitor C1 and the reference voltage VA1, the charge pump circuit PM1 performs a boost operation, and a boosted voltage BS1 is generated. Then, when the potential of the horizontal control line HlinR is level-shifted based on the boost voltage BS1, the reset signal ΦR rises. At this time, the reset transistor Tr is turned on, and excess electric charge generated due to a leakage current or the like is reset in the floating diffusion FD.

  Thereafter, when the potential of the horizontal control line HlinA is level-shifted based on the boosted voltage BS1, the row selection signal ΦA rises. At this time, the row selection transistor Ta of each of the pixels PC1 to PC12 is turned on, and the power supply potential VDD is applied to the drain of the amplification transistor Tb, so that the amplification transistor Tb and the constant current source GA constitute a source follower. A voltage corresponding to the reset level RL of the floating diffusion FD is applied to the gate of the amplification transistor Tb. Here, since the amplification transistor Tb and the constant current source GA form a source follower, the voltages of the vertical signal lines Vlin1 to Vlin12 follow the voltages applied to the gates of the amplification transistors Tb of the pixels PC1 to PC12. Then, the pixel signal Vsig at the reset level RL of each of the pixels PC1 to PC12 is output to the column ADC circuit 4 via the vertical signal lines Vlin1 to Vlin12. At this time, when the reset pulse φC is applied to the switches WD1 to WD12 and the switches WD1 to WD12 are turned on, the input voltages at the inverting input terminals of the comparators E1 to E12 are clamped by the output voltage PO, and the operating point is set. At this time, since each comparator is connected to the voltage follower, the output voltage PO becomes the same potential as the reference potential VREF. In this way, analog sampling is performed by holding charges corresponding to the differential voltages between the vertical signal lines Vlin1 to Vlin12 and the reference potential VREF in the capacitors P1 to P12, and the input voltages of the comparators E1 to E12 are set to zero. Is done.

  Then, after the switches WD1 to WD12 are turned off, the ramp wave WR is given as the reference voltage VREF, and the pixel signals Vsig of the reset levels RL of the pixels PC1 to PC12 and the reference voltage VREF are compared by the comparators E1 to E12. The Then, the pixel signal Vsig at the reset level RL of each of the pixels PC1 to PC12 is counted up by the counters N1 to N12 until the pixel signal Vsig at the reset level RL matches the level of the reference voltage VREF, so that the pixel signal Vsig at the reset level RL becomes the digital value DR. Converted. The digital value DR is converted into a negative value by bit inversion and held.

Next, when the potential of the horizontal control line HlinD is level-shifted based on the boost voltage BS1, the read signal ΦD rises. At this time, the read transistor Td of each of the pixels PC1 to PC12 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD, and the voltage corresponding to the signal level SL of the floating diffusion FD of each of the pixels PC1 to PC12. Is applied to the gate of the amplification transistor Tb. Here, since the amplification transistor Tb and the constant current source GA form a source follower, the voltages of the vertical signal lines Vlin1 to Vlin12 follow the voltages applied to the gates of the amplification transistors Tb of the pixels PC1 to PC12. Then, the pixel signal Vsig of the signal level SL of each of the pixels PC1 to PC12 is output to the column ADC circuit 4 via the vertical signal lines Vlin1 to Vlin12.
At this time, the ramp wave WS is given as the reference voltage VREF, and the pixel signals Vsig of the signal levels SL of the pixels PC1 to PC12 and the reference voltage VREF are compared by the comparators E1 to E12. The pixel signals Vsig at the signal levels SL of the pixels PC1 to PC12 are up-counted by the counters N1 to N12 until they match the level of the reference voltage VREF, so that the pixel signal Vsig at the signal level SL becomes the digital value DS. Converted. The difference DS-DR between the pixel signal Vsig at the signal level SL and the pixel signal Vsig at the reset level RL of each of the pixels PC1 to PC12 is held and output as the output signal S1.
Here, when the potential of the horizontal control line Hlin is level-shifted based on the boosted voltage BS1, the parasitic capacitance of each pixel PC1 to PC12 is charged, so that the boosted voltage BS1 decreases. At this time, the decrease in the boost voltage BS1 can be fed back to the comparator A1 via the capacitor C1, and the charge pump circuit PM1 can be driven to compensate for the decrease in the boost voltage BS1. For this reason, the overshoot and undershoot of the boost voltage BS1 can be reduced as compared with the configuration in which the decrease of the boost voltage BS1 is fed back to the comparator A1 via the resistor series circuit of the variable resistor R1 and the resistor R2. Overshoot and undershoot of the row selection signal ΦA, the read signal ΦD, and the reset signal ΦR can be reduced.

(Third embodiment)
FIG. 6 is a block diagram illustrating a configuration example of the booster circuit according to the third embodiment. Note that the booster circuit can operate as a negative booster circuit.
In FIG. 6, the booster circuit is provided with a reference voltage generation circuit VF2, a comparator A2, a charge pump circuit PM2, a capacitor C11, and a sampling circuit SE2. The sampling circuit SE2 is provided with a variable resistor R11 and switches W11 and W12. The reference voltage generation circuit VF2 is connected to the inverting input terminal of the comparator A2. A capacitor C11 is connected between the output terminal of the charge pump circuit PM2 and the non-inverting input terminal of the comparator A2. A parasitic capacitance C12 is added to the non-inverting input terminal of the comparator A2. An external capacitor C13 may be added to the output terminal of the charge pump circuit PM2 in order to stabilize the negative boost voltage BS2 of the charge pump circuit PM2. The output DET of the comparator A2 is input to the control terminal of the charge pump circuit PM2, and the clock signal CLK is input to the clock terminal of the charge pump circuit PM2. One end of the variable resistor R11 is connected to one end of the capacitor C11 via the switches W11 and W12, and the other end of the variable resistor R11 is connected to the other end of the capacitor C11. One end of the variable resistor R11 is connected to the current source G via the switch W11. The switches W11 and W12 are turned on / off according to the switching signal SP.

In the sampling period, the switches W11 and W12 are turned on. At this time, the output terminal of the charge pump circuit PM2 is connected to the current source G via the variable resistor R11, and the variable resistor R11 is connected in parallel to the capacitor C11. The negative boosted voltage BS2 output from the charge pump circuit PM2 is divided by the variable resistor R11, and the divided voltage VB2 at that time is held in the capacitor C11.
In the hold period, the switches W11 and W12 are turned off. At this time, the variable resistor R11 is disconnected from the capacitor C11. The negative boosted voltage BS2 output from the charge pump circuit PM2 is divided by the capacitor C11, and the divided voltage VB2 at that time is input to the comparator A2. The reference voltage VA2 generated by the reference voltage generation circuit VF2 is input to the comparator A2. The reference voltage VA2 can be set to about 1V, for example. The negative boost voltage BS2 can be set to −1.0 V or more, for example. When the divided voltage VB2 exceeds the reference voltage VA2, the output DET of the comparator A2 rises. At this time, when the clock CLK is supplied to the charge pump circuit PM2, the charge pump circuit PM2 is driven, and the negative boost operation of the negative boost voltage BS2 is performed. As a result of the negative boost operation of the negative boost voltage BS2, when the divided voltage VB2 falls below the reference voltage VA2, the output DET of the comparator A2 falls and the drive of the charge pump circuit PM2 is stopped.
Here, in the hold period, it is possible to prevent current from flowing to the output terminal of the charge pump circuit PM2 via the variable resistor R11. For this reason, it is possible to prevent the negative boost voltage BS2 from rising due to the feedback of the negative boost voltage BS2, and to improve the negative boost efficiency.
In the hold period, the variable resistor R11 can be removed from the feedback system of the negative boost voltage BS2. For this reason, the signal delay due to the RC component can be reduced during feedback of the negative boost voltage BS2, and the overshoot and undershoot of the negative boost voltage BS2 can be reduced.

(Fourth embodiment)
FIG. 7 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the fourth embodiment is applied.
In FIG. 7, the digital camera 21 includes a camera module 22 and a post-processing unit 23. The camera module 22 includes an imaging optical system 24 and a solid-state imaging device 25. The post-processing unit 23 includes an image signal processor (ISP) 26, a storage unit 27, and a display unit 28. The solid-state imaging device 25 can use the configuration shown in FIG. Further, at least a part of the configuration of the ISP 26 may be integrated into one chip together with the solid-state imaging device 25.

  The imaging optical system 24 takes in light from the subject and forms a subject image. The solid-state imaging device 25 captures a subject image. The ISP 26 processes an image signal obtained by imaging with the solid-state imaging device 25. The storage unit 27 stores an image that has undergone signal processing in the ISP 26. The storage unit 27 outputs an image signal to the display unit 28 according to a user operation or the like. The display unit 28 displays an image according to the image signal input from the ISP 26 or the storage unit 27. The display unit 28 is, for example, a liquid crystal display. In addition to the digital camera 21, the camera module 22 may be applied to an electronic device such as a camera-equipped mobile phone or a smartphone.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 pixel array unit, 2 vertical scanning circuit, 3 load circuit, 4 column ADC circuit, 5 horizontal scanning circuit, 6 reference voltage generating circuit, 7 timing control circuit, 8 drive voltage generating circuit, 8A boosting circuit, PC pixel, Ta row Select transistor, Tb amplification transistor, Tr reset transistor, Td read transistor, PD photodiode, FD floating diffusion, Vlin vertical signal line, Hlin horizontal control line

Claims (5)

A charge pump circuit for boosting operation;
A capacitor for holding the divided voltage obtained by dividing the boosted voltage output from the charge pump circuit;
And a comparator that operates the charge pump circuit based on a comparison result between the divided voltage held in the capacitor and a reference voltage.   The booster circuit according to claim 1, further comprising a sampling circuit that samples the divided voltage obtained by dividing the boosted voltage and holds the divided voltage in the capacitor. The sampling circuit is
A voltage dividing resistor for dividing the boosted voltage;
3. The booster circuit according to claim 2, further comprising: a switch that connects the voltage dividing resistor in parallel with the capacitor when the divided voltage is sampled, and that disconnects the voltage dividing resistor from the capacitor when the divided voltage is held. A pixel array unit in which pixels that store photoelectrically converted charges are arranged in a row direction and a column direction;
A drive voltage generation circuit for generating a drive voltage for driving the pixel based on a boosted voltage;
A column ADC circuit that AD-converts pixel signals read from the pixels in parallel;
With
The drive voltage generation circuit includes:
A charge pump circuit for performing the boosting operation;
A capacitor for holding the divided voltage obtained by dividing the boosted voltage output from the charge pump circuit;
A comparator for operating the charge pump circuit based on a comparison result between the divided voltage held in the capacitor and a reference voltage;
A solid-state imaging device comprising: a sampling circuit that samples a divided voltage obtained by dividing the boosted voltage and holds the divided voltage in the capacitor. The sampling circuit is
A voltage dividing resistor for dividing the boosted voltage;
A switch for connecting the voltage dividing resistor in parallel with the capacitor when sampling the divided voltage, and a switch for disconnecting the voltage dividing resistor from the capacitor when holding the divided voltage;
The solid-state imaging device according to claim 4, wherein the divided voltage hold period includes an AD conversion period of the column ADC circuit.

Images