JP2016208116A - Imaging device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging device capable of reducing power consumption.SOLUTION: An imaging device is configured to operate by switching a first mode and a second mode. In the first mode, the imaging device performs digital processing, and generates a digital signal on the basis of imaging data imaged by a pixel. In the second mode, the imaging device compares first imaging data imaged by the pixel with second imaging data, and detects a difference to generate a signal which becomes a trigger. Transition from the second mode to the first mode is performed on the basis of the signal which becomes the trigger.SELECTED DRAWING: Figure 3

Description

One embodiment of the present invention relates to an imaging device and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a memory device, a driving method thereof, or a driving method thereof. A manufacturing method can be mentioned as an example.

Imaging devices are mounted on various electronic devices. In addition to electronic devices, the imaging device has been used for a wide range of applications, such as surveillance cameras. Since demand is expected in the future, research and development is active (see, for example, Patent Documents 1 and 2).

US Patent Application Publication No. 2003/0052324 US Patent Application Publication No. 2011/0204371

As described above, there are a large number of configurations of the imaging device and the like. Each configuration has advantages and disadvantages, and an appropriate configuration is selected according to the situation. Therefore, if an imaging apparatus having a new configuration can be proposed, the degree of freedom in selection can be improved.

An object of one embodiment of the present invention is to provide a novel imaging device or the like.

The application of the imaging device includes the use of a surveillance camera in addition to the application of mounting on an electronic device. In the case of a surveillance camera or the like, a system that sounds an alarm when an intruder is found can be considered for crime prevention. Specifically, image processing is performed to compare the image data of the captured image with no intruder in the monitoring area captured by the CMOS image sensor and the image data of the current captured image. In such a case, a determination signal may be generated.

When performing the above image processing, first, data of each pixel of the CMOS image sensor is read and converted into digital data by A / D conversion. Subsequently, the digital data is taken into the computer, and the image processing software is executed on the computer. Therefore, enormous power such as A / D conversion in a CMOS image sensor, data transfer for capturing a large amount of digital data into a computer, storage and reading of the digital data in a storage device in the computer, execution of image processing software, etc. The determination signal is generated while consuming.

In order to further reduce the power consumption of the entire imaging apparatus, it is important to reduce the power consumption required for digital processing. Further, it is important to reduce power consumption required for analog processing for controlling digital processing.

Thus, an object of one embodiment of the present invention is to provide an imaging device or the like with a novel structure that can reduce power consumption.

Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not disturb the existence of other problems. Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described description and / or other problems.

One embodiment of the present invention is an imaging device that includes a switching circuit, a pixel, a readout circuit, and a comparison circuit, and has a function of switching between a first mode and a second mode. The pixel includes a photoelectric conversion element and first to fourth transistors, and a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor, and the fourth transistor Of the third transistor is electrically connected to one of a source and a drain of the third transistor, and the photoelectric conversion element is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor. One of the source and the drain of the second transistor is electrically connected to the first wiring, and the source or the drain of the fourth transistor One is electrically connected to the second wiring, and the reading circuit is electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fourth transistor, and the first circuit In the mode, it has a function of outputting a voltage according to the voltage of the gate of the second transistor or the gate of the fourth transistor. In the second mode, the voltage of the gate of the second transistor and the fourth transistor The switching circuit has a function of amplifying a difference from the voltage of the gate of the transistor, and the switching circuit is electrically connected to the first wiring and the second wiring, and in the first mode, the first wiring and the second wiring And a function of supplying a constant current to the first wiring and the second wiring in the second mode, and the comparison circuit includes the first wiring and the second wiring. Lines are electrically connected, in the second mode, depending on the difference between the voltage of the first wiring and the second wiring has a function of outputting a signal, which is an imaging device.

In one embodiment of the present invention, a pixel includes a fifth transistor and a sixth transistor, and one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor The other of the source and the drain of the fifth transistor is electrically connected to the readout circuit, and one of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fourth transistor In addition, an imaging device in which the other of the source and the drain of the sixth transistor is electrically connected to the readout circuit is preferable.

In one embodiment of the present invention, the pixel includes a seventh transistor, one of a source and a drain of the seventh transistor is electrically connected to the photoelectric conversion element, and the other of the source and the drain of the seventh transistor Is preferably an imaging device that is electrically connected to a wiring for supplying a reset voltage.

In one embodiment of the present invention, an imaging device in which the first transistor includes an oxide semiconductor in a channel formation region and the third transistor includes an oxide semiconductor in a channel formation region is preferable.

In one embodiment of the present invention, the photoelectric conversion element is preferably an imaging device having a material containing selenium.

Note that other aspects of the present invention are described in the following embodiments and drawings.

One embodiment of the present invention can provide a novel imaging device or the like.

Alternatively, according to one embodiment of the present invention, an imaging device or the like having a novel structure that can reduce power consumption can be provided.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the above effects and / or other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 11 is a block diagram illustrating a structure of an imaging device. 6 is a flowchart illustrating a configuration of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. 6 is a timing chart illustrating a configuration of an imaging device. 6 is a timing chart illustrating a configuration of an imaging device. 6 is a timing chart illustrating a configuration of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 10 is a circuit diagram illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. The figure explaining operation | movement of a global shutter system and a rolling shutter system. Sectional drawing explaining the connection form of a photoelectric conversion element. Sectional drawing explaining the connection form of a photoelectric conversion element. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. Sectional drawing explaining the connection form of a photoelectric conversion element. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view and a circuit diagram illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. 3A and 3B illustrate a curved imaging device. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 6A and 6B illustrate a cross section of a transistor in a channel width direction. 6A and 6B illustrate a cross section of a transistor in a channel length direction. 8A and 8B are a top view and a cross-sectional view illustrating a semiconductor layer. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 4A and 4B are a top view and cross-sectional views illustrating a transistor. 6A and 6B illustrate a cross section of a transistor in a channel width direction. 6A and 6B illustrate a cross section of a transistor in a channel length direction. 4A and 4B are a top view and cross-sectional views illustrating a transistor. FIG. 10 is a top view illustrating a transistor. The perspective view explaining a camera module. The figure of the electronic device provided with the camera module.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the present specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, a component referred to as “first” in one embodiment of the present specification may be omitted in another embodiment or in the claims.

Note that in the drawings, the same element, an element having a similar function, an element of the same material, an element formed at the same time, or the like may be denoted by the same reference numeral, and repeated description thereof may be omitted.

(Embodiment 1)
In this embodiment, an imaging device that is one embodiment of the present invention will be described with reference to drawings.

<Block Diagram and Operation of Imaging Device>
The configuration of the imaging device will be described with reference to FIG. FIG. 1 shows a block diagram of the imaging apparatus.

The imaging device includes a pixel portion 405 including a plurality of pixels 400 (PIX) arranged in a matrix of m rows and n columns, an analog processing circuit 401 (Analog), and an A / D conversion circuit 402 (ADC) that is a digital processing circuit. Column driver 403 (CDRV) and row driver 404 (RDRV).

The pixel 400 includes a photoelectric conversion element and at least one transistor. The pixel 400 can hold a plurality of analog voltage values (imaging data) obtained by imaging. For example, the first imaging data and the second imaging data can be held.

The first imaging data and the second imaging data held in the pixel 400 can be imaging data acquired at different timings. The first imaging data and the second imaging data can be acquired and held by selecting a pixel. The first imaging data and the second imaging data can be read by selecting a pixel. The first imaging data and the second imaging data can be compared by selecting pixels. Note that in the pixel portion 405, a pixel in row j and column k (1 ≦ j ≦ m, 1 ≦ k ≦ n) of the pixel 400 is illustrated as (j, k).

The pixel 400 is connected to the wiring TX (TX [1] to TX [m]). The wiring TX is supplied with a signal for controlling selection and holding of a pixel to be imaged. The pixel 400 is supplied with a signal for outputting the wiring SE (SE [1] to SE [m]). The signal SE is a signal for reading imaging data and comparing imaging data. The wiring TX and the wiring SE are connected to the row driver 404, for example. Note that a plurality of wirings TX and wirings SE are provided for each row in accordance with the number of imaging data held in the pixels.

The pixel 400 is connected to the wiring OD1 (OD1 [1] to OD1 [n]) and the wiring OD2 (OD2 [1] to OD2 [n]). The wirings OD1 and OD2 are provided according to the number of imaging data. In this embodiment, two imaging data (first imaging data and second imaging data) will be described as an example of imaging data held by the pixel 400. Therefore, the two wirings OD1 and OD2 are connected to the pixel 400. The wirings OD1 and OD2 provide a voltage for reading the imaging data and a current for comparing the imaging data. The wirings OD1 and OD2 are connected to the column driver 403 and the analog processing circuit 401, for example.

The pixel 400 is connected to the wiring OUT (OUT [1] to OUt [n]). The wiring OUT is supplied with an output voltage corresponding to the imaging data and a current corresponding to the difference between the two imaging data. The wiring OUT is connected to the A / D conversion circuit 402, for example.

The analog processing circuit 401 performs data processing on the imaging data output from each pixel 400. More specifically, a difference between two pieces of imaging data held by the pixel 400 is detected. When the two imaging data are different, that is, when a difference occurs, a Compout signal is generated. The Compout signal is sequentially extracted to the outside as a trigger signal (denoted as TRIG).

The A / D conversion circuit 402 converts the output voltage corresponding to the imaging data into digital data by A / D conversion. The A / D converted digital data is sequentially taken out as data DATA.

Various circuits such as a decoder and a shift register are used for the column driver 403 and the row driver 404.

Next, an outline of the operation of the imaging apparatus will be described with reference to FIG.

The operation in the first mode will be described. In the first mode, the pixel 400 is converted into an output voltage corresponding to the first image data captured, and the analog output voltage is A / D converted into digital data (step S101).

The operation (step S102) when transitioning from the first mode to the second mode can be performed by setting conditions in advance. For example, a condition such as the elapse of a specific period or the input of a control signal for ending digital processing. When this condition is satisfied, a transition is made from the first mode to the second mode.

The operation in the second mode will be described. In the second mode, the analog processing circuit 401 detects a difference between the first imaging data captured by the pixel 400 and the second imaging data serving as a reference (step S103). If there is no difference between the first imaging data and the second imaging data by the analog processing, that is, if no trigger signal is generated, the analog processing is continued. On the other hand, if there is a difference between the first imaging data and the second imaging data by the analog processing (step S104), that is, if a trigger signal is generated, the mode is changed to the first mode.

In the imaging apparatus having the above-described configuration, in the second mode, digital processing that consumes enormous power is not performed, and it is only necessary to perform minimum analog processing for generating a trigger signal. Can be reduced. Further, in the first mode, the cause of the trigger signal generated by digital processing, that is, the difference between the first imaging data and the second imaging data can be confirmed in detail.

<Regarding Pixel and Peripheral Circuit of Imaging Device>
Next, a configuration example of a pixel and a peripheral circuit of the imaging device that can operate the imaging device described above will be described. FIG. 3 shows an example of a circuit diagram of a pixel and main circuit blocks of a peripheral circuit.

FIG. 3 illustrates a switching circuit 201, a readout circuit 202, and a comparison circuit 203 as peripheral circuits in addition to the pixel 200. The functions of the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203 can be switched between the first mode and the second mode described above.

The pixel 200 includes a photoelectric conversion element PCL1, transistors M1 to M7, and capacitors C1 and C2. The pixel 200 corresponds to the pixel 400 in FIG. The pixel 200 has a function of acquiring and holding first imaging data and second imaging data.

The gate of the transistor M3 is connected to one of the source and the drain of the transistor M2. The node of the gate of the transistor M3 will be described as a node FD1. The gate of the transistor M6 is connected to one of the source and the drain of the transistor M5. The node of the gate of the transistor M6 will be described as a node FD2. Note that although FIG. 3 illustrates a configuration in which the capacitors C1 and C2 are connected to the nodes FD1 and FD2, respectively, it can be omitted by increasing the gate capacitance of the transistor.

The node FD1 can have a voltage corresponding to the current flowing through the photoelectric conversion element PCL1 by turning on the transistor M2. The node FD1 can hold charge by turning off the transistor M2. That is, the node FD1 can hold the first imaging data by controlling on or off of the transistor M2. The transistor M2 can be controlled by a signal given to the wiring TX1. The wiring TX1 corresponds to the wiring TX described above.

The node FD2 can have a voltage corresponding to the current flowing through the photoelectric conversion element PCL1 by turning on the transistor M5. The node FD2 can hold charge by turning off the transistor M5. That is, the node FD2 can hold the second imaging data by controlling on or off of the transistor M5. The transistor M5 can be controlled by a signal given to the wiring TX2. The wiring TX2 corresponds to the wiring TX described above.

In FIG. 3, as an example, the transistors M1 to M7 are illustrated as n-channel transistors. In particular, as the transistor M2 and the transistor M5, it is particularly preferable to use a transistor using an oxide semiconductor in a channel formation region (OS transistor).

Since the OS transistor has extremely low off-state current characteristics, the dynamic range of imaging can be expanded. In the circuit configuration of the pixel 200, when the intensity of light incident on the photoelectric conversion element PCL1 is large, the potential of the node FD1 (or FD2) corresponding to the charge storage portion is small. Since the OS transistor has an extremely low off-state current, a current corresponding to the gate potential can be accurately output even when the gate potential is extremely small. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be expanded.

In addition, the OS transistor can be used in a very wide temperature range because the temperature dependency of variation in electrical characteristics is smaller than that of a transistor using silicon as an active region or active layer (hereinafter, Si transistor). Therefore, an imaging device and a semiconductor device having an OS transistor are suitable for mounting on automobiles, aircraft, spacecrafts, and the like.

The OS transistor has a higher drain breakdown voltage than the Si transistor. In a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, it is preferable to apply a relatively high voltage (for example, 10 V or more) so that an avalanche phenomenon easily occurs. Therefore, by combining an OS transistor and a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, an imaging device with high reliability can be obtained.

One terminal of the photoelectric conversion element PCL1 is connected to the other of the source and the drain of the transistor M2 and the other of the source and the drain of the transistor M5. By turning on the transistor M2 or the transistor M5, the node FD1 or the node FD2 can have a voltage corresponding to the current flowing through the photoelectric conversion element PCL1. The other terminal of the photoelectric conversion element PCL1 may be given a voltage V _SS as an example.

The transistor M1 may be provided on the other of the source and the drain of the transistor M2 and the other of the source and the drain of the transistor M5. Transistor M1, the signal applied to the wiring PR, the node FD1 or node FD2, can provide a reset voltage _{V RS.}

One of the source and the drain of the transistor M3 is connected to the wiring OD1. The other of the source and the drain of the transistor M3 is connected to one of the source and the drain of the transistor M4. The other of the source and the drain of the transistor M4 is connected to the reading circuit 202.

One of the source and the drain of the transistor M6 is connected to the wiring OD2. The other of the source and the drain of the transistor M6 is connected to one of the source and the drain of the transistor M7. The other of the source and the drain of the transistor M7 is connected to the reading circuit 202.

In the transistor M3, the wiring OD1 is set to the voltage V _DD and the transistor M4 is turned on, whereby the voltage corresponding to the voltage of the node FD1 is set to the output voltage _VOUT, and is converted into digital data by the A / D conversion circuit described above. Can be output.

Further, the same constant current flows in the wiring OD1 and the wiring OD2, and the transistor M4 and the transistor M7 are turned on, so that the voltage of the wiring OD1 and the wiring OD2 is changed to the voltage corresponding to the voltage of the node FD1 and the voltage of the node FD2. The voltage can be set according to the voltage.

One of the source and the drain of the transistor M3 is connected to the wiring OD1. The other of the source and the drain of the transistor M3 is connected to one of the source and the drain of the transistor M4. The other of the source and the drain of the transistor M4 is connected to the reading circuit 202. The transistor M3 can output a voltage corresponding to the voltage of the node FD1 by turning on the transistor M4. The transistor M4 can be controlled by a signal supplied to the wiring SE1. The wiring SE1 corresponds to the wiring SE described above.

One of the source and the drain of the transistor M6 is connected to the wiring OD2. The other of the source and the drain of the transistor M6 is connected to one of the source and the drain of the transistor M7. The other of the source and the drain of the transistor M7 is connected to the reading circuit 202. The transistor M6 can output a voltage corresponding to the voltage of the node FD2 by turning on the transistor M7. The transistor M7 can be controlled by a signal given to the wiring SE2. The wiring SE2 corresponds to the wiring SE described above.

The switching circuit 201 is connected to the wiring OD1 and the wiring OD2. The switching circuit 201 has a function of applying a constant voltage to the wiring OD1 and the wiring OD2 in the first mode. The switching circuit 201 has a function of flowing a constant current through the wiring OD1 and the wiring OD2 in the second mode. The switching circuit 201 can switch functions by the control signal CON1. Note that the switching circuit 201 may be provided in the A / D conversion circuit 402, for example.

The read circuit 202 is connected to the other of the source and the drain of the transistor M4 and the other of the source and the drain of the transistor M7. The reading circuit 202 has a function of outputting a voltage according to the voltage of the gate of the transistor M3, that is, the node FD1 in the first mode. The reading circuit 202 has a function of outputting a voltage in accordance with the voltage of the gate of the transistor M6, that is, the node FD2. In addition, the reading circuit 202 has a function of amplifying a difference between the voltage of the node FD1 and the voltage of the node FD2 in the second mode. Note that the reading circuit 202 may be provided in the A / D conversion circuit 402, for example.

The comparison circuit 203 is connected to the wiring OD1 and the wiring OD2. The comparison circuit 203 does not operate in the first mode. The comparison circuit 203 has a function of outputting a signal in accordance with the voltage difference between the wiring OD1 and the wiring OD2 in the second mode. Note that the comparison circuit 203 may be provided in the analog processing circuit 401, for example.

In addition to the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203, which are peripheral circuits, can be switched and operated between the first mode and the second mode, so that the acquisition of imaging data and the interval between imaging data are performed. It can be set as the structure which compares the difference of these. In the configuration of FIG. 3, the imaging data can be acquired and read out in the pixel 200 in the first mode. In the second mode, the pixel 200 and peripheral circuits (the switching circuit 201, the readout circuit 202, and the comparison circuit 203) function as a differential amplifier circuit to amplify the difference between the two pieces of imaging data held in the pixel 200. Can output a trigger signal.

With each configuration described above, the imaging device is operated by switching between the first mode and the second mode. In the first mode, the voltage _VOUT is generated based on the voltage of the node FD1 corresponding to the image data captured by the pixel 200, and the digital signal can be generated based on the voltage _VOUT . In the second mode, the voltage of the node FD1 corresponding to the first image data captured by the pixel 200 is compared with the voltage of the node FD2 corresponding to the second image data, and a trigger is obtained by detecting the difference. The signal Comp _OUT can be generated. Based on this signal Comp _OUT , a signal TRIG serving as a trigger for controlling transition from the second mode to the first mode can be generated.

<About pixel operation>
Next, operations of the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203 described in FIG. 3 in the first mode and the second mode will be described.

FIG. 4 illustrates an example of a circuit configuration of the switching circuit 201, the reading circuit 202, and the comparison circuit 203 illustrated in FIG.

The switching circuit 201 illustrated in FIG. 4 includes transistors M11 to M14. In FIG. 4, the transistors M11 to M14 are illustrated as p-channel transistors. The transistors M11 and M14 can be switched between an on state and an off state by a control signal CON1. Transistors M12 and M13 constitute a constant current source by applying a bias voltage VBIAS0. When the transistors M11 and M14 are on, the wirings OD1 and OD2 are at the voltage VDD. In addition, when the transistors M11 and M14 are in an off state, the same current can flow through the wirings OD1 and OD2.

The reading circuit 202 illustrated in FIG. 4 includes a transistor M21. In FIG. 4, the transistor M21 is illustrated as an n-channel transistor. The bias voltage VBIAS1 is applied to the transistor M21 and can function as a constant current source. Therefore, the output voltage VOUT can be output according to the voltage of the node FD1 or the node FD2. Further, the voltage difference between the nodes FD1 and FD2 can be amplified.

The comparison circuit 203 illustrated in FIG. 4 includes transistors M31 to M34 and a logic circuit OR. In FIG. 4, the transistors M31 and M33 are illustrated as p-channel transistors, and the transistors M32 and M34 are illustrated as n-channel transistors. The transistor M31 has a gate connected to the wiring OD1. The transistor M33 has a gate connected to the wiring OD2. The bias voltage VBIAS2 is applied to the transistors M32 and M34 and can function as a constant current source. The logic circuit OR has a function as a logical sum. The logic circuit OR is supplied with a high level voltage when the voltages of the wirings OD1 and OD2 are different. Therefore, the logic circuit OR can output the signal Comp _OUT when the voltages of the wirings OD1 and OD2 are different.

Next, the operation in the first mode in the circuit configuration shown in FIG. 4 will be described. FIG. 5 is a timing chart for explaining voltage states and signal states in each circuit of the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203 in the first mode.

The timing chart in FIG. 5 represents a series of operations when imaging is performed by the pixel 200. In FIG. 5, a period P1 is a reset period (Reset in the figure). In FIG. 5, a period P2 is an imaging period (Exposure in the figure). In FIG. 5, a period P3 is a reading period (Readout in the figure).

In the timing chart in FIG. 5, the signal PR for initializing the node FD1 or the node FD2, the signal applied to the wiring TX1, the signal applied to the wiring TX2, the voltage of the node FD1, the voltage of the node FD2, the wirings SE1 [1] to SE1. The waveforms of the signal given to [m], the signals given to the wirings SE2 [1] to SE2 [m], the control signal CON1, and the signal Comp _OUT are shown.

First, in the period P1, the node FD1 is initialized (reset). Initialization is performed by the node FD1 and the voltage _{V RS.} The transistor M1 is turned on by setting the signal PR to a high level. By setting the signal supplied to the wiring TX1 to a high level, the transistor M2 is turned on. By setting the signal supplied to the wiring TX2 to a low level, the transistor M5 is turned off. The voltage of the node FD1 is the voltage V _RS . The voltage of the node FD2 is in the original state, that is, the low level. A signal supplied to the wirings SE1 [1] to SE1 [m] is at a low level, and the transistor M4 is off. A signal supplied to the wirings SE2 [1] to SE2 [m] is at a low level, and the transistor M7 is off. The control signal CON1 is at a low level, and the wirings OD1 and OD2 are at the voltage V _DD . Since the transistors M4 and M7 are off, no current flows between the wiring OD1 and the reading circuit 202 and between the wiring OD2 and the reading circuit 202. The wiring OD1 does not change from the voltage V _DD and the signal Comp _OUT is at a low level. Note that the node FD2 may be initialized in the period R1.

Next, in a period P2, imaging is performed by changing the voltage of the node FD1 in accordance with the current flowing by receiving light with the photoelectric conversion element PCL1. In imaging, the transistor M1 is turned off by setting the signal PR to a low level. By setting the signal supplied to the wiring TX1 to a high level, the transistor M2 is turned on. By setting the signal supplied to the wiring TX2 to a low level, the transistor M5 is turned off. The voltage of the node FD1 is changed from the voltage _{V RS} depending on the intensity of light received by the photoelectric conversion element PCL1. In the configuration of FIG. 4, when the intensity of light is large, the current flowing through the photoelectric conversion element PCL1 increases, so that the change in voltage increases (Bright in the figure). The voltage of the node FD2 is in the original state, that is, the low level. A signal supplied to the wirings SE1 [1] to SE1 [m] is at a low level, and the transistor M4 is off. A signal supplied to the wirings SE2 [1] to SE2 [m] is at a low level, and the transistor M7 is off. The control signal CON1 is at a low level, and the wirings OD1 and OD2 are at the voltage V _DD . Since the transistors M4 and M7 are off, no current flows between the wiring OD1 and the reading circuit 202 and between the wiring OD2 and the reading circuit 202. The wiring OD1 does not change from the voltage V _DD and the signal Comp _OUT is at a low level. Note that in the period T2, imaging in which the voltage of the node FD2 is changed may be performed.

Next, in a period P3, the voltage of the node FD1 is read, that is, the imaging data is read. In reading, the transistor M1 is turned off by setting the signal PR to a low level. By setting a signal supplied to the wiring TX1 to a low level, the transistor M2 is turned off. By setting the signal supplied to the wiring TX2 to a low level, the transistor M5 is turned off. By turning off the transistors M2 and M5, the voltage of the node FD1 and the voltage of the node FD2 can be held. Signals supplied to the wirings SE1 [1] to SE1 [m] are sequentially set to a high level, and the transistors M4 are sequentially turned on. A signal supplied to the wirings SE2 [1] to SE2 [m] is at a low level, and the transistor M7 is off. The control signal CON1 is at a low level, and the wirings OD1 and OD2 are at the voltage V _DD . Since the transistor M4 is on, a voltage according to the voltage of the node FD1 is output between the wiring OD1 and the reading circuit 202. The wiring OD1 does not change from the voltage V _DD and the signal Comp _OUT is at a low level.

In the first mode, each of the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203 can perform various operations of resetting, imaging, and readout using the circuit configuration illustrated in FIG. .

Next, the operation in the second mode in the circuit configuration shown in FIG. 4 will be described. 6 and 7 are timing charts for explaining voltage states and signal states in each circuit of the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203 in the second mode.

FIG. 6 is a timing chart of an operation in the case where the first imaging data serving as a reference and the second imaging data captured in another period are held and the results of comparing each other are different. FIG. 7 is a timing chart of operations in the same case as a result of holding the first imaging data serving as a reference and the second imaging data captured in another period and comparing the imaging data with each other.

The timing charts in FIGS. 6 and 7 represent a series of operations when imaging is performed by the pixel 200. 6 and 7, a period P4 is a reset period (Reset in the figure) of the node FD1. 6 and 7, a period P5 is an imaging period of the node FD1 (Exposure in the figure). 6 and 7, a period P6 is a reading period of the node FD1 (Readout in the figure). 6 and 7, a period P7 is a reset period (Reset in the figure) of the node FD2. 6 and 7, a period P8 is an imaging period of the node FD2 (Exposure in the figure). 6 and 7, a period P9 is a voltage comparison period (COMP in the drawing) of the nodes FD1 and FD2.

6 and 7, the signal PR for initializing the node FD1 or the node FD2, the signal applied to the wiring TX1, the signal applied to the wiring TX2, the voltage of the node FD1, the voltage of the node FD2, the wiring SE1 [1 To SE1 [m], the signals given to the wirings SE2 [1] to SE2 [m], the control signal CON1, and the signal Comp _OUT .

The periods P4 to P6 are the same operations as the periods P1 to P3 described above. With these operations, the reference voltage (V _REF ) is held at the node FD1. This voltage V _REF becomes reference imaging data for detecting a difference between the imaging data.

In the period P7, the node FD2 is initialized. Initialization is performed by the node FD2 voltage _{V RS.} The transistor M1 is turned on by setting the signal PR to a high level. By setting a signal supplied to the wiring TX1 to a low level, the transistor M2 is turned off. By setting the signal supplied to the wiring TX2 to a high level, the transistor M5 is turned on. The voltage of the node FD1 is still held in the voltage _{V REF,} the voltage of the node FD2 becomes the voltage _{V RS.} A signal supplied to the wirings SE1 [1] to SE1 [m] is at a low level, and the transistor M4 is off. A signal supplied to the wirings SE2 [1] to SE2 [m] is at a low level, and the transistor M7 is off. The control signal CON1 is at a low level, and the wirings OD1 and OD2 are at the voltage V _DD . Since the transistors M4 and M7 are off, no current flows between the wiring OD1 and the reading circuit 202 and between the wiring OD2 and the reading circuit 202. The wiring OD1 does not change from the voltage V _DD and the signal Comp _OUT is at a low level.

Next, in a period P8, imaging is performed by changing the voltage of the node FD2 in accordance with the current flowing by receiving light with the photoelectric conversion element PCL1. In imaging, the transistor M1 is turned off by setting the signal PR to a low level. By setting a signal supplied to the wiring TX1 to a low level, the transistor M2 is turned off. By setting the signal supplied to the wiring TX2 to a high level, the transistor M5 is turned on. The voltage of the node FD1 is still held in the voltage _{V REF,} the voltage at the node FD2 is changed from the voltage _{V RS} depending on the intensity of light received by the photoelectric conversion element PCL1. The voltage of the node FD2 is the voltage V _IMG (≠ V _REF ). A signal supplied to the wirings SE1 [1] to SE1 [m] is at a low level, and the transistor M4 is off. A signal supplied to the wirings SE2 [1] to SE2 [m] is at a low level, and the transistor M7 is off. The control signal CON1 is at a low level, and the wirings OD1 and OD2 are at the voltage V _DD . Since the transistors M4 and M7 are off, no current flows between the wiring OD1 and the reading circuit 202 and between the wiring OD2 and the reading circuit 202. The wiring OD1 does not change from the voltage V _DD and the signal Comp _OUT is at a low level.

Next, in a period P9, the voltage of the node FD1 and the voltage of the node FD2 are compared, and comparison between imaging data is performed. In the comparison of imaging data, the transistor M1 is turned off by setting the signal PR to a low level. By setting a signal supplied to the wiring TX1 to a low level, the transistor M2 is turned off. By setting the signal supplied to the wiring TX2 to a low level, the transistor M5 is turned off. By turning off the transistors M2 and M5, the voltage of the node FD1 and the voltage of the node FD2 can be held. Signals supplied to the wirings SE1 [1] to SE1 [m] are sequentially set to a high level, and the transistor M4 is sequentially turned on. Signals supplied to the wirings SE2 [1] to SE2 [m] are sequentially set to a high level, and the transistor M7 is sequentially turned on. The control signal CON1 is set to the high level, and the same current flows through the wirings OD1 and OD2. Since the transistors M4 and M7 are on, the sum of the currents flowing through the transistors M4 and M7 is equal to the current flowing through the transistor 21. The current flowing through the transistors M4 and M7 is equal to the current flowing through the transistors M3 and M6. The current flowing through the transistors M3 and M6 is determined by the voltage of the node FD1 and the voltage of the node FD2. When a difference occurs between the voltage of the node FD1 and the voltage of the node FD2, a difference occurs in currents flowing through the transistors M3 and M6, and a difference occurs in the voltages of the wiring OD1 and the wiring OD2. Specifically, the voltage of the wiring OD1 or the wiring OD2 decreases. Therefore, a current flows through the transistor M31 or M33 included in the comparison circuit 203, and one input signal of the logic circuit OR rises. Therefore, when a difference occurs between the voltage of the node FD1 and the voltage of the node FD2, the signal Comp _OUT is at a high level as illustrated in FIG.

On the other hand, when there is no difference between the voltage of the node FD1 and the voltage of the node FD2, there is no difference between the currents flowing through the transistors M3 and M6. Therefore, there is no difference between the voltages of the wiring OD1 and the wiring OD2. Therefore, a sufficient current does not flow through the transistor M31 or M33 included in the comparison circuit 203, and the input signal of the logic circuit OR remains low. Therefore, when there is no difference between the voltage of the node FD1 and the voltage of the node FD2, the signal Comp _OUT is at a low level as illustrated in FIG.

In the second mode, each circuit of the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203 performs various operations of resetting, imaging, readout, and comparison using the circuit configuration illustrated in FIG. Can do. Each transistor of the pixel 200, the switching circuit 201, the readout circuit 202, and the comparison circuit 203 has a function equivalent to that of the differential amplifier circuit in the second mode, and the voltage of the node FD1 and the voltage of the node FD2 Therefore, it is possible to amplify the difference and output a high level with the signal Comp _OUT .

<Regarding pixel modifications>
Next, a modification of the pixel 200 illustrated in FIGS. 3 and 4 will be described.

As the transistors M1 to M7 included in the pixel 200 in FIGS. 3 and 4, for example, p-channel transistors can be used. A circuit diagram in this case is shown in FIG. When the transistors M1 to M7 are p-channel transistors as in the pixel 200A in FIG. 10A, the transistors M11 to M14 can be manufactured in the same process.

The capacitors C1 and C2 included in the pixel 200 in FIGS. 3 and 4 can be omitted. A circuit diagram in this case is shown in FIG. In this case, the gate capacitances of the transistors M3 and M6 may be increased. Like the pixel 200B in FIG. 10B, the area of the pixel 200 can be reduced by omitting the capacitors C1 and C2.

3 and 4 can be a photoelectric conversion element PCL2 to which avalanche amplification can be applied by applying a high electric field. A circuit diagram in this case is shown in FIG. In order to apply a high electric field to the photoelectric conversion element PCL2, a voltage is applied from the power supply PS. By using the photoelectric conversion element PCL2 to which avalanche amplification can be applied as in the pixel 200C in FIG. 11, it is possible to detect weak light or the like.

The transistors M2 and M5 included in the pixel 200 in FIGS. 3 and 4 each have a back gate, and a voltage _VBG can be applied to the back gate. A circuit diagram in this case is shown in FIG. As in the pixel 200D in FIG. 12A, the threshold voltage of the transistor can be controlled by applying the back gate voltage _VBG to the back gate of the transistor. By controlling the threshold voltage, for example, the threshold voltage can be positively shifted, and the off-state current of the transistors for holding charges accumulated in the nodes FD1 and FD2 can be reduced.

The transistors M2 and M5 included in the pixel 200 in FIGS. 3 and 4 each have a back gate, and a signal of the wirings TX1 and TX2 can be supplied to each back gate. A circuit diagram in this case is shown in FIG. As the pixel 200E in FIG. 12 (B), the In the structure that gives a back gate voltage _{V BG} to the transistors M2, M5 respective signal wiring TX1,2 to the back gate of, controls the on and off states Easy to do. By making it easy to control the on state and the off state, the amount of current flowing through the transistor can be easily controlled.

The transistor M1 included in the pixel 200 in FIGS. 3 and 4 can be directly connected to the nodes FD1 and FD2. A circuit diagram in this case is shown in FIG. As in the pixel 200F in FIG. 13A, the transistor M1_A is connected to the node FD1, and the transistor M1_B is connected to the node FD2. Transistor M1_A control signal PR_A, by transistor M1_B control signal PR_B, can provide a reset voltage _{V RS} to the node FD1, FD2. By doing so, the initialization operation can be performed without controlling the signal applied to the wiring TX.

The transistors M4 and M7 included in the pixel 200 in FIGS. 3 and 4 may be switched in connection with the transistors M3 and M6 so as to be connected to the wirings OD1 and OD2. A circuit diagram in this case is shown in FIG. Transistors M3 to M7 are connected as in the pixel 200G in FIG. By doing in this way, it can suppress that the voltage of node FD1 and FD2 changes with the fluctuation | variation of the voltage of wiring OD1 and OD2.

3 and 4 may have a configuration in which a plurality of photoelectric conversion elements are provided in order to expand the dynamic range. A circuit diagram in this case is shown in FIG. The pixel 200H in FIG. 14 includes a photoelectric conversion element PCL3 in addition to the photoelectric conversion element PCL1. By making the characteristics of the photoelectric conversion element PCL1 and the photoelectric conversion element PCL3 different, it is possible to detect light of different wavelengths. Note that the pixel 200H can share a transistor with an adjacent pixel by providing a plurality of photoelectric conversion elements.

As described above, various modifications can be applied to one embodiment of the present invention.

<Configuration Example of Imaging Device>
Next, a specific configuration example of the imaging device of one embodiment of the present invention is described with reference to drawings. FIG. 15A is an example of a cross-sectional view of the imaging device of one embodiment of the present invention, and illustrates an example of a specific connection mode of the photoelectric conversion element 60a, the transistor 51a, and the transistor. The imaging device includes a layer 1100 provided with transistors 51a and 52a and a layer 1200 provided with a photoelectric conversion element 60a. The photoelectric conversion element 60a corresponds to, for example, the photoelectric conversion element PCL1 in the pixel 200 illustrated in FIGS. The transistor 51a corresponds to, for example, the transistor M2 in the pixel 200 shown in FIGS. The transistor 52a corresponds to, for example, the transistor M5 in the pixel 200 illustrated in FIGS.

Note that in the cross-sectional views described in this embodiment, each wiring, each electrode, and each conductor 81 are illustrated as individual elements. However, in the case where they are electrically connected, the same elements are illustrated. It may be provided as. In addition, a mode in which the gate electrode, the source electrode, or the drain electrode of the transistor is connected to each wiring through the conductor 81 is an example, and each of the gate electrode, the source electrode, and the drain electrode of the transistor functions as a wiring. May have.

In addition, an insulating layer 82, an insulating layer 83, and the like that function as a protective film, an interlayer insulating film, or a planarization film are provided over each element. For example, the insulating layer 82, the insulating layer 83, and the like can be formed using an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. The top surfaces of the insulating layer 82, the insulating layer 83, and the like are preferably subjected to planarization treatment by a CMP (Chemical Mechanical Polishing) method or the like as necessary.

Note that there are cases where some of the wirings and the like shown in the drawings are not provided, and wirings, transistors, and the like that are not shown in the drawings are included in each layer. In addition, a layer not shown in the drawing may be included in the stacked structure. In addition, some of the layers shown in the drawings may not be included.

It is particularly preferable to use OS transistors for the transistors 51a and 52a. The OS transistor has extremely low off-state current characteristics. Due to the low off-state current characteristics of the transistors 51a and 52a, the period during which charges can be held in the nodes FD1 and FD2 can be extremely long. Therefore, it is possible to apply a global shutter system in which charge accumulation operation is simultaneously performed in all pixels without complicating a circuit configuration and an operation method.

In general, in an imaging device in which pixels are arranged in a matrix, a rolling shutter method, which is a driving method for performing an imaging operation 11, a data holding operation 12, and a reading operation 13 for each row, shown in FIG. It is done. When the rolling shutter method is used, image capturing simultaneity is lost, so that the image is distorted when the subject moves.

Therefore, in one embodiment of the present invention, it is preferable to use a global shutter method which can perform the imaging operation 11 simultaneously in all rows and sequentially perform the readout operation 13 for each row, as shown in FIG. By using the global shutter system, it is possible to ensure the simultaneity of imaging in each pixel of the imaging device, and an image with small distortion can be easily obtained even when the subject moves. In addition, since the exposure time (period in which the charge accumulation operation is performed) can be extended by the global shutter method, it is also suitable for imaging in a low illumination environment.

Various types of elements can be used for the photoelectric conversion element 60 a provided in the layer 1200. FIG. 15A illustrates a mode in which a selenium-based material is used for the photoelectric conversion layer 61. The photoelectric conversion element 60a using a selenium-based material has a high external quantum efficiency with respect to visible light. The photoelectric conversion element can be a highly sensitive sensor with a large amplification of electrons with respect to the amount of incident light due to the avalanche phenomenon. Further, since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 61 can be easily thinned.

As the selenium-based material, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be obtained by heat-treating amorphous selenium after film formation. Note that by making the crystal grain size of crystalline selenium smaller than the pixel pitch, it is possible to reduce the characteristic variation of each pixel. Crystalline selenium has higher spectral sensitivity to visible light and higher light absorption coefficient than amorphous selenium.

The photoelectric conversion layer 61 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, a photoelectric conversion element that can utilize an avalanche phenomenon as in the case of a single layer of selenium can be formed.

The photoelectric conversion element 60a using a selenium-based material can be configured to include the photoelectric conversion layer 61 between the electrode 66 formed of a metal material or the like and the light-transmitting conductive layer 62, for example. CIS and CIGS are p-type semiconductors, and n-type semiconductors such as cadmium sulfide and zinc sulfide may be provided in contact with each other to form a junction.

In order to generate the avalanche phenomenon, it is preferable to apply a relatively high voltage (for example, 10 V or more) to the photoelectric conversion element. Since the OS transistor has a higher drain withstand voltage than the Si transistor, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, by combining an OS transistor with a high drain withstand voltage and a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, an imaging device with high sensitivity and high reliability can be obtained.

Note that although the photoelectric conversion layer 61 and the light-transmitting conductive layer 62 are not separated between circuits in FIG. 15A, they may be separated between circuits as shown in FIG. In addition, it is preferable to provide a partition 67 with an insulator in a region where the electrode 66 is not provided between the pixels so that the photoelectric conversion layer 61 and the light-transmitting conductive layer 62 are not cracked. It is good also as a structure which does not provide the partition 67 as shown to (B). 15A shows a structure in which the wiring 88 and the conductor 81 are interposed between the light-transmitting conductive layer 62 and the wiring 72, as shown in FIGS. 17C and 17D. Alternatively, the translucent conductive layer 62 and the wiring 72 may be in direct contact with each other.

Further, the electrode 66, the wiring 72, and the like may be multilayer. For example, as shown in FIG. 18A, the electrode 66 can be a two-layer of a conductive layer 66a and a conductive layer 66b, and the wiring 72 can be a two-layer of a conductive layer 72a and a conductive layer 72b. 18A, for example, the conductive layer 66a and the conductive layer 72a are formed by selecting a low-resistance metal or the like, and the conductive layer 66a and the conductive layer 72a are metals having good contact characteristics with the photoelectric conversion layer 61. Or the like may be selected. By setting it as such a structure, the electrical property of a photoelectric conversion element can be improved. In addition, some metals may cause electrolytic corrosion when in contact with the translucent conductive layer 62. Even when such a metal is used for the conductive layer 72a, electrolytic corrosion can be prevented through the conductive layer 72b.

For example, molybdenum, tungsten, or the like can be used for the conductive layer 66b and the conductive layer 72b. For the conductive layer 66a and the conductive layer 72a, for example, aluminum, titanium, or a stack in which aluminum is sandwiched between titanium can be used.

Further, the insulating layer 82 and the like may be multi-layered. For example, as illustrated in FIG. 18B, when the insulating layer 82 includes the insulating layer 82a and the insulating layer 82b and the etching rates of the insulating layer 82a and the insulating layer 82b are different, the conductor 81 has a step difference. Will have. Similarly, when the other insulating layers used for the interlayer insulating film and the planarizing film are multi-layered, the conductor 81 has a step. Although the example in which the insulating layer 82 is two layers is shown here, the insulating layer 82 and other insulating layers may have three or more layers.

15A, FIG. 17A to FIG. 17D, and the electrode 66 shown in FIG. 18B and the conductive layer 66b shown in FIG. In order to prevent a short circuit with the translucent conductive layer 62 due to a defect or the like, it is preferable that the flatness is high. Note that when the flatness of the electrode 66 and the conductive layer 66b described above is improved, the adhesion to the photoelectric conversion layer 61 may be improved.

As the conductive film having high flatness, for example, an indium tin oxide film to which 1 to 20% of silicon is added can be given. The high flatness of the indium tin oxide film added with silicon has been confirmed by measurement using an atomic force microscope. As a result of measuring an area of 2 μm × 2 μm with an atomic force microscope for each of an indium tin oxide film that was heat-treated at 350 ° C. for 1 hour and an indium tin oxide film to which 10% silicon was added, the former maximum height The difference (P−V) was 23.3 nm, while the latter was 7.9 nm.

The indium tin oxide film is crystallized at a relatively low temperature even if it is amorphous at the time of film formation, so that surface roughness due to crystal grain growth is likely to occur. On the other hand, in the indium tin oxide film to which silicon is added, no peak appears by X-ray diffraction analysis even when heat treatment is performed at a temperature higher than 400 ° C. That is, the indium tin oxide film to which silicon is added maintains an amorphous state even after heat treatment at a relatively high temperature. Therefore, the surface roughness of the indium tin oxide film to which silicon is added hardly occurs.

Note that the partition 67 can be formed using an inorganic insulator, an insulating organic resin, or the like. Further, the partition wall 67 may be colored black or the like for shielding light from the transistor or the like and / or for determining the area of the light receiving portion per pixel.

The photoelectric conversion element 60a may be a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like.

For example, FIG. 19 shows an example in which a pin-type thin film photodiode is used for the photoelectric conversion element 60a. The photodiode has a configuration in which a p-type semiconductor layer 65, an i-type semiconductor layer 64, and an n-type semiconductor layer 63 are sequentially stacked. Amorphous silicon is preferably used for the i-type semiconductor layer 64. For the n-type semiconductor layer 63 and the p-type semiconductor layer 65, amorphous silicon, microcrystalline silicon, or the like containing a dopant imparting each conductivity type can be used. A photodiode using amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.

In the photoelectric conversion element 60a illustrated in FIG. 19, the p-type semiconductor layer 65 is electrically connected to an electrode 66 that is electrically connected to the transistors 51a and 52a. In addition, the n-type semiconductor layer 63 is electrically connected to the wiring 72 through the conductor 81.

20A, 20B, 20C, 20D, 20D, and 20D are shown in FIGS. 20A, 20B, 20C, 20D, and 20D, and the configuration of the photoelectric conversion element 60a in the form of a pin-type thin film photodiode, The example shown to E) and (F) may be sufficient. Note that the configuration of the photoelectric conversion element 60a and the connection form of the photoelectric conversion element 60a and the wiring are not limited to these, and may be other forms.

FIG. 20A illustrates a structure in which a light-transmitting conductive layer 62 that is in contact with the p-type semiconductor layer 63 of the photoelectric conversion element 60a is provided. The translucent conductive layer 62 acts as an electrode and can increase the output current of the photoelectric conversion element 60a.

The light-transmitting conductive layer 62 includes, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, and fluorine. Tin oxide containing, tin oxide containing antimony, graphene, or the like can be used. The translucent conductive layer 62 is not limited to a single layer, and may be a stack of different films.

FIG. 20B illustrates a structure in which the n-type semiconductor layer 63 and the wiring 88 of the photoelectric conversion element 60a have an electrical connection directly.

20C illustrates a structure in which a light-transmitting conductive layer 62 that is in contact with the n-type semiconductor layer 63 of the photoelectric conversion element 60a is provided, and the wiring 88 and the light-transmitting conductive layer 62 are electrically connected.

In FIG. 20D, an opening through which the n-type semiconductor layer 63 is exposed is provided in an insulating layer that covers the photoelectric conversion element 60a, and the light-transmitting conductive layer 62 and the wiring 88 that cover the opening are electrically connected. It is the structure which has.

FIG. 20E illustrates a structure in which a conductor 81 that penetrates the photoelectric conversion element 60a is provided. In this configuration, the wiring 72 is electrically connected to the n-type semiconductor layer 63 through the conductor 81. Note that, in the drawing, the wiring 72 and the electrode 66 are apparently conducted through the p-type semiconductor layer 65. However, since the lateral resistance of the p-type semiconductor layer 65 is high, if an appropriate space is provided between the wiring 72 and the electrode 66, the resistance between the two becomes extremely high. Therefore, the photoelectric conversion element 60a can have a diode characteristic without causing a short circuit between the anode and the cathode. Note that there may be a plurality of conductors 81 electrically connected to the n-type semiconductor layer 63.

FIG. 20F illustrates a structure in which a light-transmitting conductive layer 62 in contact with the n-type semiconductor layer 63 is provided for the photoelectric conversion element 60a in FIG.

Note that the photoelectric conversion element 60a illustrated in FIGS. 20D, 20E, and 20F has an advantage of ensuring a wide light receiving area because the light receiving region and the wiring do not overlap.

Further, as shown in FIG. 21, a photodiode having the silicon substrate 30 as a photoelectric conversion layer can be used for the photoelectric conversion element 60a.

The photoelectric conversion element 60a formed using the above-described selenium-based material, amorphous silicon, or the like can be manufactured using a general semiconductor manufacturing process such as a film formation process, a lithography process, or an etching process. In addition, the selenium-based material has high resistance, and as illustrated in FIG. 15A, the photoelectric conversion layer 61 may not be separated between circuits. Therefore, the imaging device of one embodiment of the present invention can be manufactured with high yield and low cost. On the other hand, when forming a photodiode using the silicon substrate 30 as a photoelectric conversion layer, a highly difficult process such as a polishing process or a bonding process is required.

The imaging device of one embodiment of the present invention may have a structure in which a silicon substrate 30 over which a circuit is formed is stacked. For example, as illustrated in FIG. 22A, a layer 1400 including the transistor 31 and the transistor 32 each having an active region in the silicon substrate 30 may overlap with the pixel circuit. Note that FIG. 22B corresponds to a cross-sectional view of the transistor in the channel width direction.

Here, in FIGS. 23A and 23B, the Si transistor is exemplified as a fin type structure, but may be a planar type as shown in FIG. Alternatively, as shown in FIG. 23B, a transistor having an active layer 35 of a silicon thin film may be used. The active layer 35 can be made of polycrystalline silicon or SOI (Silicon on Insulator) single crystal silicon.

A circuit formed on the silicon substrate 30 can have a function of reading a signal output from the pixel circuit, a function of performing processing for converting the signal, and the like. For example, a circuit diagram illustrated in FIG. A configuration including a CMOS inverter can be adopted. Note that this circuit corresponds to the switching circuit 201, the reading circuit 202, and the comparison circuit 203 shown in FIGS. The gates of the transistor 31 (n-ch type) and the transistor 32 (p-ch type) are electrically connected. In addition, one of the source and the drain of one transistor is electrically connected to one of the source and the drain of the other transistor. In addition, the other of the source or the drain of both transistors is electrically connected to another wiring.

The silicon substrate 30 is not limited to a bulk silicon substrate, and a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor can also be used.

Here, as shown in FIGS. 21 and 22A, insulation is provided between a region where a transistor including an oxide semiconductor is formed and a region where a Si device (Si transistor or Si photodiode) is formed. A layer 80 is provided.

Hydrogen in the insulating layer provided in the vicinity of the active regions of the transistors 31 and 32 terminates dangling bonds of silicon. Therefore, the hydrogen has an effect of improving the reliability of the transistor 31 and the transistor 32. On the other hand, hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer which is an active layer of the transistor 51a or the like becomes one of the factors for generating carriers in the oxide semiconductor layer. Therefore, the hydrogen may be a factor that decreases the reliability of the transistor 51a and the like. Therefore, in the case where one layer having a transistor using a silicon-based semiconductor material and the other layer having a transistor using an oxide semiconductor are stacked, the insulating layer 80 has a function of preventing hydrogen diffusion therebetween. Is preferably provided. The reliability of the transistors 31 and 32 can be improved by confining hydrogen in one layer by the insulating layer 80. In addition, since the diffusion of hydrogen from one layer to the other layer is suppressed, the reliability of the transistor 51a and the like can be improved.

As the insulating layer 80, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

Note that in the structure illustrated in FIG. 22A, a circuit (eg, a driver circuit) formed over the silicon substrate 30, the transistor 51a, and the photoelectric conversion element 60a can be formed to overlap each other. The degree of integration of pixels can be increased. That is, the resolution of the imaging device can be increased. For example, it is suitable for use in an imaging device having the number of pixels of 4k2k, 8k4k, or 16k8k. In other words, the transistor M3, the transistor M6, and the like included in the pixel 200 illustrated in FIGS. 3 and 4 are formed of Si transistors, and overlap with the transistor M2, the transistor M5, and the photoelectric conversion element PCL1 illustrated in FIGS. It can also be set as the structure which has these.

Further, the imaging device illustrated in FIG. 22A has a structure in which no photoelectric conversion element is provided in the silicon substrate 30. Therefore, an optical path to the photoelectric conversion element 60a can be secured without being affected by various transistors and wirings, and a pixel with a high aperture ratio can be formed.

The imaging device of one embodiment of the present invention can have a structure illustrated in FIG.

The imaging device illustrated in FIG. 24 is a modification of the imaging device illustrated in FIG. 22A, and illustrates an example in which a CMOS inverter is configured with an OS transistor and a Si transistor.

Here, the transistor 32 which is an Si transistor provided in the layer 1400 is a p-ch type, and the transistor 31 which is an OS transistor provided in the layer 1100 is an n-ch type. By providing only the p-ch type transistor on the silicon substrate 30, steps such as well formation and n-type impurity layer formation can be omitted.

24 shows an example in which a selenium-based material or the like is used for the photoelectric conversion element 60a, a configuration using a pin-type thin film photodiode may be used as in FIG.

In the imaging device illustrated in FIG. 24, the transistor 31 can be manufactured in the same process as the transistors 51a and 52a formed in the layer 1100. Therefore, the manufacturing process of the imaging device can be simplified.

In addition, as illustrated in FIG. 25, the imaging device of one embodiment of the present invention includes a pixel including a photodiode formed over a silicon substrate 36 and an OS transistor formed over the photodiode, and a circuit is formed. It is good also as a structure which bonded together the silicon substrate 30 made. With such a configuration, it is easy to improve the effective area of the photodiode formed on the silicon substrate 36. Further, a high-performance semiconductor device can be provided by highly integrating a circuit formed on the silicon substrate 30 with a miniaturized Si transistor.

As a modification of FIG. 25, a circuit may be configured by an OS transistor and a Si transistor as shown in FIGS. With such a configuration, it is easy to improve the effective area of the photodiode formed on the silicon substrate 36. Further, a high-performance semiconductor device can be provided by highly integrating a circuit formed on the silicon substrate 30 with a miniaturized Si transistor.

The configuration of FIG. 26 can form a non-volatile memory composed of an OS transistor and a Si transistor on a silicon substrate 30, and is effective in forming an image processing circuit or the like. In the case of the configuration of FIG. 26, a CMOS circuit can be configured by the OS transistor and the Si transistor on the silicon substrate 30. Since the OS transistor has an extremely low off-state current, a CMOS circuit with extremely small static leakage current can be formed.

The configuration of FIG. 27 can form a non-volatile memory composed of an OS transistor on the silicon substrate 36 and an Si transistor on the silicon substrate 30, and is effective in forming an image processing circuit or the like. In the case of the configuration shown in FIG. 27, a CMOS circuit can be configured by the OS transistor on the silicon substrate 36 and the Si transistor on the silicon substrate 30.

FIG. 28A is a cross-sectional view of an example of a mode in which a color filter or the like is added to the imaging device. The cross-sectional view shows a part of a region having a pixel circuit for three pixels. An insulating layer 2500 is formed over the layer 1200 where the photoelectric conversion element 60a is formed. The insulating layer 2500 can be formed using a silicon oxide film or the like that has high light-transmitting property with respect to visible light. Alternatively, a silicon nitride film may be stacked as the passivation film. Alternatively, a dielectric film such as hafnium oxide may be stacked as the antireflection film.

A light shielding layer 2510 may be formed over the insulating layer 2500. The light shielding layer 2510 has a function of preventing color mixture of light passing through the upper color filter. The light-shielding layer 2510 can have a structure in which a metal layer such as aluminum or tungsten, or a dielectric film having a function as an antireflection film is stacked with the metal layer.

An organic resin layer 2520 can be provided as a planarization film over the insulating layer 2500 and the light-blocking layer 2510. In addition, a color filter 2530 (a color filter 2530a, a color filter 2530b, and a color filter 2530c) is formed for each pixel. For example, colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to the color filters 2530a, 2530b, and 2530c. Thus, a color image can be obtained.

An insulating layer 2560 having a light-transmitting property and the like can be provided over the color filter 2530.

As shown in FIG. 28B, an optical conversion layer 2550 may be used instead of the color filter 2530. With such a configuration, an imaging device capable of obtaining images in various wavelength regions can be obtained.

For example, when a filter that blocks light having a wavelength shorter than or equal to that of visible light is used for the optical conversion layer 2550, an infrared imaging device can be obtained. If a filter that blocks light having a wavelength of near infrared or shorter is used for the optical conversion layer 2550, a far infrared imaging device can be obtained. When a filter that blocks light having a wavelength longer than or equal to that of visible light is used for the optical conversion layer 2550, an ultraviolet imaging device can be obtained.

In addition, when a scintillator is used for the optical conversion layer 2550, an imaging device that can be used for an X-ray imaging device or the like to obtain an image that visualizes the intensity of radiation can be obtained. When radiation such as X-rays transmitted through the subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. And the image data is acquired by detecting the said light with the photoelectric conversion element 60a. Further, the imaging device having the configuration may be used for a radiation detector or the like.

The scintillator is made of a substance that absorbs energy and emits visible light or ultraviolet light when irradiated with radiation such as X-rays or gamma rays, or a material containing the substance. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO, etc. Materials and materials in which they are dispersed in resins and ceramics are known.

Note that in the photoelectric conversion element 60a using a selenium-based material, radiation such as X-rays can be directly converted into electric charge, so that a scintillator can be omitted.

A microlens array 2540 may be provided over the color filter 2530a, the color filter 2530b, and the color filter 2530c. Light passing through the individual lenses of the microlens array 2540 passes through the color filter directly below and is irradiated onto the photoelectric conversion element 60a. Note that a region other than the layer 1200 illustrated in FIGS. 28A, 28 </ b> B, and 28 </ b> C is a layer 1600.

A specific configuration of the imaging device illustrated in FIG. 28C is as illustrated in FIG. 29 when the imaging device illustrated in FIG. Further, when the imaging apparatus shown in FIG. 21 is taken as an example, it is as shown in FIG.

The imaging device of one embodiment of the present invention may be combined with a diffraction grating 1500 as illustrated in FIGS. An image of the subject (diffraction image) through the diffraction grating 1500 can be taken into a pixel, and an input image (image of the subject) can be configured by a calculation process from a captured image at the pixel. Further, the use of the diffraction grating 1500 instead of the lens can reduce the cost of the imaging device.

The diffraction grating 1500 can be formed using a light-transmitting material. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. Alternatively, a stack of the inorganic insulating film and the organic insulating film may be used.

The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. Alternatively, it can be formed using a lithography process and an etching process. It can also be formed using nanoimprint lithography or laser scribing.

Note that an interval X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be 1 mm or less, preferably 100 μm or less. Note that the interval may be a space, or a light-transmitting material may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a rare gas can be contained in the interval. Alternatively, an acrylic resin, an epoxy resin, a polyimide resin, or the like may be provided at the interval. Alternatively, a liquid such as silicone oil may be provided. Even when the microlens array 2540 is not provided, an interval X may be provided between the color filter 2530 and the diffraction grating 1500.

FIG. 33 is a cross-sectional view showing the positional relationship between the circuit 10, the circuit 20, and the light shielding layer 15. As illustrated, the light shielding layer 2510 can be used as the light shielding layer 15 by covering the circuit 20 with the light shielding layer 2510. Alternatively, as shown in FIG. 34A, a metal layer, a black resin, or the like may be provided as the light shielding layer 15 above the microlens array 2540. Alternatively, as illustrated in FIG. 34B, a structure in which color filters of different colors are superimposed on the circuit 20 may be provided as the light shielding layer 15. Note that the configurations shown in FIGS. 33, 34A, and 34B may be arbitrarily combined.

Further, the imaging device may be curved as shown in FIGS. 35A1 and 35B1. FIG. 35A1 illustrates a state where the imaging device is curved in the direction of dashed-two dotted line X1-X2. FIG. 35A2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X1-X2 in FIG. FIG. 35A3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y1-Y2 in FIG.

FIG. 35B1 shows a state in which the imaging device is curved in the direction of a two-dot chain line X3-X4 in the same figure and in the direction of a two-dot chain line Y3-Y4 in the same figure. FIG. 35B2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X3-X4 in FIG. FIG. 35B3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y3-Y4 in FIG.

By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for aberration correction can be reduced, it is possible to easily reduce the size and weight of a semiconductor device using an imaging device. In addition, the quality of the captured image can be improved.

Note that one embodiment of the present invention is described in this embodiment. Alternatively, in another embodiment, one embodiment of the present invention will be described. Note that one embodiment of the present invention is not limited thereto. That is, in this embodiment and other embodiments, various aspects of the invention are described; therefore, one embodiment of the present invention is not limited to a particular aspect. For example, although an example in which the present invention is applied to an imaging device is shown as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, one embodiment of the present invention may not be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, although an example in which a channel formation region, a source / drain region, and the like of a transistor include an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like may include various semiconductors. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, and the like can be formed using, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, a variety of transistors, channel formation regions of the transistors, source and drain regions of the transistors, and the like of the transistor may not include an oxide semiconductor. Good.

(Embodiment 2)
In this embodiment, a transistor including an oxide semiconductor that can be used for one embodiment of the present invention will be described with reference to drawings.

36A and 36B are a top view and a cross-sectional view of a transistor 101 that can be used in one embodiment of the present invention. 36A is a top view, and a cross section in the direction of dashed-dotted line B1-B2 in FIG. 36A corresponds to FIG. A cross section in the direction of dashed-dotted line B3-B4 in FIG. 36A corresponds to FIG. The direction of the alternate long and short dash line B1-B2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line B3-B4 may be referred to as a channel width direction.

The transistor 101 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, conductive layers 140 and 150 that are electrically connected to the oxide semiconductor layer 130, and the oxide semiconductor layer 130. , Insulating layer 160 in contact with conductive layer 140 and conductive layer 150, conductive layer 170 in contact with insulating layer 160, insulating layer 175 in contact with conductive layer 140, conductive layer 150, insulating layer 160, and conductive layer 170, and insulating layer 175 And an insulating layer 180 in contact with. Further, a function as a planarizing film may be added to the insulating layer 180 as necessary.

Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer.

A region 231 illustrated in FIG. 36B can function as a source region, a region 232 can function as a drain region, and a region 233 can function as a channel formation region. The region 231 and the region 232 are in contact with the conductive layer 140 and the conductive layer 150, respectively. For example, when a conductive material that easily bonds to oxygen is used as the conductive layer 140 and the conductive layer 150, the resistance of the region 231 and the region 232 can be reduced. it can.

Specifically, when the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150, oxygen vacancies are generated in the oxide semiconductor layer 130, and the oxygen vacancies remain in the oxide semiconductor layer 130 or from the outside. By the interaction with the diffusing hydrogen, the region 231 and the region 232 are low-resistance n-type.

In addition, although the example in which the conductive layer 170 is formed of two layers of the conductive layer 171 and the conductive layer 172 is illustrated, it may be a single layer or a stack of three or more layers. This structure can also be applied to other transistors described in this embodiment.

Moreover, although the example in which the conductive layer 140 and the conductive layer 150 are formed as a single layer is illustrated, a stack of two or more layers may be used. This structure can also be applied to other transistors described in this embodiment.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 36C is a top view of the transistor 102, and a cross section in the direction of dashed-dotted line C1-C2 in FIG. 36C corresponds to FIG. A cross section in the direction of dashed-dotted line C3-C4 in FIG. 36C corresponds to FIG. Further, the direction of the alternate long and short dash line C1-C2 may be referred to as a channel length direction and the direction of the alternate long and short dash line C3-C4 may be referred to as a channel width direction.

The transistor 102 has a structure similar to that of the transistor 101 except that an end portion of the insulating layer 160 functioning as a gate insulating film does not coincide with an end portion of the conductive layer 170 functioning as a gate electrode layer. The structure of the transistor 102 is characterized in that since the conductive layer 140 and the conductive layer 150 are widely covered with the insulating layer 160, the resistance between the conductive layer 140 and the conductive layer 150 and the conductive layer 170 is high and the gate leakage current is small. have.

The transistors 101 and 102 have a top-gate structure having a region where the conductive layer 170 overlaps with the conductive layer 140 and the conductive layer 150. The width of the region in the channel length direction is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since an offset region is not formed in the oxide semiconductor layer 130, a transistor with high on-state current can be easily formed.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. 36E is a top view of the transistor 103, and a cross section in the direction of dashed-dotted line D1-D2 in FIG. 36E corresponds to FIG. A cross section in the direction of dashed-dotted line D3-D4 in FIG. 36E corresponds to FIG. The direction of the alternate long and short dash line D1-D2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line D3-D4 may be referred to as a channel width direction.

The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, and an oxide semiconductor. The insulating layer 175 covering the layer 130, the insulating layer 160, and the conductive layer 170, the insulating layer 180 in contact with the insulating layer 175, and the opening provided in the insulating layer 175 and the insulating layer 180 are electrically connected to the oxide semiconductor layer 130. A conductive layer 140 and a conductive layer 150 to be connected are provided. Further, an insulating layer 180, a conductive layer 140, and an insulating layer (planarization film) in contact with the conductive layer 150 may be included as necessary.

Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer.

A region 231 illustrated in FIG. 36F can function as a source region, a region 232 can function as a drain region, and a region 233 can function as a channel formation region. The region 231 and the region 232 are in contact with the insulating layer 175. For example, when an insulating material containing hydrogen is used for the insulating layer 175, the resistance of the region 231 and the region 232 can be reduced.

Specifically, the region 231 and the region 232 are interacted with oxygen vacancies generated in the region 231 and the region 232 by the process until the insulating layer 175 is formed and hydrogen diffused from the insulating layer 175 to the region 231 and the region 232. Becomes a low-resistance n-type. Note that as the insulating material containing hydrogen, for example, silicon nitride, aluminum nitride, or the like can be used.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37A is a top view of the transistor 104, and a cross section in the direction of dashed-dotted line E1-E2 in FIG. 37A corresponds to FIG. A cross section in the direction of dashed-dotted line E3-E4 in FIG. 37A corresponds to FIG. The direction of the alternate long and short dash line E1-E2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line E3-E4 may be referred to as a channel width direction.

The transistor 104 has a structure similar to that of the transistor 103 except that the conductive layer 140 and the conductive layer 150 are in contact with each other so as to cover an end portion of the oxide semiconductor layer 130.

Further, the region 331 and the region 334 illustrated in FIG. 37B can function as a source region, the region 332 and the region 335 can function as a drain region, and the region 333 can function as a channel formation region.

The regions 331 and 332 can have low resistance as in the regions 231 and 232 in the transistor 101.

Further, the resistance of the region 334 and the region 335 can be reduced similarly to the region 231 and the region 232 in the transistor 103. Note that when the widths of the region 334 and the region 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-state current is not significantly reduced due to the contribution of the gate electric field. Therefore, the resistance of the region 334 and the region 335 may not be reduced.

The transistor 103 and the transistor 104 have a self-alignment structure in which the conductive layer 170 does not overlap with the conductive layer 140 and the conductive layer 150. A transistor having a self-aligned structure is suitable for high-speed operation because the parasitic capacitance between the gate electrode layer, the source electrode layer, and the drain electrode layer is extremely small.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37C is a top view of the transistor 105, and a cross section in the direction of dashed-dotted line F1-F2 in FIG. 37C corresponds to FIG. A cross section in the direction of dashed-dotted line F3-F4 in FIG. 37C corresponds to FIG. The direction of the alternate long and short dash line F1-F2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line F3-F4 may be referred to as a channel width direction.

The transistor 105 includes the insulating layer 120 in contact with the substrate 115, the oxide semiconductor layer 130 in contact with the insulating layer 120, the conductive layers 141 and 151 electrically connected to the oxide semiconductor layer 130, and the oxide semiconductor layer 130. , Conductive layer 141, insulating layer 160 in contact with conductive layer 151, conductive layer 170 in contact with insulating layer 160, oxide semiconductor layer 130, conductive layer 141, conductive layer 151, insulating layer 160, and insulating layer in contact with conductive layer 170 175, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 142 and a conductive layer 152 that are electrically connected to the conductive layer 141 and the conductive layer 151 through openings provided in the insulating layer 175 and the insulating layer 180, respectively. . Further, an insulating layer 180, a conductive layer 142, an insulating layer in contact with the conductive layer 152, or the like may be provided as necessary.

Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are not in contact with the side surfaces.

The transistor 105 is electrically connected to the conductive layer 141 and the conductive layer 151 through a point having the conductive layer 141 and the conductive layer 151, a point having an opening provided in the insulating layer 175 and the insulating layer 180, and the opening. The transistor 101 has the same structure as the transistor 101 except that the conductive layer 142 and the conductive layer 152 are provided. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can function as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) can function as a drain electrode layer.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37E is a top view of the transistor 106, and a cross section in the direction of dashed-dotted line G1-G2 in FIG. 37E corresponds to FIG. A cross section in the direction of dashed-dotted line G3-G4 in FIG. 37A corresponds to FIG. The direction of the alternate long and short dash line G1-G2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line G3-G4 may be referred to as a channel width direction.

The transistor 106 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, conductive layers 141 and 151 that are electrically connected to the oxide semiconductor layer 130, and the oxide semiconductor layer 130. The insulating layer 160 in contact with the insulating layer 160, the conductive layer 170 in contact with the insulating layer 160, the insulating layer 120, the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, the insulating layer 175 in contact with the conductive layer 170, and the insulating layer. The insulating layer 180 is in contact with the layer 175, and the conductive layer 142 and the conductive layer 152 are electrically connected to the conductive layer 141 and the conductive layer 151 through openings provided in the insulating layer 175 and the insulating layer 180, respectively. In addition, an insulating layer 180, a conductive layer 142, and an insulating layer (planarization film) in contact with the conductive layer 152 may be provided as necessary.

Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are not in contact with the side surfaces.

The transistor 106 has a structure similar to that of the transistor 103 except that the transistor 106 includes a conductive layer 141 and a conductive layer 151. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can function as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) can function as a drain electrode layer.

In the structure of the transistor 105 and the transistor 106, since the conductive layer 140 and the conductive layer 150 are not in contact with the insulating layer 120, oxygen in the insulating layer 120 is less likely to be taken away by the conductive layer 140 and the conductive layer 150. Oxygen can be easily supplied from 120 into the oxide semiconductor layer 130.

Note that an impurity for forming an oxygen vacancy and increasing conductivity may be added to the region 231 and the region 232 in the transistor 103 and the region 334 and the region 335 in the transistor 104 and the transistor 106. Examples of impurities that form oxygen vacancies in the oxide semiconductor layer include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, One or more selected from any of carbon and carbon can be used. As a method for adding the impurity, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

When the above element is added to the oxide semiconductor layer as the impurity element, the bond between the metal element and oxygen in the oxide semiconductor layer is cut, so that an oxygen vacancy is formed. The conductivity of the oxide semiconductor layer can be increased by the interaction between oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining in the oxide semiconductor layer or added later.

Note that when hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by addition of an impurity element, hydrogen enters the oxygen vacancy site and a donor level is formed in the vicinity of the conduction band. As a result, an oxide conductor can be formed. Here, a conductive oxide semiconductor is referred to as an oxide conductor. Note that the oxide conductor has a light-transmitting property similarly to the oxide semiconductor.

An oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level match or substantially match. Therefore, the contact between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer is ohmic contact, and the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer are in contact with each other. Contact resistance can be reduced.

In addition, a transistor that can be used in one embodiment of the present invention is a cross-sectional view in the channel length direction illustrated in FIGS. 39A, 39B, 39C, 13D, 9E, and 9F, and A conductive layer 173 may be provided between the oxide semiconductor layer 130 and the substrate 115 as in the cross-sectional views in the channel width direction shown in FIGS. By using the conductive layer as the second gate electrode layer (back gate), the on-state current can be increased and the threshold voltage can be controlled. Note that in the cross-sectional views illustrated in FIGS. 39A to 39F, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130 in the cross-sectional views illustrated in FIGS. Good. Further, the width of the conductive layer 173 may be shorter than the width of the conductive layer 170.

In order to increase the on-state current, for example, the conductive layer 170 and the conductive layer 173 may have the same potential and may be driven as a double gate transistor. In order to control the threshold voltage, a constant potential different from that of the conductive layer 170 may be supplied to the conductive layer 173. In order to set the conductive layer 170 and the conductive layer 173 to the same potential, for example, as illustrated in FIG. 38D, the conductive layer 170 and the conductive layer 173 may be electrically connected to each other through a contact hole.

36 and 37, the example in which the oxide semiconductor layer 130 is a single layer is illustrated; however, the oxide semiconductor layer 130 may be a stacked layer. The oxide semiconductor layer 130 of the transistors 101 to 106 can be replaced with the oxide semiconductor layer 130 illustrated in FIGS. 40B and 40C or FIGS.

40A is a top view of the oxide semiconductor layer 130, and FIGS. 40B and 40C are cross-sectional views of the oxide semiconductor layer 130 having a two-layer structure. 40B and 40C are cross-sectional views of the oxide semiconductor layer 130 having a three-layer structure.

As the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, oxide semiconductor layers having different compositions can be used.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. 41A is a top view of the transistor 107, and a cross section in the direction of dashed-dotted line H1-H2 in FIG. 41A corresponds to FIG. A cross section in the direction of dashed-dotted line H3-H4 in FIG. 41A corresponds to FIG. The direction of the alternate long and short dash line H1-H2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line H3-H4 may be referred to as a channel width direction.

The transistor 107 includes an insulating layer 120 in contact with the substrate 115, a stack including the oxide semiconductor layer 130a and the oxide semiconductor layer 130b in contact with the insulating layer 120, a conductive layer 140 and a conductive layer 150 electrically connected to the stack. The oxide semiconductor layer 130c in contact with the stack, the conductive layer 140 and the conductive layer 150, the insulating layer 160 in contact with the oxide semiconductor layer 130c, the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, The insulating layer 175 is in contact with the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, and the insulating layer 180 is in contact with the insulating layer 175. Further, a function as a planarizing film may be added to the insulating layer 180 as necessary.

In the transistor 107, the oxide semiconductor layer 130 has two layers (the oxide semiconductor layer 130a and the oxide semiconductor layer 130b) in the regions 231 and 232, and the oxide semiconductor layer 130 in the region 233 has three layers (oxide semiconductor). Layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c), and part of the oxide semiconductor layer (oxide semiconductor layer 130c) is provided between the conductive layer 140 and the conductive layer 150 and the insulating layer 160. The structure is similar to that of the transistor 101 except that it is interposed.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 41C is a top view of the transistor 108, and a cross section in the direction of dashed-dotted line I1-I2 in FIG. 41C corresponds to FIG. A cross section in the direction of dashed-dotted line I3-I4 in FIG. 41C corresponds to FIG. The direction of the alternate long and short dash line I1-I2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line I3-I4 may be referred to as a channel width direction.

The transistor 108 is different from the transistor 107 in that the end portions of the insulating layer 160 and the oxide semiconductor layer 130 c do not match the end portions of the conductive layer 170.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. 41E is a top view of the transistor 109, and a cross section in the direction of dashed-dotted line J1-J2 in FIG. 41E corresponds to FIG. A cross section in the direction of dashed-dotted line J3-J4 in FIG. 41E corresponds to FIG. Further, the direction of the alternate long and short dash line J1-J2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line J3-J4 may be referred to as a channel width direction.

The transistor 109 includes an insulating layer 120 in contact with the substrate 115, a stack including the oxide semiconductor layer 130a and the oxide semiconductor layer 130b in contact with the insulating layer 120, an oxide semiconductor layer 130c in contact with the stack, and an oxide semiconductor layer 130c. An insulating layer 160 in contact with the insulating layer 160, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the stacked layer, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, The conductive layer 140 and the conductive layer 150 are electrically connected to the stack through openings provided in the insulating layer 175 and the insulating layer 180. Further, an insulating layer 180, a conductive layer 140, and an insulating layer (planarization film) in contact with the conductive layer 150 may be included as necessary.

The transistor 109 includes two oxide semiconductor layers 130 (an oxide semiconductor layer 130a and an oxide semiconductor layer 130b) in the regions 231 and 232, and three oxide semiconductor layers 130 (an oxide semiconductor layer) in the region 233. The transistor 103 has a structure similar to that of the transistor 103 except that it is a layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c).

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. 42A is a top view of the transistor 110, and a cross section in the direction of dashed-dotted line K1-K2 in FIG. 42A corresponds to FIG. A cross section in the direction of dashed-dotted line K3-K4 in FIG. 42A corresponds to FIG. Further, the direction of the alternate long and short dash line K1-K2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line K3-K4 may be referred to as a channel width direction.

The transistor 110 includes two oxide semiconductor layers 130 (an oxide semiconductor layer 130a and an oxide semiconductor layer 130b) in the region 331 and the region 332, and three oxide semiconductor layers 130 (an oxide semiconductor layer in the region 333). The transistor 104 has the same structure as the transistor 104 except that the transistor 130 a, the oxide semiconductor layer 130 b, and the oxide semiconductor layer 130 c).

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. 42C is a top view of the transistor 111, and a cross section in the direction of dashed-dotted line K1-K2 in FIG. 42C corresponds to FIG. A cross section in the direction of dashed-dotted line K3-K4 in FIG. 42C corresponds to FIG. Further, the direction of the alternate long and short dash line K1-K2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line K3-K4 may be referred to as a channel width direction.

The transistor 111 includes an insulating layer 120 in contact with the substrate 115, a stack including the oxide semiconductor layer 130a and the oxide semiconductor layer 130b in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 electrically connected to the stack. The oxide semiconductor layer 130c in contact with the stacked layer, the conductive layer 141, and the conductive layer 151, the insulating layer 160 in contact with the oxide semiconductor layer 130c, the conductive layer 170 in contact with the insulating layer 160, the stacked layer, the conductive layer 141, and the conductive layer The insulating layer 175 in contact with the layer 151, the oxide semiconductor layer 130 c, the insulating layer 160, and the conductive layer 170, the insulating layer 180 in contact with the insulating layer 175, and the conductive layer 141 through openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the conductive layer 151 and the conductive layer 151, respectively. In addition, an insulating layer 180, a conductive layer 142, and an insulating layer (planarization film) in contact with the conductive layer 152 may be provided as necessary.

In the transistor 111, the oxide semiconductor layer 130 has two layers (the oxide semiconductor layer 130a and the oxide semiconductor layer 130b) in the region 231 and the region 232, and the oxide semiconductor layer 130 has three layers (the oxide semiconductor layer in the region 233). A layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c), and part of the oxide semiconductor layer (the oxide semiconductor layer 130c) is provided between the conductive layer 141 and the conductive layer 151 and the insulating layer 160. The structure is similar to that of the transistor 105 except that it is interposed.

A transistor that can be used in one embodiment of the present invention may have a structure illustrated in FIGS. 42E is a top view of the transistor 112, and a cross section in the direction of dashed-dotted line M1-M2 in FIG. 42E corresponds to FIG. A cross section in the direction of dashed-dotted line M3-M4 in FIG. The direction of the alternate long and short dash line M1-M2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line M3-M4 may be referred to as a channel width direction.

The transistor 112 includes two oxide semiconductor layers 130 (an oxide semiconductor layer 130a and an oxide semiconductor layer 130b) in the region 331, the region 332, the region 334, and the region 335, and the oxide semiconductor layer 130 in the region 333. The transistor has a structure similar to that of the transistor 106 except that the transistor has a three-layer structure (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c).

A transistor that can be used in one embodiment of the present invention includes cross-sectional views in the channel length direction illustrated in FIGS. 44A, 44B, C, D, E, and F, and As illustrated in cross-sectional views in the channel width direction illustrated in FIGS. 43C and 43D, a conductive layer 173 may be provided between the oxide semiconductor layer 130 and the substrate 115. By using the conductive layer as the second gate electrode layer (back gate), the on-state current can be further increased and the threshold voltage can be controlled. Note that in the cross-sectional views illustrated in FIGS. 44A, 44B, C, D, E, and F, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Good. Further, the width of the conductive layer 173 may be shorter than the width of the conductive layer 170.

A transistor that can be used in one embodiment of the present invention can have a structure illustrated in FIGS. 45A is a top view, and FIG. 45B is a cross-sectional view corresponding to the dashed-dotted line N1-N2 and the dashed-dotted line N3-N4 shown in FIG. 45A. Note that in the top view of FIG. 45A, some elements are omitted for clarity.

A transistor 113 illustrated in FIGS. 45A and 45B includes a substrate 115, an insulating layer 120 over the substrate 115, and an oxide semiconductor layer 130 over the insulating layer 120 (an oxide semiconductor layer 330a and an oxide semiconductor). Layer 330b, oxide semiconductor layer 330c), conductive layer 140 and conductive layer 150 which are in contact with and spaced apart from oxide semiconductor layer 330, insulating layer 160 in contact with oxide semiconductor layer 130c, and insulating layer 160 A conductive layer 170 in contact with the conductive layer 170. Note that the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170 are provided in openings that reach the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the insulating layer 180 provided in the insulating layer 190 over the transistor 113. ing.

The structure of the transistor 113 can reduce parasitic capacitance because there is less region where the conductor serving as the source electrode or the drain electrode overlaps with the conductor serving as the gate electrode as compared with the structures of the other transistors described above. Therefore, the transistor 113 is suitable as an element of a circuit that requires high-speed operation. Note that although the top surface of the transistor 113 is preferably planarized by a CMP (Chemical Mechanical Polishing) method or the like as illustrated in FIG. 45B, a structure without planarization may be employed.

A conductive layer 140 (source electrode layer) and a conductive layer 150 (drain electrode layer) in a transistor that can be used in one embodiment of the present invention are top views (oxide semiconductors) illustrated in FIGS. The width (W _SD ) of the conductive layer 140 and the conductive layer 150 may be formed longer than the width (W _OS ) of the oxide semiconductor layer as in the case of the layer 130, the conductive layer 140, and the conductive layer 150). However, it may be formed short. When W _OS ≧ W _SD (W _SD is equal to or lower than W _OS ), the gate electric field is easily applied to the entire oxide semiconductor layer 130, so that the electrical characteristics of the transistor can be improved. As shown in FIG. 46C, the conductive layer 140 and the conductive layer 150 may be formed only in a region overlapping with the oxide semiconductor layer 130.

In any of the structures of the transistors (the transistors 101 to 113) that can be used in one embodiment of the present invention, the conductive layer 170 that is a gate electrode layer is provided with the oxide semiconductor through the insulating layer 160 that is a gate insulating film. The channel width direction of the layer 130 is electrically surrounded, and the on-current is increased. Such a transistor structure is called a surround channel (s-channel) structure.

In the transistor including the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, and the transistor including the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, the oxide semiconductor layer 130 is formed. A current can be passed through the oxide semiconductor layer 130b by appropriately selecting a material of three layers or three layers. When a current flows through the oxide semiconductor layer 130b, it is difficult to be affected by interface scattering and a high on-state current can be obtained. Therefore, the on-state current may be improved by increasing the thickness of the oxide semiconductor layer 130b.

By using the transistor having the above structure, favorable electrical characteristics can be imparted to the semiconductor device.

(Embodiment 3)
In this embodiment, components of the transistor described in Embodiment 2 will be described in detail.

<About substrate>
As the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is insulated, or the like can be used. Alternatively, a silicon substrate over which a transistor is formed and a substrate in which an insulating layer, a wiring, a conductor functioning as a contact plug, or the like is formed over the silicon substrate can be used. Note that in the case where only a p-ch transistor is formed on a silicon substrate, it is preferable to use a silicon substrate having n ⁻ type conductivity. Alternatively, an SOI substrate having an n ^- type or i-type silicon layer may be used. In addition, the plane orientation of the surface on which the transistor is formed in the silicon substrate is preferably a (110) plane. By forming a p-ch transistor on the (110) plane, mobility can be increased.

<Insulating layer>
The insulating layer 120 can serve to prevent diffusion of impurities from elements included in the substrate 115 and can supply oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing oxygen larger than the stoichiometric composition. For example, a film having an oxygen release amount of 1.0 × 10 ¹⁹ atoms / cm ³ or more in terms of oxygen atoms by a temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)) is used. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C. In the case where the substrate 115 is a substrate over which another device is formed, the insulating layer 120 also has a function as an interlayer insulating film. In that case, it is preferable to perform a planarization process by a CMP method or the like so that the surface becomes flat.

For example, the insulating layer 120 includes an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. A nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixed material thereof can be used. Alternatively, a laminate of the above materials may be used.

<About oxide semiconductor layers>
In this embodiment, the oxide semiconductor layer 130 included in the transistor mainly has a three-layer structure in which an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c are stacked in that order from the insulating layer 120 side. Will be explained.

Note that in the case where the oxide semiconductor layer 130 is a single layer, a layer corresponding to the oxide semiconductor layer 130b described in this embodiment may be used.

In the case where the oxide semiconductor layer 130 is a two-layer structure, a stack in which a layer corresponding to the oxide semiconductor layer 130a and a layer corresponding to the oxide semiconductor layer 130b described in this embodiment are stacked in this order from the insulating layer 120 side. May be used. In the case of this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b can be interchanged.

In the case where the oxide semiconductor layer 130 has four or more layers, for example, another oxide semiconductor layer is added to the oxide semiconductor layer 130 with a three-layer structure described in this embodiment. Can do.

As an example, for the oxide semiconductor layer 130b, an oxide semiconductor having a higher electron affinity (energy from the vacuum level to the lower end of the conduction band) than that of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is used. The electron affinity can be obtained as a value obtained by subtracting the energy difference (energy gap) between the lower end of the conduction band and the upper end of the valence band from the energy difference (ionization potential) between the vacuum level and the upper end of the valence band.

The oxide semiconductor layer 130a and the oxide semiconductor layer 130c include one or more metal elements included in the oxide semiconductor layer 130b. For example, the energy at the lower end of the conduction band is 0.05 eV, 0. The oxide semiconductor is preferably formed of an oxide semiconductor close to a vacuum level in a range of any one of 07 eV, 0.1 eV, and 0.15 eV and any of 2 eV, 1 eV, 0.5 eV, and 0.4 eV.

In such a structure, when an electric field is applied to the conductive layer 170, a channel is formed in the oxide semiconductor layer 130 b having the lowest energy at the lower end of the conduction band in the oxide semiconductor layer 130.

In addition, since the oxide semiconductor layer 130a includes one or more metal elements included in the oxide semiconductor layer 130b, the oxide semiconductor layer 130a is oxidized compared with the interface in the case where the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other. Interface states are unlikely to be formed at the interface between the physical semiconductor layer 130b and the oxide semiconductor layer 130a. Since the interface state may form a channel, the threshold voltage of the transistor may fluctuate. Therefore, by providing the oxide semiconductor layer 130a, variation in electrical characteristics such as threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

In addition, since the oxide semiconductor layer 130c includes one or more metal elements included in the oxide semiconductor layer 130b, an interface between the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) is in contact with the oxide semiconductor layer 130c. In comparison, carrier scattering hardly occurs at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c. Therefore, the field-effect mobility of the transistor can be increased by providing the oxide semiconductor layer 130c.

The oxide semiconductor layer 130a and the oxide semiconductor layer 130c include, for example, a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at a higher atomic ratio than the oxide semiconductor layer 130b. Can be used. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more. The above element is strongly bonded to oxygen and thus has a function of suppressing generation of oxygen vacancies in the oxide semiconductor layer. That is, oxygen vacancies are less likely to occur in the oxide semiconductor layer 130a and the oxide semiconductor layer 130c than in the oxide semiconductor layer 130b.

An oxide semiconductor that can be used as the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably contains at least In or Zn. Or it is preferable that both In and Zn are included. In addition, in order to reduce variation in electrical characteristics of the transistor including the oxide semiconductor, a stabilizer is preferably included together with the transistor.

Examples of the stabilizer include Ga, Sn, Hf, Al, and Zr. Other stabilizers include lanthanoids such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

For example, as an oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In -Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In -Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er -Zn oxide, In-Tm-Zn oxide, In- b-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn oxide, In—Sn—Hf—Zn oxide, or In—Hf—Al—Zn oxide can be used.

Note that here, for example, an In—Ga—Zn oxide means an oxide containing In, Ga, and Zn as its main components. Moreover, metal elements other than In, Ga, and Zn may be contained. In this specification, a film formed using an In—Ga—Zn oxide is also referred to as an IGZO film.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 and m is not an integer) may be used. Note that M represents one metal element or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 and n is an integer) may be used.

Note that the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c each include at least indium, zinc, and M (a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). ), The oxide semiconductor layer 130a is formed of In: M: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], and the oxide semiconductor layer 130b is formed of In: M: When Zn = x ₂ : y ₂ : z ₂ [atomic number ratio] and the oxide semiconductor layer 130c is In: M: Zn = x ₃ : y ₃ : z ₃ [atomic number ratio], y ₁ / x ₁ and It is preferable that y ₃ / x ₃ is larger than y ₂ / x ₂ . y ₁ / x ₁ and y ₃ / x ₃ are 1.5 times or more, preferably 2 times or more, more preferably 3 times or more than y ₂ / x ₂ . In this case, in the oxide semiconductor layer 130b, the y ₂ is at x ₂ or more electrical characteristics of the transistor can be stabilized. However, when y ₂ is 3 times or more of x ₂ , the field-effect mobility of the transistor is lowered. Therefore, y ₂ is preferably less than 3 times x ₂ .

In the case where Zn and O are excluded from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, the atomic ratio of In and M is preferably such that In is less than 50 atomic%, M is greater than 50 atomic%, and more preferably, In is 25 atomic%. % And M is 75 atomic% or more. The atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 130b is preferably that In is 25 atomic% or more, M is less than 75 atomic%, more preferably In is 34 atomic% or more, and M is 66 atomic%. %.

In addition, the oxide semiconductor layer 130b preferably contains more indium than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c. In oxide semiconductors, s orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the In content, more s orbitals overlap, so an oxide having a composition with more In than M is In. Is higher in mobility than an oxide having a composition equal to or less than that of M. Therefore, by using an oxide containing a large amount of indium for the oxide semiconductor layer 130b, a transistor with high field-effect mobility can be realized.

The thickness of the oxide semiconductor layer 130a is 3 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm. The thickness of the oxide semiconductor layer 130b is 3 nm to 200 nm, preferably 5 nm to 150 nm, more preferably 10 nm to 100 nm. The thickness of the oxide semiconductor layer 130c is 1 nm to 50 nm, preferably 2 nm to 30 nm, more preferably 3 nm to 15 nm. The oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 130c.

Note that in order to impart stable electric characteristics to the transistor including the oxide semiconductor layer as a channel, the impurity concentration in the oxide semiconductor layer is reduced so that the oxide semiconductor layer is intrinsic or substantially intrinsic. It is valid. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁵ / cm ^3, less than 1 × 10 ¹³ / cm ³ , and 8 × 10 ¹¹ / cm ^3. Or less than 1 × 10 ⁸ / cm ³ and 1 × 10 ⁻⁹ / cm ³ or more.

In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than the main component are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Silicon contributes to formation of impurity levels in the oxide semiconductor layer. The impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, or at each interface.

In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the silicon concentration estimated by SIMS (Secondary Ion Mass Spectrometry) is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm 3. Control is performed so as to have a region of less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . Further, the hydrogen concentration is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and further preferably 5 × 10 ¹⁸ atoms / cm ³ or less. Control is performed so as to have a region of cm ³ or less. The nitrogen concentration is, for example, less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less at a certain depth of the oxide semiconductor layer or in a region where the oxide semiconductor layer is present. More preferably, it is 1 × 10 ¹⁸ atoms / cm ³ or less, and further preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. In order not to lower the crystallinity of the oxide semiconductor layer, for example, the silicon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably 1 × 10 ¹⁸ atoms / cm 3. Control to have an area that is less than ³ . In addition, the carbon concentration is controlled to have a region that is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

In addition, the off-state current of the transistor in which the oxide semiconductor film purified as described above is used for a channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current per channel width of the transistor can be reduced to several yA / μm to several zA / μm. It becomes possible.

Note that since an insulating film containing silicon is often used as a gate insulating film of a transistor, a region serving as a channel of an oxide semiconductor layer is in contact with the gate insulating film as in the transistor of one embodiment of the present invention for the above reason. It can be said that the structure which does not do is preferable. In addition, in the case where a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface, and the field-effect mobility of the transistor may be reduced. From this point of view, it can be said that it is preferable to separate a region to be a channel of the oxide semiconductor layer from the gate insulating film.

Therefore, when the oxide semiconductor layer 130 has a stacked structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b, and a high electric field effect can be obtained. A transistor having mobility and stable electric characteristics can be formed.

In the band structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, the energy at the lower end of the conduction band changes continuously. This can also be understood from the point that oxygen is easily diffused to each other when the compositions of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are approximated. Therefore, although the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are stacked bodies having different compositions, it can also be said that they are physically continuous. The interface of is represented by a dotted line.

The oxide semiconductor layer 130 laminated with the main component in common is not simply laminated, but a continuous junction (here, in particular, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the layers). (U Shape Well)) is formed. That is, the stacked structure is formed so that there is no impurity that forms a defect level such as a trap center or a recombination center at the interface of each layer. If impurities are mixed between the stacked oxide semiconductor layers, the continuity of the energy band is lost, and carriers disappear at the interface by trapping or recombination.

For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c include In: Ga: Zn = 1: 3: 2, 1: 3: 3, 1: 3: 4, 1: 3: 6, and 1: 4: 5. In-Ga-Zn oxide such as 1: 6: 4 or 1: 9: 6 (atomic ratio) can be used. The oxide semiconductor layer 130b includes In: Ga: Zn = 1: 1: 1, 2: 1: 3, 5: 5: 6, or 3: 1: 2 (atomic ratio). Zn oxide or the like can be used. Note that the atomic ratios of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c each include a variation of plus or minus 40% of the above atomic ratio as an error.

The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and a channel is formed in the oxide semiconductor layer 130b. Note that the oxide semiconductor layer 130 can also be referred to as a U-shaped well because energy at the bottom of the conduction band continuously changes. A channel formed in such a configuration can also be referred to as a buried channel.

In addition, trap levels due to impurities and defects can be formed in the vicinity of the interface between the oxide semiconductor layer 130a and the oxide semiconductor layer 130c and an insulating layer such as a silicon oxide film. With the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, the oxide semiconductor layer 130b and the trap level can be separated from each other.

However, when the difference between the energy at the lower end of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c and the energy at the lower end of the conduction band of the oxide semiconductor layer 130b is small, electrons in the oxide semiconductor layer 130b May reach the trap level. When electrons are trapped in the trap level, negative charges are generated at the interface of the insulating layer, and the threshold voltage of the transistor is shifted in the positive direction.

The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably include a crystal part. In particular, stable electrical characteristics can be imparted to the transistor by using crystals oriented in the c-axis. In addition, crystals oriented in the c-axis are resistant to distortion, and the reliability of a semiconductor device using a flexible substrate can be improved.

<About source electrode layer and drain electrode layer>
Examples of the conductive layer 140 that functions as the source electrode layer and the conductive layer 150 that functions as the drain electrode layer include Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and the metal material. A single layer or a stack of materials selected from these alloys can be used. Typically, it is more preferable to use W having a high melting point because Ti that easily binds to oxygen or a subsequent process temperature can be made relatively high. Moreover, you may use the lamination | stacking of alloys, such as low resistance Cu and Cu-Mn, and the said material. Note that in the transistors 105, 106, 111, and 112, for example, W can be used for the conductive layer 141 and the conductive layer 151, and a stacked film of Ti and Al can be used for the conductive layer 142 and the conductive layer 152.

The above material has a property of extracting oxygen from the oxide semiconductor film. Therefore, oxygen in the oxide semiconductor layer is released from part of the oxide semiconductor film in contact with the material, so that oxygen vacancies are formed. The region is remarkably n-type by combining the oxygen slightly contained in the film with the oxygen deficiency. Therefore, the n-type region can serve as the source or drain of the transistor.

In the case where W is used for the conductive layer 140 and the conductive layer 150, nitrogen may be doped. Doping nitrogen can moderately weaken the property of extracting oxygen and can prevent the n-type region from expanding to the channel region. Further, the conductive layer 140 and the conductive layer 150 are stacked with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are brought into contact with each other, so that the n-type region is prevented from expanding to the channel region. be able to. As the n-type semiconductor layer, an In—Ga—Zn oxide to which nitrogen is added, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like can be used.

<Gate insulation film>
The insulating layer 160 serving as a gate insulating film includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a stack of the above materials. Note that the insulating layer 160 may contain La, N, Zr, or the like as an impurity.

An example of a stacked structure of the insulating layer 160 will be described. The insulating layer 160 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide and aluminum oxide have a higher dielectric constant than silicon oxide and silicon oxynitride. Accordingly, since the thickness of the insulating layer 160 can be increased as compared with the case where silicon oxide is used, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are preferably formed using a film with a small amount of released nitrogen oxide. In the case where the insulating layer with a large amount of released nitrogen oxide is in contact with the oxide semiconductor, the level density of the nitrogen oxide may increase. For the insulating layer 120 and the insulating layer 160, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film with a small amount of released nitrogen oxides can be used.

Note that a silicon oxynitride film with a small amount of released nitrogen oxide is a film in which the amount of released ammonia is larger than the amount of released nitrogen oxide in the TDS method. Typically, the amount of released ammonia is 1 × 10 ^18. The number of pieces / cm ^{3 is} 5 × 10 ¹⁹ pieces / cm ³ or less. Note that the amount of ammonia released is the amount released by heat treatment at a film surface temperature of 50 ° C. to 650 ° C., preferably 50 ° C. to 550 ° C.

By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, a shift in threshold voltage of the transistor can be reduced and variation in electrical characteristics of the transistor can be reduced.

For the conductive layer 170 acting as the gate electrode layer, for example, a conductive film such as Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W is used. Can be used. Alternatively, an alloy of the above material or a conductive nitride of the above material may be used. Further, it may be a stack of a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials. Typically, tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, or the like can be used. Alternatively, a low resistance alloy such as Cu or Cu—Mn, or a laminate of the above material and an alloy such as Cu or Cu—Mn may be used. In this embodiment, the conductive layer 170 is formed using tantalum nitride for the conductive layer 171 and tungsten for the conductive layer 172.

As the insulating layer 175, a silicon nitride film containing aluminum, an aluminum nitride film, or the like can be used. In the transistor 103, the transistor 104, the transistor 106, the transistor 109, the transistor 110, and the transistor 112 described in Embodiment 2, a part of the oxide semiconductor layer is n-type by using an insulating film containing hydrogen as the insulating layer 175. Can be The nitride insulating film also has a function as a blocking film for moisture and the like, and can improve the reliability of the transistor.

As the insulating layer 175, an aluminum oxide film can be used. In particular, in the transistor 101, the transistor 102, the transistor 105, the transistor 107, the transistor 108, and the transistor 111 described in Embodiment 2, an aluminum oxide film is preferably used for the insulating layer 175. The aluminum oxide film has a high blocking effect that prevents the film from permeating both of impurities such as hydrogen and moisture and oxygen. Therefore, the aluminum oxide film prevents impurities such as hydrogen and moisture from entering the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and from the insulating layer 120 during and after the manufacturing process of the transistor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

In addition, an insulating layer 180 is preferably formed over the insulating layer 175. The insulating layer includes one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film can be used. The insulating layer may be a stack of the above materials.

Here, like the insulating layer 120, the insulating layer 180 preferably contains more oxygen than the stoichiometric composition. Since oxygen released from the insulating layer 180 can be diffused into the channel formation region of the oxide semiconductor layer 130 through the insulating layer 160, oxygen can be filled in oxygen vacancies formed in the channel formation region. . Therefore, stable electrical characteristics of the transistor can be obtained.

<About transistors>
Miniaturization of transistors is indispensable for high integration of semiconductor devices. On the other hand, it is known that the electrical characteristics of a transistor deteriorate due to the miniaturization of the transistor. In particular, when the channel width is reduced, the on-current is reduced.

In the transistors 107 to 112 of one embodiment of the present invention, the oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b where a channel is formed, and the channel formation layer and the gate insulating film are not in contact with each other. It has become. Therefore, carrier scattering generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the on-state current of the transistor can be increased.

In the transistor of one embodiment of the present invention, since the gate electrode layer (the conductive layer 170) is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 130 as described above, the oxide semiconductor layer In addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to 130. That is, the gate electric field is applied to the entire channel formation layer and the effective channel width is expanded, so that the on-current can be further increased.

In a transistor having two or three oxide semiconductor layers 130 in one embodiment of the present invention, an interface state is formed by forming the oxide semiconductor layer 130b in which a channel is formed over the oxide semiconductor layer 130a. It has the effect of making it difficult to do. In addition, in a transistor in which the oxide semiconductor layer 130 in one embodiment of the present invention has three layers, the effect of mixing impurities from above and below can be eliminated by forming the oxide semiconductor layer 130b in the middle of the three-layer structure. And so on. Therefore, in addition to improving the on-state current of the transistor described above, it is possible to stabilize the threshold voltage and reduce the S value (subthreshold value). Therefore, the current when the gate voltage VG is 0 V can be reduced, and the power consumption can be reduced. In addition, since the threshold voltage of the transistor is stabilized, long-term reliability of the semiconductor device can be improved. In addition, the transistor of one embodiment of the present invention can be said to be suitable for forming a highly integrated semiconductor device because deterioration in electrical characteristics due to miniaturization is suppressed.

<About the production method of each film>
Note that various films such as a metal film, a semiconductor film, and an inorganic insulating film described in this embodiment can be typically formed by a sputtering method or a plasma CVD method; however, other methods such as thermal CVD are used. You may form by a method. Examples of the thermal CVD method include a MOCVD (Metal Organic Chemical Deposition) method and an ALD (Atomic Layer Deposition) method.

The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma.

In the thermal CVD method, a source gas and an oxidant are simultaneously sent into a chamber, and the inside of the chamber is subjected to atmospheric pressure or reduced pressure. The film is formed by reacting in the vicinity of or on the substrate and depositing on the substrate. Also good.

In the ALD method, film formation is performed by setting the inside of a chamber to atmospheric pressure or reduced pressure, introducing and reacting a source gas for reaction into the chamber, and repeating this. An inert gas (such as argon or nitrogen) may be introduced as a carrier gas together with the source gas. For example, two or more kinds of source gases may be sequentially supplied to the chamber. At that time, an inert gas is introduced after the reaction of the first source gas so that a plurality of types of source gases are not mixed, and a second source gas is introduced. Alternatively, the second source gas may be introduced after the first source gas is exhausted by evacuation instead of introducing the inert gas. The first source gas is adsorbed and reacted on the surface of the substrate to form the first layer, and the second source gas introduced later is adsorbed and reacted to make the second layer the first layer. A thin film is formed by being laminated on top. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repeated gas introductions, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

A thermal CVD method such as an MOCVD method or an ALD method can form various films such as a metal film, a semiconductor film, and an inorganic insulating film disclosed in the embodiments described so far. For example, In—Ga—Zn In the case where a —O film is formed, trimethylindium (In (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ ), and dimethylzinc (Zn (CH ₃ ) ₂ ) can be used. Without being limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn (C ₂ H ₅ ) ₂ ) is used instead of dimethylzinc. You can also.

For example, when a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf [N (CH ₃ ) ₂ ] ₄ ) ) Or tetrakis (ethylmethylamide) hafnium) or the like, and two gases of ozone (O ₃ ) are used as an oxidizing agent.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a raw material gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA, Al (CH ₃ ) ₃ )) containing a solvent and an aluminum precursor is used. Two types of gas, H ₂ O, are used as the oxidizing agent. Other materials include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. React with things.

For example, when a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then WF ₆ gas and H ₂ gas. Are sequentially introduced to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a film formation apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced, and In— After forming an O layer, Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ and O ₃ gas are sequentially introduced to form a ZnO layer. Form. Note that the order of these layers is not limited to this example. A mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred.

Note that a facing target sputtering apparatus can be used for forming the oxide semiconductor layer. A film formation method using the facing target sputtering apparatus can also be referred to as VDSP (vapor deposition SP).

When the oxide semiconductor layer is formed using the facing target sputtering apparatus, plasma damage during the formation of the oxide semiconductor layer can be reduced. Therefore, oxygen vacancies in the film can be reduced. In addition, since an opposing target sputtering apparatus can be used to form a film at a low pressure, the impurity concentration (eg, hydrogen, rare gas (such as argon), or water) in the formed oxide semiconductor layer is reduced. Can be made.

(Embodiment 4)
The structure of an oxide semiconductor film that can be used for one embodiment of the present invention is described below.

In this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

<About CAAC-OS Film>
First, the CAAC-OS film is described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Confirming a plurality of crystal parts by observing a bright field image of a CAAC-OS film and a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope). Can do. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when a high-resolution TEM image of the plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film is unlikely to have electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, a transistor including a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

<About Microcrystalline Oxide Semiconductor Film>
Next, a microcrystalline oxide semiconductor film is described.

The microcrystalline oxide semiconductor film includes a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS film, spots distributed in a circumferential shape may be observed. Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

<About amorphous oxide semiconductor film>
Next, an amorphous oxide semiconductor film is described.

An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

In the amorphous oxide semiconductor film, a crystal part cannot be confirmed in a high-resolution TEM image.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

Note that the oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In the a-like OS film, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. In some cases, the a-like OS film is crystallized by a small amount of electron irradiation as observed by a TEM, and a crystal part is grown. On the other hand, in the case of a good-quality nc-OS film, crystallization due to a small amount of electron irradiation comparable to that observed by TEM is hardly observed.

Note that the crystal part size of the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. .
(Embodiment 5)

An imaging device according to one embodiment of the present invention is used in a camera module and can be mounted on various electronic devices. In this embodiment, an example of a camera module to which the imaging device described in the above embodiment is applied and an example of an electronic device in which the camera module is mounted will be described.

A camera module 800 illustrated in FIG. 47 includes a lens unit 801, an autofocus unit 802, a lid glass 803, a sensor cover 804, an imaging device 805, a substrate 806, and an FPC 807.

A camera module 800 shown in FIG. 47 includes a display device, a personal computer, and an image playback apparatus including a recording medium (typically a display that can play back a recording medium such as a DVD: Digital Versatile Disc and display the image. Device). In addition, as an electronic device to which the camera module can be applied, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a camera such as a digital still camera, a goggle type display (head mounted display), Examples include navigation systems, sound reproduction devices (car audio, digital audio player, etc.), copying machines, facsimile machines, printers, printer multifunction devices, automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 48A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, speakers 906, operation keys 907, a stylus 908, a camera module 8909, and the like. Note that although the portable game machine illustrated in FIG. 48A includes the two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto. The imaging device of one embodiment of the present invention can be used for the camera module 8909.

FIG. 48B illustrates a portable data terminal, which includes a first housing 911, a display portion 912, a camera module 8919, and the like. Information can be input and output by a touch panel function of the display portion 912. The imaging device of one embodiment of the present invention can be used for the camera module 8909.

FIG. 48C illustrates a wristwatch type information terminal, which includes a housing 931, a display portion 932, a wristband 933, a camera module 8939, and the like. The display unit 932 may be a touch panel. The imaging device of one embodiment of the present invention can be used for the camera module 8909.

FIG. 48D illustrates a monitoring camera, which includes a housing 951, a lens 952, a support portion 953, and the like. The imaging device of one embodiment of the present invention can be provided at a position where the lens 952 is focused.

FIG. 48E illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device of one embodiment of the present invention can be provided at a position where the lens 965 becomes a focal point.

FIG. 48F illustrates a video camera, which includes a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, and the like. The operation key 974 and the lens 975 are provided in the first housing 971, and the display portion 973 is provided in the second housing 972. The first housing 971 and the second housing 972 are connected by a connection portion 976, and the angle between the first housing 971 and the second housing 972 can be changed by the connection portion 976. is there. It is good also as a structure which switches the image | video in the display part 973 according to the angle between the 1st housing | casing 971 and the 2nd housing | casing 972 in the connection part 976. The imaging device of one embodiment of the present invention can be provided at the focal point of the lens 975.

(Additional notes regarding the description of this specification etc.)
The above embodiment and description of each component in the embodiment will be added below.

<Supplementary Note on One Aspect of the Invention described in Embodiment>
The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In addition, in the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined as appropriate.

Note that the content (may be a part of content) described in one embodiment is different from the content (may be a part of content) described in the embodiment and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

<Additional notes regarding the description explaining the drawings>
In this specification and the like, terms indicating arrangement such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between the components appropriately changes depending on the direction in which each component is drawn. Therefore, the phrase indicating the arrangement is not limited to the description described in the specification, and can be appropriately rephrased depending on the situation.

Further, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below, and is in direct contact with each other. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

Further, in the present specification and the like, in the block diagram, the constituent elements are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

In the drawings, some components may be omitted from the top view (also referred to as a plan view or a layout view) or a perspective view in order to clarify the drawing.

<Additional notes on paraphrased descriptions>
In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground voltage (ground voltage), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

<Notes on the definition of words>
In the following, the definition of the phrase that was desired to be mentioned in the above embodiment will be described.
<Off current>
In this specification, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off-state current of the transistor may depend on Vgs. Therefore, when there is Vgs at which the off-state current of the transistor is I or less, the off-state current of the transistor is sometimes I or less. The off-state current of the transistor is a value at which an off-state current when Vgs is a predetermined value, an off-current when Vgs is a value within a predetermined range, or an off-current with sufficiently reduced Vgs is obtained. Sometimes refers to off-state current.

As an example, the drain current when the threshold voltage Vth is 0.5 V and Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ^−13. Assume an n-channel transistor in which the drain current is 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and the drain current is 1 × 10 ⁻²² A when Vgs is −0.8 V. . Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

In this specification, the off-state current of a transistor having a channel width W may be expressed by a value per channel width W. Further, it may be expressed by a current value per predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be expressed as current / length (for example, A / μm).

The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature of 5 ° C. to 35 ° C.). May represent off-state current. Room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or a temperature at which the semiconductor device including the transistor is used (for example, 5 When the Vgs at which the off-state current of the transistor is equal to or lower than I is present at any one temperature of from 35 ° C. to 35 ° C., the off-state current of the transistor is sometimes equal to or lower than I.

The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-state current has an absolute value of Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, It may represent off current at 12V, 16V, or 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. When Vds is a predetermined value and there is Vgs where the off-state current of the transistor is I or less, the off-state current of the transistor is sometimes I or less. Here, the predetermined value is, for example, 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, This is the value of Vds that ensures the reliability of the included semiconductor device or the like, or the value of Vds used in the semiconductor device or the like that includes the transistor.

In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

In this specification, the term “leakage current” may be used to mean the same as off-state current.

In this specification, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

<< About the switch >>
In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source and the drain of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source and drain of the transistor can be regarded as being electrically cut off. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

An example of a mechanical switch is a switch using MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

<< About channel length >>
In this specification and the like, the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap with each other, or a channel is formed. This is the distance between the source and drain in the region.

Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

<< About channel width >>
In this specification and the like, the channel width refers to, for example, a source in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed And the length of the part where the drain faces.

Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW : Surrounded Channel Width) ”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

<< About Pixels >>
In this specification and the like, a pixel means, for example, one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and brightness is expressed by one color element. Therefore, at that time, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is an R pixel, a G pixel, and a B pixel. It is assumed to be composed of three pixels.

Note that the color elements are not limited to three colors and may be more than that, for example, RGBW (W is white), or RGB with yellow, cyan, and magenta added.

<< About display elements >>
In this specification and the like, a display element includes a display medium whose contrast, luminance, reflectance, transmittance, and the like change due to an electric action or a magnetic action. Examples of display elements include EL (electroluminescence) elements, LED chips (white LED chips, red LED chips, green LED chips, blue LED chips, etc.), transistors (transistors that emit light in response to current), electron-emitting devices, Display elements using carbon nanotubes, liquid crystal elements, electronic ink, electrowetting elements, electrophoretic elements, plasma display (PDP), display elements using MEMS (micro electro mechanical system) (for example, grating light valves) (GLV), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, shutter type MEMS table Element, MEMS display device employing optical interferometry, such as a piezoelectric ceramic display), a carbon nanotube, or the like quantum dots, there is. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper. An example of a display device using a quantum dot for each pixel is a quantum dot display. Note that the quantum dots may be provided not in the display element but in part of the backlight. By using quantum dots, display with high color purity can be performed. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced. In addition, when using an LED chip, you may arrange | position graphene or a graphite under the electrode and nitride semiconductor of an LED chip. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor, for example, an n-type GaN semiconductor layer having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor layer having a crystal or the like can be provided thereon to form an LED chip. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having a crystal. Note that the GaN semiconductor layer of the LED chip may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED chip can be formed by a sputtering method. In a display element using a MEMS (micro electro mechanical system), a space in which the display element is sealed (for example, an element substrate on which the display element is arranged, and an element substrate facing the element substrate) A desiccant may be disposed between the opposite substrate). By arranging the desiccant, it is possible to prevent the MEMS and the like from becoming difficult to move due to moisture or from being easily deteriorated.

<< About connection >>
In this specification and the like, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.

Alternatively, as another expression method, for example, “a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor. The first connection path is a path through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path. The third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2. " Or, “the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path. , Y, and the third connection path does not have the second connection path. Or “the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is a second electrical path Does not have an electrical path, and the second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor; The drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is a fourth electrical path. The fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor. can do. Using the same expression method as those examples, by defining the connection path in the circuit configuration, the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are distinguished. The technical scope can be determined.

In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

B1-B2 One-dot chain line B3-B4 One-dot chain line C1 Capacitor C1-C2 One-dot chain line C3-C4 One-dot chain line CON1 Control signal D1-D2 One-dot chain line D3-D4 One-dot chain line E1-E2 One-dot chain line E3-E4 One-dot chain line F1-F2 One-dot chain line F3-F4 One-dot chain line FD1 Node FD2 Node G1-G2 One-dot chain line G3-G4 One-dot chain line H1-H2 One-dot chain line I3-I2 One-dot chain line I3-I4 One-dot chain line J1-J2 One-dot chain line J3-J4 One-dot chain line K1 -K2 Dash-dot line K3-K4 Dash-dot line M1 Transistor M1-M2 Dash-dot line M1_A Transistor M1_B Transistor M2 Transistor M3 Transistor M3-M4 Dash-dot line M4 Transistor M5 Transistor M6 Transistor M7 Transistor M11 Transistor M12 Transistor M1 4 Transistor M21 Transistor M31 Transistor M32 Transistor M33 Transistor M34 Transistor N1-N2 Dotted line N3-N4 Dotted line OD1 Line OD2 Line ODD1 Line P1 Period P2 Period P3 Period P4 Period P5 Period P6 Period P7 Period P8 Period P9 Period PCL1 Photoelectric conversion element PCL2 photoelectric conversion element PCL3 photoelectric conversion element R1 period SE1 wiring SE2 wiring T2 period TX1 wiring TX2 wiring VBIAS1 bias voltage VBIAS2 bias voltage X1-X2 two-dot chain line X3-X4 two-dot chain line Y1-Y2 two-dot chain line Y3-Y4 two-dot chain line 10 circuit 11 imaging operation 12 data holding operation 13 operation 15 light shielding layer 20 circuit 21 transistor 30 silicon substrate 31 transistor 32 transistor 35 active layer 36 silicon substrate 1a transistor 52a transistor 60a photoelectric conversion element 61 photoelectric conversion layer 62 translucent conductive layer 63 semiconductor layer 64 semiconductor layer 65 semiconductor layer 66 electrode 66a conductive layer 66b partition layer 72 wiring 72a conductive layer 72b conductive layer 80 insulating layer 81 conductive Body 82 insulating layer 82a insulating layer 82b insulating layer 83 insulating layer 88 wiring 101 transistor 102 transistor 103 transistor 104 transistor 105 transistor 106 transistor 107 transistor 108 transistor 109 transistor 110 transistor 111 transistor 112 transistor 113 transistor 115 substrate 120 insulating layer 130 oxide semiconductor Layer 130a oxide semiconductor layer 130b oxide semiconductor layer 130c oxide semiconductor layer 140 conductive layer 141 conductive layer 142 conductive Layer 150 conductive layer 151 conductive layer 152 conductive layer 160 insulating layer 170 conductive layer 171 conductive layer 172 conductive layer 173 conductive layer 175 insulating layer 180 insulating layer 190 insulating layer 200 pixel 200A pixel 200B pixel 200C pixel 200D pixel 200E pixel 200F pixel 200G pixel 200H pixel 201 circuit 202 circuit 203 comparison circuit 231 region 232 region 233 region 330 oxide semiconductor layer 330a oxide semiconductor layer 330b oxide semiconductor layer 330c oxide semiconductor layer 331 region 332 region 333 region 334 region 335 region 400 pixel 401 analog processing Circuit 402 A / D conversion circuit 403 Column driver 404 Row driver 405 Pixel unit 800 Camera module 801 Lens unit 802 Autofocus unit 803 Lid glass 804 Sakaba 805 imaging device 806 substrate 807 FPC
901 Case 902 Case 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Case 912 Display unit 931 Case 932 Display unit 933 Wristband 951 Case 952 Lens 953 Support unit 961 Case 962 Shutter button 963 Microphone 965 Lens 967 Light emitting portion 971 Case 972 Case 973 Display portion 974 Operation key 975 Lens 976 Connection portion 1100 Layer 1200 Layer 1400 Layer 1500 Diffraction grating 1600 Layer 2500 Insulating layer 2510 Light shielding layer 2520 Organic resin layer 2530 Color filter 2530a Color Filter 2530b Color filter 2530c Color filter 2540 Microlens array 2550 Optical conversion layer 2560 Insulating layer 8909 Camera module 8919 Camera module Le 8939 camera module

Claims (6)

A switching circuit, a pixel, a readout circuit, and a comparison circuit;
An imaging apparatus having a function of switching between a first mode and a second mode,
The pixel includes a photoelectric conversion element and first to fourth transistors,
A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor;
A gate of the fourth transistor is electrically connected to one of a source and a drain of the third transistor;
The photoelectric conversion element is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor;
One of a source and a drain of the second transistor is electrically connected to the first wiring;
One of a source and a drain of the fourth transistor is electrically connected to the second wiring;
The readout circuit is electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fourth transistor;
A function of outputting a voltage according to a voltage of the gate of the second transistor or the gate of the fourth transistor in the first mode;
A function of amplifying a difference between a voltage of a gate of the second transistor and a voltage of a gate of the fourth transistor in the second mode;
The switching circuit is electrically connected to the first wiring and the second wiring,
In the first mode, a function of applying a constant voltage to the first wiring and the second wiring is provided.
In the second mode, it has a function of flowing a constant current through the first wiring and the second wiring;
The comparison circuit is electrically connected to the first wiring and the second wiring;
An imaging device having a function of outputting a signal in accordance with a voltage difference between the first wiring and the second wiring in the second mode. In claim 1,
The pixel includes a fifth transistor and a sixth transistor,
One of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor;
The other of the source and the drain of the fifth transistor is electrically connected to the readout circuit;
One of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fourth transistor;
The imaging device, wherein the other of the source and the drain of the sixth transistor is electrically connected to the readout circuit. In claim 1 or 2,
The pixel includes a seventh transistor;
One of a source and a drain of the seventh transistor is electrically connected to the photoelectric conversion element;
The other of the source and the drain of the seventh transistor is electrically connected to a wiring for applying a reset voltage. In any one of Claims 1 thru | or 3,
The first transistor includes an oxide semiconductor in a channel formation region,
The imaging device, wherein the third transistor includes an oxide semiconductor in a channel formation region. In any one of Claims 1 thru | or 4,
The said photoelectric conversion element is an imaging device which has the material containing selenium. An electronic apparatus comprising the imaging device according to claim 1 and a display device.

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