JP2016207243A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of reducing stress in reading by decreasing the number of accesses to a reference cell at the time of reading.SOLUTION: A memory 1 includes, as a reading circuit of a data cell 2, a reference cell 3, a detection part 4, a reference generation part 5, and a comparison part 8. After a power is turned on, when reading data of the data cell 3, the memory 1 reads a reference current of the reference cell 3 by the detection part 4, and sets it at the reference generation part 5 as a reference value. The comparison part 6 compares a data current of the data cell 3 with the reference value of the reference generation part 5, for outputting data. After that, by reading the data of the data cell 2 by using the reference value of the reference generation part 5, the number of times of accessing to the reference cell 3 can be significantly decreased, for improved reliability.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor memory device.

  As a semiconductor memory device, there is a read type memory using a reference cell. In this memory, in order to reduce stress due to access to a reference cell, for example, there is a technique for setting a voltage to a reference cell at the time of reading smaller than that of a cell storing data (hereinafter referred to as a data cell). is there. This reduces read stress on the reference cell and improves reliability.

  However, in such a technique, since the applied voltages of the data cell and the reference cell are different, a difference occurs between the operating points of the respective cells, and there is a problem that an appropriate read reference cannot be generated.

JP 2008-65972 A

  The present invention has been made in view of the above circumstances, and an object thereof is to reduce the number of accesses to the reference cell at the time of reading in a configuration using the reference cell at the time of reading and to reduce the read stress to the reference cell. It is an object of the present invention to provide a semiconductor memory device capable of achieving the above.

  The semiconductor memory device according to claim 1, a data cell, a reference cell that outputs a reference current or a reference voltage for reading data of the data cell as a reference value, and a detection unit that detects a reference value of the reference cell A reference generation unit that generates a reference value detected by the detection circuit; and a comparison unit that compares the output of the data cell with the reference value generated by the reference generation unit and reads data. .

  In the above configuration, when reading data in the data cell, first, the detection unit reads the reference current or reference voltage of the reference cell as a reference value, and the reference generation unit sets the detected reference value in the comparison unit. Thereafter, the comparison unit compares the output of the data cell with the reference value generated by the reference generation unit, and reads the data. Thereafter, when reading the data of the data cell, the reference value by the reference generation unit is used in the comparison unit without reading the reference current or reference voltage of the reference cell each time. As a result, the number of times of reading the reference current or reference voltage from the reference cell can be reduced, the reading stress to the reference cell can be reduced, and the reliability can be improved.

Electrical block diagram showing the first embodiment Diagram showing the flow of operation Electrical block diagram showing the second embodiment Diagram showing the flow of operation The figure which shows the flow of operation | movement of 3rd Embodiment. Electrical block diagram showing the fourth embodiment Electrical block diagram showing the fifth embodiment Diagram showing the flow of operation Electrical block diagram showing the sixth embodiment Diagram showing the flow of operation Electrical block diagram showing the seventh embodiment Electrical block diagram showing the eighth embodiment Circuit diagram of detector according to ninth embodiment (No. 1) Circuit diagram of detector (Part 2) Circuit diagram of detector (Part 3) Circuit diagram of detector (Part 4) The figure which shows the flow of operation | movement of 10th Embodiment.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
FIG. 1 shows an electrical block configuration. In FIG. 1, a memory 1 as a semiconductor memory device is provided on a chip by forming circuit elements on a semiconductor substrate (not shown). As a basic configuration of the memory 1, a large number of data cells 2 for storing data in bit units are provided. Further, a circuit for reading and writing data, a control circuit for controlling these operations, and the like are provided for the data cell 2.

  FIG. 1 shows a read circuit portion targeted by this embodiment. The readout circuit includes a reference cell 3, a detection unit 4, a reference generation unit 5, and a comparison unit 8. The reference cell 3 has the same configuration as that of the data cell 2 and outputs a reference current corresponding to a threshold level for determining data stored in the data cell 2. One reference cell 3 is provided corresponding to the plurality of data cells 2.

  The detection unit 4 reads the reference current from the reference cell 3 and sets it in the reference generation unit 5 as a reference current. The detection unit 4 can be configured by combining, for example, an AD conversion circuit and a DA conversion circuit as a circuit that converts the detected current into a digital signal. The reference generation unit 5 outputs the reference current set by the detection unit 4 to the comparison unit 6 as a reference value. The comparison unit 6 is provided with a circuit for comparing the magnitude of the current value or converting the current value into a voltage, and comparing the current corresponding to the data in the data cell 2 with the reference current. Is output.

  Next, the operation of the above configuration will be described with reference to FIG. First, when the power is turned on and power is supplied to the memory 1 (A1), a program for reading data is set in the control unit in the memory 1. Next, the memory 1 detects the reference current of the reference cell 3 by the detection unit 4 (A2). Next, the memory 1 sets the reference current value detected by the detection unit 4 as a reference value in the reference generation unit 5 and outputs the reference value to the comparison unit 6.

  The memory 1 determines and outputs the data value in the comparison unit 6 based on the data current input from the data cell 2 and the reference value input from the reference generation unit 5 (A3). Thereafter, when data is read from the data cell 2 during the power-on period, the comparison unit 6 uses the reference value of the reference generation unit 5 to compare the data current of the data cell 2 and read the data. (A3). Then, after the power is turned off, when the power is turned on again (A1), the memory 1 executes the processes of A2 and A3 in the same manner as described above to perform the data reading process.

  According to the first embodiment, when the data of the data cell 2 is read, the reference current of the reference cell 3 is not read each time, but before the reading is executed when the power is turned on, the reference unit 4 performs the reference. The reference current is read from the cell 3 and the reference value is set by the reference generator 5. In the reading process, the data in the data cell 2 is read in the comparison unit 6 based on the reference value set by the reference generation unit 5. As a result, the number of accesses to the reference cell 3 can be significantly reduced, read stress on the reference cell 3 can be reduced, and reliability can be improved.

(Second Embodiment)
FIG. 3 and FIG. 4 show the second embodiment, and the following description will be focused on differences from the first embodiment. In this embodiment, the reference cell 3 and the reference generation unit 5 are connected to the comparison unit 6 via the switching unit 7. The switching unit 7 includes two switches SW1 and SW2 made of semiconductor elements. The switching unit 7 connects the reference cell 3 to the comparison unit 6 by the switch SW1, and connects the reference generation unit 5 to the comparison unit 6 by the switch SW2. The detection unit 4 detects the reference current and sets the reference generation unit 5 when the switch SW <b> 1 of the switching unit 7 is turned on and the reference cell 3 is connected to the comparison unit 6.

  Next, the operation of the above configuration will be described with reference to FIG. First, when the power is turned on and power is supplied to the memory 1 (A1), a program for reading data is set in the control unit in the memory 1. First, the memory 1 turns on the switch SW1 and turns off the switch SW2 of the switching unit 7 (A11). As a result, the reference cell 3 is connected to the comparison unit 6 via the switch SW1 of the switching unit 7.

  Next, the memory 1 detects the reference current of the reference cell 3 by the detection unit 4 (A2). Subsequently, the memory 1 uses the detection unit 4 to set the detected reference current value as a reference value in the reference generation unit 5. Thereafter, the memory 1 turns off the switch SW1 of the switching unit 7 and turns on the switch SW2 (A12). As a result, the reference cell 3 is disconnected from the comparison unit 6, and the reference generation unit 4 is connected to the comparison unit 6 via the switch SW2.

  Thereafter, the comparison unit 6 determines and outputs the data value based on the data current input from the data cell 2 and the reference value input from the reference generation unit 5. Thereafter, when data is read from the data cell 2 during the power-on period, the comparison unit 6 uses the reference value of the reference generation unit 5 to compare the data current of the data cell 2 and read the data. . When the power is turned on again after the power is turned off (A1), the processes of A11, A2, A12, and A3 are executed in the same manner as described above to perform the data reading process.

  According to the second embodiment as described above, when reading the data of the data cell 2, as in the first embodiment, the reference current of the reference cell 3 is not read each time, but is read when the power is turned on. Before, the reference current is read from the reference cell 3 by the detection unit 4 and the reference value is set by the reference generation unit 5. In the reading process, the data in the data cell 2 is read in the comparison unit 6 based on the reference value set by the reference generation unit 5. As a result, as in the first embodiment, the number of accesses to the reference cell 3 can be significantly reduced, read stress on the reference cell 3 can be reduced, and reliability can be improved. it can.

(Third embodiment)
FIG. 5 shows a third embodiment. Hereinafter, parts different from the second embodiment will be described. In this embodiment, the same configuration as that of the second embodiment is adopted. Different processing steps are included in the reading process.

  That is, in the second embodiment, the process of reading the data in the data cell 2 is performed after setting the reference value. In this embodiment, the reference unit 3 of the reference cell 3 is detected by the detection unit 4. In the current detection process (A2), the memory 1 also performs the first read process.

  That is, when the power is turned on and power is supplied to the memory 1 (A1), the control unit in the memory 1 sets a program for reading data. First, the memory 1 turns on the switch SW1 and turns off the switch SW2 of the switching unit 7 (A11). As a result, the reference cell 3 is connected to the comparison unit 6 via the switch SW1 of the switching unit 7.

  Next, in the memory 1, the comparison unit 6 determines and outputs a data value based on the data current input from the data cell 2 and the reference current input from the reference cell 3. Further, the memory 1 detects the reference current of the reference cell 3 by the detection unit 4, and sets the detected reference current value as a reference value in the reference generation unit 5 (A2a).

  Thereafter, the memory 1 turns off the switch SW1 of the switching unit 7 and turns on the switch SW2 (A12). As a result, the reference cell 3 is disconnected from the comparison unit 6 and the reference generation unit 4 is connected to the comparison unit via the switch SW2.

  Thereafter, the memory 1 determines and outputs the data value by the comparison unit 6 based on the data current input from the data cell 2 and the reference value input from the reference generation unit 5. Thereafter, when data is read from the data cell 2 during the power-on period, the comparison unit 6 uses the reference value of the reference generation unit 5 to compare the data current of the data cell 2 and read the data. . When the power is turned on again after the power is turned off (A1), the processes of A11, A2a, A12, and A3 are executed in the same manner as described above to perform the data read process.

  According to the third embodiment, it is possible to obtain the same effect as that of the second embodiment, and at the same time when the data of the first data cell 2 is read when the power is turned on, the reference unit 3 is simultaneously detected by the detection unit 4. Since the reference current is read out and the reference value is set by the reference generation unit 5, the data reading process can be performed quickly.

(Fourth embodiment)
FIG. 6 shows the fourth embodiment. The difference from the first embodiment is that the comparison unit 6a constitutes a voltage input type comparator. In this embodiment, the data cell current of the data cell 2 and the reference current of the reference cell 3 are not compared, but the respective input voltages are compared with the voltage by the comparison unit 6a to determine the data value. .

In this case, the detection unit 4a detects the reference voltage of the reference cell 3 and sets it as a reference value in the reference generation unit 5a. The reference generation unit 5a is configured to input a reference voltage as a reference value to the comparison unit 6a.
Therefore, according to the fourth embodiment, it is possible to obtain the same effect as that of the first embodiment.

(Fifth embodiment)
FIG. 7 and FIG. 8 show the fifth embodiment, and the following description will be focused on differences from the first embodiment. In this embodiment, the reference current read from the reference cell 3 is read at a predetermined frequency in consideration of environmental variation factors, and the reference value is updated to improve the accuracy.

  In a state in which environmental fluctuation factors such as the temperature of the memory 1 fluctuate, the data current of the data cell 2 fluctuates, and if the reference value set by the reference generation unit 5 remains as it is, the fluctuation state is not followed. This is to prevent the possibility of false detection.

  That is, as shown in FIG. 7, in this embodiment, a timer 8 is provided in addition to the configuration of the first embodiment. The timer 8 sets the timing at which the detection unit 4 detects the reference current from the reference cell 3, and sets the read timing repeatedly at regular intervals.

  In this embodiment, the operation of the timer 8 is performed as shown in FIG. That is, first, when the power is turned on and power is supplied to the memory 1 (A1), a program for reading data is set in the control unit in the memory 1. In addition, the memory 1 starts a timer operation by the timer 8.

  Next, the memory 1 detects the reference current of the reference cell 3 by the detection unit 4 (A2). Next, the memory 1 sets the reference current value detected by the detection unit 4 as a reference value in the reference generation unit 5 and outputs the reference value to the comparison unit 6.

  The memory 1 determines and outputs the data value in the comparison unit 6 based on the data current input from the data cell 2 and the reference value input from the reference generation unit 5 (A3). Thereafter, the memory 1 determines whether or not the timer time by the timer 8 has elapsed (A21). When the timer time of the timer 8 has not elapsed (NO in A21), the memory 1 reads data using the reference value of the reference generation unit 5 when reading data from the data cell 2 (A3).

  When the timer time of the timer 8 elapses (YES in A21), the memory 1 detects the reference current of the reference cell 3 again by the detection unit 4 and sets it as the reference value in the reference generation unit 5 (A2). Subsequently, the memory 1 determines and outputs the data value from the data current input from the data cell 2 and the newly set reference value in the comparison unit 6 (A3). Thereafter, the memory 1 updates the reference value with the newly detected reference current every time the timer time of the timer 8 elapses (YES in A21).

  According to the fifth embodiment, the timer 8 is provided, and the reference current is detected and reset as the reference value every time the timer time elapses. As a result, for example, the reference value can be updated following a change in the current value of the reference cell 3 and the data cell 2 due to the state of the environment at the time of data read processing, for example, the temperature of the memory 1 or a change with time. As a result, data reading from the data cell 2 can be performed with high accuracy, and even in this case, the frequency of reading the reference current of the reference cell 3 can be reduced as much as possible, so that the operational effects of the first embodiment can be sufficiently achieved.

(Sixth embodiment)
9 and 10 show the sixth embodiment. The difference from the fifth embodiment is that a temperature sensor 9 is provided instead of the timer 8. In this embodiment, the temperature sensor 9 is provided so as to detect the chip temperature of the memory 1. When the change in temperature detected by the temperature sensor 9 changes by a predetermined temperature or more, the reference current of the reference cell 3 is detected and the reference value is updated.

  This is because when the chip temperature of the memory 1 fluctuates, the currents of the data cell 2 and the reference cell 3 change, and the reference current of the reference cell 3 detected at the time of power-on fluctuation fluctuates. It is intended to prevent this from being followed.

  In this embodiment, the operation of the temperature sensor 9 is performed as shown in FIG. The processing (A1 to A3) from the memory 1 until the data of the data cell 2 is first read after the power is turned on is the same as described above. In this embodiment, the memory 1 monitors the detected temperature of the temperature sensor 9 and holds the temperature at the time when the reference current of the reference cell 3 is read, that is, when the detection operation is performed by the detection unit 4 at A2. To do.

  Thereafter, the memory 1 calculates a temperature change ΔT that is a difference between the temperature of the chip detected by the temperature sensor 9 and the previous detected temperature, and the calculated temperature change ΔT is larger than a preset predetermined temperature difference Tp. Whether or not (A22). When the temperature change ΔT is not greater than the predetermined temperature difference Tp (NO in A22), the memory 1 reads data using the reference value of the reference generation unit 5 when reading data from the data cell 2 (A3). The predetermined temperature difference Tp can be set in consideration of detection accuracy and use environment, and can be set in a range from about several degrees Celsius to about 10 degrees Celsius as an example.

  When the temperature change ΔT becomes larger than the predetermined temperature difference Tp (YES in A22), the memory 1 detects the reference current of the reference cell 3 again by the detection unit 4 and supplies the reference generation unit 5 as a reference value. Set (A2). At this time, the memory 1 stores the temperature detected by the temperature sensor 9.

  Subsequently, the memory 1 determines and outputs the data value from the data current input from the data cell 2 and the newly set reference value in the comparison unit 6 (A3). Thereafter, when the temperature change ΔT becomes larger than the predetermined temperature difference Tp (YES in A22), the memory 1 updates the reference value with the newly detected reference current.

  According to the sixth embodiment as described above, the temperature sensor 9 is provided, and when the temperature change ΔT becomes larger than the predetermined temperature difference Tp, the reference current is detected and reset as the reference value. Thereby, for example, the reference value can be updated following the temperature fluctuation of the memory 1 during the data reading process. As a result, data reading from the data cell 2 can be performed with high accuracy, and even in this case, the frequency of reading the reference current of the reference cell 3 can be reduced as much as possible, so that the operational effects of the first embodiment can be sufficiently achieved.

(Seventh embodiment)
FIG. 11 shows the seventh embodiment. The difference from the sixth embodiment is that a voltage sensor 10 as a power supply voltage detection unit is provided in place of the temperature sensor 9. In this embodiment, the power supply voltage input to the memory 1 by the voltage sensor 10 is detected. When the change of the power supply voltage by the voltage sensor 10 changes more than a predetermined value, the reference current of the reference cell 3 is detected and the reference value is updated.

  This is because when the power supply voltage to the memory 1 fluctuates, the currents of the data cell 2 and the reference cell 3 change, and the reference current of the reference cell 3 detected at the time of power-on fluctuation fluctuates. Are not following this.

  In this embodiment, step A22 is performed in the sixth embodiment, but determination is made based on whether or not the change in the detected voltage of the power supply voltage by the voltage sensor 10 is greater than a predetermined value. As a result, when a voltage variation is detected by the voltage sensor 10, the memory 1 again detects the reference current of the reference cell 3 by the detection unit 4 and sets it as a reference value in the reference generation unit 5 (A2). In this case, the value of the voltage fluctuation for updating and setting the reference value can be set by the rate at which the reference current value of the reference cell 3 fluctuates due to the voltage fluctuation.

  According to the seventh embodiment, the voltage sensor 10 is provided, and when the fluctuation of the power supply voltage changes by a predetermined value or more, the reference current is detected and reset as the reference value. Thereby, for example, even if the power supply voltage fluctuates during the data reading process, the reference value can be updated following this. As a result, data reading from the data cell 2 can be performed with high accuracy, and even in this case, the frequency of reading the reference current of the reference cell 3 can be reduced as much as possible, so that the operational effects of the first embodiment can be sufficiently achieved.

(Eighth embodiment)
FIG. 12 shows an eighth embodiment. The difference from the first embodiment is that a spare reference cell 11 is provided, and a switching unit that switches the reference cell 3 and the spare reference cell 11 to connect to the detector 4. 12 is provided.

  In the above configuration, the memory 1 first detects the reference current (voltage) by the detection unit 4 using the reference cell 3, and sets this as a reference value. Thereafter, when the switching condition of the reference cell 3 is satisfied, the memory 1 controls the switch of the switching unit 12 by the detection unit 4 and reads the reference current (voltage) of the spare reference cell 11 instead of the reference cell 3. It becomes like this.

  In this case, in this configuration, the condition for switching from the reference cell 3 to the spare reference cell 11 is, for example, that the number of times of use of the reference cell 3 is counted by the detection unit 4 and that the number of times of use has reached a predetermined number of times. can do. Moreover, it can also be made a condition that the amount of change in the value of the reference current (voltage) detected by the detection unit 4 has become a predetermined value or more.

  Furthermore, various applications such as a condition that a predetermined time has passed or a condition that the reference current (voltage) of the reference cell 3 detected by the detection unit 4 has an abnormal value are possible. Moreover, these conditions can also be used in combination.

  In addition, as a switching condition, for example, a method of using the reference cell 3 and the spare reference cell 11 with the same frequency by alternately switching and connecting them can be adopted.

According to such an eighth embodiment, by providing the spare reference cell 11 and using it as a spare for the reference cell 3, it is possible to further improve the reliability.
In the above configuration, one spare reference cell 11 is provided. However, the present invention is not limited to this, and two or more spare reference cells may be provided. In this case, the switching unit 12 may also have a configuration in which the changeover switch is increased by a corresponding amount.
Moreover, although the case where it applied to 1st Embodiment was shown in the said 8th Embodiment, it is not restricted to this, It can also apply to the thing of 2nd-7th Embodiment.

(Ninth embodiment)
FIGS. 13 to 16 show a ninth embodiment and show a specific configuration of the detection unit 4 that reads the reference current (voltage) of the reference cell 3. Instead of the configuration using the above-described DA conversion circuit or AD conversion circuit, a configuration using a simple analog circuit is adopted here.

  That is, the configuration shown in FIG. 13 is configured to detect the reference current of the reference cell 3 and is provided with a current mirror circuit 13. The current mirror circuit 13 includes MOSFETs 13a and 13b and includes a capacitor 13c for holding a gate voltage.

  The MOSFET 13a is provided so as to detect the reference current of the reference cell 3. The source and gate of the MOSFET 13a are short-circuited. The MOSFET 13b is an element for reference generation provided in the reference generation unit 5, and the MOSFET 13a and the gate are connected in common, thereby allowing a reference current to flow through the MOSFET 13b.

  The capacitor 13c holds the gate voltage when the reference current is passed, and the reference current can be passed by the MOSFET 13b of the reference generation unit 5 even when the reference cell 3 is off. In this configuration, holding the terminal voltage of the capacitor 13c maintains an accurate reference current. Therefore, when charge is discharged due to a leak current or the like, a refresh operation is performed to hold the potential of the capacitor 13c. can do.

  Next, in the configuration shown in FIG. 14, the current mirror circuit 14 provided with the charge holding switch 14a is provided in the current mirror circuit 13. The switch 14a is provided so as to be interposed in a path from the gate of the MOSFET 13a to the terminal of the capacitor 13c. As the switch 14a, for example, a switching element such as a MOSFET can be used.

  During the operation of detecting the reference current of the reference cell 3, the switch 14a is turned on, and the capacitor 13c is charged with a charge to set a reference value. After that, the reference value corresponding to the reference current can be set by applying a voltage from the capacitor 13c to the gate of the MOSFET 13b of the reference generation unit 5 with the switch 14a turned off.

  At this time, since the switch 14a is turned off, a leakage current to the reference cell 3 side can be prevented, thereby suppressing a decrease in the terminal voltage of the capacitor 13c and reducing the frequency of refreshing. can do.

  Next, what is shown in FIG. 15 corresponds to that of the fourth embodiment configured using the reference voltage of the reference cell 3. In this case, the output voltage of the reference cell 3 is stored by being charged by the capacitor 15. A reference value can be set in the reference generator 5 by the terminal voltage of the capacitor 15.

Further, the configuration shown in FIG. 16 has a configuration in which a switch 16 is added to the configuration of FIG. The switch 16 is separated from the reference cell 3 side. As the switch 16, for example, a switching element such as a MOSFET can be used. Thus, after the switch 16 is turned on and the reference voltage of the reference cell 3 is detected by charging the capacitor 15, the switch 16 is turned off and the reference value can be set by the terminal voltage of the capacitor 15. At this time, since the switch 16 is turned off, the terminal voltage of the capacitor 15 is less discharged and the reference value can be held for a long time.
Also according to the ninth embodiment, the same operational effects as those of the first embodiment or the fourth embodiment can be obtained.

(10th Embodiment)
FIG. 17 shows the tenth embodiment. Hereinafter, parts different from the first embodiment will be described. Although not shown, the memory 1 is provided with a circuit for writing and erasing data in the data cell 2 and performs control for writing and erasing data to be stored. In this case, in normal writing processing, it is always confirmed by performing verification processing whether the written data is correct. In the erasure process, it is confirmed by the verify process whether the erased data is erased.

  Here, in the writing process (erase process), when there is a control for accurately aligning the writing state by repeating the short-time writing processing and the writing state verifying processing instead of simple time-controlled writing or the like. Is assumed. In the write state verify process, the reference value generated by the reference current read from the reference cell 3 is used as in the normal read operation.

  Further, in such an operation, since the short-time write process and the write state verify process are repeated until the write state verify process passes (PASS), the reference cell 3 is accessed many times during one write operation. Current will be detected.

  In the present embodiment, the reference cell 3 is accessed only during the first verification process and the reference current is detected and set as a reference value at the same time in the verification process in this embodiment. By using the reference value by the reference generation unit 5, stress due to repeated access to the reference cell 3 can be reduced.

  A specific operation will be described with reference to FIG. When the memory 1 performs a data write process on the target data cell 2 (B1), the memory 1 performs a write verify process (B2). Here, the memory 1 detects the reference current of the reference cell 3 by the detection unit 4, sets the detected reference current value as the reference value in the reference generation unit 5, and outputs the reference value to the comparison unit 6. In the memory 1, the comparison unit 6 determines and outputs the data value based on the data current input from the data cell 2 and the reference value input from the reference generation unit 5.

  Next, if the determined data value matches the written data (PASS in B3), the memory 1 ends the verification process (END) because the writing is successful. On the other hand, if the determined data value does not match the written data (FAIL in B3), the memory 1 executes the writing process again (B4).

  Thereafter, the memory 1 performs the verify process again (B5). At this time, the memory 1 does not access the reference cell 3 and performs a verify process using the reference value set by the reference generation unit 5. If the data value read by the verify process matches the written data (PASS in B6), the memory 1 ends the verify process (END) because the write has succeeded. If the determined data value does not match the written data (FAIL in B6), the memory 1 executes the writing process again (B7).

  Thereafter, the above-described B5 to B7 are repeated, and when the data value read by the verify process matches the written data (PASS in B6), the verify process is ended (END). Note that not only the writing process but also the erasing process can be performed as described above by the same verify process.

  According to the tenth embodiment, since the reference value is set from the reference current detected from the reference cell 3 when the verify process during the write process is performed a plurality of times, the reference cell 3 can be read even when repeated reading is performed. It is possible to reduce deterioration and prevent deterioration.

(Other embodiments)
In addition, this invention is not limited only to one embodiment mentioned above, It can apply to various embodiment in the range which does not deviate from the summary, For example, it can deform | transform or expand as follows. .

One reference cell 3 can be provided for each data cell 2 in units of two or more.
The detection unit 4 can adopt an appropriate configuration as long as it can detect the reference current or the reference voltage of the reference cell 3 and set it as a reference value other than those shown in the embodiment.

  In the drawings, 1 is a memory, 2 is a data cell, 3 is a reference cell, 4 and 4a are detection units, 5 and 5a are reference generation units, 6 and 6a are comparison units, 7 is a switching unit, 8 is a timer, and 9 is Temperature sensor, 10 is a voltage sensor (power supply voltage detection unit), 11 is a spare reference cell, 12 is a switching unit, 13 and 14 are current mirror circuits, 13a and 13b are MOSFETs, 13c and 15 are capacitors, and 14a and 16 are switches. It is.

Claims (11)

Data cell (2);
A reference cell (3) for outputting a reference current or a reference voltage for reading data of the data cell as a reference value;
A detection unit (4, 4a) for detecting a reference value of the reference cell;
A reference generator (5, 5a) for generating a reference value detected by the detection circuit;
A semiconductor memory device, comprising: a comparison unit (6, 6a) for comparing the output of the data cell and the reference value generated by the reference generation unit to read data. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein after the reference value is set by the reference generation unit (4), the data of the data cell is read by the comparison unit (6). The semiconductor memory device according to claim 1 or 2,
A switching unit (7) for switching between the reference cell and the reference generation unit (5);
The detection unit (4) detects a reference value of the reference cell at the time of data reading of the data cell, and then switches to the reference generation unit instead of the reference cell by the switching unit and transfers the reference to the comparison unit. A semiconductor memory device characterized by setting a value. The semiconductor memory device according to claim 3.
When reading the data of the data cell, when the reference value of the reference cell is detected, the first time data is read by the comparison unit, and after the reference value is set by the reference generation unit, the second and subsequent data is read. A semiconductor memory device. The semiconductor memory device according to claim 1,
A timer (8) for setting the second and subsequent read timings of the reference value of the reference cell;
The detection unit detects and updates a reference value of the reference cell when a read timing is set by the timer. The semiconductor memory device according to any one of claims 1 to 5,
It has a temperature sensor (9) that detects the temperature of the usage environment or the chip temperature,
The reference value of the reference cell is detected by the detecting unit when the temperature sensor detects a fluctuation of a detected temperature that is greater than a certain level. The semiconductor memory device according to any one of claims 1 to 6,
A power supply voltage detector (10) for detecting a power supply voltage;
The detection of the reference value of the reference cell by the detection unit is performed when a fluctuation of the detected value of the power supply voltage is detected by the power supply voltage detection unit. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the detection unit includes a current mirror circuit (113, 14) for copying a reference current of the reference cell and a capacitor (13c) for holding a mirror operation state. The semiconductor memory device according to claim 8.
The semiconductor memory device, wherein the current mirror circuit (14) is provided with a switch (14a) for suppressing charge discharge of the capacitor. The semiconductor memory device according to any one of claims 1 to 9,
The detecting unit detects a reference value of the reference cell at the time of data reading for verifying data writing or erasing to the data cell, and then the switching unit replaces the reference cell with the reference generating unit. A semiconductor memory device, wherein the reference value is set in the comparison unit by switching. The semiconductor memory device according to any one of claims 1 to 10,
A semiconductor memory device comprising a spare reference cell (11) having a function equivalent to that of the reference cell.

Images