JP2016207236A - Semiconductor integrated circuit device and analysis method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce failure analysis time.SOLUTION: A semiconductor integrated circuit device according to one embodiment comprises: a MOSFET m1 connected to a word line WL of a memory cell array 10; and an OR logic gate g1 connected to the MOSFET m1. The OR logic gate g1 includes a first input terminal to which a low power consumption mode control signal n2 is inputted, a second input terminal to which an analysis control signal n3 is inputted, and an output terminal connected to a gate of the MOSFET m1. The semiconductor integrated circuit device is brought into an analysis state when the analysis control signal n3 is at H-level.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor integrated circuit device and an analysis method thereof, and more particularly to a technique for facilitating identification of a defective word line of a memory.

  An example of the semiconductor integrated circuit device is a microcomputer (hereinafter also referred to as a microcomputer). The microcomputer includes a memory such as a CPU (Central Processing Unit) and a RAM (Random Access Memory), a voltage generation circuit that generates various voltages, and the like. For example, there is Patent Literature 1 as a technology related to a microcomputer.

JP 2009-187611 A

  The microcomputer described above includes a so-called microcomputer on-chip RAM in which a RAM is mounted on a chip. In the on-chip RAM of this microcomputer, the defect of the word line starts by confirming the coincidence between the logical address and the actual wiring arrangement. However, because of dummy wiring, multi-stage decoding, and multi-addressing, the logical address and the actual wiring arrangement do not always match. In addition, in the old product, the above-mentioned confirmation is difficult due to incompleteness or loss of wiring plan information on the floor plan or layout.

  In such a case, a good word line is cut and processed by FIB (Focused Ion Beam) to perform logical evaluation, and the position is confirmed by failing at an assumed logical address. However, with this method, there is a risk that the increase in man-hours between FIB processing and tester evaluation will be about one day, and if the estimation is deviated, repetition will occur, and the man-hour will increase. On the contrary, if the defective part can be confirmed by observing the defective product itself, it can be expected to shorten the time required for analysis.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor integrated circuit device according to an embodiment includes a memory cell array including a plurality of memory cells and a plurality of word lines, a plurality of transistors connected to the plurality of word lines, and a logic circuit connected to the plurality of transistors. And having. In the logic circuit, a control signal is input to a first input terminal, an analysis control signal is input to a second input terminal, and an output terminal is connected to the gate of the transistor.

  Another semiconductor integrated circuit device according to an embodiment includes a memory cell array including a plurality of memory cells and a plurality of word lines, a plurality of first transistors and a plurality of second transistors connected to the plurality of word lines, Have. In the first transistor, a control signal is input to a gate, a source is connected to a ground voltage, and a drain is connected to the word line. The second transistor has a gate to which an analysis control signal is input, a source connected to a power supply voltage, and a drain connected to the word line.

  An analysis method of a semiconductor integrated circuit device according to an embodiment includes a step of identifying a position of a word line causing a defect by passing a current through each word line of a memory cell array and observing a state of occurrence of a physical phenomenon. Have.

  According to one embodiment, the failure analysis time can be shortened.

FIG. 10 is a diagram for explaining an operation of a RAM in a low power consumption mode in a comparison technique with respect to the embodiment of the present invention. In the comparison technique with respect to the embodiment of the present invention, it is a diagram for explaining a defect related to the word line of the memory, (a) is a diagram showing the relationship between the word line and the memory cell, (b) is a cut of the word line It is a figure which shows the confirmation method of the defect position by this. In the microcomputer in Embodiment 1 of this invention, it is a figure for demonstrating the structure of the whole chip | tip including RAM and control signal wiring. In the microcomputer according to the first embodiment of the present invention, it is a diagram for explaining the connection of the gate control signal of the MOSFET of the word line floating prevention transistor. In the microcomputer in Embodiment 1 of this invention, it is a figure for demonstrating the state of the memory by the combination of the low power consumption mode control signal and the control signal for analysis. 4 is a flowchart for explaining a procedure of a failure analysis method in the microcomputer according to the first embodiment of the present invention. In the comparison technique with respect to the embodiment of the present invention, it is a diagram showing a circuit corresponding only to the control function of the low power consumption mode and its layout. In the microcomputer in Embodiment 1 of this invention, it is a figure which shows the circuit which added the control function by the control signal for an analysis to the control function of the low power consumption mode, and its layout. In the microcomputer in Embodiment 2 of this invention, it is a figure for demonstrating the structure of the whole chip | tip including RAM and control signal wiring. In the microcomputer in Embodiment 3 of this invention, it is a figure for demonstrating the structure which connected MOSFET of the word line floating prevention transistor and MOSFET for analysis evaluation to the word line. In the microcomputer according to the fourth embodiment of the present invention, a configuration of the entire chip including a plurality of RAMs and control signal wirings (a configuration in which a gate control signal of a word line floating prevention transistor is separately sent to a plurality of memories) will be described. FIG. In the microcomputer according to the fourth embodiment of the present invention, another configuration of the entire chip including a plurality of RAMs and control signal wirings (a configuration in which a gate control signal of a word line floating prevention transistor is shared with a plurality of memories) will be described. It is a figure for doing. In the microcomputer in Embodiment 5 of this invention, it is a figure for demonstrating the structure of the whole chip | tip of the example which switches and uses the control signal for analysis and a separate logic by an I / O function switching function.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

[Outline of the embodiment]
First, an outline of the embodiment will be described. In the outline of the present embodiment, as an example, description will be given with the corresponding constituent elements and reference numerals of the embodiment in parentheses.

  A semiconductor integrated circuit device according to an embodiment includes a memory cell array (memory cell array 10) including a plurality of memory cells and a plurality of word lines, a plurality of transistors (MOSFET m1) connected to the plurality of word lines, and the plurality And a logic circuit (OR logic gate g1) connected to the transistors. In the logic circuit, a control signal (low power consumption mode control signal n2) is input to a first input terminal, an analysis control signal (analysis control signal n3) is input to a second input terminal, and an output terminal is the transistor Connected to the gate.

  Another semiconductor integrated circuit device according to an embodiment includes a memory cell array (memory cell array 10) including a plurality of memory cells and a plurality of word lines, and a plurality of first transistors (MOSFET m1) connected to the plurality of word lines. ) And a plurality of second transistors (MOSFET m2). The first transistor has a gate receiving a control signal (low power consumption mode control signal n2), a source connected to a ground voltage, and a drain connected to the word line. The second transistor has a gate to which an analysis control signal (analysis control signal n3) is input, a source connected to a power supply voltage, and a drain connected to the word line.

  According to an analysis method of a semiconductor integrated circuit device in an embodiment, a current is passed through each word line of a memory cell array, and a physical phenomenon occurrence state is observed to identify a position of a word line causing a defect ( S4).

  Hereinafter, each embodiment based on the outline | summary of embodiment mentioned above is described in detail based on drawing. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  Further, in the following, in order to make the features of the embodiment easier to understand, a description will be given in comparison with a comparative technique for the embodiment.

[Comparison technology to the embodiment]
A comparison technique with respect to the present embodiment will be described with reference to FIGS. FIG. 1 is a diagram for explaining the operation of a RAM in a low power consumption mode in a comparison technique with respect to the present embodiment. FIG. 1 is a diagram corresponding to FIG. 2 in Patent Document 1 described above. 2A and 2B are diagrams for explaining a defect related to a word line of a memory. FIG. 2A is a diagram illustrating a relationship between a word line and a memory cell, and FIG. 2B is a method for confirming a defect position by cutting the word line. FIG.

  FIG. 1 shows a so-called microcomputer on-chip RAM in which a RAM is mounted on a chip in a microcomputer as an example of a semiconductor integrated circuit device. In FIG. 1, an SRAM is shown as an example of the on-chip RAM. As shown in FIG. 1, the RAM includes a memory cell array 10 driven by an internal power supply voltage SVDD and a memory peripheral circuit 20 driven by the internal power supply voltage VDD.

  Memory cell array 10 includes a plurality of memory cells MC arranged in a matrix, a plurality of word lines WL provided corresponding to each row of memory cells MC, and a plurality provided corresponding to each column of memory cells MC. Data line pair DL, / DL. FIG. 1 schematically shows one memory cell MC, one word line WL and a pair of data lines DL, / DL connected to the memory cell MC.

  The RAM memory cell MC includes two inverters 14 and 15 connected between the storage node ND1 and the storage node ND2, and an N-channel MOSFET (Metal Oxide) connected between the storage node ND1 and the data line DL. Semiconductor Field Effect Transistor) 12 and an N-channel MOSFET 13 connected between the storage node ND2 and the data line / DL. Inverters 14 and 15 function as a latch circuit that holds data in storage nodes ND1 and ND2.

  In order to rewrite the data held in storage nodes ND1 and ND2, one of data lines DL and / DL is set to H level and the other is set to L level according to write data. In this state, when the word line WL is activated to H level, the MOSFETs 12 and 13 become conductive, so that the voltages of the storage nodes ND1 and ND2 are changed according to the voltages of the data lines DL and / DL. .

  The memory peripheral circuit 20 shown in FIG. 1 includes a decoder that selects a memory cell MC in accordance with an address signal, a circuit for reading / writing data in the selected memory cell MC, and the like. As shown in FIG. 1, the memory peripheral circuit 20 includes a word line driver WD provided corresponding to each word line WL. This word line driver WD is driven by the internal power supply voltage VDD and activates the word line WL corresponding to the selected memory cell MC to H level.

  The RAM shown in FIG. 1 further includes an N-channel MOSFET 11 connected between each word line WL and the ground voltage VSS, and a P provided on a power supply line for supplying the internal power supply voltage VDD to the word line driver WD. Channel MOSFET 21.

  MOSFET 11 becomes conductive when the gate electrode receives control signal WLPD at H level from the control circuit in the low power consumption mode of the microcomputer. As a result, the voltage of the word line WL becomes the ground voltage VSS. Thus, the MOSFET 11 functions as a switch for fixing the word line WL to the L level in the low power consumption mode. As a result, fluctuations in the voltage of the word line WL due to noise or the like are suppressed, and erroneous writing to the memory cell MC is prevented.

  The MOSFET 21 is a switch for previously shutting off the internal power supply voltage VDD supplied to the word line driver WD when the operation mode is switched. When noise is generated along with the rise / fall of the internal power supply voltage VDD when the operation mode is switched, the generated noise flows from the word line driver WD to the word line WL. This is prevented by providing the MOSFET 21. The

  The RAM shown in FIG. 1 further includes an inverter 22 driven by the internal power supply voltage VDD and an inverter 23 driven by the internal power supply voltage SVDD as drivers for driving the gate electrode of the MOSFET 21. When the control signal WLPD becomes H level in the low power consumption mode, the MOSFETs 22B and 23A become conductive. In this case, even if the supply of the internal power supply voltage VDD that drives the inverter 22 is stopped, the conduction state of the MOSFETs 22B and 23A is maintained, so that the output voltage of the inverter 23 also remains at the H level. Therefore, MOSFET 21 can be turned off during the low power consumption mode regardless of the stop of supply of internal power supply voltage VDD.

  In the RAM described above, the MOSFET 11 that connects the word line WL of the memory cell MC and the ground voltage VSS is provided, and when switching to the low power consumption mode, the MOSFET 11 is turned on to bring the word line WL to the ground voltage VSS. Fix it. As a result, the MOSFETs 12 and 13 of the memory cell MC become non-conductive, and the data lines DL and / DL are separated from the memory cell MC, so that erroneous writing to the memory cell MC due to noise at the time of operation mode switching. Can be prevented. The MOSFET 11 is also referred to as a “word line floating prevention transistor” because the word line WL is fixed to the ground voltage VSS to prevent the floating state.

  As described above, the MOSFET 11, which is also called “word line floating prevention transistor”, is an element added for use in the user mode, and does not function during failure analysis.

  On the other hand, in the case of a defect relating to a memory word line, it is necessary to first specify the position of the defective word line from the logic defect address information. In a memory that does not support the EDA (Electronic Design Automation) tool that finds the actual coordinates from the FBM (Fail Bit Map), the position is compared with the defective state of the non-defective sample in which the word line is cut by FIB (Focused Ion Beam) processing. Confirmation is in progress.

  In FIG. 2A, the memory cell MC is selected by utilizing the potential change of the word line WL connected to the output of the word line driver WD, thereby executing the memory write / read operation. Here, if the word line WL is cut at the position shown in FIG. 2B by FIB processing, the memory cell MC cannot be selected, and a defect occurs in the write / read operation at the address corresponding to the word line WL. It will be.

  Using this, the word line corresponding to the defective address derived from the evaluation result of the tester is cut in the non-defective sample, deliberately deteriorated, and the defective product is compared with the defective address to perform the cutting process. It is possible to determine whether or not the word line corresponds to a defect phenomenon.

  However, confirmation of word line placement by FIB processing requires materials, time, and man-hours for evaluation, and depending on the wiring structure of the memory layout, there may be no place suitable for cutting on the word line.

  On the other hand, the MOSFET 11, which is also referred to as “word line floating prevention transistor” shown in FIG. 1, is an element that shorts the word line and the ground voltage. You can expect a reaction specific to the location. However, the MOSFET 11 is an element added for the purpose of use in the user mode in Patent Document 1 described above, and cannot be used for failure analysis.

  Therefore, in the present embodiment, MOSFET 11 also referred to as “word line floating prevention transistor” shown in FIG. 1 is used not only for use in the user mode but also for failure analysis. In the following, this embodiment will be described in detail.

[Embodiment 1]
A semiconductor integrated circuit device and an analysis method thereof according to the first embodiment will be described with reference to FIGS.

<Microchip on-chip RAM>
First, in the microcomputer as an example of the semiconductor integrated circuit device according to the first embodiment, an on-chip RAM of the microcomputer will be described. FIG. 3 is a diagram for explaining a configuration of the entire chip including the RAM and the control signal wiring in the microcomputer according to the first embodiment. FIG. 4 is a diagram for explaining the connection of the gate control signal of the MOSFET of the word line floating prevention transistor. FIG. 5 is a diagram for explaining the state of the memory by a combination of the low power consumption mode control signal and the analysis control signal. FIG. 6 is a flowchart for explaining the procedure of the failure analysis method.

  In FIG. 3, m1 in the RAM corresponds to the MOSFET 11 also referred to as “word line floating prevention transistor” in FIG. N1 represents a MOSFET control line connected to the gate electrode of the MOSFET m1, n2 represents a low power consumption mode control signal (WLPD), n3 represents an analysis control signal, and g1 represents an OR logic gate.

  In the chip shown in FIG. 3, a RAM 1 including a MOSFET m1 and an OR logic gate g1 are mounted on the chip. Further, an input / output pad I / O for external input / output is provided on the outer peripheral portion on the chip. On the chip, a MOSFET control line n1 for connecting the gate electrode of the MOSFET m1 and the output of the OR logic gate g1, and a control line for the low power consumption mode control signal n2 connected to one input of the OR logic gate g1. And a control line for the analysis control signal n3 connected to the other input of the OR logic gate g1. The control line for the analysis control signal n3 has one end connected to the other input of the OR logic gate g1 and the other end connected to a dedicated input / output pad I / O. The control line of the low power consumption mode control signal n2 has one end connected to one input of the OR logic gate g1 and the other end connected to a control circuit (not shown) on the chip.

  FIG. 4 shows details centering on the RAM 1 in FIG. 3 is the MOSFET m1 in FIG. 4, the low power consumption mode control signal n2 in FIG. 3 is the low power consumption mode control signal n2 in FIG. 4, and the analysis control signal n3 in FIG. 3 is the analysis control signal in FIG. 3 corresponds to the OR logic gate g1 of FIG. 4 and the OR logic gate g1 of FIG.

  4 shows the memory cell array 10 and the memory peripheral circuit 20 described with reference to FIG. The memory cell array 10 schematically shows one memory cell MC, one word line WL and a pair of data lines DL, / DL connected to the memory cell MC. The memory peripheral circuit 20 illustrates a word line driver WD provided corresponding to each word line WL.

  4 shows one memory cell MC, one word line WL, and one pair of data lines DL, / DL as the memory cell array 10, but in this embodiment, they are arranged in a matrix. A plurality of memory cells MC, a plurality of word lines WL provided corresponding to each row of the memory cells MC, and a plurality of data line pairs DL and / DL provided corresponding to each column of the memory cells MC. Is included.

  In FIG. 4, one word line driver WD is shown as the memory peripheral circuit 20, but in this embodiment, a plurality of word line drivers WD provided corresponding to the plurality of word lines WL are provided. Is included. Further, in the present embodiment, the memory peripheral circuit 20 includes a decoder that selects the memory cell MC according to the address signal, a circuit for reading / writing data in the selected memory cell MC, and the like. .

  In FIG. 4, a word line driver WD, a word line WL driven by the word line driver WD, and a MOSFET m1 (word line anti-floating transistor) connected to the far end of the word line WL are the comparison techniques of the present embodiment. Use without changing the configuration. The MOSFET m1 is connected between the word line WL and the ground voltage, the drain electrode is connected to the word line WL, and the source electrode is connected to the ground voltage.

  In this embodiment, an OR logic gate g1 is inserted between the gate electrode of the MOSFET m1 and the low power consumption mode control signal n2, thereby enabling control by the analysis control signal n3. The OR logic gate g1 is an example of a logic circuit, the low power consumption mode control signal n2 is input to the first input terminal, the analysis control signal n3 is input to the second input terminal, and the output terminal is the gate electrode of the MOSFET m1. It is connected to the. The relationship between the combination of the low power consumption mode control signal n2 and the analysis control signal n3 and the state of the memory (RAM1) is as shown in FIG.

  For example, since the OR logic gate g1 operates as a buffer for the low power consumption mode control signal n2 when the analysis control signal n3 is at the L level, the memory content destruction preventing function at the time of transition to the low power consumption mode in the comparison technique To realize. In this low power consumption mode, the low power consumption mode control signal n2 is at the H level, the analysis control signal n3 is at the L level, and the gate electrode of the MOSFET m1 is at the H level potential. In this low power consumption mode, the supply of power to the circuits is stopped except for some circuits necessary for data retention.

  When the H level is applied through the dedicated input / output pad I / O, the analysis control signal n3 becomes the H level. Then, regardless of the state (L level, H level) of the low power consumption mode control signal n2, the H level potential is transmitted to the gate electrode of the MOSFET m1, and the MOSFET m1 is in the ON state. Current I flows from the word line driver WD to the MOSFET m1 via the word line WL. As a result, the memory state becomes the analysis state. In this analysis state, the position of the defective word line WL is specified by observing the occurrence state of the physical phenomenon for the word line WL through which a current flows.

  When the memory is in the normal operation mode, the low power consumption mode control signal n2 and the analysis control signal n3 are both at the L level, and the gate electrode of the MOSFET m1 is at the L level potential. In this normal operation mode, an operation is performed by reading / writing data from / to the memory cell MC.

  In the present embodiment, the failure analysis method is performed in the procedure as shown in FIG. 6, for example. For a failed product, first, an appearance inspection of the package is performed (S1), and then a failure mode is classified by evaluating logic operation and electrical characteristics (S2). Next, after analyzing the package interior according to the failure mode (S3), identifying the failure location inside the chip, and performing chip physical analysis (S4, S5), the failure location is observed. Finally, a failure mechanism is determined from comprehensive judgment (S6), and a countermeasure is established (S7). Thereby, the failure analysis is completed. In this series of failure analysis methods, the analysis method according to the present embodiment using the analysis control signal n3 is performed, for example, in a step (S4) of identifying a failure location inside the chip.

  In the analysis method in the present embodiment, control is performed using the analysis control signal n3 in a configuration in which the OR logic gate g1 is inserted between the gate electrode of the MOSFET m1 and the control line of the low power consumption mode control signal n2. When the analysis control signal n3 becomes H level, the MOSFET m1 can be turned on (conductive state) even when not in the low power consumption mode. As a result, during the memory access operation, when the word line driver WD corresponding to the address to be accessed is in an H level output state, a current I flows from the word line driver WD to the MOSFET m1 via the word line WL.

  In a state where the current I flows through the MOSFET m1, the occurrence state of the physical phenomenon is observed. For example, if photon emission or OBIRCH (Optical Beam Induced Resistance Change) reaction is observed, a specific reaction can be obtained in the range from the word line driver WD to the MOSFET m1 via the word line WL.

  Observation of photon emission is a technique for identifying a fault location by detecting extremely weak light generated due to current leakage and capturing its position and intensity as a two-dimensional image. The observation of the OBIRCH reaction is a technique for identifying a failure location by utilizing the fact that the change in electrical resistance due to heat generation during laser irradiation differs at the failure location. Other techniques for observing the state of occurrence of such physical phenomena include OBIC (Optical Beam Induced Current) analysis technology that uses an electromotive force generated by photoexcitation during laser irradiation, and the location of heat generation due to chip surface leakage. There are exothermic analysis technologies.

  Here, consider a case where a defect in the wiring process exists in a specific word line WL. As defects in the wiring process, disconnection or high resistance due to defective formation of wiring or through-holes between wirings, and short-circuiting between wirings can be considered. The former reduces the intensity of photon emission and OBIRCH reaction due to a decrease in current flowing through MOSFET m1. In the latter case, since the potential between the word line being accessed and the adjacent word line is different, a potential drop occurs due to a short circuit, a potential drop between the drain and source of the MOSFET m1 and a current decrease occur. Therefore, photon emission and OBIRCH reaction The strength of is reduced.

  As described above, in the present embodiment, there is a difference in the intensity of photon emission or OBIRCH reaction between a normal word line and a defective word line. It becomes possible to confirm the position of the line. Therefore, the reduction effect of the material and man-hour at the time of processing and verifying the good quality sample which was performed conventionally can be acquired.

  In this embodiment, since the analysis control signal n3 is applied by external setting, it is not necessary to change the test pattern when observing photon emission or OBIRCH reaction using a logic tester. In other words, since it is possible to analyze a failure by using a test pattern in which a memory failure is detected as it is in a logical test, it is not necessary to newly create a test pattern dedicated to analysis, thereby reducing failure analysis TAT (Turn Around Time). Connected.

<Layout>
Next, how the layout is added and changed according to the present embodiment will be described with reference to FIGS. The layout change is accompanied by the addition of the OR logic gate g1 in FIG.

  FIG. 7 shows a circuit and a layout of a comparative technique corresponding only to the control function in the low power consumption mode. The circuit of the comparative technique includes an inverter G1. The inverter G1 receives the low power consumption mode control signal n2 as an input, generates a logic inversion signal of the low power consumption mode control signal n2 (a signal of the MOSFET control line n1, which is also referred to as a logic inversion signal n1), The configuration is distributed to the RAM.

  On the other hand, FIG. 8 shows a circuit of this embodiment in which a control function based on the control signal for analysis n3 is added to the control function in the low power consumption mode and its layout. The circuit of this embodiment includes an inverter G3 that receives a low power consumption mode control signal n2, an NOR gate G2 that receives an output from the inverter G3 and an analysis control signal n3, and an output from the NOR gate G2. Including an inverter G1. The low power consumption mode control signal n2 and the analysis control signal n3 are output as the logic inversion signal n1 through the OR logic configured by the NOR gate G2 and the inverter G1.

  The inverter G3 that receives the low power consumption mode control signal n2 is a gate inserted for the purpose of matching the logic polarity. As a result, the low power consumption mode control signal n2 and the logic inversion signal n1 in FIG. An inversion relationship is maintained between the logics. Therefore, when the low power consumption mode control signal n2 and the logic inversion signal n1 in FIG. 7 have the same logic and the inverter G1 is a gate having only a buffer function for driving the logic inversion signal n1, the inverter in FIG. G3 becomes unnecessary.

  The increase in the required area on the layout by adding the NOR gate G2 and the inverter G3 is about one for each of the two-input and one-input basic cells, and the layout shown in FIG. 7 is accommodated in an unused portion of the logic gate region in the layout shown in FIG.

<Effect of Embodiment 1>
According to the semiconductor integrated circuit device and the analysis method thereof according to the first embodiment described above, the failure analysis time can be shortened. That is, the MOSFET m1 that connects between the word line WL and the ground voltage can be turned on during failure analysis, and used for the purpose of identifying the defective portion by observing the reaction of the current of the driven word line WL. Thereby, if a defective location can be confirmed, the time required for analysis can be shortened. Further, the MOSFET m1 can be used for the purpose of preventing the memory contents from being destroyed by setting the MOSFET m1 to the ON state during the low power consumption mode and operating as a word line floating prevention transistor during the transition to the low power consumption mode. More details are as follows.

  (1) The microcomputer includes a MOSFET m1 connected to the word line WL of the memory cell array 10 and an OR logic gate g1 connected to the MOSFET m1. In the OR logic gate g1, the low power consumption mode control signal n2 is input to the first input terminal, the analysis control signal n3 is input to the second input terminal, and the output terminal is connected to the gate of the MOSFET m1. Thereby, it can be used for the use which specifies a defective location, and the use which prevents destruction of the memory content. Moreover, in the use which pinpoints a defective location, the failure analysis time can be shortened.

  (2) The microcomputer enters the analysis state when the analysis control signal n3 is at the H level. In this analysis state, it is possible to identify the position of the word line WL causing the defect by observing the physical phenomenon occurrence state of the word line WL through which a current flows by applying the analysis control signal n3.

  (3) The microcomputer enters the low power consumption mode when the analysis control signal n3 is at the L level and the low power consumption mode control signal n2 is at the H level. In this low power consumption mode, power supply to the circuits is stopped except for some circuits necessary for data retention, so that power consumption can be reduced.

  (4) The microcomputer enters the normal operation mode when the analysis control signal n3 is L level and the low power consumption mode control signal n2 is L level. In this normal operation mode, a normal operation by reading / writing data from / to the memory cell MC can be performed.

  (5) The analysis control signal n3 can be applied through a dedicated input / output pad I / O.

  (6) In the step (S4) of identifying the failure location inside the chip, a current is passed through each word line WL of the memory cell array 10 and the occurrence of a physical phenomenon is observed, thereby observing the occurrence of a defect in the word line WL. The position can be specified.

[Embodiment 2]
A semiconductor integrated circuit device and an analysis method thereof according to the second embodiment will be described with reference to FIG. In the second embodiment, differences from the first embodiment will be mainly described. FIG. 9 is a diagram for explaining a configuration of the entire chip including the RAM and the control signal wiring in the microcomputer according to the second embodiment.

  In the chip shown in FIG. 9, a RAM 1 including a MOSFET m1 (word line floating prevention transistor), an OR logic gate g1, a function setting register r1, and a CPU are mounted on the chip. Further, on the chip, a MOSFET control line n1 for connecting the gate electrode of the MOSFET m1 and the output of the OR logic gate g1, and a control line for the low power consumption mode control signal n2 connected to one input of the OR logic gate g1. And an analysis control signal n3 control line for connecting the other input of the OR logic gate g1 to the function setting register r1. The function setting register r1 and the CPU are connected by an internal bus n4.

  In the second embodiment, the output of the corresponding bit of the function setting register r1 provided on the chip is connected to the control line of the analysis control signal n3, and the ON / OFF of the MOSFET m1 is controlled via the OR logic gate g1. It becomes the composition which is done.

  In the analysis method according to the second embodiment, the setting value is written into the function setting register r1 using the CPU at the start of failure analysis. The set value at this time is a logical value that enables the analysis control signal n3 to turn on the MOSFET m1. As a result, the analysis control signal n3 becomes H level, passes through the OR logic gate g1, is transmitted to the MOSFET control line n1, and the MOSFET m1 is turned on.

  The function setting register r1 can also be used as an existing state setting bit used in the test mode.

  According to the semiconductor integrated circuit device and the analysis method thereof in the second embodiment described above, the same effect as in the first embodiment can be obtained. Further, according to the second embodiment, since the function setting register r1 is mounted on the chip, the analysis control signal n3 is applied from the function setting register r1 as an effect different from the first embodiment. be able to. The function setting register r1 can be set from a CPU provided in the microcomputer.

  Further, according to the second embodiment, the function setting register r1 is required to be operated in the analysis test pattern, but the analysis control signal n3 does not occupy the input / output pad I / O. It is no longer necessary to change the pin correspondence table of the control program of the logic tester, and existing analysis evaluation hardware can be used without change. In addition, it is easy to apply the technique in the second embodiment to a small pin product.

[Embodiment 3]
A semiconductor integrated circuit device and an analysis method thereof according to the third embodiment will be described with reference to FIG. In the third embodiment, differences from the first embodiment will be mainly described. FIG. 10 is a diagram for explaining a configuration in which a word line floating prevention MOSFET and an analysis evaluation MOSFET are connected to a word line in the microcomputer according to the third embodiment.

  The RAM 1 shown in FIG. 10 includes an N channel MOSFET m1 (word line floating prevention transistor) and an analysis evaluation P channel MOSFET m2. Similar to the N-channel MOSFET m1, the analysis-evaluation P-channel MOSFET m2 is connected to the far end of the word line WL with respect to the word line driver WD. The P-channel MOSFET m2 is connected between the power supply voltage and the word line WL, and the source electrode is connected to the power supply voltage and the drain electrode is connected to the word line WL. The control line for the analysis control signal n3 is connected to the gate electrode of the P-channel MOSFET m2 separately from the control line for the low power consumption mode control signal n2.

  As in the first embodiment, the N-channel MOSFET m1 is used without changing the comparison technique. The N-channel MOSFET m1 is connected between the word line WL and the ground voltage, the drain electrode is connected to the word line WL, and the source electrode is connected to the ground voltage. The control line of the low power consumption mode control signal n2 is connected to the gate electrode of the N-channel MOSFET m1.

  In the analysis method according to the third embodiment, the low power consumption mode control signal n2 is at the L level and the N-channel MOSFET m1 is in the OFF state because the low power consumption mode is not set during failure analysis. At this time, when the analysis control signal n3 is changed to the L level, the analysis evaluation P-channel MOSFET m2 is turned on, and the current I flows to the word line driver WD through the word line WL not performing the access operation. Thereby, photon emission and OBIRCH reaction are obtained in the MOSFET and wiring in the current path.

  For example, when the word line WL has a disconnection or a high resistance defect, the current I does not flow to the word line driver WD, and no photon emission or OBIRCH reaction can be obtained, so that a defective word line can be specified.

  In the low power consumption mode, the low power consumption mode control signal n2 is at the H level, and the N-channel MOSFET m1 is turned on. At this time, the analysis control signal n3 is at the H level, and the P-channel MOSFET m2 is in the OFF state.

  According to the semiconductor integrated circuit device and the analysis method thereof in the third embodiment described above, an analysis evaluation P-channel MOSFET m2 is connected to the word line WL instead of the OR logic gate g1 in the first embodiment. By controlling the control, the same effect as in the first embodiment can be obtained. More details are as follows.

  (1) The microcomputer has an N-channel MOSFET m1 and a P-channel MOSFET m2 connected to the word line WL of the memory cell array 10. In the N-channel MOSFET m1, a low power consumption mode control signal n2 is input to the gate, the source is connected to the ground voltage, and the drain is connected to the word line WL. In the P-channel MOSFET m2, the analysis control signal n3 is input to the gate, the source is connected to the power supply voltage, and the drain is connected to the word line WL. Thereby, it can be used for the use which specifies a defective location, and the use which prevents destruction of the memory content. Moreover, in the use which pinpoints a defective location, the failure analysis time can be shortened.

  (2) The microcomputer enters the analysis state when the analysis control signal n3 is at the L level and the low power consumption mode control signal n2 is at the L level. In this analysis state, it is possible to identify the position of the word line WL causing the defect by observing the physical phenomenon occurrence state of the word line WL through which a current flows by applying the analysis control signal n3.

  (3) The microcomputer enters the low power consumption mode when the analysis control signal n3 is at the H level and the low power consumption mode control signal n2 is at the H level. In this low power consumption mode, power supply to the circuits is stopped except for some circuits necessary for data retention, so that power consumption can be reduced.

[Embodiment 4]
A semiconductor integrated circuit device and an analysis method thereof according to the fourth embodiment will be described with reference to FIGS. In the fourth embodiment, differences from the first embodiment will be mainly described. FIG. 11 and FIG. 12 are diagrams for explaining the configuration of the entire chip including a plurality of RAMs and control signal wirings in the microcomputer according to the fourth embodiment. FIG. FIG. 12 shows a configuration in which the gate control signal of the word line floating prevention transistor is made common to a plurality of memories. The configuration shown in FIGS. 11 and 12 is a modification of the configuration of the first embodiment.

  In the chip shown in FIG. 11, a plurality (two examples in FIG. 11) of RAMs 1 and 2 including MOSFETs m1a and m1b (word line floating prevention transistors) on the chip, and OR logic gates g1a corresponding to the RAMs 1 and 2, respectively. , G1b. Further, on the chip, the MOSFET control lines n1a and n1b for connecting the gate electrodes of the MOSFETs m1a and m1b and the outputs of the OR logic gates g1a and g1b and the low consumption connected to one input of the OR logic gates g1a and g1b. A control line for the power mode control signal n2 and a control line for the analysis control signal n3 connected to the other input of the OR logic gates g1a and g1b are provided.

  In the configuration shown in FIG. 11, when there are a plurality of RAMs 1 and 2, the gate control signals of MOSFETs m1a and m1b are separated for each of RAMs 1 and 2. The low power consumption mode control signal n2 and the analysis control signal n3 are input to the OR logic gates g1a and g1b for each of the RAMs 1 and 2, and the MOSFET control lines n1a and m1b for controlling the MOSFETs m1a and m1b through the OR logic gates g1a and g1b. An n1b control signal is generated. In the analysis method in this configuration, control by the analysis control signal n3 can be performed as in the first embodiment.

  In the chip shown in FIG. 12, a plurality (two examples in FIG. 12) of RAMs 1 and 2 including MOSFETs m1a and m1b (word line floating prevention transistors) on the chip, and an OR logic gate g1 common to the RAMs 1 and 2 are used. And are installed. Further, on the chip, a MOSFET control line n1 for connecting the gate electrodes of the MOSFETs m1a and m1b and the output of the OR logic gate g1, and a low power consumption mode control signal n2 connected to one input of the OR logic gate g1. A control line and a control line for the analysis control signal n3 connected to the other input of the OR logic gate g1 are provided.

  In the configuration shown in FIG. 12, when there are a plurality of RAMs 1 and 2, the gate control signals of the MOSFETs m1a and m1b are commonly used by the plurality of RAMs 1 and 2. The low power consumption mode control signal n2 and the analysis control signal n3 are input to the OR logic gate g1 common to the RAMs 1 and 2, and the control signal of the MOSFET control line n1 for controlling the MOSFETs m1a and m1b through the OR logic gate g1. Is generated. In the analysis method in this configuration, control by the analysis control signal n3 can be performed as in the first embodiment.

  According to the semiconductor integrated circuit device and the analysis method thereof according to the fourth embodiment described above, the configuration in which a plurality of RAMs 1 and 2 including MOSFETs m1a and m1b are mounted on the chip is the same as in the first embodiment. The effect of can be obtained.

[Embodiment 5]
A semiconductor integrated circuit device and an analysis method thereof according to the fifth embodiment will be described with reference to FIG. In the fifth embodiment, differences from the first embodiment will be mainly described. FIG. 13 is a diagram for explaining a configuration of an entire chip in an example in which the microcomputer according to the fifth embodiment uses the control signal for analysis and the separate logic by using the I / O function switching function. The configuration shown in FIG. 13 is a modification of the configuration of the first embodiment.

  In the chip shown in FIG. 13, a RAM 1 including a MOSFET m1 (word line floating prevention transistor), an OR logic gate g1, an I / O function switching logic circuit b1, and a function block b2 are mounted on the chip. Further, on the chip, a MOSFET control line n1 for connecting the gate electrode of the MOSFET m1 and the output of the OR logic gate g1, and a control line for the low power consumption mode control signal n2 connected to one input of the OR logic gate g1. A control line for the analysis control signal n3 that connects the other input of the OR logic gate g1 and the I / O function switching logic circuit b1, and a wiring that connects the I / O function switching logic circuit b1 and the function block b2 n4. The input of the I / O function switching logic circuit b1 is connected to the common input / output pad I / O.

  In the configuration shown in FIG. 13, the I / O function switching logic circuit b1 having the same function as the general microcomputer I / O function switching is used, and the analysis control signal n3 is evaluated by the RAM instead of the dedicated input / output pad. A wiring n4 is connected to the common input / output pad I / O only occasionally. The I / O function switching logic circuit b1 switches the analysis control signal n3 and the wiring n4 connected to the separate function block b2 to connect to the common input / output pad I / O. This switching is performed by setting a control logic in the I / O function switching logic circuit b1.

  In the analysis method in the configuration shown in FIG. 13, the I / O function switching logic circuit b1 switches to the analysis control signal n3 and connects to the common input / output pad I / O at the time of RAM evaluation. In the same manner as described above, control using the analysis control signal n3 can be performed.

  According to the semiconductor integrated circuit device and the analysis method thereof in the fifth embodiment described above, the I / O function switching logic circuit b1 switches between the analysis control signal n3 and the wiring n4 connected to the separate functional block b2. The same effect as that of the first embodiment can be obtained in the configuration connected to the common input / output pad I / O. Further, in the configuration shown in FIG. 13, it is possible to avoid the influence on the number of pins that can be used by the user.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

m1, m1a, m1b MOSFET
g1, g1a, g1b OR logic gates n1, n1a, n1b MOSFET control line n2 Low power consumption mode control signal n3 Control signal for analysis

Claims (15)

A memory cell array including a plurality of memory cells and a plurality of word lines;
A plurality of transistors connected to the plurality of word lines;
A logic circuit connected to the plurality of transistors;
Have
The semiconductor integrated circuit device, wherein the logic circuit has a control signal input to a first input terminal, an analysis control signal input to a second input terminal, and an output terminal connected to the gate of the transistor. The semiconductor integrated circuit device according to claim 1.
The logic circuit is an OR circuit having the first input terminal, the second input terminal, and the output terminal;
In the semiconductor integrated circuit, the control signal is input to the first input terminal, the analysis control signal is input to the second input terminal, and the output terminal is connected to the gate of the transistor. Circuit device. The semiconductor integrated circuit device according to claim 2.
The semiconductor integrated circuit device is in an analysis state when the analysis control signal is at a first voltage level. The semiconductor integrated circuit device according to claim 3.
A semiconductor integrated circuit device, wherein in the analysis state, a position of a word line causing a defect is specified by observing a physical phenomenon occurrence state of a word line through which a current flows by applying the analysis control signal. The semiconductor integrated circuit device according to claim 4.
The semiconductor integrated circuit device is in a low power consumption mode when the control signal for analysis is at a second voltage level different from the first voltage level and the control signal is at the first voltage level. . The semiconductor integrated circuit device according to claim 5.
The semiconductor integrated circuit device is in a normal operation mode when the analysis control signal is at the second voltage level and the control signal is at the second voltage level. The semiconductor integrated circuit device according to claim 2.
The analysis control signal is applied through a dedicated input / output pad. The semiconductor integrated circuit device according to claim 2.
The semiconductor integrated circuit device, wherein the analysis control signal is applied from a function setting register inside the semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 8.
The function setting register is a semiconductor integrated circuit device set from a CPU provided in the semiconductor integrated circuit device. A memory cell array including a plurality of memory cells and a plurality of word lines;
A plurality of first transistors and a plurality of second transistors connected to the plurality of word lines;
Have
The first transistor has a gate receiving a control signal, a source connected to a ground voltage, a drain connected to the word line,
The second transistor is a semiconductor integrated circuit device, wherein an analysis control signal is input to a gate, a source is connected to a power supply voltage, and a drain is connected to the word line. The semiconductor integrated circuit device according to claim 10.
The first transistor is an N-channel MOSFET;
The semiconductor integrated circuit device, wherein the second transistor is a P-channel MOSFET. The semiconductor integrated circuit device according to claim 11.
The semiconductor integrated circuit device is in an analysis state when the analysis control signal is at a first voltage level and the control signal is at the first voltage level. The semiconductor integrated circuit device according to claim 12, wherein
A semiconductor integrated circuit device, wherein in the analysis state, a position of a word line causing a defect is specified by observing a physical phenomenon occurrence state of a word line through which a current flows by applying the analysis control signal. The semiconductor integrated circuit device according to claim 13.
The semiconductor integrated circuit device is in a low power consumption mode when the analysis control signal is at a second voltage level different from the first voltage level and the control signal is at the second voltage level. . A method for analyzing a semiconductor integrated circuit device having a memory cell array including a plurality of memory cells and a plurality of word lines,
A method for analyzing a semiconductor integrated circuit device, comprising a step of identifying a position of a word line causing a defect by passing a current through each word line of the memory cell array and observing a state of occurrence of a physical phenomenon.

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