JP2016201155A - Semiconductor device and control method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time for setting selection information in a holding section without increasing the circuit scale of a semiconductor device.SOLUTION: A semiconductor device comprises: a plurality of circuit blocks each including a plurality of internal circuits, and a selection section for selecting an internal circuit to be used from the plurality of internal circuits based on selection information; a storage section that stores selection information to be supplied to a selection section of a change circuit block, the change circuit block which is a circuit block in which the selection states of the plurality of internal circuits are changed from an initial state, from the plurality of circuit blocks; a plurality of holding sections provided corresponding respectively to the plurality of circuit blocks, connected in the order corresponding to a circuit block the selection state of which is highly likely to be changed from the initial state, and holding selection information to be supplied to the selection section of the plurality of circuit blocks; and a control section that sequentially transfers the selection information stored in the storage section to a holding section of the plurality of holding sections, corresponding to the change circuit block.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for controlling the semiconductor device.

  In a semiconductor memory device, the yield which is a non-defective product rate is improved by switching a defective memory cell to a redundant memory cell. For example, in a semiconductor memory device including a plurality of memory blocks, a shift register storing defect information for repairing a defect is provided corresponding to each memory block, and the shift registers are connected in series via a selector. The shift register corresponding to the memory block having no defect is separated from the transfer path for transferring the defect information indicating the defective memory cell by the selector, and the defect information is transferred only to the shift register corresponding to the memory block having the defect. . Each memory block switches a defective memory cell to a redundant memory cell based on information held in the shift register. Thereby, compared with the case where the shift register corresponding to the memory block having no defect is not separated from the transfer path, the defective memory cell is switched to the redundant memory cell with a small amount of information (for example, see Patent Document 1).

  In a semiconductor device including a plurality of memory macros, defective address information indicating a defective position is transferred from a fuse box to a memory macro via a common fuse bus. Thereby, the scale of the circuit for transferring the defective address information to the memory macro is reduced as compared with the case where the defective address information is individually transferred to the memory macro (see, for example, Patent Document 2).

  Further, the semiconductor memory device replaces the defective memory cell with a redundant memory cell by decoding the defective address information received from the fuse circuit using a decoding circuit that identifies the position of the defective memory cell. In this case, by setting the address assigned to the decoding circuit so that the number of fuse elements to be cut is reduced, the fuse element cutting time is shortened compared to the case where addresses are sequentially assigned to the decoding circuit ( For example, see Patent Document 3).

JP 2013-30238 A JP 2006-107590 A JP 2005-222658 A

  When a shift register to which defect information is transferred is provided corresponding to each memory block, the position of the shift register to which the defect information is transferred changes depending on the defect status. For example, when a defect exists in the memory block corresponding to the terminal shift register, the defect information is transferred to the terminal shift register through all other shift registers. Further, when a shift register corresponding to a memory block having no defect is separated from a transfer path by a selector, the selector and a signal wiring for supplying information for controlling the selector to the selector are provided in the semiconductor memory device. The circuit scale increases.

  An object of the semiconductor device and the method for controlling the semiconductor device disclosed herein is to reduce the time for setting selection information in a holding unit without increasing the circuit scale of the semiconductor device.

  According to one aspect, a semiconductor device includes a plurality of circuit blocks each including a plurality of internal circuits, a selection unit that selects an internal circuit to be used among the plurality of internal circuits based on selection information, and a plurality of circuits Among the blocks, a storage unit that stores selection information supplied to a selection unit of a change circuit block that is a circuit block that changes a selection state of a plurality of internal circuits from an initial state, and a plurality of circuit blocks are provided correspondingly A plurality of holding units that are connected in the order corresponding to the circuit blocks having a high probability of changing the selection state from the initial state, and that respectively hold selection information supplied to the selection units of the plurality of circuit blocks, and a plurality of holding units And a controller that sequentially transfers the selection information stored in the storage unit to the holding unit corresponding to the changed circuit block.

  According to another aspect, a plurality of circuit blocks each including a plurality of internal circuits and a selection unit that selects an internal circuit to be used among the plurality of internal circuits based on selection information, and respectively correspond to the plurality of circuit blocks A plurality of holding units that are connected in the order corresponding to the circuit blocks having a high probability of changing the selection state of the plurality of internal circuits from the initial state, and that respectively hold selection information supplied to the selection units of the plurality of circuit blocks A method for controlling a semiconductor device including: selection information supplied from a storage unit to a selection unit of a change circuit block that is a circuit block that changes a selection state of a plurality of internal circuits from an initial state among a plurality of circuit blocks The read and read selection information is sequentially transferred to a holding unit corresponding to the changed circuit block among the plurality of holding units.

  In one aspect, the semiconductor device and the method for controlling the semiconductor device disclosed herein can reduce the time for setting selection information in the holding unit without increasing the circuit scale of the semiconductor device.

It is a figure which shows one Embodiment of the control method of a semiconductor device and a semiconductor device. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device. FIG. 3 is a diagram illustrating an example of a shift register illustrated in FIG. 2. FIG. 3 is a diagram illustrating an example of a memory illustrated in FIG. 2. It is a figure which shows an example of the defect condition of the memory shown in FIG. 2, and the information programmed by the program part. FIG. 3 is a diagram illustrating an example of an operation flow for setting defect information in the scan chain illustrated in FIG. 2. FIG. 7 is a diagram illustrating an example (continuation of FIG. 6) of an operation flow for setting defect information in the scan chain illustrated in FIG. 2. It is a figure which shows an example of the operation | movement which sets defect information to the scan chain shown in FIG. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device. It is a figure which shows an example of the defect condition of the memory shown in FIG. 9, and the information programmed by the program part. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device. It is a figure which shows an example of the adjustment circuit which is mounted in each memory shown in FIG. 11, and adjusts the operation timing of the control circuit in each memory. It is a figure which shows an example of the operation timing of the control circuit in the memory shown in FIG. 11, and the information programmed in a program part. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device. It is a figure which shows an example of the operation timing of the control circuit in the memory shown in FIG. 14, and the information programmed in a program part. It is a figure which shows an example of the clock control part shown in FIG. It is a figure which shows an example of operation | movement of the clock control part shown in FIG. It is a figure which shows an example of the shift register shown in FIG. FIG. 19 is a diagram illustrating an example of operation of the shift register illustrated in FIG. 18. It is a figure which shows an example of the operation | movement flow which sets defect information to the scan chain shown in FIG. FIG. 15 is a diagram illustrating an example of operation flow for setting defect information in the scan chain illustrated in FIG. 14 (continuation of FIG. 20). It is a figure which shows an example of the operation | movement which sets defect information to the scan chain shown in FIG. It is a figure which shows an example of the adjustment circuit which is mounted in each circuit block in a semiconductor device, and adjusts the voltage used with a circuit block.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a semiconductor device and a method for controlling the semiconductor device. The semiconductor device SEM1 of this embodiment includes a plurality of circuit blocks CBLK (CBLK1, CBLK2, CBLK3, CBLK4), a plurality of holding units HLD (HLD1, HLD2, HLD3, HLD4), a control unit CNTL, and a storage unit MEM.

  Each circuit block CBLK includes a plurality of internal circuit ICs (IC1, IC2) and a selection unit SEL (SEL1, SEL2, SEL3, SEL4) that selects an internal circuit IC used in the circuit block CBLK based on selection information. . The holding unit HLD holds selection information SINT or selection information SI (SI1, SI2). The selection information SINIT is initial selection information held in the holding units HLD1 to HLD4, and the selection information SI1 and SI2 are selection information newly held by the holding units HLD1 and HLD2 that hold the selection information SINIT.

  For example, the selection unit SEL1 selects the internal circuit IC1 when receiving the selection information SINIT from the holding unit HLD1, and selects the internal circuit IC2 when receiving the selection information SI1 from the holding unit HLD1. Similarly, the selection units SEL2-SEL4 select the internal circuit IC1 when receiving selection information SINIT from the holding units HLD2-HLD4, respectively, and receive the selection information SI2-SI4 from the holding units HLD2-HLD4. The circuit IC2 is selected. The circuit block CBLK operates using the internal circuit IC selected by the selection unit SEL.

  In the example illustrated in FIG. 1, the selection unit SEL1 selects the internal circuit IC2 based on the selection information SI1, the selection unit SEL2 selects the internal circuit IC2 based on the selection information SI2, and the selection units SEL3 and SEL4 are Based on the selection information SINIT, the internal circuit IC1 is selected. The internal circuit IC selected by the selection units SEL1-SEL4 is indicated by a thick frame. The state in which the internal circuit IC1 is selected by the selection information SINIT is an initial state, and the state in which the internal circuit IC2 is selected by the selection information SI1 and SI2 is a changed state that is changed from the initial state.

  Each holding unit HLD is provided corresponding to each circuit block CBLK, and is connected to the control unit CNTL in the order corresponding to the circuit block having a high probability of changing the selection state of the internal circuit IC from the initial state. That is, the probability of changing the selection state of the internal circuit IC from the initial state is higher in the order of the circuit blocks CBLK1, BCLK2, CBLK3, and CBLK4. Each holding unit HLD holds selection information (SINIT or SI1, SI2) set in the selection unit SEL of the circuit block CBLK.

  The storage unit MEM stores selection information SI (SI1, SI2) set in the circuit block CBLK that changes from an initial state in which the internal circuit IC1 is selected to a selection state in which the internal circuit IC2 is selected. In the example illustrated in FIG. 1, the selection state of the circuit blocks CBLK3 and CBLK4 is not changed from the initial state. Therefore, the selection information SI3 and SI4 for changing the selection state of the circuit blocks CBLK3 and CBLK4 is not stored in the storage unit MEM. For example, the circuit block CBLK that changes the selected state from the initial state is determined by a test apparatus that tests the semiconductor device SEM1. The test apparatus stores selection information in the storage unit MEM based on the test result.

  The control unit CNTL reads selection information SI2 and SI1 set in the selection unit SEL of the circuit block CBLK that changes the selection state of the internal circuit IC from the initial state among the plurality of circuit blocks CBLK from the storage unit MEM. The control unit CNTL sequentially transfers the read selection information SI2 and SI1 to the holding units HLD1 and HLD2 corresponding to the circuit block CBLK (in this example, CBLK1 and CBLK2) that changes the selection state of the internal circuit IC from the initial state. To do.

  The probability of changing the selected state from the initial state is higher in the order of the circuit blocks CBLK1, CBLK2, CBLK3, and CBLK4. Therefore, the selection information SI is transferred to change the selection state from the initial state, compared to the case where the holding unit HLD corresponding to the circuit block CBLK is connected without considering the probability of changing the selection state from the initial state. The number of holding parts HLD to be performed can be reduced. As a result, the time required for setting the setting information SI1 and SI2 in the holding unit HLD before operating the semiconductor device SEM1 can be reduced as compared with the case where the probability of changing the selected state from the initial state is not considered.

  For example, the probability of changing the selected state from the initial state is higher as the area of the circuit block CBLK is larger. In this case, the area of the circuit block CBLK is larger in the order of CBLK1, CBLK2, CBLK3, and CBLK4, and the holding units HLD1 to HLD4 are connected to the control unit CNTL in the order corresponding to the circuit blocks CBLK1 to CBLK4 having the larger area. Alternatively, the probability that the selected state is changed from the initial state is higher as the timing margin of the circuit block CBLK is smaller or as the voltage margin of the circuit block CBLK is smaller. An example in which the probability of changing the selection state of the internal circuit IC from the initial state depends on the area of the circuit block CBLK will be described with reference to FIGS. An example in which the probability of changing the selection state of the internal circuit IC from the initial state depends on the timing margin of the circuit block CBLK will be described with reference to FIGS. An example in which the probability of changing the selection state of the internal circuit IC from the initial state depends on the voltage margin of the circuit block CBLK will be described with reference to FIG.

  As described above, in the embodiment illustrated in FIG. 1, the holding unit HLD is connected to the control unit CNTL in descending order of the probability of changing the selection state of the internal circuit IC from the initial state. Accordingly, the selection state of all the circuit blocks CBLK can be set by transferring the setting information to a predetermined number of holding units HLD located on the side closer to the control unit CNTL. As a result, when setting the selection state of the circuit block CBLK by sequentially transferring the selection information SI to the plurality of holding units HLD connected in series, the time until the setting information SI is set in the holding unit HLD. Can be shortened compared to the conventional case. Therefore, it is possible to shorten the time until the operation of the semiconductor device SEM1 becomes possible (for example, the start-up time) compared to the conventional case.

  In addition, since it is not necessary to provide an area for holding setting information to be set in the holding unit HLD corresponding to the selection unit SEL of all the circuit blocks CBLK in the storage unit MEM, the circuit scale of the storage unit MEM is reduced as compared with the conventional case. be able to. Further, the control unit CNTL transfers the selection information SI to the selection unit SEL of each circuit block CBLK via the holding units HLD connected in series. For this reason, the number of signal lines can be reduced as compared with the case where the selection information SI is transferred in parallel from the control unit CNTL to the selection unit SEL of each circuit block CBLK using a plurality of bus lines. Therefore, the circuit scale of the semiconductor device SEM1 including the plurality of circuit blocks CBLK whose selection state is changed can be reduced as compared with the conventional one. As a result, the time for setting the defect information in the holding unit HLD can be shortened without increasing the circuit scale of the semiconductor device SEM1.

  FIG. 2 shows another embodiment of the semiconductor device and the method for controlling the semiconductor device. The semiconductor device SEM2 of this embodiment includes an operation control unit 10, a transfer control unit 20, a program unit 30, a scan chain SCANC, and a plurality of memories M (in the example shown in FIG. 2, M1, M2, M3,..., M10).

  The memories M1 to M10 are semiconductor memories such as an SRAM (Static Random Access Memory) or a ferroelectric memory, and have a redundant circuit that relieves defects generated in the manufacturing process. Memory M1-M10 is an example of a circuit block. The memory M1 has a larger area than the memory M2, the memory M2 has a larger area than the memory M3, and the memory M10 has a smaller area than the other memories M. That is, the area of the memory M connected to the side closer to the transfer control unit 20 upstream of the scan chain SCANC is the area of the memory M connected to the side farther from the transfer control unit 20 downstream of the scan chain SCANC. Bigger than Of the memories M1 to M10, the areas of a predetermined number of memories M arranged adjacent to each other may be equal to each other.

  For example, since the semiconductor device SEM2 (semiconductor chip) is manufactured using a common semiconductor process, the defect densities of the memories M1-M10 are the same. For this reason, the number of defects included in the memory M increases as the area of the memory M increases, and the probability (possibility) that a defect occurs in the memory M increases as the area increases. In this embodiment, the area of the memory M is larger as the memory M is connected to the shift register SR located upstream of the scan chain SCANC. For this reason, the probability that a defect occurs in the memory M is higher as the memory M is connected to the shift register SR closer to the transfer control unit 20. In other words, the probability of using the redundant circuit (redundant memory cell unit RMC shown in FIG. 4) for relieving a defect is higher in the memory M connected to the shift register SR closer to the transfer control unit 20.

  In the scan chain SCANC, the first stage is connected to the transfer control unit 20, and a plurality of shift registers SR (in the example shown in FIG. 2, SR1, SR2, SR3,..., SR10 in the example shown in FIG. 2) are connected. Have. Shift registers SR1-SR10 are provided corresponding to memories M1-M10, respectively, and connected to corresponding memories M1-M10, respectively. That is, the shift registers SR1 to SR10 are connected to the transfer control unit 20 in the order corresponding to the memories M1 to M10 that have a high probability of occurrence of defects. The shift registers SR1 to SR10 are examples of holding units that respectively hold defect information supplied to the redundancy changeover switches RSW (FIG. 4) of the memories M1 to M10.

  Each shift register SR1-SR10 includes a predetermined number (for example, seven) of flip-flop circuits connected in series. Each flip-flop circuit of the shift registers SR1-SR10 is set to an initial value (default value) in synchronization with the reset signal RST. Shift registers SR1-SR10 hold data DT in synchronization with scan clock signal SCLK, and sequentially transfer the held data DT from the upstream side to the downstream side. The data DT includes a defect code CD for relieving a defect in the memory M and a redundancy enable bit REN indicating that a defect exists in the memory M. The defective code CD and the redundancy enable bit REN are examples of selection information. An example of the operation of the scan chain SCANC is shown in FIG.

  The transfer control unit 20 includes counters FLINE, IRAM, ICB, a reset generation unit RSTGEN1, and a clock generation unit CLKGEN1. The reset generation unit RSTGEN1 generates a reset signal RST based on the activation signal PON. The clock generation unit CLKGEN1 generates the scan clock signal SCLK after the selection information held in the shift registers SR1-SR10 is reset to the initial value by the reset signal RST. Here, the initial value set in each of the shift registers SR1 to SR10 is a value indicating that there is no defect in the memory M corresponding to each shift register SR and that the repair process for the defect in the memory M is not executed. Then, the transfer control unit 20 transfers data DT (selection information) to the scan chain SCANC based on the information programmed in the program unit 30 in synchronization with the scan clock signal SCLK. After transferring the data DT to the scan chain SCANC, the transfer control unit 20 stops generating the scan clock signal SCLK and outputs the operation enable signal OPE to the operation control unit 10.

  The counters FLINE, IRAM, and ICB are used when data DT is transferred to the scan chain SCANC based on information programmed in the program unit 30. An example of using the counters FLINE, IRAM, and ICB will be described with reference to FIGS. The transfer control unit 20 is an example of a control unit that sequentially transfers selection information stored in the program unit 30 to the shift register SR corresponding to the memory M that repairs a defect. Examples of the operation of the transfer control unit 20 are shown in FIGS.

  The program unit 30 includes a plurality of program elements in which information is programmed by a program signal PGM. The program element is a nonvolatile storage element such as a fuse circuit, a flash memory, or a ferroelectric memory. An example of the program unit 30 is shown in FIG.

  The operation control unit 10 includes a power supply control unit 12. The operation control unit 10 controls the entire operation of the semiconductor device SEM2. The power supply control unit 12 generates a power supply voltage IVDD to be supplied to the functional block mounted on the semiconductor device SEM2, and activates the function block based on the supply of the power supply voltage IVDD to the functional block. Is output. The memories M1-M10 are a kind of functional blocks. The power supply voltage IVDD is supplied to a circuit region including at least the memories M1-M10 and the shift registers SR1-SR10.

  Note that, instead of generating the power supply voltage IVDD, the power supply control unit 12 may generate a voltage control signal for controlling a power supply generation circuit that generates the power supply voltage IVDD. For example, the power supply voltage IVDD is an internal power supply voltage generated in the semiconductor device SEM2 using an external power supply voltage supplied to the semiconductor device SEM2.

  For example, the semiconductor device SEM2 includes functional blocks such as a CPU (Central Processing Unit), a peripheral circuit, and an input / output interface circuit, in addition to the memory M illustrated in FIG. The peripheral circuits are a DMAC (Direct Memory Access Controller), a timer, an image processing circuit, and the like. That is, the semiconductor device SEM2 is a SoC (System on a Chip). When the semiconductor device SEM2 includes a plurality of functional blocks, the power supply control unit 12 may control the power supply voltage for each predetermined number of functional blocks, or may output the activation signal PON for each predetermined number of functional blocks. . After outputting the activation signal PON, the operation control unit 10 recognizes that the memories M1-M10 are operable based on the operation enable signal OPE from the transfer control unit 20, and makes the memories M1-M10 accessible. Notify the CPU or the like.

  For example, the activation signal PON is set to an inactive level during the sleep mode in which the operation of the functional blocks including the memories M1-M10 and the shift registers SR1-SR10 is stopped, and is based on the transition from the sleep mode to the normal operation mode. To set the activation level. In this case, the power supply control unit 12 stops supplying the power supply voltage IVDD to the circuit area including the memories M1-M10 and the shift registers SR1-SR10 during the sleep mode. Then, based on the return from the sleep mode to the normal operation mode, the power supply control unit 12 sets the activation signal PON to the activation level after the power supply voltage IVDD exceeds a predetermined value.

  For example, when the memories M1 and M2 have a defect and the memories M3-M10 do not include a defect, the redundancy enable bits REN of the shift registers SR3-SR10 corresponding to the memories M3-M10 are initially set to a logic that does not use a redundancy circuit. (Reset). Thereby, the setting of the data DT in the shift registers SR3-SR10 can be omitted. As a result, the time from when the activation signal PON is output until the memories M1-M10 can be operated can be shortened as compared with the case where data is set in all the shift registers SR1-SR10.

  FIG. 3 shows an example of the shift register SR1 shown in FIG. Shift registers SR2-SR10 have the same configuration as shift register SR1 shown in FIG.

  The shift register SR1 has a plurality of flip-flop circuits FF connected in series. Each flip-flop FF receives a reset signal RST at a reset terminal RESET and receives a scan clock signal SCLK at a clock terminal CK. The first flip-flop circuit FF receives data DT output from the transfer control unit 20 at the data input terminal D, and the second and subsequent flip-flop circuits FF receive the data of the previous flip-flop circuit FF at the data input terminal D. Data output from the output terminal Q is received. Data output from the data output terminal Q of the flip-flop circuit FF at the final stage is output to the shift register SR2.

  After predetermined defect information is set in the shift register SR1, the flip-flop circuits FF except the final flip-flop circuit FF output the defect code CD to the memory M1. The flip-flop circuit FF at the final stage outputs the value of the redundancy enable bit REN to the memory M1. Note that the shift registers SR1-SR10 may include a master-slave flip-flop circuit MSFF1 shown in FIG. 18 instead of the flip-flop circuit FF.

  FIG. 4 shows an example of the memory M1 shown in FIG. Memory M2-M10 has the same configuration as memory M1 shown in FIG. 4 except that the areas are different.

  The memory M1 has an address decoder ADEC, a memory cell array ARY, a redundancy changeover switch RSW, and 64 data input / output terminals IO (IO0 to IO63). The address decoder ADEC decodes the address signal AD output from the CPU or the like, and sets one of the word lines WL (WL0, WL1, WL2, WL3, WL4,...) Indicated by the address AD to the activation level. To do.

  The memory cell array ARY is used in place of the memory cell unit MC (MC0, MC1, MC2, MC3,..., MC62, MC63) corresponding to each data input / output terminal IO and the memory cell unit MC. A redundant memory cell portion RMC. The memory cell units MC0 to MC63 have a plurality of memory cells connected to each word line WL, and the redundant memory cell unit RMC is connected to each word line WL and a plurality of memory cell units having a defect are relieved. It has redundant memory cells. Each of memory cell portions MC0-MC63 and redundant memory cell portion RMC is an example of an internal circuit.

  The redundancy changeover switch RSW includes a plurality of switches for switching the memory cell unit MC to which the input / output terminals IO0 to IO63 are connected and the redundancy memory cell unit RMC based on the defective code CD and the redundancy enable bit REN held in the shift register SR1. Have. The redundancy changeover switch RSW is an example of a selection unit that selects the memory cell unit MC and the redundant memory cell unit RMC to be used from the memory cell unit MC and the redundant memory cell unit RMC based on the defective code CD and the redundancy enable bit REN. It is.

  With the shift registers SR1-SR10 reset by the reset signal RST, the redundancy changeover switch RSW sets the initial state in which the data input / output terminals IO0-IO63 are connected to the memory cell units MC0-MC63, respectively. That is, in the initial state, each memory M is set to a state in which no defect exists and the redundant memory cell unit RMC is not used. Thereafter, the defect code CD indicating the defect in the memory cell array ARY and the redundancy enable bit REN are supplied to the redundancy changeover switch RSW via the shift register SR. Then, the redundancy changeover switch RSW switches the connection state between the memory cell units MC0 to MC63 and the redundant memory cell unit RMC and the data input / output terminals IO0 to DO63, and the defect of the memory cell array ARY is relieved.

  In the example shown in FIG. 4, the redundancy changeover switch RSW operates based on the failure code CD and the redundancy enable bit REN, and the failure (indicated by X) of the memory cell connected to the word line WL4 in the memory cell portion MC2 is relieved. Is done. That is, the data input / output terminal IO2 is connected to the memory cell part MC3, the data input / output terminals IO61 and IO62 are connected to the memory cell parts MC62 and MC63, respectively, and the data input / output terminal IO63 is connected to the redundant memory cell part RMC. . As described above, the data input / output terminals IO0 to IO63 are connected to the memory cell array ARY while avoiding the memory cell portion MC2 including the defect, so that the defect of the memory M1 is relieved.

  FIG. 5 shows an example of the failure status of the memories M1 to M10 shown in FIG. For example, the failure of the memories M1 to M10 is detected by a test apparatus such as an LSI (Large Scale Integration) tester that tests the semiconductor device SEM2. The test apparatus stores the defect data FDT for each of the memories M1-M10 identified by the memory number MN based on the test result of the memories M1-M10. In FIG. 5, for easy understanding, the memory M corresponding to the memory number MN is shown in parentheses on the right side of the memory number MN. The test apparatus stores, as the defect data FDT, the number indicating the memory cell portion MC that repairs the defect when there is a defect that can be relieved in the memory M, and information indicating “good product” when there is no defect in the memory M. Is stored as defective data FDT.

  In the example shown in FIG. 5, the defect exists in the memory cell unit MC2 of the memory M1, the memory cell unit MC10 of the memory M2, and the memory cell unit MC22 of the memory M6, and the memories M3-M5 and M7-M10 have There is no defect. In the following description, it is assumed that a defect that is difficult to repair, such as a defect in a plurality of memory cell portions MC, does not occur.

  The test apparatus outputs the program signal PGM shown in FIG. 2 to the program unit 30 and programs information in the program unit 30 based on the failure status of the memories M1 to M10.

  The program unit 30 stores a storage area for storing the difference FDIF of the memory number MN of the memory M in which the failure has occurred, a storage area for storing the failure code CD that is the number of the defective memory cell unit MC, and the redundancy enable bit REN. A plurality of rows including a storage area for storing logic. The program unit 30 is an example of a storage unit that stores defect information (defective code CD and redundant enable bit REN) supplied to the memory M that repairs a defect among the memories M1 to M10. Among the memories M1 to M10, the memory M whose defect is remedied is changed from the initial state in which the redundant memory cell unit RMC is not selected to the selected state in which the redundant memory cell unit RMC is selected by the redundant selector switch RSW shown in FIG. It is an example of a change circuit block.

  In the program unit 30, the storage areas for storing the logic of the defective code CD and the redundant enable bit REN, respectively, store the defective code CD and the redundant enable bit REN that are selection information supplied to the memory M for repairing the defect. This is an example of the storage area. In the program unit 30, the storage area for storing the differential FDIF is an example of a second storage area for storing the differential FDIF indicating the interval between the two shift registers SR corresponding to the memory M for repairing a defect. The difference FDIF is an example of interval information. Since the line of the program part 30 is identified by the value of the counter FLINE, the line of the program part 30 is indicated below using the symbol FLINE.

  The defective code CD is 6 bits for identifying the 64 memory cell portions MC0 to MC63, and is the sum of the number of bits of the defective code CD and the redundant enable bit REN (stored in each shift register SR1-SR10). The number of information bits is 7 bits. As shown in FIG. 7, in order to set the defective code CD and the redundant enable bit REN in each shift register SR, the code bit number NCB which is the maximum value set in the counter ICB shown in FIG. 6 ″. The number of code bits NCB indicates the number of shifts for storing information such as the defect code CD and the redundancy enable bit REN in each shift register SR1-SR10.

  First, the test apparatus calculates a difference (“4”) between the largest memory number MN (= 6) and the second largest memory number MN (= 2) among the memory numbers MN indicating the defective memory M. Then, the difference FDIF is stored in the first line FLINE0. The test apparatus stores a value (binary number “010110”) indicating the defective memory cell portion MC22 of the memory M6 corresponding to the largest memory number MN in the area of the defective code CD in the row FLINE0. The test apparatus stores “1” in the area of the redundancy enable bit REN in the row FLINE0, which indicates that the defect is to be relieved (the redundancy memory cell unit RMC is used).

  Next, the test apparatus compares the difference (“1”) between the second largest memory number MN (= 2) and the third largest memory number MN (= 1) among the memory numbers MN indicating the defective memory M. ) And is stored in the differential FDIF area in the second row FLINE1. The test apparatus stores a value (binary number “001010”) indicating the defective memory cell part MC10 of the memory M2 corresponding to the second largest memory number MN in the area of the defective code CD in the row FLINE1. The test apparatus stores “1” in the area of the redundancy enable bit REN in the row FLINE1.

  The test apparatus stores the same value as the memory number MN in the area of the difference FDIF in the row FLINE2 as the difference with respect to the smallest memory number MN (= 1) among the memory numbers MN indicating the defective memory M. The test apparatus stores a value (“000010” in binary number) indicating the defective memory cell part MC2 of the memory M1 corresponding to the smallest memory number MN in the area of the defective code CD in the row FLINE2. The test apparatus stores “1” in the area of the redundancy enable bit REN in the row FLINE2. As described above, the value of the difference FDIF, the defect code CD, and the redundancy enable bit REN are sequentially stored in the row FLINE in the order of the memory number MN. And the program of the program part 30 by a test apparatus is completed. In the program unit 30, an unprogrammed area indicates “0”.

  If the memories M2, M3, and M6 are defective and the other memories M1, M4, M5, and M7 to M10 are non-defective, the difference FDIF area in the row FLINE0 has the memory number MN of the memories M6 and M3. “3” indicating the difference is stored. In the area of the difference FDIF in the row FLINE1, “1” indicating the difference between the memory numbers MN of the memories M3 and M2 is stored. In the differential FDIF area of the line FLINE2, “2” indicating the memory number MN of the memory M2 is stored.

  In the example shown in FIG. 5, the program unit 30 has five rows FLINE0 to FLINE5. Therefore, if there are defects in more than five memories M, the program unit 30 lacks an area for storing information indicating defects. . In this case, the test apparatus processes the semiconductor device SEM2 as a defective product. By increasing the number of rows FILNE provided in the program unit 30, it is possible to increase the number of memories M for repairing defects. Note that the line LINE included in the program unit 30 may be 2 or more and less than the number of memories M (= 10).

  6 and 7 show an example of an operation flow for setting defect information in the scan chain SCANC shown in FIG. Here, the defect information is a defect code CD and a redundancy enable bit REN stored in the program unit 30 shown in FIG. The process shown in FIGS. 6 and 7 shows a control method of the semiconductor device SEM2, and is executed by the transfer control unit 20 shown in FIG. The processing illustrated in FIGS. 6 and 7 is executed using the hardware of the transfer control unit 20, but may be executed using software when the transfer control unit 20 includes a processor such as a CPU.

  First, in step S <b> 100, the transfer control unit 20 waits for reception of the activation signal PON from the power supply control unit 12. When the activation signal PON is received, in step S102, the transfer control unit 20 initializes the counters FLINE, IRAM, and ICB to “0”. Next, in step S104, the transfer control unit 20 outputs a reset signal RST to the shift registers SR1-SR10. Shift registers SR1-SR2 are initialized to default values based on reset signal RST. For example, the default value is a value at which the relief process of the memories M1 to M10 is not executed, and is all “0”, for example.

  Next, in step S106, the transfer control unit 20 reads the differential FDIF, the defective code CD, and the redundancy enable bit REN stored in the row LINE of the program unit 30 indicated by the value of the counter FLINE. Next, in step S108, when the read differential FDIF indicates “0”, the transfer control unit 20 determines that the defect information has been set in the scan chain SCANC, and the process proceeds to step S126 illustrated in FIG. Transition. On the other hand, when the read difference FDIF indicates a value other than “0” (positive value), the transfer control unit 20 shifts the process to step S110 illustrated in FIG. 7 in order to set defect information in the scan chain SCANC.

  In step S110 of FIG. 7, the transfer control unit 20 sets the value indicated by the differential FDIF acquired in step S106 in the counter IRAM. Next, in step S112, the transfer control unit 20 increments the counter ICB until the value of the counter ICB reaches the shift number NCB (= “6”), and sends the redundancy enable bit REN and the defect code CD to the scan chain SCCANC. Forward. That is, the transfer control unit 20 performs an operation of sequentially transferring the redundancy enable bit REN and the defective code CD to the scan chain SCANC and an operation of incrementing the counter ICB by “1”, and the value of the counter ICB is the number of code bits. Repeat until NCB.

  Next, the transfer control unit 20 decrements the value of the counter IRAM by “1” in step S114, and resets the counter ICB to “0” in step S116. Next, in step S118, when the value of the counter IRAM is “0”, the transfer control unit 20 sends the redundancy enable bit REN and the defective code CD stored in the target row FLINE to a predetermined position in the scan chain SCCANC. Judge that it was transferred. Then, the transfer control unit 20 moves the process to step S122. On the other hand, when the value of the counter IRAM is other than “0” (positive value), the transfer control unit 20 sends the redundancy enable bit REN and the defective code CD stored in the target row FLINE to a predetermined position in the scan chain SCCANC. Judge that it has not been transferred. Then, the transfer control unit 20 moves the process to step S120.

  In step S120, the transfer control unit 20 transfers “0” to the scan chain SCANC while incrementing the counter ICB until the value of the counter ICB reaches the shift number NCB (= “6”). That is, the transfer control unit 20 repeats the operation of sequentially transferring “0” to the scan chain SCANC and the operation of incrementing the counter ICB by “1” until the value of the counter ICB reaches the number of code bits NCB. The processes in steps S114, S116, and S120 are repeated until the value of the counter IRAM becomes “0”. As a result, a default value is set in the shift register SR corresponding to a memory (M3-M5, etc. in FIG. 5) between which there are no defects (M2, M6, etc. in FIG. 5).

  In step S122, the transfer control unit 20 increments the counter LINE by “1”. Next, in step S124, the transfer control unit 20 determines whether or not the value of the counter LINE is the maximum number of lines (= 5 lines) of the program unit 30. When the value of the counter LINE is the maximum number of rows of the program unit 30, it is determined that all the defective codes CD and the redundancy enable bit REN stored in the program unit 30 are set in the predetermined shift register SR, and the process The process proceeds to S126. The transition from step S124 to step S126 is executed when the defective code CD and the redundancy enable bit REN are stored in all the rows FLINE0-FLINE4 of the program unit 30 shown in FIG. On the other hand, when the value of the counter LINE does not reach the maximum number of rows of the program unit 30, there is a possibility that all the defective codes CD and the redundancy enable bit REN stored in the program unit 30 have not been read by the transfer control unit 20. There is. Therefore, the process proceeds to step S106 illustrated in FIG. Then, the defective code CD and the redundancy enable bit REN for the next row LINE are read and transferred to the scan chain SCANC.

  In step S126, the transfer control unit 20 outputs the operation enable signal OPE to the operation control unit 20 shown in FIG. 2 because the defect information has been set in the scan chain SCANC. The operation control unit 20 notifies the CPU, peripheral circuits, and the like in the semiconductor device SEM2 that the memories M1-M10 are operable based on the reception of the operation enable signal OPE. Then, the semiconductor device SEM2 starts to operate as a system that realizes a predetermined function.

  6 and 7, the redundancy enable bit REN and the defect code CD are set in the shift register SR corresponding to the memory M in which a defect exists, and the default value is set in the shift register SR corresponding to the memory M in which no defect exists. Is set. At this time, the probability of repairing a defect using the redundant memory cell unit RMC is lower in the memory M connected to the shift register SR located on the downstream side than the memory M connected to the shift register SR located on the upstream side. . Of the shift registers SR for which defect information is set, the shift register SR further downstream than the shift register SR located on the most downstream side is set to a default value by the reset signal RST. Setting can be omitted. Therefore, the time for setting information in the scan chain SCANC can be shortened compared to the conventional case, and the startup time of the semiconductor device SEM2 can be shortened compared to the conventional case.

  FIG. 8 shows an example of an operation for setting defect information in the scan chain shown in FIG. FIG. 8 shows operations of the transfer control unit 20 and the scan chain SCANC when transferring the defect information of the program unit 30 shown in FIG. 5 to the scan chain SCANC. In FIG. 8, the underlined number indicates that the value has changed. The defect information set in the shift registers SR1-SR10 is indicated by a thick frame.

  First, the transfer control unit 20 sets a default value (= “0”) in all the shift registers SR1 to SR10 by the reset signal RST (FIG. 8A). Thereby, setting of information in the downstream shift registers SR7 to SR10 by the scan operation of the scan chain SCANC can be omitted. Next, the transfer control unit 20 reads the differential FDIF, the defective code CD, and the redundancy enable bit REN stored in the row FLINE0 of the program unit 30 (FIG. 8 (b)).

  Next, the transfer control unit 20 sets the value (= “4”) indicated by the differential FDIF in the counter IRAM, and scans the defective code CD (decimal number “22”) and the redundancy enable bit REN (“1”). Transfer to the chain SCANC (FIG. 8C). Thereafter, the transfer control unit 20 transfers the default value “0” to the scan chain SCANC until the value of the counter IRAM becomes “0” (FIGS. 8D, 8E, and 8F). As a result, values set in the shift registers SR corresponding to the memories M3, M4, and M5 having no defect are transferred to the scan chain SCANC.

  Next, the transfer control unit 20 increments the counter FLINE by “1” (= “1”), and the value of the counter FLINE is less than the maximum value, so that the difference FDIF stored in the row FILNE1, the fault code CD, and the redundancy The enable bit REN is read (FIG. 8 (g)). Thereafter, the transfer control unit 20 sets the value (= “1”) indicated by the differential FDIF in the counter IRAM in the same manner as in FIG. 8C, and sets the defect code CD (decimal number “10”) and the redundancy enable. The bit REN (“1”) is transferred to the scan chain SCANC (FIG. 8 (h)). Since the value of the counter IRAM becomes “0” by decrementing, the transfer of the default value “0” to the scan chain SCANC is not executed.

  Next, the transfer control unit 20 increments the counter LINE by “1” (= “2”) as in FIG. Since the value of the counter FLINE has not reached the maximum value, the transfer control unit 20 reads the differential FDIF, the defective code CD, and the redundancy enable bit REN stored in the row FILNE2 (FIG. 8 (i)).

  Thereafter, as in FIG. 8C, the transfer control unit 20 sets the value (= “1”) indicated by the differential FDIF in the counter IRAM, the defective code CD (decimal number “2”), and the redundancy enable. The bit REN (“1”) is transferred to the scan chain SCANC (FIG. 8 (j)).

  Next, the transfer control unit 20 increments the counter LINE by “1” (= “3”). Since the value of the counter FLINE has not reached the maximum value, the transfer control unit 20 reads “0” stored in the area for storing the difference FDIF of the row FILNE3, the defective code CD, and the redundancy enable bit REN (FIG. 8). (K)). Since the value indicating the differential FDIF is “0”, the transfer control unit 20 determines that the setting of the defect information in the scan chain SCANC is completed, and outputs the operation enable signal OPE.

  As described above, also in the embodiment shown in FIGS. 2 to 8, the shift register SR is connected to the transfer control unit 20 in the order corresponding to the memory M having a high probability of occurrence of a defect, as in the embodiment shown in FIG. . As a result, it is possible to reduce the time required to set the defect information in the shift register SR as compared with the conventional case, and it is possible to reduce the startup time until the operation of the semiconductor device SEM2 becomes possible. In addition, the program unit 30 does not have an area for holding information to be set in all the shift registers SR, and the semiconductor device SEM2 does not have a selector or the like that separates the shift register SR corresponding to the memory M having no defect from the transfer path. . As a result, the time for setting the defect information in the shift register SR can be shortened without increasing the circuit scale of the semiconductor device SEM2.

  Further, in the embodiment shown in FIG. 2 to FIG. 8, the transfer control unit 20 outputs a reset signal RST before transferring the failure information to the scan chain SCANC, and does not execute a failure relief process for the memory M ( (Default value) is set in each shift register SR. Thereby, it is possible to omit setting a default value by a scan operation to the shift register SR further downstream than the shift register SR located most downstream on which defect information is set. Therefore, the time for setting information in the scan chain SCANC can be shortened compared to the conventional case, and the startup time of the semiconductor device SEM2 can be shortened compared to the conventional case. In other words, since the transfer control unit 20 can output the operation enable signal OPE earlier than the conventional one, the operation control unit 10 informs the CPU or the like that the memories M1 to M10 are accessible compared to the conventional one. You can notify early. Thereby, the performance of the semiconductor device SEM2 can be improved as compared with the conventional one.

  The transfer control unit 20 transfers the default value to the shift register SR based on the differential FDIF stored in the program unit 30. Thereby, even when the default value set in the shift register SR by the reset signal RST is lost due to the transfer of the defect information, the default value can be reset.

  FIG. 9 shows another embodiment of the semiconductor device and the method for controlling the semiconductor device. The same or similar elements as those described in the embodiment shown in FIGS. 2 to 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The semiconductor device SEM3 of this embodiment includes a transfer control unit 20A and a program unit 30A instead of the transfer control unit 20 and the program unit 30 shown in FIG. The semiconductor device SEM3 includes a scan chain SCANC1 connected to the six memories M1-M6 and a scan chain SCANC2 connected to the four memories M7-M10. Memory M1-M10 is the same as memory M1-M10 shown in FIG. That is, in the memories M1 to M6, the probability of occurrence of a defect is higher as the memory M is connected to the shift register SR closer to the transfer control unit 20A. In the memories M7 to M10, the probability of occurrence of a defect is higher as the memory M is connected to the shift register SR closer to the transfer control unit 20A. In other words, the probability that the redundant memory cell unit RMC shown in FIG. Similar to FIG. 2, the probability that a failure occurs in each of the memories M1 to M6 is higher than the probability that a failure occurs in each of the memories M7 to M10. The memories M1 to M6 are an example of a first circuit block group, and the memories M7 to M10 are an example of a second circuit block group.

  The scan chain SCANC1 includes shift registers SR1-SR6 connected in series corresponding to the memories M1-M6. The first-stage shift register SR1 receives data DT1 output from the transfer control unit 20A. Each shift register SR1-SR6 is set to a default value “0” based on the reset signal RST1, and sequentially transfers data DT1 from the upstream side (transfer control unit 20A side) to the downstream side in synchronization with the scan clock signal SCLK1. To do.

  The scan chain SCANC2 includes shift registers SR7-SR10 connected in series corresponding to the memories M7-M10. The first-stage shift register SR7 receives data DT2 output from the transfer control unit 20A. Each shift register SR7-SR10 is set to a default value “0” based on the reset signal RST2, and sequentially transfers data DT2 from the upstream side (transfer control unit 20A side) to the downstream side in synchronization with the scan clock signal SCLK2. To do.

  The transfer control unit 20A includes a reset generation unit RSTGEN2 that generates a reset signal RST1 output to the scan chain SCANC1 and a reset signal RST2 output to the scan chain SCANC2. The transfer control unit 20A includes a clock generation unit CLKGEN2 that generates a scan clock signal SCLK1 to be output to the scan chain SCANC1 and a scan clock signal SCLK2 to be output to the scan chain SCANC2. The reset generation unit RSTGEN2 has the same function as the reset generation unit RSTGEN1 shown in FIG. 2, and the clock generation unit CLKGEN2 has the same function as the clock generation unit CLKGEN1 shown in FIG.

  The transfer control unit 20A also includes counters LINE1, IRAM1, and ICB1 that are used to transfer defect information to the scan chain SCCANC1, and counters LINE2, IRAM2, and ICB2 that are used to transfer defect information to the scan chain SCANC2. The counters FLINE1 and FLINE2 are used to identify the row of the program unit 30A, similarly to the counter FLINE shown in FIG. Similarly to the counter IRAM shown in FIG. 2, the counters IRAM1 and IRAM2 are used for setting a default value “0” in the shift register SR by the scan operation of the scan chains SCANC1 and SCANC2. The counters ICB1 and ICB2 are used to count the number of shifts for storing information in each shift register SR, similarly to the counter ICB shown in FIG.

  The transfer control unit 20A uses the counters FLINE1, IRAM1, and ICB1 to transfer defect information to the scan chain SCANC1, and uses the counters FLINE2, IRAM2, and ICB2 to transfer defect information to the scan chain SCANC2. The operation in which the transfer control unit 20A transfers the defect information to the scan chains SCANC1 and SCCANC2 is performed by the transfer control unit 20 shown in FIG. 2 transferring the defect information to the scan chain SCCANC except for the procedure for reading the defect information from the program unit 30A. The operation is the same.

  Since the transfer control unit 20A includes the counter groups FLINE1, IRAM1, and ICB1 and the counter groups FLINE2, IRAM2, and ICB2, it can transfer defect information to the scan chains SCANC1 and SCANC2 in parallel. Note that the transfer control unit 20A may sequentially transfer defect information to each of the scan chains SCANC1 and SCANC2 using one counter group FLINE, IRAM, and ICB as in FIG.

  Similar to the program unit 30 shown in FIG. 2, the program unit 30A includes a plurality of program elements in which information is stored by the program signal PGM. An example of the program unit 30A is shown in FIG.

  FIG. 10 shows an example of the failure status of the memories M1-M10 shown in FIG. 9 and information programmed in the program unit 30A. Elements that are the same as or similar to those in FIG. 5 are denoted by the same reference numerals as those in FIG. The failure status of the memories M1 to M10 is the same as that shown in FIG. 5 except that a failure exists in the memory M8, and is found by a test apparatus that tests the semiconductor device SEM3.

  The configuration of the program unit 30A is the same as that of the program unit 30 shown in FIG. However, the test apparatus sequentially stores the defect information and the difference FDIF transferred to the scan chain SCCANC1 from the row FILNE0 to the row FLINE4. Further, the test apparatus sequentially stores the defect information and the difference FDIF transferred to the scan chain SCCANC2 from the row FILNE4 to the row FLINE0. Thereby, the defect information transferred to the two scan chains SCANC1 and SCANC2 can be stored in one program unit 30A.

  In the example shown in FIG. 10, the memories M1, M2, M6, and M8 have a defect. The defect information of the memories M1, M2, and M6 connected to the scan chain SCANC1 is stored in the rows FLINE2, FLINE1, and FLINE0, as in FIG. On the other hand, the defect information of the memory M8 connected to the scan chain SCANC2 is stored in the last row LINE4. At this time, since there is a defect only in one memory M8 corresponding to the scan chain SCANC2, “6” is subtracted from the memory number MN (= “8”) of the memory M8 in the differential FDIF area of the row FLINE4. Stored value (“2”) is stored. That is, the value obtained by subtracting “6” from the memory number MN as the difference with respect to the smallest memory number MN among the memory numbers MN indicating the defective memory M connected to the scan chain SCANC2 is the difference FDIF of the row FLINE4. Stored in the area. Here, “6” is used to determine the position of the memory M having a defect from the upstream side when the memory M having a defect is one of the memories M7 to M10.

  The program unit 30A stores defect information from both the first row LINE0 and the last row LINE4. Therefore, the program unit 30A can determine whether the defect information corresponds to one of the scan chains SCANC1 and SCANC2. Stored. For example, one or more blank rows FLINE are provided between an area for storing defect information in the memories M1 to M6 and an area for storing defect information in the memories M7 to M10. Thereby, the transfer control unit 20A can discriminate between the defect information transferred to the scan chain SCANC1 and the defect information transferred to the scan chain SCANC2.

  In the example shown in FIG. 10, when there is a defect in the memory M connected to either of the scan chains SCANC1 and SCANC2, the defect information of up to five memories M can be stored in five rows FLINE0 to FLINE4. On the other hand, when there is a defect in the memory M connected to each of the scan chains SCANC1 and SCANC2, the defect information of up to four memories M can be stored in the five rows FLINE0 to FLINE4.

  The setting of defect information in the scan chain SCANC1 is realized by the transfer control unit 20A executing the same processing as in FIG. 6 and FIG. On the other hand, the setting of defect information in the scan chain SCANC2 is realized by changing the processing shown in FIGS. 6 and 7 as follows. In step S102 shown in FIG. 6, the value of the counter LINE is initialized to “5”. In step S122 shown in FIG. 7, the counter FLINE is decremented by “1”. In step S124 shown in FIG. 7, when the value of the counter FLINE is “1” or more, the process proceeds to step S106 shown in FIG. 6, and when the value of the counter FLINE is “0”, the process proceeds to step S126. The Note that there is no defect in the memories M1-M6, and the probability that a defect exists in the memories M7-M10 is extremely low (almost “0”). For this reason, in the setting operation of defect information in the scan chain SCCANC2, the determination in step S124 may be omitted, and the process may be always shifted to the process in step S106 after the process in step S122.

  By the information transfer operation to the scan chains SCANC1 and SCANC2 by the transfer control unit 20A, the same information as the information shown in FIG. 8K is set in the shift registers SR1 to SR10. When there is no defect in the memory M8, the transfer of defect information to the scan chain SCANC2 can be omitted. The probability that a failure will occur in the memories M7-M10 connected to the scan chain SCANC2 is lower than the probability that a failure will occur in the memories M1-M6 connected to the scan chain SCANC1. For this reason, the frequency at which the transfer of defect information to the scan chain SCANC2 is omitted is higher than when the memory M is connected to one of the scan chains SCANC1 and SCANC2 without considering the probability of occurrence of a defect. When the failure information is not transferred to the scan chain SCANC2, the shift registers SR7 to SR10 do not receive the scan clock signal SCLK2, and the transfer operation of the scan chain SCANC2 is not executed. For this reason, the power consumption of the semiconductor memory device MEM3 can be reduced as compared with the case where defective information is transferred by operating all the shift registers SR1-SR10.

  As described above, in the embodiment shown in FIGS. 9 to 10 as well, as in the embodiment shown in FIGS. 1 to 8, the time for setting the defect information in the shift register SR is increased without increasing the circuit scale of the semiconductor device SEM3. It can be shortened.

  Further, in the embodiment shown in FIGS. 9 to 10, in each scan chain SCANC1 and SCANC2, the shift register SR is connected to the transfer control unit 20A in the order corresponding to the memory M having a high probability of using the redundant memory cell unit RMC. . The defect information is set in the memories M1 to M6 using the scan chain SCANC1, and the defect information is set in the memories M7 to M10 using the scan chain SCANC2. The probability that a failure occurs in the memories M1-M6 connected to the scan chain SCANC1 is higher than the probability that a failure occurs in the memories M7-M10 connected to the scan chain SCANC2. As a result, the frequency of setting the defect information in the shift registers SR7-SR10 by operating the scan chain SCCANC2 can be reduced, and the power consumption of the semiconductor memory device MEM3 can be reduced.

  Further, in the case where defect information is transferred in parallel to both the scan chains SCANC1 and SCANC2, the time required for setting the defect information in each shift register SR can be shortened compared to the conventional case. As a result, the startup time until the semiconductor device SEM3 can be operated can be shortened compared to the conventional case.

  FIG. 11 shows another embodiment of a semiconductor device and a method for controlling the semiconductor device. Elements that are the same as or similar to those described in the embodiment shown in FIGS. 2 to 10 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The semiconductor device SEM4 of this embodiment has a program unit 30B instead of the program unit 30 shown in FIG. An example of the program unit 30B is shown in FIG. Each shift register SR1-SR10 of the scan chain SCANC includes, for example, four flip-flop circuits connected in series to hold 4-bit information. Each shift register SR1-SR10 stores a speed code SPDC for adjusting the operation timing of the control circuit in each memory M1-M10. An example of the control circuit is shown in FIG.

  For example, the control circuit is a sense amplifier that is arranged between the memory cell array ARY and the redundancy changeover switch RSW shown in FIG. 4 and amplifies the signal amount of data read from the memory cell. Alternatively, the control circuit is a word line drive circuit that activates a word line WL (FIG. 4) for selecting a memory cell in a read operation or a write operation of the memory M.

  Similar to the transfer control unit 20 shown in FIG. 2, the transfer control unit 20 generates the reset signal RST based on the activation signal PON, and then generates the scan clock signal SCLK having a predetermined number of pulses. Then, the transfer control unit 20 performs an operation of transferring the data DT read from the program unit 30B to the scan chain SCANC. However, the data DT transferred to the scan chain SCANC does not include defect information for repairing a memory defect, but includes a speed code SPDC for changing the operation timing of the control circuit in the memory M from the initial state (default state).

  In the memories M1 to M10 shown in FIG. 11, the memory M with a smaller number has a smaller (stricter) timing margin than the memory M with a larger number. The shift registers SR1 to SR10 are connected to the transfer control unit 20 in the order corresponding to the memories M1 to M10 having a small timing margin.

  The memory M with a small timing margin has a higher probability of being determined to be defective in the test by the test apparatus than the memory M with a large timing margin. In addition, there is a case where the memory M determined to be defective can be relieved by changing the operation timing of the control circuit without using a relief circuit for relieving the defect. That is, the memory M with a small timing margin has a higher probability (possibility) of changing the operation timing of the control circuit from the standard value than the memory M with a large timing margin. Whether or not to change the operation timing of the control circuit is determined based on the test result by a test apparatus that tests the memory M.

  The area of each memory M1-M10 may be different from the area of each memory M1-M10 shown in FIG. For example, the area of the memory M1 may be smaller than the area of the memory M2. However, the larger the area of the memory M, the longer the signal wiring in the memory M. As a result, the timing margin of the memory M tends to be smaller as the area of the memory M is larger.

  If the timing margin of the memory M becomes smaller as the area of the memory M becomes larger, the scan chain SCANC shown in FIG. 11 and the scan chain SCANC shown in FIG. 2 may be merged. That is, the speed code SPDC for changing the operation timing of the control circuit in the memory M and the defect information for repairing the defect of the memory M may be transferred to the shift registers SR1 to SR10 of the scan chain SCANC. In this case, each of the memories M1 to M10 includes a redundant memory cell unit RMC that relieves a defective memory cell unit MC as shown in FIG. The program unit 30B has a plurality of rows FLINE including an area for storing the speed code SPDC and defect information. The transfer control unit 20 transfers the speed code SPDC and the defect information read from the program unit 30B to the scan chain SCANC.

  Further, as shown in FIG. 9, the scan chain SCANC may be divided into two scan chains SCANC1 and SCANC2.

  FIG. 12 shows an example of the adjustment circuit ADJ1 that is mounted in each memory M shown in FIG. 11 and adjusts the operation timing of the control circuit in each memory M. The adjustment circuit ADJ1 includes a plurality of delay circuits DLY (DLY1-DLY7) that receive a control signal CNT that operates a control circuit (such as a sense amplifier or a word line driving circuit), and a selection unit SEL. The propagation delay times of the delay circuits DLY1-DLY7 are different from each other. In FIG. 12, the amount of propagation delay time is indicated by the length in the horizontal direction of the delay circuits DLY1 to DLY7. That is, among the delay circuits DLY1 to DLY7, the propagation delay time of the delay circuit DLY1 is the shortest, and the propagation delay time of the delay circuit DLY7 is the longest. Delay circuits DLY1-DLY7 are examples of internal circuits included in each of memories M1-M10.

  The selection unit SEL selects one of the delay signals obtained by delaying the control signal CNT by the delay circuits DLY1 to DLY7 based on the speed code SPDC, and outputs the selected delay signal to the control circuit as the adjustment control signal ACNT. That is, the selection unit SEL selects any one of the delay circuits DLY1 to DLY7 that output a delay signal based on the speed code SPDC.

  The “high speed 3”, “high speed 2”, “high speed 1”, “standard”, “low speed 1”, “low speed 2”, and “low speed 3” attached to the outputs of the delay circuits DLY1 to DLY7 are the delay circuits DLY1- The operation timing of the control circuit in the memory M when the output of DLY7 is selected by the selection unit SEL is shown. “High speed 3”, “High speed 2”, and “High speed 1” indicate that the operation timing of the control circuit is earlier than that of “Standard”. The operation timing of “High Speed 3” is earlier than the operation timing of “High Speed 2”, and the operation timing of “High Speed 2” is earlier than the operation timing of “High Speed 1”. “Low speed 1”, “Low speed 2”, and “Low speed 3” indicate that the operation timing of the control circuit is later than “standard”. The operation timing of “low speed 3” is later than the operation timing of “low speed 2”, and the operation timing of “low speed 2” is later than the operation timing of “low speed 1”.

  FIG. 13 shows an example of the operation timing of the control circuit in the memory M1-M10 shown in FIG. 11 and information programmed in the program unit 30B. Elements that are the same as or similar to those in FIG. 5 are denoted by the same reference numerals as those in FIG.

  The test apparatus that tests the semiconductor device SEM4 tests the timing margin of each of the memories M1-M10, and determines the memory M that changes the operation timing of the control circuit with respect to the standard value (default value). For example, when the threshold voltage of the transistor included in the semiconductor device SEM4 is lower than the standard value due to a change in the semiconductor manufacturing process for manufacturing the semiconductor device SEM4, the operation speed of the memories M1 to M10 is higher than the operation speed corresponding to the standard value. Become. The test apparatus decides to delay the operation timing of the control circuit of the memory M in which the timing margin becomes smaller than a predetermined value due to the increase in the operation speed (“low speed 1”, “low speed 2”, “low speed 3” shown in FIG. 12). "Any one). As a result, the timing margin of the memory M can be kept within a predetermined margin, and the semiconductor device SEM4 can be prevented from becoming defective. In this embodiment, the operation timing of the control circuit can be lowered to three levels with respect to the standard value.

  On the other hand, when the threshold voltage of the transistor included in the semiconductor device SEM4 is higher than the standard value, the operation speed of the memories M1 to M10 is lower than the operation speed corresponding to the standard value. The test apparatus decides to advance the operation timing of the control circuit of the memory M in which the timing margin becomes smaller than a predetermined value due to the decrease in the operation speed (“high speed 1”, “high speed 2”, “high speed 3” shown in FIG. "Any one). As a result, the timing margin of the memory M can be kept within a predetermined margin, and the semiconductor device SEM4 can be prevented from becoming defective. In this embodiment, the operation timing of the control circuit can be increased up to three levels with respect to the standard value.

  In the example shown in FIG. 13, the test apparatus determines to set the operation mode SPD indicating the operation timing of the control circuits of the memories M1 and M2 whose timing margin is smaller than a predetermined value to “low speed 2”. Further, the test apparatus determines to set the operation mode SPD of the memory M6 whose timing margin is smaller than a predetermined value to “low speed 1”. Further, the test apparatus determines to set the operation mode SPD of the memories M3-M5 and M7-M10 whose timing margin is larger than a predetermined value to “standard” (default value).

  The program unit 30B has a plurality of rows including an area for storing the difference FDIF of the memory number MN of the memory M for changing the operation mode SPD to “standard” and an area for storing the speed code SPDC indicating the operation mode SPD. Has LINE. The area for storing the speed code SPDC has 2 bits for changing the operation mode SPD in three stages to the low speed side and 2 bits for changing the operation mode SPD in three stages to the high speed side (total of 4 bits). In order to set the speed code SPDC in each shift register SR, the number of code bits NCB which is the maximum value set in the counter ICB shown in FIG. 11 is “3”.

  The test apparatus programs the speed code SPDC indicating the operation mode SPD of the memory M for changing the operation timing of the control circuit in the program unit 30B based on the test result of the timing margin of the memories M1-M10. The method of programming the speed code SPDC into the program unit 30B is the same as in FIG.

  For example, the test apparatus sets the largest memory number MN (= 6) and the second largest memory number MN (= 2) among the memory numbers MN indicating the memory M whose operation mode SPD is changed with respect to “standard”. The difference (“4”) is calculated. Then, the test apparatus stores the difference obtained by the calculation in the difference FDIF area in the first row LINE0. The test apparatus stores a value (“0100” in binary number; low speed 1) indicating the operation mode SPD of the memory M6 corresponding to the largest memory number MN in the area of the speed code SPDC in the line FLINE0.

  Next, the test apparatus sets the second largest memory number MN (= 2) and the third largest memory number MN (=) among the memory numbers MN indicating the memory M whose operation mode SPD is changed with respect to “standard”. The difference ("1") from 1) is calculated. Then, the test apparatus stores the difference obtained by the calculation in the area of the difference FDIF in the second row FLINE1. The test apparatus stores a value (“1000” in binary number; low speed 2) indicating the operation mode SPD of the memory M2 corresponding to the second largest memory number MN in the area of the speed code SPDC in the line FLINE1.

  The test apparatus sets the same value as the memory number MN as the difference in the row FLINE2 as the difference with respect to the smallest memory number MN (= 1) among the memory numbers MN indicating the memory M that changes the operation mode SPD with respect to “standard”. Store in the FDIF area. The test apparatus stores a value (“1000” in binary number; low speed 2) indicating the operation mode SPD of the memory M1 corresponding to the smallest memory number MN in the area of the speed code SPDC in the line FLINE2. As described above, the value of the differential FDIF and the speed code SPDC are sequentially stored in the row FLINE in descending order of the memory number MN. And the program of the program part 30B by a test apparatus is completed. In the program unit 30B, an unprogrammed area indicates “0”.

  Similarly to FIG. 5, since the program unit 30B has five rows FLINE0 to FLINE5, when changing the operation timing of the control circuit of more than five memories M, the area for storing the speed code SPDC in the program unit 30B is Run short. In this case, the test apparatus processes the semiconductor device SEM4 as a defective product. By increasing the number of rows FILNE provided in the program unit 30B, the number of memories M that change the operation timing of the control circuit can be increased. Note that the line LINE included in the program unit 30B may be 2 or more and less than the number of memories M (= 10).

  The process of transferring the speed code SPDC to the scan chain SCANC by the transfer control unit 20 is realized by replacing the defective code CD and the redundant enable bit REN with the speed code SPDC in steps S106 and S112 of FIGS. However, the value of the number of code bits NCB in steps S112 and S120 is set to “3”. The operation of transferring the speed code SPDC to the scan chain SCANC by the transfer control unit 20 is realized by replacing the defective code CD and the redundancy enable bit REN in FIG. 8 with the speed code SPDC.

  In the example shown in FIG. 13, the speed code SPDC is not transferred to the shift registers SR7-SR10 corresponding to the memories M7-M10 in which the speed code SPDC is set to “standard”, as in the example shown in FIG. As a result, when the semiconductor memories M1 to M10 are started up, the time until the speed code SPDC is set in the shift register SR can be shortened compared to the conventional case.

  The value (default value) of the speed code SPDC set in each shift register SR corresponding to “standard” may be other than “0”. For example, in FIG. 13, the speed code SPDC indicating "high speed 3"-"high speed 1", "standard", "low speed 1"-"low speed 3" is expressed in binary numbers "000"-"010", "011". , “100”-“110” (“Standard” is “011”). In this case, the flip-flop circuit of each shift register SR has a set terminal that sets the value to be held to logic 1, and a reset terminal that resets the value to be held to logic 0. The reset signal RST is supplied to the set terminal or reset terminal of each flip-flop circuit according to the default value held by each shift register SR. In step S120 shown in FIG. 7, a logic indicating a default value is transferred to the scan chain SCANC instead of “0”. As a result, the default value can be assigned to a value other than “0”.

  As described above, also in the embodiment shown in FIGS. 11 to 13, the time for setting the speed code SPDC in the shift register SR without increasing the circuit scale of the semiconductor device SEM4 as in the embodiment shown in FIGS. Can be shortened.

  Furthermore, in the embodiment shown in FIGS. 11 to 13, the shift register SR is connected to the transfer control unit 20 in the order corresponding to the memory M having a small timing margin and a high probability of being determined to be defective in the test by the test apparatus. . As a result, the time until the speed code SPDC for adjusting the timing margin of the memory M is set in the shift register SR can be shortened compared to the conventional case, and the startup time until the operation of the semiconductor device SEM4 can be reduced. It can be shortened compared to

  FIG. 14 shows another embodiment of a semiconductor device and a method for controlling the semiconductor device. Elements that are the same as or similar to those described in the embodiment shown in FIGS. 2 to 13 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The semiconductor device SEM5 of this embodiment has a transfer control unit 20C and a program unit 30C instead of the transfer control unit 20 and the program unit 30B shown in FIG. An example of the program unit 30C is shown in FIG. Each shift register SR1-SR10 of the scan chain SCANC has two flip-flop circuits connected in series to hold 2-bit information. Each shift register SR1-SR10 stores a part of the speed code SPDC (speed level SLVL shown in FIG. 15) for adjusting the operation speed of each memory M1-M10. Each of the memories M1 to M10 includes an adjustment circuit similar to the adjustment circuit ADJ1 illustrated in FIG.

  The transfer control unit 20C includes counters FLINE, IRAM, ICB, a reset generation unit RSTGEN1, and a clock generation unit CLKGEN3. The clock generator CLKGEN3 has a function of fixing the logic of the scan clock signal SCLK to a high level or a low level after transferring the speed level SLVL, which is a part of the speed code SPDC, to the scan chain SCANC. An example of the clock generation unit CLKGEN3 is shown in FIG. Note that the clock generation unit CLKGEN3 may be arranged outside the transfer control unit 20C. Examples of the operation of the transfer control unit 20C are shown in FIGS.

  The memories M1-M10 are the same as the memories M1-M10 shown in FIG. 11 except that the number of bits of the received speed code SPDC is different. However, in the semiconductor device SEM5, the logic of the scan clock signal SCLK is used for one bit (mode bit MD shown in FIG. 15) of the speed code SPDC supplied to each of the memories M1 to M10. Therefore, the clock signal line for transmitting the scan clock signal SCLK is connected to the memories M1 to M10 in order to supply one bit of the speed code SPDC to the selection unit SEL shown in FIG.

  Thereby, the number of flip-flop circuits of each shift register SR1-SR10 can be reduced as compared with the case where all bits of the speed code SPDC are supplied to the memories M1-M10 via the shift registers SR1-SR10. As a result, the setting time of the speed code SPDC in the scan chain SCANC can be shortened compared to the conventional case, and the startup time of the semiconductor device SEM5 can be shortened compared to the conventional case.

  If the timing margin of the memory M becomes smaller as the area of the memory M becomes larger, the scan chain SCANC shown in FIG. 14 and the scan chain SCANC shown in FIG. 2 may be merged. That is, the speed code SPDC for changing the operation timing of the control circuit in the memory M and the defect information for repairing the defect of the memory M may be transferred to the shift registers SR1 to SR10 of the scan chain SCANC. In this case, each of the memories M1 to M10 includes a redundant memory cell unit RMC that relieves a defective memory cell unit MC as shown in FIG. The program unit 30C has a plurality of rows FLINE including an area for storing the speed code SPDC and defect information. The transfer control unit 20C transfers the speed code SPDC and defect information read from the program unit 30C to the scan chain SCANC.

  Further, as shown in FIG. 9, the scan chain SCANC may be divided into two scan chains SCANC1 and SCANC2.

  FIG. 15 shows an example of the operation timing of the control circuit in the memory M1-M10 shown in FIG. 14 and information programmed in the program unit. Elements that are the same as or similar to those in FIGS. 5 and 13 are denoted by the same reference numerals as in FIGS. 5 and 13 and will not be described in detail.

  The test apparatus for testing the semiconductor device SEM5 tests the timing margin of each of the memories M1-M10 and sets the operation timing of the control circuit such as the sense amplifier or the word line driving circuit to a standard value (default value), as in FIG. On the other hand, the memory M to be changed is determined. As in FIG. 13, the operation timing can be increased up to three levels with respect to the standard value (high speed 1, high speed 2, high speed 3), or can be decreased to three levels with respect to the standard value. Possible (low speed 1, low speed 2, low speed 3).

  In the example shown in FIG. 15, the test apparatus determines to set the operation mode SPD indicating the operation timing of the control circuits of the memories M1 and M2 whose timing margin is smaller than a predetermined value to 2 at high speed. Further, the test apparatus determines to set the operation mode SPD of the memory M6 whose timing margin is smaller than a predetermined value to 1 at high speed. Further, the test apparatus determines to set the operation mode SPD of the memories M3-M5 and M7-M10 whose timing margin is greater than a predetermined value to a standard value (default value).

  Similarly to the program unit 30B shown in FIG. 13, the program unit 30C includes an area for storing the difference FDIF of the memory number MN of the memory M that changes the operation mode SPD to “standard”, and an area for storing the speed code SPDC. Has a plurality of rows FLINE. However, the area for storing the speed code SPDC includes an area for storing the mode bit MD (1 bit) and an area for storing the speed level SLVL (2 bits). As described with reference to FIG. 22, the speed level SLVL is transferred to the scan chain SCANC, but the mode bit MD is not transferred. In order to set the speed level SLVL in each shift register SR, the number of code bits NCB which is the maximum value set in the counter ICB shown in FIG. 14 is “1”.

  The mode bit MD is set to “0” indicating the low speed mode when the speed level SLVL is set to any one of “low speed 1”, “low speed 2”, and “low speed 3”. The mode bit MD is set to “1” indicating the high speed mode when the speed level SLVL is set to any one of “high speed 1”, “high speed 2”, and “high speed 3”. The mode bit MD is an example of second selection information that is commonly supplied to the selection units SEL (FIG. 12) of the memories M1 to M10. 12 receives the value of the mode bit MD and the value of the speed level SLVL as the speed code SPDC, and sends one of the delay signals output from the delay circuits DLY1 to DLY7 to the speed code SPDC. Select based on.

  The low speed mode is set when the timing margin of the memory M becomes smaller than a predetermined margin due to the threshold voltage of the transistor included in the semiconductor device SEM5 being lower than the standard value. The high-speed mode is set when the timing margin of the memory M is smaller than a predetermined margin due to the threshold voltage of the transistors included in the semiconductor device SEM5 being higher than the standard value. Since the tendency of the threshold voltage variation is the same in all the circuits in the semiconductor device SEM5, “low speed” and “high speed” are not mixedly programmed in the program unit 30C.

  The speed level SLVL is set to any one of “standard”, “low speed 1”, “low speed 2”, and “low speed 3” according to the logical value of 2 bits when the mode bit MD indicates the low speed mode. The speed level SLVL is set to “standard”, “high speed 1”, “high speed 2”, or “high speed 3” according to the logical value of 2 bits when the mode bit MD indicates the high speed mode. The The speed level SLVL is an example of first selection information supplied individually to the selection unit SEL (FIG. 12).

  The test apparatus programs the speed code SPDC (MB, SLVL) indicating the operation mode SPD of the memory M for changing the operation timing of the control circuit in the program unit 30C based on the test result of the timing margin of the memories M1-M10. The method of programming the speed code SPDC into the program unit 30C is the same as that shown in FIGS.

  For example, the test apparatus sets the largest memory number MN (= 6) and the second largest memory number MN (= 2) among the memory numbers MN indicating the memory M whose operation mode SPD is changed with respect to “standard”. The difference (“4”) is calculated. Then, the test apparatus stores the difference obtained by the calculation in the difference FDIF area in the first row LINE0. The test apparatus stores a value (“101” in binary number; high speed 1) indicating the operation mode SPD of the memory M6 corresponding to the largest memory number MN in the area of the speed code SPDC in the line FLINE0.

  Next, the test apparatus sets the second largest memory number MN (= 2) and the third largest memory number MN (= 1) among the memory numbers MN indicating the memory M whose operation mode SPD is changed with respect to the default value. ) And the difference (“1”). Then, the test apparatus stores the difference obtained by the calculation in the area of the difference FDIF in the second row FLINE1. The test apparatus stores a value (“110” in binary number; high speed 2) indicating the operation mode SPD of the memory M2 corresponding to the second largest memory number MN in the area of the speed code SPDC in the line FLINE1.

  The test apparatus sets the same value as the memory number MN as the difference in the row FLINE2 as the difference with respect to the smallest memory number MN (= 1) among the memory numbers MN indicating the memory M that changes the operation mode SPD with respect to “standard”. Store in the FDIF area. The test apparatus stores a value (“110” in binary number; high speed 2) indicating the operation mode SPD of the memory M1 corresponding to the smallest memory number MN in the area of the speed code SPDC in the line FLINE2.

  FIG. 16 illustrates an example of the clock generation unit CLKGEN3 illustrated in FIG. The clock generation unit CLKGEN3 includes a counter COUNT, an enable generation circuit ENBGEN, and a clock counter CLKC. The clock counter CLKC has a flip-flop circuit FF and an inverter IV.

  The counter COUNT maintains the counter value CV in the reset state (“0”) until the activation level of the activation signal PON is received at the reset terminal RESET. The counter COUNT releases the reset state in response to the change of the power-on signal PON to the activation level, performs a count operation in synchronization with the scan clock signal SCLK received at the clock terminal CK, and sets the counter value CV to “1”. "Increment by one.

  The enable generation circuit ENBGEN includes a comparator CMP. The enable generation circuit ENBGEN sets the enable signal ENB to the activation level in response to the change of the power-on signal PON received at the reset terminal RESET to the activation level, and starts the operation of the comparator CMP. The comparator CMP compares the counter value CV and the shift number NSFT, and outputs a match signal CON when the counter value CV matches the shift number NSFT. Here, the shift number NSFT is the number of pulses of the scan clock signal SCLK generated to transfer all the speed levels SLVL programmed in the program unit 30C to the scan chain SCANC (the number of shifts of the scan chain SCANC).

  When the mode bit MD of the last speed code SPDC from the program unit 30C is “1”, the enable generation circuit ENBGEN generates the enable signal ENB when the scan clock signal SCLK becomes high level based on the coincidence signal CON. Deactivate. When the mode bit MD of the last speed code SPDC from the program unit 30C is “0”, the enable generation circuit ENBGEN deactivates the enable signal ENB while the scan clock signal SCLK is at the low level based on the coincidence signal CON. Set to level.

  The flip-flop circuit FF of the clock counter CLKC receives the activation signal PON at the reset terminal RESET, the clock signal CLK at the clock terminal CK, and the enable signal ENB at the enable terminal ENB. The clock signal CLK may be a system clock signal supplied to the semiconductor device SEM5, or may be another clock signal generated based on the system clock signal. The flip-flop circuit FF receives a signal obtained by inverting the logic of the scan clock signal SCLK via the inverter IV at the data input terminal D, and outputs the scan clock signal SCLK from the data output terminal Q.

  When the activation signal PON and the enable signal ENB are at the activation level, the flip-flop circuit FF generates the scan clock signal SCLK from the data output terminal Q in synchronization with the clock signal CLK received at the clock terminal CK. Further, the flip-flop circuit FF fixes the scan clock signal SCLK at a low level while the activation signal PON is at the inactive level, and stops generating the scan clock signal SCLK while the enable signal ENB is at the inactive level.

  The clock generation unit CLKGEN3 sets the logic of the scan clock signal SCLK to the logic of the mode bit MD when the number of pulses of the scan clock signal SCLK matches the shift number NSFT after the activation signal PON changes to the activation level. . An example of the operation of the clock generation unit CLKGEN3 is shown in FIG.

  FIG. 17 shows an example of the operation of the clock generation unit CLKGEN3 shown in FIG. The example illustrated in FIG. 17 illustrates the operation of the clock generation unit CLKGEN3 when sequentially transferring 2-bit information indicating the speed level SLVL to the shift registers SR1-SR6 corresponding to the memories M1-M6. Since information including the speed level SLVL programmed in the program unit 30C is sequentially transferred to the six shift registers SR1-SR6, the shift number NSFT calculated by the transfer control unit 20C is “12”. The operation when the mode bit MD is “1” (= high-speed mode) indicates a case where the information shown in FIG. 15 is programmed in the program unit 30C.

  First, the enable generation circuit ENBGEN changes the enable signal ENB to the activation level in response to the activation signal PON changing to the activation level (FIGS. 17A and 17B). The clock counter CLKC inverts the logic of the scan clock signal SCLK in synchronization with the rising edge of the clock signal CLK during the activation period of the enable signal ENB (FIGS. 17C and 17D). The counter COUNT counts the number of clocks of the scan clock signal SCLK and outputs a counter value CV (FIG. 17 (e)).

  The comparator CMP outputs a coincidence signal CON when the counter value CV coincides with the shift number NSFT (FIG. 17 (f)). When the mode bit MD is “1”, the enable generation circuit ENBGEN sets the enable signal ENB to the inactive level after the scan clock signal SCLK changes to the high level “H” based on the output of the coincidence signal CON. It is changed (FIG. 17 (g)). As a result, the scan clock signal SCLK is fixed to the high level “H” (FIG. 17H).

  On the other hand, when the mode bit MD is “0”, the enable generation circuit ENBGEN changes the enable signal ENB to the inactivation level while the scan clock signal SCLK is at the low level “L” based on the output of the coincidence signal CON ( Thus, the scan clock signal SCLK is fixed at the low level “L” (FIG. 17J).

  FIG. 18 illustrates an example of the shift register SR1 illustrated in FIG. The other shift registers SR2-SR10 have the same circuit configuration as FIG. 18 except that the received data is different from the memory M to be connected.

  The shift register SR1 has two master-slave flip-flop circuits MSFF1 and MSFF2 connected in series. The master-slave flip-flop circuit MSFF1 has a master latch circuit MLT1 and a slave latch circuit SLT1, and the master-slave flip-flop circuit MSFF2 has a master latch circuit MLT2 and a slave latch circuit SLT2. Master latch circuits MLT1 and MLT2 and slave latch circuits SLT1 and SLT2 are the same circuit, and have a data input terminal D, a data output terminal Q, a reset terminal RST, and a clock terminal CK.

  Master latch circuits MLT1 and MLT2 and slave latch circuits SLT1 and SLT2 are reset when reset signal RST is at the activation level at reset terminal RST, and outputs "0" from data output terminal Q. Master latch circuits MLT1 and MLT2 operate in synchronization with scan clock signal SCLK when reset signal RST is at an inactive level. Slave latch circuits SLT1 and SLT2 operate in synchronization with a signal obtained by inverting the logic of scan clock signal SCLK by inverter IV when reset signal RST is at an inactive level.

  Each master latch circuit MLT1, MLT2 latches the logic of the data DT received at the data input terminal D in synchronization with the rising edge of the scan clock signal SCLK, and outputs the latched logic from the data output terminal Q. Each slave latch circuit SLT1, SLT2 latches the logic of data received at the data input terminal D in synchronization with the falling edge of the scan clock signal SCLK, and outputs the latched logic from the data output terminal Q. The logic output from the slave latch circuit SLT1 is supplied to the memory M1 and the master slave flip-flop circuit MSFF2, and the logic output from the slave latch circuit SLT2 is supplied to the memory M1 and the shift register SR2 at the next stage.

  FIG. 19 shows an example of the operation of the shift register SR1 shown in FIG. The other shift registers SR2-SR10 operate in the same manner as in FIG. In the example shown in FIG. 19, the master-slave flip-flop circuit MSFF1 sequentially latches data D1, D2, D3, D4, and D5 in synchronization with the scan clock signal SCLK, and sequentially outputs the latched data D1-D5. . The master-slave flip-flop circuit MSFF2 sequentially latches the data D1, D2, D3, D4 in synchronization with the scan clock signal SCLK, and sequentially outputs the latched data D1-D4.

  The data output from each slave latch circuit SLT1, SLT2 does not change between the low level period of one clock cycle of the scan clock signal SCLK and the high level period of the next clock cycle. For example, during the low level period “L” of the fifth clock cycle and the high level period “H” of the sixth clock cycle, the slave latch circuit SLT1 outputs data D5, and the slave latch circuit SLT2 outputs data D4. Therefore, as shown in FIG. 17, even if the logic of the scan clock signal SCLK is changed according to the logic of the mode bit MD, the logic held in the shift register SR does not change. As a result, even if the logic of the scan clock signal SCLK is changed according to the logic of the mode bit MD, it is possible to prevent the erroneous speed level SLVL from being set in the memory M. Furthermore, the logic of the mode bit MD can be set in the memory M without using the scan chain SCANC by using the logic of the scan clock signal SCLK after transferring the speed level SLVL to the scan chain SCANC. Thereby, the number of flip-flop circuits FF (FIG. 3) included in each shift register SR1-SR10 can be reduced as compared with FIG. 11, and the circuit scale of the semiconductor device SEM5 can be reduced to that of the semiconductor device SEM4 shown in FIG. It can be made smaller.

  FIG. 20 shows an example of an operation flow for setting defect information in the scan chain SCANC shown in FIG. The process shown in FIG. 20 shows the control method of the semiconductor device SEM5, and is executed by the transfer control unit 20C shown in FIG. 6 that are the same as or similar to those in FIG. 6 are given the same reference numerals as in FIG. The transfer control unit 20C executes the process of step S106C instead of the process of step S106 shown in FIG. Processing excluding step S106C is the same as that in FIG.

  In step S106C, the transfer control unit 20C reads the differential FDIF and speed code SPDC (mode bit MD and speed level SLVL) stored in the row LINE of the program unit 30C indicated by the value of the counter FLINE.

  FIG. 21 shows an example of an operation flow for setting defect information in the scan chain SCANC shown in FIG. 14 (continuation of FIG. 20). The process shown in FIG. 21 shows a control method of the semiconductor device SEM5 and is executed by the transfer control unit 20C shown in FIG. The same or similar processes as those in FIG. 7 are denoted by the same reference numerals as those in FIG. The transfer control unit 20C executes steps S112C and S120C instead of the steps S112 and S120 shown in FIG. In addition, the transfer control unit 20C executes the process of step S125C between step S124 and step S126. Other processes are the same as those in FIG.

  In step S112C, the transfer control unit 20C transfers the logic of the speed level SLVL to the scan chain SCANC while incrementing the counter ICB until the value of the counter ICB reaches the shift number NCB (= “1”). That is, the transfer control unit 20C performs the operation of sequentially transferring the logic of the speed level SLVL to the scan chain SCANC and the operation of incrementing the counter ICB by “1” until the value of the counter ICB reaches the code bit number NCB. repeat.

  In step S120C, the transfer control unit 20C transfers “0” to the scan chain SCANC while incrementing the counter ICB until the value of the counter ICB reaches the shift number NCB (= “1”). That is, the transfer control unit 20C repeats the operation of sequentially transferring “0” to the scan chain SCANC and the operation of incrementing the counter ICB by “1” until the value of the counter ICB reaches the number of code bits NCB. Then, the processes in steps S114, S116, and S120C are repeated until the value of the counter IRAM becomes “0”. This allows the shift register SR corresponding to the memory (such as the memory M3-M5 in FIG. 13) that does not change the operation mode SPD between the pair of memories (M2, M6, etc. in FIG. 13) to change the operation mode SPD to “standard”. A value indicating "" is set.

  In step S125C, as shown in FIG. 17, the transfer control unit 20C sets the scan clock signal SCLK to the high level “H” or the low level “L” based on the logic of the mode bit MD.

  FIG. 22 shows an example of an operation for setting defect information in the scan chain SCANC shown in FIG. FIG. 22 shows operations of the transfer control unit 20C and the scan chain SCANC when transferring the speed level SLVL stored in the program unit 30C shown in FIG. 15 to the scan chain SCANC. Detailed description of the same or similar operations as those in FIG. 8 will be omitted. As in FIG. 8, the underlined number indicates that the value has changed, and the value of the speed level SLVL set in the shift registers SR1-SR10 is indicated by a thick frame.

  The operation of the transfer control unit 20C is the same as that shown in FIG. 5 except that the speed level SLVL is transferred to the scan chain SCANC instead of the defect information, and the logic of the scan clock signal SCLK is fixed to the logic of the mode bit MB after the transfer. The operation is the same as that shown in FIG.

  The transfer control unit 20C determines the completion of transfer to the scan chain SCANC of the speed level SLVL based on the fact that the differential FDIF read from the program unit 30C indicates “0” (FIG. 22A). Then, the transfer control unit 20C fixes the logic of the scan clock signal SCLK to the logic of the mode bit MD included in the effective speed code SPDC that is finally read from the program unit 30C (FIG. 22B). In the example shown in FIG. 22, since the logic of the last valid mode bit MD read is “1”, the scan clock signal SCLK is fixed at the high level “H”.

  As described above, in the embodiment shown in FIGS. 14 to 22 as well, as in the embodiment shown in FIGS. 1 to 13, the time for setting the speed level SLVL in the shift register SR without increasing the circuit scale of the semiconductor device SEM5. Can be shortened.

  Further, in the embodiment shown in FIGS. 14 to 22, the logic of the mode bit MD is supplied to the memory M using the logic of the scan clock signal SCLK without going through the shift register SR. For this reason, the number of flip-flop circuits of each shift register SR can be reduced, and the setting time of the speed code SPDC to the scan chain SCANC can be shortened compared to the semiconductor device SEM4 shown in FIG. As a result, the startup time of the semiconductor device SEM5 can be shortened compared with the semiconductor device SEM4 shown in FIG. 11 without increasing the circuit scale of the semiconductor device SEM5.

  In the embodiment shown in FIG. 11 to FIG. 22, an example in which the operation timing of the control circuit in each memory M is adjusted based on the test result of each memory M is shown. May be adjusted based on the test result of each memory M. That is, the operation timing of the control circuit may be adjusted based on the operation voltage. Alternatively, the internal power supply voltage supplied to the control circuit in each memory M may be adjusted based on the test result (internal power supply voltage margin) of each memory M.

  When the operating voltage or the internal power supply voltage of the control circuit is adjusted, the shift registers SR1 to SR10 are connected to the transfer control unit in the order corresponding to the memory M having a small voltage margin. The shift registers SR1 to SR10 hold selection information for selecting any one of a plurality of voltages generated in each memory M. For example, in the memories M1 to M10 shown in FIG. 11, the memory M having a smaller number has a smaller (stricter) voltage margin than the memory M having a larger number.

  Further, in the embodiments shown in FIGS. 2 to 22, the example in which the defect of the memory M1-M10 is remedied or the operation timing of the control circuit in the memory M1-M10 is adjusted has been described. However, the embodiment shown in FIG. 2 to FIG. 22 may be used to relieve a defect in a circuit block such as a peripheral circuit other than the memory M mounted in the semiconductor device, or the operation timing of the circuit block (or It may be used to adjust the operating voltage.

  FIG. 23 shows an example of the adjustment circuit ADJ2 that is mounted on each circuit block in the semiconductor device and adjusts the voltage used in the circuit block. The adjustment circuit ADJ2 includes a plurality of voltage generation circuits VGEN (VGEN1, VGEN2, VGEN3, VGEN4, VGEN5) that generate internal voltages VI (VI1, VI2, VI3, VI4, VI5) for operating the control circuit, and a selection unit SEL. Have The internal voltages VI1, VI2, VI3, VI4, and VI5 gradually increase in the order of VI1, VI2, VI3, VI4, and VI5 (VI1 <VI2 <VI3 <VI4 <VI5). For example, the internal voltage VI3 is a standard value (default value). For example, the circuit block is the memory M1-M10 shown in FIG. 11 or the like, and the circuit including the voltage generation circuits VGEN1-VGEN5 is an example of an internal circuit included in each of the memories M1-M10. Internal voltage VI is used for the activation level voltage of word line WL shown in FIG. 4, or internal voltage VI is used for the substrate voltage of memory cell array ARY shown in FIG.

  The selection unit SEL selects any one of the internal voltages VI1 to VI5 based on the voltage code VC indicating the operation specification of the control circuit, and applies the substrate voltage to the substrate of the word line driving circuit or the memory cell array ARY as the selected internal voltage VI. Output to a control circuit such as a supply circuit to be supplied. That is, the selection unit SEL selects one of the voltage generation circuits VGEN1 to VGEN5 that output the internal voltages VI1 to VI5 based on the voltage code VC. In the program unit 30B and the like shown in FIG. 11, a voltage code VC for setting the internal voltage VI in the memory M to be changed from the standard internal voltage VI3 and a differential FDIF are programmed. The shift registers SR1 to SR10 are connected to the transfer control unit 20 in the order corresponding to the memories M1 to M10 having a small voltage margin.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10 ... Operation control part; 12 ... Power supply control part; 20, 20A, 20C ... Transfer control part; 30, 30A, 30B, 30C ... Program part; ACNT ... Adjustment control signal; ADEC ... Address decoder; ADJ1, ADJ2 ... Adjustment circuit ARY: Memory cell array; CBLK (CBLK1-CBLK4) ... circuit block; CD ... defective code; CLKC ... clock counter; CLKGEN1, CLKGEN2, CLKGEN3 ... clock generation unit; CMP ... comparator; CNT ... control signal; CNTL ... control unit COUNT ... Counter; DLY (DLY1-DLY7) ... Delay circuit; DT ... Data; ENB ... Enable signal; ENBGEN ... Enable generation circuit; FDIF ... Difference; FF ... Flip-flop circuit; FLINE, FLINE1, FLINE2 ... Counter; HL (HLD1-HLD4) ... holding unit; IC (IC1, IC2) ... internal circuit; ICB, ICB1, ICB2 ... counter; IO (IO0-IO63) ... data input / output terminal; IRAM, IRAM1, IRAM2 ... counter; IV ... inverter IVDD: power supply voltage; M (M1-M10): memory; MC (MC0-MC63): memory cell unit; MD: mode bit; MEM: storage unit; MLT1, MLT2: master latch circuit; NCB: Number of code bits; NSFT: Number of shifts; OPE: Operation enable signal; PGM ... Program signal; PON ... Start signal; REN ... Redundancy enable bit; RMC ... Redundant memory cell unit; RST ... Reset signal; RSTGEN2 ... Reset Generation unit; RSW: Redundant changeover switch; SCANC, SCANC1, SCANC2 ... Scan chain; SCLK ... Scan clock signal; SEL (SEL1, SEL2, SEL3, SEL4) ... Selection unit; SI1, SI2 ... selection information; SINIT ... selection information; SLT1, SLT2 ... slave latch circuit; SLVL ... speed level; SPD ... operation mode; SPDC ... speed code; SR (SR1-SR10) ... shift register; VC ... voltage code VI1, VI2, VI3, VI4, VI5... Internal voltage; VGEN (VGEN1-VGEN5) ... Voltage generation circuit; WL (WL0-WL4) ... Word line

Claims (11)

A plurality of circuit blocks each including a plurality of internal circuits and a selection unit that selects an internal circuit to be used among the plurality of internal circuits based on selection information;
A storage unit that stores selection information supplied to the selection unit of a change circuit block that is a circuit block that changes a selection state of the plurality of internal circuits from an initial state among the plurality of circuit blocks;
The selection information provided corresponding to each of the plurality of circuit blocks, connected in the order corresponding to the circuit blocks having a high probability of changing the selection state from the initial state, and supplied to the selection unit of the plurality of circuit blocks, respectively A plurality of holding parts to hold;
A semiconductor device comprising: a control unit that sequentially transfers selection information stored in the storage unit to a holding unit corresponding to the change circuit block among the plurality of holding units. The control unit includes a reset generation unit that generates a reset signal before transferring selection information to a holding unit corresponding to the change circuit block,
The semiconductor device according to claim 1, wherein the plurality of holding units are reset to a state in which selection information corresponding to the initial state is held based on the reset signal. A power supply control unit that controls a power supply voltage supplied to a circuit region including the plurality of circuit blocks and the plurality of holding units, and generates a start signal based on the supply of the power supply voltage to the circuit region;
The semiconductor device according to claim 2, wherein the control unit starts transferring the selection information stored in the storage unit after generating the reset signal based on the activation signal. The storage unit
A plurality of first storage areas each storing selection information supplied to the selection unit of the change circuit block;
A plurality of second storage areas each storing interval information indicating an interval between two holding units corresponding to two of the change circuit blocks among the plurality of holding units;
The control unit transfers the selection information corresponding to the initial state while sequentially transferring the selection information stored in the two first storage areas to the plurality of holding units based on the interval information. The semiconductor device according to claim 1, wherein the semiconductor device is transferred to a plurality of holding units. The plurality of holding units are respectively connected in series corresponding to the first circuit block group and the second circuit block group among the plurality of circuit blocks,
Among the plurality of holding units, the holding unit corresponding to each circuit block of the first circuit block group is connected to the control unit in the order corresponding to the circuit block having a high probability of changing the selected state from the initial state. ,
Among the plurality of holding units, the holding unit corresponding to each circuit block of the second circuit block group is connected to the control unit in the order corresponding to the circuit block having a high probability of changing the selected state from the initial state. ,
The probability of changing the selection state in each circuit block of the first circuit block group from the initial state is higher than the probability of changing the selection state in each circuit block of the second circuit block group from the initial state. 5. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: The selection information stored in the storage unit includes first selection information that is individually supplied to the selection unit of the change circuit block, and second that is commonly supplied to the selection unit of the plurality of circuit blocks. Selection information,
The control unit generates a clock signal for operating the plurality of holding units, and after transferring the first selection information to the holding unit corresponding to the change circuit block, based on the second selection information A clock generator for fixing the clock signal to either a high level or a low level;
A clock signal line for transmitting the clock signal is connected to the plurality of circuit blocks;
The said selection part receives the level of the said clock signal fixed after transfer of the said 1st selection information to the holding | maintenance part corresponding to the said change circuit block as said 2nd selection information. The semiconductor device according to claim 5. The semiconductor device according to claim 6, wherein each of the plurality of holding units includes a plurality of master-slave flip-flop circuits connected in series. The plurality of internal circuits included in each of the plurality of circuit blocks is either a memory cell unit including a plurality of memory cells or a redundant memory cell unit including a redundant memory cell that relieves a defective memory cell unit. Including
The selection unit included in each of the plurality of circuit blocks selects the redundant memory cell unit instead of the memory cell unit having a defect based on selection information,
The semiconductor device according to claim 1, wherein the plurality of holding units are connected to the control unit in an order corresponding to a circuit block having a large area. The plurality of internal circuits included in each of the plurality of circuit blocks each include a plurality of delay circuits having different propagation delay times,
The selection unit included in each of the plurality of circuit blocks selects one of the signals generated by the plurality of delay circuits based on selection information,
The semiconductor device according to claim 1, wherein the plurality of holding units are connected to the control unit in an order corresponding to a circuit block having a small timing margin. The plurality of internal circuits included in each of the plurality of circuit blocks include a plurality of voltage generation circuits that generate different voltages, respectively.
The selection unit included in each of the plurality of circuit blocks selects any one of the voltages generated by the plurality of voltage generation circuits based on selection information,
The semiconductor device according to claim 1, wherein the plurality of holding units are connected to the control unit in an order corresponding to a circuit block having a small voltage margin. A plurality of circuit blocks each including a plurality of internal circuits and a selection unit that selects an internal circuit to be used among the plurality of internal circuits based on selection information, and provided corresponding to each of the plurality of circuit blocks, A plurality of holding units that are connected in the order corresponding to the circuit blocks having a high probability of changing the selection state of the plurality of internal circuits from the initial state, and respectively hold selection information supplied to the selection unit of the plurality of circuit blocks; A method for controlling a semiconductor device comprising:
Among the plurality of circuit blocks, the selection information supplied to the selection unit of the change circuit block that is a circuit block that changes the selection state of the plurality of internal circuits from the initial state is read from the storage unit,
The method of controlling a semiconductor device, wherein the read selection information is sequentially transferred to a holding unit corresponding to the change circuit block among the plurality of holding units.

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