JP2016189366A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a power semiconductor device having a high withstanding voltage and a sufficiently high ON-state current.SOLUTION: A semiconductor device 10 comprises: oxide films 26 and gate electrodes 27 which are provided in respective grooves 24, in which a plurality of grooves 24 and structures relevant to the grooves 24 extend in a direction perpendicular to a plane of a paper in FIG.1 and arranged in parallel with each other. The semiconductor device 10 further comprises: columnar p-type layers (columnar semiconductor layers) 11 which are provided just below respective grooves 24 but not provided between neighboring grooves 24. Since a width of the columnar p-type layer 11 is smaller than a width of the groove 24, the columnar p-type layer 11 is formed within a region where the groove 24 is formed in plan view.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a structure of a trench gate type semiconductor device that performs a switching operation.

  A power MOSFET, an insulated gate bipolar transistor (IGBT), or the like is used as a switching element (power semiconductor element) that performs a large current switching operation. In such a switching element, a trench gate type in which an oxide film and a gate electrode are formed in a groove (trench) formed in a semiconductor substrate is used.

FIG. 5 is a cross-sectional view showing an example of the configuration of such a trench gate type power MOSFET (semiconductor device) 100. In FIG. 5, in this semiconductor substrate 80, an n ⁻ layer 82 and a p ⁻ layer 83 serving as a drift layer are sequentially formed on an n ⁺ layer 81 serving as a drain layer. On the surface side of the semiconductor substrate 80, a groove (cell region groove: trench) 84 penetrating the p ⁻ layer 83 is formed. A plurality of grooves 84 (four in the illustrated range) are formed in parallel to extend in the direction perpendicular to the paper surface in FIG. An oxide film 86 is uniformly formed on the inner surface of each trench 84, and a gate electrode 87 is formed so as to fill the trench 84. The gate electrode 87 is usually formed of polycrystalline silicon doped at a high concentration.

Further, on the surface side of the semiconductor substrate 80, n ⁺ layers 85 serving as source regions are formed on both sides of the groove 84. A source electrode (first main electrode) 89 is formed on the surface of the semiconductor substrate 80. On the other hand, a drain electrode 90 (second main electrode) is formed on the entire back surface of the semiconductor substrate 80 in contact with the n ⁺ layer (drain layer) 81. On the other hand, since the interlayer insulating layer 88 is formed so as to cover the groove 84 on the surface side of the semiconductor substrate 80, the source electrode 89 is in contact with both the n ⁺ layer 85 and the p ⁻ layer 83, and the gate electrode 87. Is insulated. On the surface side outside the range shown in FIG. 5, for example, all the gate electrodes 87 are connected on the end side in the extending direction (perpendicular to the paper surface) of the groove 84 and connected to a common gate wiring. Further, the source electrode 89 is formed on the entire surface within the range shown in FIG. 5, but on the surface side, the gate wiring and the source electrode 89 are formed separately. Therefore, for each groove 84, a channel is formed in the p ⁻ layer 83 on the side surface of the groove 84 by the voltage applied to the gate wiring (gate electrode 87), and n between the n ⁻ layer 82 and the n ⁺ layer 85. It operates as a type MOSFET and this MOSFET is turned on. That is, current switching between the source electrode 89 and the drain electrode 90 can be controlled by the voltage applied to the gate electrode 87. Since the MOSFETs formed for each groove 84 are all connected in parallel, a large current can flow between the source electrode 89 and the drain electrode 90.

Although the figure shows the structure of the power MOSFET, the same structure can be applied to the IGBT. In this case, for example, the n ⁺ layer 81 in FIG. 5 may be a p ⁺ layer serving as a collector layer, the source electrode 89 may be replaced with an emitter electrode, and the drain electrode 90 may be replaced with a collector electrode.

Such a power MOSFET is required to have a high breakdown voltage between the source electrode 89 and the drain electrode 90 when the power MOSFET is turned off (when the gate voltage is set so that the MOSFET is turned off). In the structure of FIG. 5, in such a state, a depletion layer is formed between the p ⁻ layer 83 and the n ⁻ layer 82, or the trench 84 in which the gate electrode 87 is provided and the n ⁻ layer 82. This depletion layer extends mainly along the interface between the p ⁻ layer 83 and the n ⁻ layer 82, and the electric field in the depletion layer is mainly in the vertical direction. Here, since the electric field locally increases at the location where the width of the depletion layer becomes narrow, it is required that the depletion layer be formed widely and uniformly in order to increase the breakdown voltage. For this purpose, it is effective to lower the donor concentration (carrier concentration) of the n ⁻ layer 82 that functions as a drift layer. However, in this case, since the resistance when the current flows through the n ⁻ layer 82 at the time of turning on becomes high, the current (on current) flowing between the source electrode 89 and the drain electrode 90 when the MOSFET is turned on is increased. Is no longer possible. That is, the withstand voltage at the time of off and the on-current were in a trade-off relationship.

As described in Patent Document 1, a super junction (SJ) structure has been proposed to solve this problem. The SJ structure is effective in both the planar gate type and the trench gate type, and FIG. 6 is a diagram showing the structure of the semiconductor device 101 in which the SJ structure is applied to a trench gate type power MOSFET corresponding to FIG. is there. Here, a columnar p-type layer 91 connected to the upper p ⁻ layer 83 is formed in the n ⁻ layer 82 between the adjacent grooves 24. In the structure of FIG. 5 in which the columnar p-type layer 91 is not formed, the depletion layer mainly extends in the horizontal direction so that the internal electric field is in the vertical direction. On the other hand, in the structure of FIG. 6 in which the columnar p-type layer 91 is formed, the depletion layer is also formed at the interface between the columnar p-type layer 91 and the n ⁻ layer 82. The depletion layer also extends in the vertical direction, and the depletion layer is uniformly formed in a wider area in the semiconductor substrate 80 than the structure of FIG. As a result, the local increase of the electric field inside the depletion layer is suppressed, and a higher breakdown voltage can be obtained. Alternatively, by using this structure, a high breakdown voltage can be obtained even if the donor concentration of the n ⁻ layer 82 is increased, so that both a high breakdown voltage and a large on-current can be achieved.

JP 2002-184985 A

In the structure of FIG. 6, the area occupied by the drift layer (n ⁻ layer 82) serving as a current path in the semiconductor substrate 80 in plan view is greatly reduced by forming the columnar p-type layer 91. Therefore, when at least the donor concentration of the n ⁻ layer 82 is equal, the on-current is reduced as compared with the structure of FIG. 5 that does not include the columnar p-type layer 91. Therefore, the effect of obtaining a large on-current is actually insufficient with the structure of FIG.

  For this reason, it has been difficult to obtain a power semiconductor device having a high breakdown voltage and a sufficiently large on-current.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The semiconductor device according to the present invention is a semiconductor substrate including a first semiconductor layer having a first conductivity type, and is formed above the first semiconductor layer in the semiconductor substrate and is opposite to the first conductivity type. A second semiconductor layer having the second conductivity type, a groove formed from the upper side to the lower side of the semiconductor substrate, and a gate electrode formed in the groove, and the gate The current flowing between the first main electrode formed on the second semiconductor layer and the second main electrode connected to the first semiconductor layer is controlled by the voltage applied to the electrode. A semiconductor device having a structure in which a plurality of grooves are formed in the semiconductor substrate at intervals, and a columnar semiconductor layer extending in the vertical direction and having the second conductivity type is formed in the grooves. Formed locally in the first semiconductor layer immediately below And in plan view, characterized in that it is not formed between the adjacent two of said groove.
In the semiconductor device of the present invention, the columnar semiconductor layer is electrically connected to the second semiconductor layer.
In the semiconductor device of the present invention, the second semiconductor layer is connected to the first main electrode.
The semiconductor device according to the present invention is characterized in that the columnar semiconductor layer is locally formed in a region where the groove is formed in a plan view.
The semiconductor device of the present invention is a power MOSFET in which the first main electrode is a source electrode and the second main electrode is a drain electrode.

  Since the present invention is configured as described above, a power semiconductor device having a high breakdown voltage and a sufficiently large on-current can be obtained.

It is sectional drawing which shows the structure of the semiconductor device used as embodiment of this invention. It is a figure which shows typically the electric current path at the time of ON of the conventional semiconductor device. It is a figure which shows typically the electric current path at the time of ON of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the modification of the semiconductor device used as embodiment of this invention. It is sectional drawing which shows the structure of the 1st example of the conventional trench gate type semiconductor device. It is sectional drawing which shows the structure of the 2nd example of the conventional trench gate type semiconductor device.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is a trench gate type power MOSFET in which channel on / off is controlled by a voltage (gate voltage) applied to a gate electrode and current switching is controlled. The gate electrode is formed in a plurality of grooves (trench) formed in parallel to the surface of the semiconductor substrate, and the gate electrodes are connected in parallel. A current flowing between the source electrode and the drain electrode flows through a channel formed on the side wall of the groove and an n ⁻ layer formed on the drain electrode side and serving as a drift region.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device (power MOSFET) 10 and corresponds to FIG. In this semiconductor device 10 as well, as in the semiconductor device of FIG. 5 or FIG. 6, the semiconductor substrate 20 in which the n ⁻ layer 22 that becomes the drift layer is formed on the n ⁺ layer 21 that becomes the drain layer, and the n ⁻ layer 22. The p ⁻ layer 23 is formed on the surface side, and the n ⁺ layer 25 locally formed in the p ⁻ layer 23 is provided. A groove 24 is also provided in the same manner, and an oxide film 26 and a gate electrode 27 are provided in the groove 24. Similarly, the interlayer insulating layer 28, the source electrode 29, and the drain electrode 30 are also provided. Further, the groove 24 extends in the direction perpendicular to the paper surface in FIG. 1, and the same is true in that the groove 24 and a plurality of structures related thereto are provided in parallel.

However, in this semiconductor device 10, the columnar p-type layer (columnar semiconductor layer) 11 is provided immediately below the groove 24 and is not provided between the adjacent grooves 24. Further, since the width of the columnar p-type layer 11 is made smaller than the width of the groove 24, the columnar p-type layer 11 is formed in a region where the groove 24 is formed in plan view. For this reason, the columnar p-type layer 11 and the p ⁻ layer 23 are not in contact with each other within the range shown in FIG.

The columnar p-type layer 11 also extends in the direction perpendicular to the paper surface in FIG. The columnar p-type layer 11 is connected to the source electrode 29 at an end in the extending direction (outside the range shown). For this reason, the columnar p-type layer 11 and the p ⁻ layer 23 are not in contact with each other within the range shown in FIG. 1, but they are actually set to the same potential. This is the same as the gate electrode 27 provided for each groove 24 being connected to the common gate wiring at the end of the groove 24. Therefore, like the columnar p-type layer 91 in the semiconductor device 101 (FIG. 6), depletion layers are formed on both the left and right sides of the columnar p-type layer 11 when the semiconductor device 10 is off. As a result, the depletion layer uniformly spreads in the semiconductor substrate 20, thereby suppressing local electric field concentration and obtaining a high breakdown voltage.

  However, in this semiconductor device 10, the current (on current) flowing between the source electrode 29 and the drain electrode 30 at the time of turning on becomes larger, or the on resistance becomes smaller. This will be described below.

First, as a reference, FIG. 2 schematically shows a current path that flows vertically between the source electrode 89 and the drain electrode 90 when the semiconductor device 101 having the conventional SJ structure shown in FIG. 6 is turned on. This current path is a series connection of X0 which is a channel in the p ⁻ layer 23 and Y0 which is a path flowing in the n ⁻ layer 82 which is a drift layer. Here, since the flow of electrons is shown, the direction of the current is actually opposite to the arrow.

Here, the current path X 0 is actually formed on the side surface of the groove 84. On the other hand, the current path Y0 is a drift path in the n ⁻ layer 82 including a portion immediately below the current path X0. The current path Y0 is on the side where the groove 84 is provided (on the right side in the current path Y0 on the left side of the groove 84 in FIG. 2 and on the left side in the current path Y0 on the right side of the groove 84 in FIG. 2). Limited. Further, the current path Y0 is on the side opposite to the side where the groove 84 is provided (the left side in the current path Y0 on the left side of the groove 84 in FIG. 2 and the right side in the current path Y0 on the right side of the groove 84 in FIG. 2) Limited by the presence of the columnar p-type layer 91. That is, in the structure of FIG. 6, the groove 84 and the columnar p-type layer 91 are obstacles to on-current.

On the other hand, an on-state current path in the semiconductor device 10 is shown in FIG. Again, as in FIG. 2, this current path is configured by connecting in series X1 which is a channel in MOSFET and Y1 which flows in n ⁻ layer 22 which is a drift layer. Here, the current path X1, which is the channel of the MOSFET, is not different from the current path X0 in FIG.

On the other hand, the situation of current path Y1 in n ⁻ layer 22 serving as the drift region is different from the situation of current path Y0 in FIG. First, the current path Y1 is on the side where the groove 24 is provided (on the right side in the current path Y1 on the left side of the groove 24 in FIG. 3 and on the left side in the current path Y1 on the right side of the groove 24 in FIG. 3). The points limited by the existence are the same as in the case of FIG. However, on the side opposite to the side where the groove 24 is provided (the left side in the current path Y1 on the left side of the groove 24 in FIG. 3 and the right side in the current path Y1 on the right side of the groove 24 in FIG. 3) There is no obstacle layer.

Here, although the columnar p-type layer 11 that obstructs the current exists immediately below the groove 24, the region where the columnar p-type layer 11 is formed depends on the presence of the groove 24 regardless of the presence or absence of the columnar p-type layer 11. This is a region where the current path Y1 is limited. Therefore, regardless of whether or not the columnar p-type layer 11 is formed immediately below the groove 24, it is difficult for current to flow directly below the groove 24. Compared to the case of FIG. 2, the columnar shape in FIG. The p-type layer 11 does not become a factor that increases the resistance of the current flowing in the vertical direction through the n ⁻ layer 22. That is, in the structure of FIG. 3, the resistance component with respect to the current path Y1 is smaller than the structure of FIG. 2 on the side away from the groove 24, and is equivalent to the structure of FIG. For this reason, the electrical resistance to the current path Y1 in the structure of FIG. 3 is smaller than that of the structure of FIG.

For this reason, in the semiconductor device 10 described above, the on-resistance is reduced as compared with the semiconductor device 101 described above. On the other hand, since the action of the columnar p-type layer 11 on the depletion layer formation at the off time is the same, the breakdown voltage at the off time can be increased. Alternatively, even if the donor concentration of the n ⁻ layer 22 is decreased to further increase the breakdown voltage, a large on-current can be obtained. For this reason, it is possible to achieve both a high breakdown voltage and a large on-current.

In FIG. 2, in order to sufficiently prevent the columnar p-type layer 11 from becoming an obstacle to the current path Y <b> 1, the width of the columnar p-type layer 11 is made smaller than the width of the groove 24. It is preferably formed in the groove 24 in plan view. Similar to the method described in Patent Document 1 and the like, the columnar p-type layer 11 can be formed by, for example, locally implanting acceptor ions into the n ⁻ layer 22 before the groove 24 is formed. This step can be performed before and after ion implantation for forming the p ⁻ layer 23 and the n ⁺ layer 25. The energy at the time of ion implantation for forming the columnar p-type layer 11 is made higher than the energy at the time of ion implantation when the p ⁻ layer 23 is formed, or the acceptor species is changed from that when the p ⁻ layer 23 is formed. Thus, the columnar p-type layer 11 can be formed in the shape shown in FIG. However, the columnar p-type layer 11 may be formed by ion implantation after the groove 24 is formed.

In the above example, the columnar p-type layer 11 is electrically connected to the source electrode 29 or the p ^- layer 23 via the source electrode 29. However, the columnar p-type layer is floated, that is, columnar. Even when the p-type layer is not electrically connected to any of the source electrode, the drain electrode, and the gate electrode, the depletion layer can be uniformly expanded at the off time. On the other hand, the influence of the columnar p-type layer on the on-current is the same. Therefore, the above configuration is effective even when the columnar p-type layer is floating.

The acceptor concentration of the columnar p-type layer 11 is such that the width of the depletion layer formed between the n ⁻ layer 22 and the n ⁺ layer 21 in contact with the columnar p-type layer 11 is sufficiently large and electric field concentration does not occur. Is set. At this time, the acceptor concentration of the columnar p-type layer 11 does not need to be uniform in the vertical direction, and in order to form a depletion layer uniformly, the distribution is such that the concentration increases on one side in the vertical direction. You can also

  Such a columnar p-type layer can also be provided in a semiconductor device other than the structure of FIG. 4 is a cross-sectional view showing a structure of a semiconductor device 40 which is a modification of the semiconductor device 10 of FIG. The structure in the groove 24 of the semiconductor device 40 is the same as that described in Japanese Patent Application Laid-Open No. 2013-069852. In this structure, since the capacitance between the gate electrode 27 and the drain electrode 30 serving as the feedback capacitance Crss can be reduced, the semiconductor device 40 can be operated at high speed. In the structure of FIG. 4, the gate electrode 27 is thinly separated only on the left and right sides of the groove 24 and is formed only on the upper side of the groove 24. In the groove 24, a trench source electrode (shield electrode) 41 is embedded between the left and right gate electrodes 27. Since the trench source electrode 41 is made of polycrystalline silicon doped at a high concentration, like the gate electrode 27, the trench source electrode 41 is formed in the trench 24 by a separate process using the same formation method as the gate electrode 27. Since the trench source electrode 41 is connected to the source electrode 29 outside the illustrated range, the potential thereof is maintained at the source potential. For this reason, the trench source electrode 41 functions as a shield electrode that maintains the potential of this portion at the source potential.

On the other hand, in this structure, a capacitance between the gate electrode 27 and the source electrode 29 is generated between the trench source electrode 41 connected to the source electrode 29 and the gate electrode 27 on both sides thereof. However, the width of the trench source electrode 41 in the drawing is narrower on the upper side than on the lower side, and the oxide film 26 between the gate electrode 27 and the sidewall of the trench 24 (the oxidation on the left side of the left gate electrode 27 in FIG. 4). Compared with the film 26 and the oxide film 26 on the right side of the right gate electrode 27), the oxide film 26 between the trench source electrode 41 and the gate electrodes 27 on both sides thereof can be made sufficiently thick. Such a structure has an oxidation rate at the time of thermal oxidation of the trench source electrode 41 made of polycrystalline silicon highly doped so as to function as an electrode, as described in JP 2013-069852. The p ^- layer 23 and the n ^- layer 22 constituting the inner surface of the groove 24 can be easily manufactured by utilizing the fact that it is larger than the oxidation rate. For this reason, the capacitance between the gate electrode 27 and the source electrode 29 can be kept small.

According to this structure, the feedback capacitance Crss can be reduced. On the other hand, in this structure, since the oxide film 26 on the p ⁻ layer 23 (side surface) on the side surface of the groove 24 where the channel is formed in the MOSFET is thinned, a power MOSFET having good characteristics can be obtained. .

  In this semiconductor device 40 as well, the columnar p-type layer 11 can be provided in the same manner as the semiconductor device 10 described above. Thereby, the depletion layer spreads in a wider range in the semiconductor substrate 20 at the time of off, and the breakdown voltage can be improved. Even when such a shield electrode is used, the breakdown voltage and the on-current are generally in a trade-off relationship, but the semiconductor device 40 can achieve both a high breakdown voltage and a large on-current.

Although the above configuration is an n-channel power MOSFET, the conductivity type (p-type, n-type) can be reversed in all cases, and a p-channel element can be obtained in the same manner. That is, the n ⁻ layer 22 is the first semiconductor layer having the first conductivity type, and the p ⁻ layer 23 and the columnar p-type layer 11 are the second conductivity type opposite to the first conductivity type. In the case of the second semiconductor layer having, it is obvious that a structure similar to the above can be formed and the same effect can be obtained. It is also clear that the same configuration can be applied to a trench gate type IGBT.

10, 40, 100, 101 Semiconductor device (power MOSFET)
11, 91 Columnar p-type layer (columnar semiconductor layer)
20, 80 Semiconductor substrate 21, 25, 81, 85 n ⁺ layer 22, 82 n ⁻ layer 23, 83 p ⁻ layer 24, 84 Groove 26, 86 Oxide film 27, 87 Gate electrode 28, 88 Interlayer insulating layers 29, 89 Source electrode (first main electrode)
30, 90 Drain electrode (second main electrode)
41 Trench source electrode (shield electrode)

Claims (5)

A semiconductor substrate including a first semiconductor layer having a first conductivity type, wherein the second conductivity type is formed above the first semiconductor layer in the semiconductor substrate and is opposite to the first conductivity type. A second semiconductor layer, a groove formed from the upper side to the lower side of the semiconductor substrate, and a gate electrode formed in the groove, and a voltage applied to the gate electrode A plurality of grooves in which a current flowing between a first main electrode formed on the second semiconductor layer and a second main electrode connected to the first semiconductor layer is controlled; A semiconductor device having a structure formed on the semiconductor substrate at an interval,
A columnar semiconductor layer extending in the vertical direction and having the second conductivity type is locally formed in the first semiconductor layer immediately below the groove, and in the plan view, the two adjacent grooves are A semiconductor device which is not formed between.   The semiconductor device according to claim 1, wherein the columnar semiconductor layer is electrically connected to the second semiconductor layer.   The semiconductor device according to claim 2, wherein the second semiconductor layer is connected to the first main electrode.   4. The semiconductor device according to claim 1, wherein the columnar semiconductor layer is locally formed in a region where the groove is formed in a plan view. 5.   5. The semiconductor device according to claim 1, wherein the semiconductor device is a power MOSFET in which the first main electrode is a source electrode and the second main electrode is a drain electrode. 6.

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