JP2016171263A - Processing method of semiconductor wafer, semiconductor chip, and surface protective tape for processing semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processing method of a semiconductor wafer, relating to a processing method of dividing a semiconductor wafer into individual chips by plasma dicing, in which steps of the method are simplified and generation of chipping is suppressed, and to provide a semiconductor chip and a surface protective tape for processing a semiconductor wafer.SOLUTION: The processing method of a semiconductor wafer includes a processing method of a semiconductor wafer by plasma dicing, in which a resist film is formed on a patterned surface of a wafer by, for example, laminating a surface protective tape for protecting the patterned surface, which is integrated with a resist, on the patterned surface; the tape is cut by use of a COlaser in a portion corresponding to a street (scribe line) to form a mask; the wafer is subjected to dicing by SFplasma; and the tack layer and the resist are removed by ashing by Oplasma. A semiconductor chip and a surface protective tape for processing a semiconductor wafer are also disclosed.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a processing method for dividing a semiconductor wafer into chips, more specifically, a semiconductor wafer processing method using plasma dicing, a surface protection tape for semiconductor wafer processing used for plasma dicing, and a semiconductor wafer processing method Relates to a semiconductor chip obtained by:

  The recent evolution of semiconductor chips to thinner and smaller chips is remarkable, especially for IC cards with built-in semiconductor IC chips such as memory cards and smart cards. There is a demand for smaller chips in devices and the like. As these demands increase in the future, the need for thinner and smaller semiconductor chips is expected to increase further.

  These semiconductor chips are obtained by thinning a semiconductor wafer into a predetermined thickness in a back grinding process, an etching process, etc., and then dividing it into individual chips through a dicing process. In this dicing process, a blade dicing method in which cutting is performed by a dicing blade has been used. In the blade dicing method, the cutting resistance by the blade is directly applied to the semiconductor wafer at the time of cutting, and this chipping resistance may cause minute chipping (chipping) in the semiconductor chip. The occurrence of chipping not only impairs the appearance of the semiconductor chip, but in some cases may cause damage to the circuit pattern on the chip, such as chip breakage during pick-up due to insufficient bending strength. Further, in such a physical dicing process using a blade, the width of the kerf (also referred to as a scribe line or street), which is the distance between the chips, cannot be made smaller than the width of the thick blade, and can be taken from a single wafer. The chip yield could not be increased. In addition, the wafer processing time is also a problem.

  In addition to the blade cutting method, various methods are used for the dicing process. In view of the difficulty of dicing after thinning the wafer, grooves are first formed in the wafer by a predetermined thickness, and then grinding is performed to simultaneously reduce the thickness and divide into chips. There is a DBG (first dicing) method. According to this method, the kerf width is the same as that of the blade dicing process, but there is an advantage that the chip bending strength is increased and the chip breakage can be suppressed.

There is also a laser dicing method in which dicing is performed with a laser. Laser dicing can reduce the kerf width and has the advantage of a dry process, but there is a disadvantage that the wafer surface becomes dirty with sublimated material when cutting with laser, and pretreatment to protect with a predetermined liquid protective material is performed There is also. Also, the dry process cannot be completely dry. In the case of a laser, it is possible to perform processing faster than a blade, but since there is no change in processing one line at a time, it takes time to manufacture a very small chip.
When using a wet process such as a water jet method in which dicing is performed with water pressure, a problem may occur in an area where surface contamination is a concern, such as a MEMS device or a CMOS sensor. There are also disadvantages that the kerf width cannot be narrowed and the chip yield does not increase.

  The stealth dicing method, in which a modified layer is formed with a laser in the thickness direction of the wafer, expanded, divided and separated into individual pieces, has the merit that the kerf width can be reduced to zero and processing can be performed dry. However, the chip bending strength does not increase as expected from the thermal history when the modified layer is formed, and silicon scraps may be generated when expanding and dividing. Furthermore, there is a possibility that the bending strength will be insufficient due to a collision with an adjacent chip.

  Furthermore, as a method that combines stealth dicing and tip dicing, a modified layer is formed by a predetermined thickness before thinning, and then grinding from the back side is performed to reduce the thickness of the thin film and form individual chips. There is a chip singulation method corresponding to a narrow scribe width that performs singulation simultaneously. This technology improves the disadvantages of the above process, and the modified layer of silicon is cleaved and separated by stress during wafer back grinding, so the kerf width is zero, the chip yield is high, There is a merit that folding strength is improved. However, since it is divided into individual pieces during the back surface grinding process, there is a case where a chip end face collides with an adjacent chip and a chip corner is chipped.

  There is a plasma dicing method (see, for example, Patent Document 1). Plasma dicing is a method of dividing a semiconductor wafer by selectively etching a portion not covered with a mask with plasma. When this dicing method is used, the chip can be selectively divided, and even if the scribe line is bent, it can be divided without any problem. In addition, since the etching rate is very high, it has been regarded as one of the most suitable processes for chip cutting in recent years.

JP 2007-19385 A

In the plasma dicing method, a fluorine-based gas having a very high reactivity with a wafer, such as sulfur hexafluoride (SF ₆ ) or carbon tetrafluoride (CF ₄ ), is used as a plasma generating gas. From the rate, it is essential to protect the non-etched surface with a mask, and it is necessary to form a mask with a resist or tape in advance.

  In order to form this mask, as described in Patent Document 1, after a resist is applied to the back surface of the wafer, a portion corresponding to the street is removed by a photolithography process to form a mask. is there. Therefore, in order to perform the plasma dicing, a photolithographic process facility other than the plasma dicing facility is necessary, and there is a problem that the chip cost increases. Further, since the resist film remains after the plasma etching, if a large amount of solvent is used for removing the resist and the resist cannot be removed, there is a possibility that a defective chip is generated due to adhesive residue. Furthermore, since the resist masking process is performed, there is a disadvantage that the entire processing process becomes long.

The present invention has been made in view of such problems, and in the processing of a semiconductor wafer using plasma dicing, the generation of a new semiconductor wafer that suppresses the occurrence of chipping and eliminates the conventional disadvantages when performing plasma dicing is provided. An object is to provide a processing method.
Another object of the present invention is to provide a semiconductor chip obtained through this semiconductor wafer processing method, and to provide a surface protection tape for semiconductor wafer processing necessary for carrying out this semiconductor wafer processing method.

The said subject of this invention is realizable by the following means.
[1] A method for processing a semiconductor wafer,
(A) a step of providing a resist film on the pattern surface side of the semiconductor wafer by any of the following (a1) or (a2);
(A1) A resist is applied to the pattern surface of the semiconductor wafer and prebaked, and then a surface protection tape having a tack layer on the base film is bonded to the surface on which the resist is applied.
(A2) A resist-coated surface protective tape in which a tack layer and a resist layer are laminated in order on the base film is bonded to the pattern surface side of the semiconductor wafer.
(B) A process of grinding the back surface of the semiconductor wafer, bonding the wafer fixing tape to the ground back surface, and supporting and fixing with a ring frame in a state where any one of the above surface protection tapes is bonded,
(C) Opening the street from the pattern surface side of the semiconductor wafer by a process including cutting of the portion corresponding to the street of the semiconductor wafer with a CO ₂ laser and peeling of the base film from any one of the above surface protective tapes The process of
(D) a plasma dicing step in which the semiconductor wafer is divided at the streets by SF ₆ plasma and separated into semiconductor chips, and
(E) An ashing step of removing the tack layer and the resist film with O ₂ plasma.
[2] The step (a) is the step (a1), and the step (c) includes (i) a step of peeling only the base film bonded to the pattern surface of the semiconductor wafer, and (Ii) A step of opening the street of the semiconductor wafer by cutting the tack layer corresponding to the street of the semiconductor wafer and the resist film with a CO ₂ laser in the exposed tack layer [1] A method for processing a semiconductor wafer according to claim 1.
[3] The (a) step is the (a2), and the (c) step is (iii) the resist-coated surface protective tape bonded to the pattern surface of the semiconductor wafer. A step of peeling the film, and (iv) a step of opening the street of the semiconductor wafer by cutting the tack layer corresponding to the street of the semiconductor wafer and the resist film with a CO ₂ laser in the exposed tack layer. The method for processing a semiconductor wafer according to [1], wherein:
[4] The step (a) is the step (a2), and the step (c) is (v) a portion of the resist-coated surface protective tape corresponding to the street of the semiconductor wafer is a CO ₂ laser. And (vi) irradiating the piece of resist-coated surface protective tape with ultraviolet rays and peeling the substrate film [1]. A method for processing a semiconductor wafer according to claim 1.
[5] The step (a) is the step (a2), and after the back surface of the semiconductor wafer is ground in the step (b), the bonded surface protective tape with resist is irradiated with ultraviolet rays. And (v) the step of (v) cutting the portion of the resist-coated surface protective tape corresponding to the street of the semiconductor wafer with a CO ₂ laser to open the street of the semiconductor wafer; and (vii) The method for treating a semiconductor wafer according to [1], wherein the substrate film is peeled from the resist-coated surface protective tape separated into pieces.
[6] The semiconductor wafer according to [5], wherein the step (a) is the step (a2), and the bonding of the resist-coated surface protective tape is performed while heating. Processing method.
[7] The method of processing a semiconductor wafer according to any one of [1] to [6], wherein the wafer fixing tape in the step (b) is a dicing tape or a dicing die bonding tape.
[8] The method for processing a semiconductor wafer according to any one of [1] to [7], further including a step of picking up a chip from the wafer fixing tape after the step (f).
[9] The method for processing a semiconductor wafer according to [8], including a step of transferring the picked-up chip to a die bonding step.
[10] The semiconductor wafer according to [1] or [2], wherein the surface protective tape in (a1) is a tack film in which a base film portion and a tack layer are formed by coextrusion. Processing method.
[11] A semiconductor chip manufactured by the method for processing a semiconductor wafer according to any one of [1] to [10].
[12] A surface protection tape for semiconductor wafer processing, comprising a tack layer on a base film and a resist layer on the tack layer.
[13] The semiconductor wafer processing surface protective tape is a resist-coated surface protective tape used in the semiconductor wafer processing method according to any one of [1] and [3] to [10]. The surface protection tape for semiconductor wafer processing as described in [12].

  According to the present invention, chipping of the chip cut surface can be reduced. Moreover, the manufacturing cost can be simplified and the process cost can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic sectional drawing explaining the process until surface protection tape bonding to the semiconductor wafer in 1st Embodiment of this invention, Minute drawing 1 (a) shows a semiconductor wafer, Minute drawing 1 (b) shows a resist. The applied state is shown, and FIG. 1 (c) shows a state in which the surface protection tape is bonded. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic sectional drawing explaining the process from thinning of the semiconductor wafer to peeling of a base film in 1st Embodiment of this invention, FIG.2 (a) shows the thinning process of a semiconductor wafer, 2 (b) shows a state where the wafer fixing tape is bonded and fixed to the ring frame, and FIG. 2 (c) shows a state where the base film is peeled off. It is a schematic sectional drawing explaining the process to the plasma dicing in 1st Embodiment of this invention, FIG.3 (a) shows the process of excising the tack layer and resist film which correspond to a street with a laser, and FIG. (B) shows a state where plasma dicing is performed, and FIG. 3 (c) shows a state of being divided into chips. FIGS. 4A and 4B are schematic cross-sectional views illustrating a process until a chip is picked up according to the first embodiment of the present invention, where FIG. 4A shows a state where plasma ashing is performed, and FIG. 4B becomes a mask. FIG. 4C shows a state where the tack layer and the resist film are removed, and FIG. 4C shows a state where the chip is picked up. It is a schematic sectional drawing which shows the mode of bonding of the surface protection tape with a resist in 2nd Embodiment of this invention. It is a schematic sectional drawing explaining the state before and behind the ultraviolet irradiation process in the case of performing an ultraviolet irradiation process in 1st, 2nd embodiment of this invention, and FIG.6 (a) is each a surface protection tape on both front and back of a semiconductor wafer. FIG. 6 (b) shows a state in which ultraviolet rays are irradiated, and FIG. 6 (c) shows a state in which the base film is peeled off from the surface protection tape. It is a schematic sectional drawing of the preferable aspect explaining the process centering on the process of cutting off the surface protection tape corresponding to a street and the resist film with the laser in 3rd Embodiment of this invention, and FIG.7 (a) is a laser. FIG. 7 (b) shows a state in which the tack layer corresponding to the street and the resist film are removed, and FIG. 7 (b) shows a state in which ultraviolet rays are irradiated. FIG. 7 (c) shows a state in which the base film is peeled off from the surface protection tape. Indicates. It is a schematic sectional drawing explaining another preferable aspect explaining the process centering on the process of excising the surface protection tape corresponding to a street and the resist film with the laser in 3rd Embodiment of this invention, FIG. ) Shows a state in which ultraviolet rays are irradiated, FIG. 8B shows a step of cutting the surface protective tape corresponding to the street and the resist film with a laser, and FIG. 8C shows the substrate from the surface protective tape. The state where the film is peeled off is shown.

The semiconductor wafer processing method of the present invention corresponds to a street in a semiconductor wafer in which a resist film is provided on a pattern surface and a tack film and a base film of a surface protection tape are provided on the resist film as described below. By cutting the portion to be cut with a CO ₂ laser to form a mask and dicing with this mask using SF ₆ plasma, a photolithography process is not required, and the manufacturing cost can be reduced.

The semiconductor wafer processing method of the present invention includes at least the following steps (a) to (e).
(A) a step of providing a resist film on the pattern surface side of the semiconductor wafer by any of the following (a1) or (a2);
(A1) A resist is applied to the pattern surface of the semiconductor wafer and prebaked, and then a surface protection tape having a tack layer on the base film is bonded to the surface on which the resist is applied.
(A2) A resist-coated surface protective tape in which a tack layer and a resist layer are laminated in order on the base film is bonded to the pattern surface side of the semiconductor wafer.
(B) A process of grinding the back surface of the semiconductor wafer, bonding the wafer fixing tape to the ground back surface, and supporting and fixing with a ring frame in a state where any one of the above surface protection tapes is bonded,
(C) A step of opening the street from the pattern surface side of the semiconductor wafer by a step including cutting of the portion corresponding to the street of the semiconductor wafer with a CO ₂ laser and peeling of the base film from any one of the above surface protective tapes ,
(D) a plasma dicing process in which the semiconductor wafer is divided into streets by dividing the semiconductor wafer with SF ₆ plasma into pieces, and
(E) Ashing process for removing tack layer and resist film with O ₂ plasma

Here, in the step (c), even if the base film is peeled after being cut by the CO ₂ laser, the base film is peeled first, and then the CO ₂ laser is cut. Also good.
In the step (a), in the case of (a1), it is preferable that the base film is peeled first and then cut with a CO ₂ laser. In the case of (a2), either may be used.

It is also preferable to cure the tack layer by irradiating with ultraviolet rays before peeling off the base film, and in particular, in the case of (a2), the surface protective tape with resist is bonded to the surface of the semiconductor wafer in the step (a). preferable.
In the case of (a2), in the step (a), a surface protection tape with a resist is bonded to the surface of the semiconductor wafer, after the back surface of the semiconductor wafer is ground in the step (b) (preferably, wafer fixing) It is preferable to irradiate the resist-coated surface protective tape with ultraviolet rays before bonding the tape.
Furthermore, in the above step (a), in the case of bonding the surface protective tape with resist to the surface of the semiconductor wafer (a2), when bonding the surface protective tape with resist to the surface of the semiconductor wafer, it is stretched while heating. It is preferable to do.

Here, in the plasma treatment using SF ₆ plasma in the step (d), a portion corresponding to the street is opened from the pattern surface side of the semiconductor wafer, and plasma is applied to the opening portion from the side where the resist film is provided. The chip is separated into individual pieces by processing.

Hereinafter, preferred embodiments of the semiconductor wafer processing method of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
The semiconductor wafer processing method of the present invention is preferably classified into the following first to third embodiments as described below.
In addition, as long as there is no notice, the apparatus and material which are used for the process shown below can use the apparatus etc. which were conventionally used for the processing of a semiconductor wafer, The use conditions are appropriate conditions by a conventional method. Can be set. In addition, duplicate descriptions of materials, structures, methods, effects, and the like common to the embodiments are omitted.

<< First Embodiment [FIGS. 1 to 4] >>
A semiconductor wafer singulation method according to a first preferred embodiment of the present invention will be described with reference to FIGS.
The semiconductor wafer 1 has a pattern surface 2 on which a circuit of a semiconductor element and the like are formed on the surface S (see FIG. 1A). A resist 3 is applied to the pattern surface 2 and prebaked (see FIG. 1B). And the surface protection tape 4 is further bonded to the surface in which this resist 3 was formed (refer FIG.1 (c)). The surface protective tape 4 is a tape configured by providing a tack layer 4b on the surface of the base film 4a. Thus, the semiconductor wafer 1 in which the pattern surface 2 is coated with the resist 3 and the surface protective tape 4 is obtained.

  Next, the back surface B of the semiconductor wafer 1 is ground by the wafer grinding apparatus M1 to reduce the thickness of the semiconductor wafer 1 (see FIG. 2A). Wafer fixing tape 5 is bonded to the ground back surface B and supported and fixed to the ring frame F (see FIG. 2B). Next, the base film 4a of the surface protection tape 4 is peeled off from the semiconductor wafer 1 and the tack layer 4b is left on the semiconductor wafer 1 (see FIG. 2C) to expose the tack layer 4b.

Then, a CO ₂ laser L is irradiated to a plurality of streets (not shown) appropriately formed in a lattice shape or the like on the pattern surface 2 from the surface S side, and the tack layer 4b and the resist 3 are removed and opened. (See FIG. 3 (a)). Next, the surface of the surface S is treated with SF ₆ gas plasma P1, and the semiconductor wafer 1 exposed at the street portion is etched (see FIG. 3 (b)). (See FIG. 3 (c)).

Next, ashing is performed by plasma P2 of O ₂ gas (see FIG. 4A), and the tack layer 4b and the resist 3 remaining on the surface S are removed (see FIG. 4B). The separated chip 7 is pushed up by the pin M2 and picked up by being picked up by the collet M3 (see FIG. 4C).

Here, the Si etching process of the semiconductor wafer using SF ₆ gas is also referred to as a BOSCH process, and the exposed Si reacts with F atoms generated by converting SF ₆ into plasma to produce silicon tetrafluoride (SiF ₄ ) And is also called reactive ion etching (RIE). On the other hand, the removal by O ₂ plasma is also used as a plasma cleaner in the semiconductor manufacturing process and is called ashing (ashing), and is one of the methods for removing organic matter. This is performed in order to clean the organic residue remaining on the surface of the semiconductor device.

Next, materials used in the above method will be described.
The semiconductor wafer 1 is a silicon wafer or the like having a pattern surface 2 on which a semiconductor element circuit or the like is formed on one side. The pattern surface 2 is a surface on which a semiconductor element circuit or the like is formed, and is a lattice in plan view. It has a street shape.

As the resist 3, a conventionally known general material such as a resist used in a photolithography process can be applied. Moreover, the application | coating process to the pattern surface 2 can utilize common methods, such as a spin coat, The thickness can also be made into a general thickness.
For example, the resist includes dry film type solder resist: SRF series made by Toa Gosei, photosensitive dry film: Asahi Kasei SUNFORT series, photosensitive film: Hitachi Chemical Fotec series, photosensitive liquid solder resist: made by Hitachi Chemical, JSR Among these, a photosensitive liquid solder resist is preferable. Moreover, 1-20 micrometers is preferable, as for thickness, 5-15 micrometers is more preferable, and 5-10 micrometers is further more preferable.

  The surface protection tape 4 has a structure in which a tack layer 4b is provided on a base film 4a, and has a function of protecting a semiconductor element formed on the pattern surface 2. That is, in the subsequent wafer thinning process, since the semiconductor wafer 1 is supported by the pattern surface 2 and the back surface of the wafer is ground, it is necessary to withstand the load during grinding. Therefore, the surface protective tape 4 is different from the mere resist 3 in that it has a thickness sufficient to cover the elements formed on the pattern surface, has a low pressing resistance, and does not allow ingress of dust or grinding water during grinding. It has a high degree of adhesion that allows the device to be closely attached.

  Of the surface protection tape 4, the base film 4a is made of plastic, rubber, or the like. For example, polyethylene, polypropylene, ethylene-propylene copolymer, polybutene-1, poly-4-methylpentene-1, ethylene-vinyl acetate copolymer. , Homopolymers or copolymers of α-olefins such as ethylene-acrylic acid copolymers and ionomers, or mixtures thereof, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyetherimide, polyimide, polycarbonate, polymethyl methacrylate , Polyurethane, styrene-ethylene-butene- or a pentene-based copolymer or a mixture of two or more of them, and a resin composition in which other resins, fillers, additives, etc. are blended. So It can be cited as the material can be arbitrarily selected depending on the required characteristics. Low density polyethylene and ethylene vinyl acetate copolymer laminates, polypropylene and polyethylene terephthalate laminates, polyethylene terephthalate, and polyethylene naphthalate are suitable materials.

  These base films 4a can be manufactured by using a general extrusion method. However, when the base film 4a is obtained by laminating various resins, the base film 4a is manufactured by a co-extrusion method, a laminating method, etc. An adhesive layer may be provided between the resins, as is normally done in the ordinary laminate film manufacturing process. The thickness of the base film 4a is preferably 20 to 200 [mu] m, and 25 [mu] m is one of preferred embodiments from the viewpoints of strength / elongation characteristics and radiation transparency.

The tack layer 4b may be any layer that does not damage the semiconductor element or the like when adhered to the pattern surface 2 and does not cause damage to the semiconductor element or residual adhesive on the surface when removed. However, it is preferable to have plasma resistance that functions as a mask during plasma dicing.
Therefore, the tack layer 4b has a non-curing pressure-sensitive adhesive having such properties, and preferably a surface after the pressure-sensitive adhesive is three-dimensionally reticulated by radiation, more preferably by UV curing, and the pressure-sensitive adhesive force decreases and peels off. In addition, it is possible to use a radiation polymerization type pressure sensitive adhesive such as an ultraviolet curable type or an ionizing radiation curable type such as an electron beam which hardly causes a residue such as a pressure sensitive adhesive.
Radiation is a concept including light rays such as ultraviolet rays and ionizing radiations such as electron beams.

As such an adhesive, an acrylic adhesive or an adhesive mainly composed of this acrylic adhesive and a radiation polymerizable compound can be used.
The acrylic pressure-sensitive adhesive contains a (meth) acrylic copolymer and a curing agent as components. The (meth) acrylic copolymer is, for example, a polymer having a (meth) acrylic acid ester as a polymer constituent unit, and a (meth) acrylic polymer of a (meth) acrylic acid ester copolymer, or functionality. Examples include copolymers with monomers, and mixtures of these polymers. As the molecular weight of these polymers, those having a mass average molecular weight of about 500,000 to 1,000,000 are generally applied.

  A hardening | curing agent is used in order to make it react with the functional group which a (meth) acrylic-type copolymer has, and to adjust adhesive force and cohesion force. For example, 1,3-bis (N, N-diglycidylaminomethyl) cyclohexane, 1,3-bis (N, N-diglycidylaminomethyl) toluene, 1,3-bis (N, N-diglycidylaminomethyl) ) Epoxy compounds having two or more epoxy groups in the molecule such as benzene, N, N, N, N′-tetraglycidyl-m-xylenediamine, 2,4-tolylene diisocyanate, 2,6-tolylene diisocyanate , 1,3-xylylene diisocyanate, 1,4-xylene diisocyanate, diphenylmethane-4,4′-diisocyanate and the like, an isocyanate compound having two or more isocyanate groups in the molecule, tetramethylol-tri-β-aziridini Lupropionate, trimethylol-tri-β-aziridinylpropionate, Examples thereof include aziridine compounds having two or more aziridinyl groups in the molecule, such as dimethylolpropane-tri-β-aziridinylpropionate and trimethylolpropane-tri-β- (2-methylaziridine) propionate. . What is necessary is just to adjust the addition amount of a hardening | curing agent according to desired adhesive force, and 0.1-5.0 mass parts is suitable with respect to 100 mass parts of (meth) acrylic-type copolymers.

A pressure-sensitive adhesive that is cured by radiation is referred to as a radiation-curable pressure-sensitive adhesive, and a pressure-sensitive adhesive that is not cured by radiation is referred to as a pressure-sensitive pressure-sensitive adhesive.
The radiation curable pressure-sensitive adhesive generally comprises the above acrylic pressure-sensitive adhesive and a radiation polymerizable compound as main components. As the radiation-polymerizable compound, for example, a low molecular weight compound having at least two photopolymerizable carbon-carbon double bonds in a molecule that can be three-dimensionally reticulated by irradiation with ultraviolet rays is widely used. Specifically, trimethylol is used. Propane triacrylate, tetramethylol methane tetraacrylate, pentaerythritol triacrylate, pentaerythritol tetraacrylate, dipentaerythritol monohydroxypentaacrylate, dipentaerythritol hexaacrylate, 1,4-butylene glycol diacrylate, 1,6-hexanediol di Acrylate, polyethylene glycol diacrylate, oligoester acrylate and the like are widely applicable.

  In addition to the above acrylate compounds, urethane acrylate oligomers can also be used. The urethane acrylate oligomer includes a polyol compound such as a polyester type or a polyether type, and a polyvalent isocyanate compound (for example, 2,4-tolylene diisocyanate, 2,6-tolylene diisocyanate, 1,3-xylylene diene). A terminal isocyanate urethane prepolymer obtained by reacting isocyanate, 1,4-xylylene diisocyanate, diphenylmethane 4,4-diisocyanate, etc.) with an acrylate or methacrylate having a hydroxyl group (for example, 2-hydroxyethyl) Acrylate, 2-hydroxyethyl methacrylate, 2-hydroxypropyl acrylate, 2-hydroxypropyl methacrylate, polyethylene glycol acrylate, polyethylene glycol methacrylate, etc.) Obtained by the reaction.

As a compounding ratio of the acrylic pressure-sensitive adhesive and the radiation-polymerizable compound in the radiation-curable pressure-sensitive adhesive, the radiation-polymerizable compound is 50 to 200 parts by weight, preferably 50 to 150 parts by weight with respect to 100 parts by weight of the acrylic pressure-sensitive adhesive. It is desirable to blend in the range of parts. When the blending ratio is in this range, the tack strength of the tack layer is greatly reduced after irradiation.
Furthermore, the radiation-curable pressure-sensitive adhesive can be made into a radiation-polymerizable acrylic ester copolymer instead of blending the radiation-polymerizable compound with the acrylic pressure-sensitive adhesive as described above. is there.
The radiation-polymerizable acrylic acid ester copolymer is a copolymer having a reactive group capable of undergoing a polymerization reaction by irradiation with radiation, particularly ultraviolet rays, in the copolymer molecule. Such a reactive group is preferably an ethylenically unsaturated group, that is, a group having a carbon-carbon double bond. For example, a vinyl group, an allyl group, a styryl group, a (meth) acryloyloxy group, (meta ) Acryloroylamino group and the like.
Such a reactive group has, for example, a copolymer having a hydroxyl group in a side chain of the copolymer polymer, a group that reacts with a hydroxyl group, such as an isocyanate group, and a polymerization reaction by ultraviolet irradiation. It can be obtained by reacting the above-mentioned compound having a reactive group [typically, 2- (meth) acryloyloxyethyl isocyanate].

  When the tack layer is polymerized by radiation, a photopolymerization initiator such as isopropyl benzoin ether, isobutyl benzoin ether, benzophenone, Michler's ketone, chlorothioxanthone, benzyl methyl ketal, α-hydroxycyclohexyl phenyl ketone, 2-hydroxymethyl Phenylpropane can be used in combination. By adding at least one of these to the tack layer, the polymerization reaction can proceed efficiently.

  An acrylic pressure-sensitive adhesive composed of a copolymer of 2-ethylhexyl acrylate and n-butyl acrylate contains a (meth) acrylate compound having a UV-curable carbon-carbon double bond, a photoinitiator and a light A preferred embodiment is a pressure-sensitive adhesive comprising a sensitizer and other conventionally known tackifiers, softeners, antioxidants and the like.

  The tack layer made of a radiation curable pressure sensitive adhesive or a radiation curable pressure sensitive adhesive is a radiation curable pressure sensitive adhesive or a pressure sensitive adhesive made of a radiation curable pressure sensitive adhesive described in paragraph numbers 0036 to 0055 of JP-A-2014-192204. A layer is preferred.

5-100 micrometers is preferable and, as for the thickness of the tack layer 4b, 5-30 micrometers is more preferable. If the thickness is less than 5 μm, protection of the elements formed on the pattern surface 2 may be insufficient, and if the adhesion to the unevenness of the pattern surface is insufficient, the invasion of SF ₆ gas may damage the device. Damage occurs. On the other hand, if it exceeds 100 μm, ashing with O ₂ plasma becomes difficult. Although depending on the type of device, the unevenness of the pattern surface is about several μm to 15 μm, and therefore 5 to 30 μm is more preferable.

  In addition to the surface protective tape 4 made of the above material, a known surface protective tape that protects the pattern surface 2 of the semiconductor wafer 1 can also be used as the surface protective tape 4.

  In addition to the pressure-sensitive adhesive made of the above materials, the tack layer 4b can be provided by including an anchor layer on the base film 4a side. This anchor layer is usually made of an acrylic pressure-sensitive adhesive having a (meth) acrylic copolymer and a curing agent as essential components, and a pressure-sensitive pressure-sensitive adhesive is used.

In order to easily peel off only the base film 4a between the base film 4a and the tack layer 4b, it is preferable not to perform a corona treatment as an adhesion improving process or an easy adhesion primer coating.
For the same purpose, the tack layer 4b is preferably laminated on the smooth surface of the base film 4a, and the tack layer 4b is not laminated on the uneven surface (texture surface) of the base film 4a. preferable. This is because the adhesion of the tack layer 4b to the base film 4a is enhanced when laminated on the uneven surface. Moreover, it is also preferable to use the separator which makes easy peeling with the tack layer 4b as the base film 4a.

  In addition, it is also preferable to use the fine tack film formed into the surface protection tape 4 by co-pushing. The micro-tack film formed by co-extrusion is obtained by extruding two different types of resins on the base film 4a by a technique used for masking tape, etc. The layers on the base film 4a are two layers. Or it has a sea-island structure, and the resin on one side of the two types of resins has tack at room temperature. Examples of the resin having tack at normal temperature include ethylene-vinyl alcohol copolymer (EVA) whose vinyl alcohol (VA) content exceeds 30% by mass, ethylene-acrylate copolymer (EMA), and the like. . The layer on the base film 4a corresponds to the tack layer 4b.

  The wafer fixing tape 5 holds the semiconductor wafer 1 and needs to have a plasma resistance that can withstand even if it is exposed to a plasma dicing process. Further, in the pick-up process, good pick-up properties and, in some cases, expandability and the like are also required. As the wafer fixing tape 5, the same tape as the surface protective tape 4 can be used. Moreover, the well-known dicing tape utilized with the conventional plasma dicing system generally called a dicing tape can be used. In order to facilitate the transition to the die bonding step after pickup, a die bonding tape in which a die bonding adhesive is laminated between the tack layer and the base film can also be used.

For the laser irradiation for cutting the tack layer 4b and the resist 3, a laser irradiation apparatus that irradiates ultraviolet or infrared laser light can be used. In this laser beam irradiation apparatus, a laser irradiation unit is disposed so as to be movable along the streets of the semiconductor wafer 1, and a laser with an appropriately controlled output can be irradiated to remove the tack layer 4b. If a CO ₂ laser is used as the laser light, a large output of several W to several tens W can be obtained, and a CO ₂ laser can be suitably used among lasers.

  A plasma etching apparatus can be used to perform plasma dicing and plasma ashing. The plasma etching apparatus is an apparatus capable of performing dry etching on the semiconductor wafer 1. The plasma etching apparatus creates a sealed processing space in the vacuum chamber, the semiconductor wafer 1 is placed on the high frequency side electrode, and faces the high frequency side electrode. The gas for generating plasma is supplied from the gas supply electrode provided. If a high-frequency voltage is applied to the high-frequency side electrode, plasma is generated between the gas supply electrode and the high-frequency side electrode, and this plasma is used. A refrigerant is circulated in the heat generating high frequency electrode to prevent the temperature of the semiconductor wafer 1 from being raised by the heat of the plasma.

According to the semiconductor wafer processing method, a mask can be formed by removing the surface protection tape and the resist for protecting the pattern surface with a CO ₂ laser, so that high-level alignment such as printing and transfer is required for the mask formation Therefore, the photolithography process and the like used in the conventional plasma dicing process are also unnecessary.
Further, since the tack layer 4b and the resist 3 can be removed by O ₂ plasma, the mask portion can be removed by the same apparatus as that for plasma dicing. In addition, since plasma dicing is performed from the pattern surface 2 side (surface S side), it is not necessary to invert the chip upside down before the picking operation. For these reasons, the equipment can be simplified and the process cost can be greatly reduced.

<< Second Embodiment [FIG. 5] >>
In 1st Embodiment, after apply | coating the resist 3, the surface protection tape 4 was bonded, However, In this embodiment, the surface protection tape 6 with a resist with which the surface protection tape and the resist were united is used. It is different. In other words, the step of laminating the resist 3 on the surface protective tape 4 and integrating it with the surface protective tape is performed in advance.
Specifically, referring to the drawings, a resist-coated surface protective tape 6 in which a surface protective tape 4 and a resist 3 are integrated is bonded to a semiconductor wafer 1 on which a pattern surface 2 is formed (see FIG. 5). Subsequent steps are the same as those in the first embodiment.

In order to obtain the resist-coated surface protective tape 6, the resist 3 is laminated on the tack layer 4 b of the surface protective tape 4.
More specifically, in the case of a liquid solder resist, the surface protective tape 4 is laminated and integrated after being applied and dried. In the case of a dry resist film, the protective tape 4 is laminated and integrated as it is.

  The bonding of the resist-coated surface protective tape 6 to the pattern surface 2 can be performed while heating the resist-coated surface protective tape 6. The resist 3 can be softened by heating, and the followability and adhesion to the pattern surface 2 can be improved.

  In this embodiment, since the resist-coated surface protective tape 6 is used, it is not necessary to apply the resist 3, so that the manufacturing equipment can be further simplified.

In both the first and second embodiments, the tack layer 4b may be cured by irradiating with ultraviolet rays before the step of peeling the base film 4a. For example, FIG. 6 shows a process in which the wafer fixing tape 5 is bonded to the ground back surface, supported and fixed by the ring frame F, and then irradiated with ultraviolet rays to peel off the base film 4a.
That is, if it demonstrates based on drawing, on the surface S side in which the pattern surface 2 of the semiconductor wafer 1 was formed, the resist 3 is apply | coated and the surface protection tape 4 is bonded, or the surface protection tape 6 with a resist is bonded. Then, the wafer fixing tape 5 is bonded to the ground back surface B side of the semiconductor wafer 1 and supported and fixed to the ring frame F (see FIGS. 2B and 6A). Next, ultraviolet rays UV are irradiated from the surface S side (see FIG. 6B). Then, after the tack layer 4b is cured, the base film 4a is removed (see FIG. 6C), and the tack layer 4b is exposed. Next, the process moves to the step of removing the tack layer 4b and the resist 3 corresponding to the streets by the laser L.

<< Third Embodiment [FIG. 7], [FIG. 8] >>
In the first and second embodiments, after removing the base film 4a of the surface protective tape 4 or the resist-coated surface protective tape 6 from the semiconductor wafer 1, the tack layer 4b and the resist 3 are removed by irradiation with a CO ₂ laser L. Then, although the street portion is opened, in this embodiment, the base film 4a, the tack layer 4b, and the resist 3 are removed and the treat portion is opened without peeling off the base film 4a. For this reason, the base film 4a peels after opening.
Subsequent steps are the same as those in the first embodiment.

In this embodiment, it is preferable when using the resist-coated surface protective tape 6.
Moreover, it is preferable to cure the tack layer 4b by irradiating with ultraviolet rays before the step of peeling the base film 4a. Before the step of peeling the base film 4a, it may be any time as long as it is before the step of peeling the base film 4a, but after the back surface B of the semiconductor wafer 1 is ground, After grinding the back surface B and before bonding of the wafer fixing tape 5 or immediately before peeling the base film 4a (the street portion is cut with a CO ₂ laser L and the street is opened from the pattern surface side of the semiconductor wafer 1) Is more preferable. By curing the tack layer 4b with ultraviolet rays or the like, peeling from the base film 4a can be facilitated, and plasma resistance during plasma dicing can be improved.

  In this embodiment, since the base film 4a is cut with a laser, the peeling process can be simplified by one process.

  In particular, when the tack layer 4b is cured, the surface protective tape 4 or resist-coated surface protective tape 6 used in this embodiment is the surface protective tape 4 or resist-coated surface protective tape shown in the first or second embodiment. Among them, those using a material curable with radiation such as ultraviolet rays for the tack layer 4b are preferable.

  In addition, when using the surface protection tape 6 with a resist, similarly to 2nd Embodiment, bonding to the pattern surface 2 of the surface protection tape 6 with a resist is performed, heating this surface protection tape 6 with a resist. be able to.

The case immediately before ultraviolet irradiation peels the base film 4a is demonstrated based on FIG.
The case where ultraviolet irradiation is after grinding the back surface B of the semiconductor wafer 1 and before bonding of the wafer fixing tape 5 will be described with reference to FIG.

In FIG. 7, the surface protective tape 4 or the resist-coated surface protective tape 6 is bonded to the surface S side of the semiconductor wafer 1 on which the pattern surface 2 is formed, and the wafer fixing tape is applied to the ground back surface B side of the semiconductor wafer 1. 5 is bonded and fixed to the ring frame F, and then irradiated with CO ₂ laser L to a plurality of streets (not shown) appropriately formed in a lattice shape or the like from the surface S side, and the surface protection tape 4 and the resist 3 or the resist-coated surface protective tape 6 are removed to open the street portion (see FIG. 7A). Next, ultraviolet rays UV are irradiated from the surface S side toward the surface protective tape 4 or the resist-coated surface protective tape 6 (see FIG. 7B), and the tack layer 4b of the surface protective tape 4 or the resist-coated surface protective tape 6 is applied. After curing, the base film 4a is removed (see FIG. 7C), and the tack layer 4b is exposed. And it transfers to a plasma dicing process.

  The substrate film 4a remaining on the mask portion can be easily removed by attaching a separately prepared adhesive tape to the substrate film 4a to be removed and removing the substrate film 4a together with the adhesive tape. The film 4a can be removed, which is preferable.

In FIG. 8, the surface protective tape 4 or the resist-coated surface protective tape 6 is bonded to the surface S side of the semiconductor wafer 1 on which the pattern surface 2 is formed, and the wafer fixing tape is applied to the ground back surface B side of the semiconductor wafer 1. 5 is bonded and fixed to the ring frame F, and then UV light is irradiated from the surface S side toward the surface protective tape 4 or the surface protective tape 6 with resist (see FIG. 8A). 4 or the tack layer 4b of the resist-coated surface protective tape 6 is cured. Next, a plurality of streets (not shown) appropriately formed in a lattice shape or the like from the surface S side are irradiated with CO ₂ laser L, and the surface protective tape 4 and the resist 3 or the surface protective tape 6 with a resist are formed. The street portion is removed and removed (see FIG. 8B). And the base film 4a is removed (refer FIG.8 (c)), and the tack layer 4b is exposed. Thereafter, the process proceeds to a plasma dicing process.

  The above embodiment is an example of the present invention, and the present invention is not limited to such a form, and can add, delete, or change a known process in each process as long as it does not contradict the gist of the present invention. .

  EXAMPLES Hereinafter, although this invention is demonstrated further in detail based on an Example, this invention is not limited to this.

Example 1
The resists and surface protection tapes of Samples 1 to 8 having the configurations shown in Table 1 below were prepared, and the following processes were performed using the respective resists and surface protection tapes.
First, a resist is applied to the pattern surface side of an 8-inch diameter silicon wafer, and a surface protection tape is pasted on the surface so that the diameter is substantially the same as that of the wafer, and a back grinder (DFD 8540 (manufactured by DISCO Corporation)) The wafer was ground until the wafer thickness reached 50 μm. Next, a UV curable dicing tape (UC-353EP-110 (manufactured by Furukawa Electric)) was bonded to the ground back side of the wafer and supported and fixed by a ring frame. Next, the base film was peeled off from the surface protection tape, and the tack layer and the resist were removed with a CO ₂ laser along the street portion of the silicon wafer from the exposed tack layer to open the street portion.

Thereafter, SF ₆ gas is used as a plasma generating gas, plasma is irradiated from the surface side of the exposed tack layer at an etching rate of 0.5 μm / min, plasma dicing is performed, the wafer is cut, and individual wafers are cut. Divided into chips. Next, O ₂ gas was used as a plasma generating gas, and ashing was performed at an etching rate of 1.0 μm / min to remove the tack layer and the resist remaining on the pattern surface. Thereafter, ultraviolet light was irradiated from the dicing tape side to reduce the adhesive strength of the dicing tape, and the chip was picked up in the pick-up process.

  Here, the separator in Table 1 is Toyobo E7006. Reactive P is an ultraviolet curable pressure-sensitive adhesive whose main component is an acrylic pressure-sensitive adhesive having a carbon-carbon double bond in the polymer molecule. The pressure-sensitive adhesive layer A comprises an acrylic pressure-sensitive adhesive and a radiation polymerizable compound. Is a layer of an ultraviolet curable pressure-sensitive adhesive mainly composed of The pressure-sensitive adhesive for the anchor layer is a pressure-sensitive adhesive mainly composed of an acrylic copolymer and a curing agent. The resist A is a photosensitive liquid solder resist.

  When the chip after pickup was checked, no chipping was observed in any of the samples 1 to 8 tested using any resist and surface protective tape. Moreover, it was able to pick up well.

Example 2
The process which changes a part of Example 1 using the resist and surface protection tape of the samples 1-8 which consist of the structure shown in the said Table 1 was performed.
That is, the resist was applied in advance to the tack layer side of the surface protective tape to prepare a resist-coated surface protective tape, and this was bonded to the pattern surface. The other processes were the same as in Example 1.
When the chip after pickup was checked, no chipping was observed in any of the samples 1 to 8 tested using any resist and surface protective tape. Moreover, it was able to pick up well.

Example 3
The process which changes a part of Example 2 was performed using the resist of sample 1-8 which consists of a structure shown in the said Table 1, and a surface protection tape (surface protection tape with a resist).
First, the resist-coated surface protective tape prepared in Example 2 was bonded to the pattern surface side of an 8-inch diameter silicon wafer so as to be approximately the same diameter as the wafer, and a back grinder (DFD 8540 (manufactured by DISCO Corporation) ) Until the wafer thickness is 50 μm. Next, a UV curable dicing tape (UC-353EP-110 (manufactured by Furukawa Electric)) was bonded to the ground back side of the wafer and supported and fixed by a ring frame. From the top of the resist-coated surface protective tape, along the street portion of the silicon wafer, the resist-coated surface protective tape was removed with a CO ₂ laser to open the street portion. Next, after irradiating the individual surface protection tape with resist separated with ultraviolet rays, the base film of the surface protection tape with resist was peeled off.
Subsequent plasma treatment was performed in the same manner as in Example 1.

  When the chip after pick-up was checked, no chipping was observed in any of the examples tested using the resists of Samples 1 to 8 and the surface protective tape (surface protective tape with resist). Moreover, it was able to pick up well.

Example 4
The process which changes a part of Example 3 was performed.
That is, in Example 3, the resist-coated surface protective tape with the resist was irradiated with ultraviolet rays, but this ultraviolet irradiation was not applied to the resist-coated surface protective tape with the resist after the street portion was opened. This was performed in the same manner as in Example 3 except that this was performed after the wafer grinding.
When the chip after pick-up was checked, no chipping was observed in any of the examples tested using the resists of Samples 1 to 8 and the surface protective tape (surface protective tape with resist). Moreover, it was able to pick up well.

Example 5
The process which changes a part of Example 4 was performed.
That is, in Example 4, when the surface protective tape with resist was bonded to the surface of the semiconductor wafer, it was performed in the same manner as in Example 4 except that the surface protective tape with resist was bonded while heating.
When the chip after pick-up was checked, no chipping was observed in any of the examples tested using the resists of Samples 1 to 8 and the surface protective tape (surface protective tape with resist). Moreover, it was able to pick up well.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Pattern surface 3 Resist 4 Surface protection tape 4a Base film 4b Tack layer 5 Wafer fixing tape 6 Surface protection tape with resist 7 Chip S Surface B Back M1 Wafer grinding device M2 Pin M3 Collet F Ring frame L CO ₂ Laser P1 SF ₆ gas plasma P2 O ₂ gas plasma

Claims (13)

A method for processing a semiconductor wafer, comprising:
(A) a step of providing a resist film on the pattern surface side of the semiconductor wafer by any of the following (a1) or (a2);
(A1) A resist is applied to the pattern surface of the semiconductor wafer and prebaked, and then a surface protection tape having a tack layer on the base film is bonded to the surface on which the resist is applied.
(A2) A resist-coated surface protective tape in which a tack layer and a resist layer are laminated in order on the base film is bonded to the pattern surface side of the semiconductor wafer.
(B) A process of grinding the back surface of the semiconductor wafer, bonding the wafer fixing tape to the ground back surface, and supporting and fixing with a ring frame in a state where any one of the above surface protection tapes is bonded,
(C) Opening the street from the pattern surface side of the semiconductor wafer by a process including cutting of the portion corresponding to the street of the semiconductor wafer with a CO ₂ laser and peeling of the base film from any one of the above surface protective tapes The process of
(D) a plasma dicing step in which the semiconductor wafer is divided at the streets by SF ₆ plasma and separated into semiconductor chips, and
(E) An ashing step of removing the tack layer and the resist film with O ₂ plasma. The step (a) is the step (a1), and the step (c) includes (i) a step of peeling only the base film bonded to the pattern surface of the semiconductor wafer, and (ii) _{2. The} step of opening a street of the semiconductor wafer by cutting the tack layer corresponding to the street of the semiconductor wafer and the resist film of the exposed tack layer with a CO ₂ laser. Semiconductor wafer processing method. The step (a) is the step (a2), and the step (c) is (iii) peeling the base film from the resist-coated surface protective tape bonded to the pattern surface of the semiconductor wafer. And (iv) a step of opening the street of the semiconductor wafer by cutting the tack layer corresponding to the street of the semiconductor wafer and the resist film with a CO ₂ laser in the exposed tack layer. A method for processing a semiconductor wafer according to claim 1. The step (a) is the step (a2), and the step (c) is a step (v) cutting a portion corresponding to the street of the semiconductor wafer in the resist-coated surface protective tape with a CO ₂ laser. The step of opening the street of the semiconductor wafer, and (vi) the step of irradiating the singulated resist-coated surface protective tape with ultraviolet rays and peeling off the base film. Semiconductor wafer processing method. The step (a) is the step (a2), and after the back surface of the semiconductor wafer is ground in the step (b), the resist-coated surface protective tape that has been bonded is irradiated with ultraviolet rays, and ( c) a step comprising: (v) cutting a portion corresponding to the street of the semiconductor wafer of the resist-coated surface protective tape with a CO ₂ laser to open the street of the semiconductor wafer; and (vii) dividing into pieces. The method for processing a semiconductor wafer according to claim 1, wherein the substrate film is peeled off from the resist-coated surface protective tape.   6. The method for processing a semiconductor wafer according to claim 5, wherein the step (a) is the step (a2), and the bonding of the resist-coated surface protective tape is performed while heating.   The method for processing a semiconductor wafer according to claim 1, wherein the wafer fixing tape in the step (b) is a dicing tape or a dicing die bonding tape.   The method for processing a semiconductor wafer according to claim 1, further comprising a step of picking up a chip from the wafer fixing tape after the step (f).   The semiconductor wafer processing method according to claim 8, further comprising a step of transferring the picked-up chip to a die bonding step.   The method for processing a semiconductor wafer according to claim 1 or 2, wherein the surface protective tape in (a1) is a tack film in which a base film portion and a tack layer are formed by coextrusion.   A semiconductor chip manufactured by the semiconductor wafer processing method according to claim 1.   A surface protection tape for semiconductor wafer processing, comprising a tack layer on a base film and a resist layer on the tack layer.   The surface protection tape for semiconductor wafer processing is a surface protection tape with a resist used in the semiconductor wafer processing method according to any one of claims 1, 3 to 10. Surface protection tape for semiconductor wafer processing.

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