JP2016162889A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a gate leakage current and reduce collapse, in a HEMT (a high electron mobility transistor) that has a MIS electrode using InAlN for an electron supply layer.SOLUTION: A semiconductor device comprises: a first semiconductor layer 21 formed of a nitride semiconductor, on a substrate 10; a second semiconductor layer 23 formed of a material containing InAlN, on the first semiconductor layer 21; an oxide film 50 formed by oxidizing a part of a surface of the second semiconductor layer 23; an insulating film 60 formed on the second semiconductor layer 23 and the oxide film 50; a gate electrode 31 formed on the insulating film 60, in a region where the oxide film 50 is formed; and a source electrode 32 and a drain electrode 33 formed on the first semiconductor layer 21 or the second semiconductor layer 23.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A nitride semiconductor such as GaN, AlN, InN, or a mixed crystal material thereof has a wide band gap, and is used as a high-power electronic device or a short-wavelength light-emitting device. For example, GaN, which is a nitride semiconductor, has a band gap of 3.4 eV, which is larger than the Si band gap of 1.1 eV and the GaAs band gap of 1.4 eV.

  As such a high-power electronic device, there is a field effect transistor (FET), in particular, a high electron mobility transistor (HEMT) (for example, Patent Document 1). HEMTs using nitride semiconductors are used in high power / high efficiency amplifiers, high power switching devices, and the like. Specifically, in a HEMT using AlGaN as an electron supply layer and GaN as an electron transit layer, piezoelectric polarization or the like occurs in AlGaN due to strain due to a difference in lattice constant between AlGaN and GaN, and a high concentration of 2DEG (Two-Dimensional Electron). Gas: two-dimensional electron gas) is generated. For this reason, the operation | movement in a high voltage is possible and it can use for the high voltage | pressure-resistant electric power device in a highly efficient switching element, an electric vehicle use, etc.

  By the way, in some ultrahigh frequency devices using nitride semiconductors, InAlN having high spontaneous polarization is used in place of AlGaN for the electron supply layer in order to realize high output of the device. InAlN is attracting attention as a material having both high output and high frequency properties because it can induce a high concentration of two-dimensional electron gas even if it is thin.

JP 2002-359256 A

  However, the HEMT using InAlN for the electron supply layer has a high electric field strength inside the electron supply layer due to the high spontaneous polarization in InAlN. there were.

  Therefore, in a HEMT having a Schottky gate electrode using InAlN in the electron supply layer, a semiconductor device having a low gate leakage current is required.

  According to one aspect of the present embodiment, a first semiconductor layer formed of a nitride semiconductor on a substrate and a second semiconductor formed of a material containing InAlN on the first semiconductor layer. An oxide film formed by oxidizing part of the surface of the second semiconductor layer, an insulating film formed on the second semiconductor layer and the oxide film, and the oxide film A gate electrode formed on the insulating film in a formed region; and a source electrode and a drain electrode formed on the first semiconductor layer or the second semiconductor layer. And

  According to the disclosed semiconductor device, a gate leakage current can be reduced in a HEMT having a Schottky gate electrode using InAlN as an electron supply layer.

Structure diagram of semiconductor device using InAlN for electron supply layer Correlation diagram between gate-drain voltage and gate leakage current of the semiconductor device shown in FIG. Structure diagram of a semiconductor device having a structure provided with a gate insulating film Structure diagram of the semiconductor device in the first embodiment Figure of XPS analysis result in oxide film Correlation diagram between oxidation method and Al / In ratio when forming oxide film Composition distribution diagram of oxide film of semiconductor device in first embodiment Correlation diagram between gate voltage and leakage current of semiconductor device in first embodiment Correlation diagram between gate voltage and leakage current of the semiconductor device shown in FIG. Correlation diagram between drain voltage and drain current of the semiconductor device in the first embodiment Correlation diagram between drain voltage and drain current of the semiconductor device shown in FIG. Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (4) of the manufacturing method of the semiconductor device in the first embodiment Process drawing of the manufacturing method of the semiconductor device in the first embodiment (5) Process drawing (6) of the manufacturing method of the semiconductor device in the first embodiment Correlation diagram between gate voltage and leakage current of semiconductor device in second embodiment Correlation diagram between drain voltage and drain current of semiconductor device in second embodiment Structure diagram of semiconductor device according to third embodiment Explanatory drawing of the semiconductor device in 3rd Embodiment Correlation diagram between gate voltage and leakage current of semiconductor device in third embodiment Explanatory diagram of characteristics of the semiconductor device in the first embodiment and the third embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (3) Process drawing (4) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (5) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (6) of the manufacturing method of the semiconductor device in 3rd Embodiment Explanatory drawing of the semiconductor device in 4th Embodiment Circuit diagram of PFC circuit in fourth embodiment Circuit diagram of power supply device according to fourth embodiment Structure diagram of high-power amplifier in fourth embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
First, a semiconductor device using InAlN for an electron supply layer will be described with reference to FIG. As shown in FIG. 1, the semiconductor device using InAlN for the electron supply layer has a buffer layer (not shown) on the substrate 910, an electron transit layer 921 formed of i-GaN, and an intermediate layer formed of AlN. 922, an electron supply layer 923 formed of InAlN is stacked. On the electron supply layer 923, a gate electrode 931, a source electrode 932, and a drain electrode 933 are formed. In a region where the gate electrode 931, the source electrode 932, and the drain electrode 933 are not formed on the electron supply layer 923, a protective film 940 is formed of SiN or the like. The substrate 910 is formed of a semi-insulating SiC substrate, and 2DEG 921a is generated in the vicinity of the interface between the electron transit layer 921 and the intermediate layer 922 in the electron transit layer 921.

In the semiconductor device having the structure shown in FIG. 1, when a potential of 0 V is applied to the gate electrode 931 and the potential at the drain electrode 933 is increased, the gate leakage current I _g leak is as shown by the dashed arrow in FIG. May flow. As shown in FIG. 2, the gate leakage current I _g leak increases exponentially as the gate-drain voltage V _gd increases. Specifically, when the gate-drain voltage, which is a gate reverse voltage applied between the gate electrode 931 and the drain electrode 933, exceeds about 20 V, the gate leakage current I _g leak increases rapidly and exponentially increases. To do. For this reason, it is difficult to increase the output of the semiconductor device because a gate-drain voltage exceeding about 20 V cannot be applied.

As a method for reducing gate leakage current in a semiconductor device using InAlN for the electron supply layer 923, there is a method of forming a MIS structure by forming a gate insulating film 960 as shown in FIG. Specifically, a gate insulating film 960 is formed using Al ₂ O ₃ or the like over the electron supply layer 923 and a gate electrode 931 is formed over the gate insulating film 960. However, it is difficult to form a good insulating film on InAlN, and when the gate insulating film 960 is formed on the electron supply layer 923, a new problem arises that current collapse occurs and on-resistance increases. End up. As described above, the cause of current collapse is that when Al ₂ O ₃ or the like serving as the gate insulating film 960 is formed on InAlN serving as the electron supply layer 923, the current collapse occurs between InAlN and Al ₂ O ₃ . It is assumed that the electron trap concentration increases at the interface.

(Semiconductor device)
Next, the semiconductor device in this embodiment will be described with reference to FIG. As shown in FIG. 4, the semiconductor device in the present embodiment includes a buffer layer (not shown), an electron transit layer 21 formed of i-GaN, an intermediate layer 22 formed of AlN, and InAlN on a substrate 10. The electron supply layer 23 formed by the above is laminated. A source electrode 32 and a drain electrode 33 are formed on the electron supply layer 23, and the electron supply layer 23 is formed on the surface of the electron supply layer 23 immediately below the region where the gate electrode 31 is formed. An oxide film 50 is formed by oxidizing the existing material. On the electron supply layer 23 and the oxide film 50, an insulating film 60 serving as a gate insulating film is formed of Al ₂ O ₃ or the like, and on the insulating film 60 in the region where the oxide film 50 is formed. A gate electrode 31 is formed. Note that the source electrode 32 and the drain electrode 33 may be formed on the electron transit layer 21 or may be formed on the intermediate layer 22.

  In the present embodiment, the substrate 10 is formed of a semi-insulating SiC substrate, and 2DEG 21 a is generated in the electron transit layer 21 in the vicinity of the interface between the electron transit layer 21 and the intermediate layer 22. In the present embodiment, the electron transit layer 21 may be referred to as a first semiconductor layer, the electron supply layer 23 may be referred to as a second semiconductor layer, and the intermediate layer 22 may be referred to as a third semiconductor layer.

  In the semiconductor device in the present embodiment, the oxide film 50 is formed by oxidizing the electron supply layer 23. As described above, by forming the oxide film 50 under the gate electrode 31, a good insulating film 60 can be formed on the oxide film 50. As a result, the insulation directly under the gate electrode 31 can be improved, the gate leakage current can be reduced, and the output of the semiconductor device can be increased. Further, when the insulating film 60 is an oxide, the oxide film 50 and the insulating film 60 are formed by forming the insulating film 60 on the oxide film 50 having good consistency with the material forming the insulating film 60. At the interface between them, electrons are not easily trapped or the concentration of electron traps can be reduced, and the occurrence of current collapse can be suppressed.

In the present embodiment, the oxide film 50 is formed by oxidizing part of the electron supply layer 23. However, since the electron supply layer 23 is formed of InAlN, the oxide film 50 oxidizes InAlN. In ₂ O ₃ and Al ₂ O ₃ formed by doing so. Here, In ₂ O ₃ has a narrow band gap, a low ability to prevent a gate leakage current, and is unstable, so that its characteristics are likely to vary. Therefore, it is not preferable as a material for forming the oxide film 50. Absent. On the other hand, Al ₂ O ₃ has a wide band gap and is stable, and is preferable as a material for forming the oxide film 50. Therefore, in order to obtain high insulation in the oxide film 50, it is preferable that more Al ₂ O ₃ is contained than In ₂ O ₃ . Thereby, gate leakage current can be reduced and generation | occurrence | production of a current collapse can be suppressed.

Although the case where the gate electrode 31 is a T-type gate electrode has been described in this embodiment, an overhanging gate electrode or a rectangular gate electrode may be used instead of the T-type gate electrode. The thickness of the oxide film 50 to be formed is preferably 1 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. In the present embodiment, the oxide film 50 is formed to have a thickness of 1.5 nm. Examples of the insulating film 60 to be formed include oxides, nitrides, oxynitrides, and the like. However, since the oxide film 50 contains a large amount of oxides of Al, Al ₂ O ₃ , AlN, AlON or the like is preferable, and Al ₂ O ₃ which is an oxide of Al is particularly preferable.

(InAlN oxidation)
By the way, as a method for oxidizing a nitride semiconductor such as InAlN, there are H ₂ O oxidation using water vapor, O plasma oxidation, thermal oxidation using oxygen, and the like. Thermal oxidation using oxygen is not preferable because the temperature at the time of oxidation is relatively high, about 600 ° C., and damages the manufactured semiconductor device. In H ₂ O oxidation and O plasma oxidation using water vapor, the temperature at the time of oxidation is relatively low, about 300 ° C., so that the semiconductor device can be manufactured without damaging the semiconductor device.

Next, results obtained by analyzing an oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor and an oxide obtained by oxidation by O plasma oxidation by XPS (X-ray Photoelectron Spectroscopy) will be described. FIG. 5A shows the result of XPS analysis of an oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor. FIG. 5B shows the oxide obtained by oxidizing InAlN by O plasma oxidation. It is the result of having analyzed by XPS about. The temperature in H ₂ O oxidation using water vapor and O plasma oxidation when oxidizing InAlN is 300 ° C.

As shown in FIG. 5A, in the oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor, more Al—O is observed than In—O. On the other hand, as shown in FIG. 5B, in the oxide obtained by oxidizing InAlN by O plasma oxidation, more In—O is observed than Al—O. Therefore, an oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor has more Al ₂ O ₃ than an oxide obtained by oxidizing InAlN by O plasma oxidation. Therefore, the oxide film 50 is formed by H ₂ O oxidation using water vapor in which Al—O is observed more than In—O than in O plasma oxidation in which In—O is observed more than Al—O. However, it is possible to increase the insulation.

FIG. 6 shows InAlN, an oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor, and an oxide obtained by oxidizing InAlN by O plasma oxidation before Al is oxidized. It shows the Al / In ratio which is the ratio. The composition of InAlN used is In ₁₇ Al ₈₃ N. As shown in FIG. 6, when the InAlN is oxidized by H ₂ O oxidation using water vapor and O plasma oxidation, both values of the Al / In ratio are increased. Furthermore, an oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor has a higher Al / In ratio than when InAlN is oxidized by O plasma oxidation. That is, In can be reduced by oxidizing InAlN. In particular, an oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor is more indium than an oxide obtained by oxidizing InAlN by O plasma oxidation. Is decreasing.

(H ₂ O oxidation using water vapor)
Next, it will be described that when InAlN is oxidized by H ₂ O oxidation using water vapor, the value of the Al / In ratio is higher than when InAlN is oxidized by O plasma oxidation.

Chemical formula 1 in the following is a chemical reaction formula when Al is oxidized by H ₂ O oxidation using water vapor, and chemical formula 2 and chemical formula 3 are chemical reaction formulas in the reaction process of the chemical reaction formula shown in chemical formula 1. . Chemical formula 4 is a chemical reaction formula when In is oxidized by H ₂ O oxidation using water vapor, and chemical formula 5 and chemical formula 6 are chemical reaction formulas in the reaction process of the chemical reaction formula shown in chemical formula 4. .

As shown in Chemical Formula 1, Al ₂ O ₃ is generated by oxidizing Al contained in InAlN by H ₂ O oxidation using water vapor. In this reaction, first, as shown in Chemical Formula ₂ , Al (OH) ₃ is generated by oxidizing Al contained in InAlN by H ₂ O oxidation using water vapor. As shown, Al ₂ O ₃ is produced from Al (OH) ₃ via a dehydration reaction.

Further, as shown in Chemical formula 4, In ₂ O ₃ is generated by oxidizing In contained in InAlN by H ₂ O oxidation using water vapor. In this reaction, as shown in Chemical Formula 5, first, In (OH) ₃ is generated by oxidizing In contained in InAlN by H ₂ O oxidation using water vapor. As shown, In ₂ O ₃ is produced from In (OH) ₃ via a dehydration reaction.

As described above, when InAlN is oxidized by H ₂ O oxidation using water vapor, a hydroxide is generated, and then an oxide is generated from the generated hydroxide via a dehydration reaction. Is done.

By the way, Al (OH) ₃ generated in Chemical Formula 2 is a solid, but In (OH) ₃ generated in Chemical Formula 5 is unstable in solid phase and easily vaporized. Thus, in the process of oxidation by _{H 2} O oxidation with steam InAlN, because some of the In is vaporized, In is decreased in the oxide oxidized by _{H 2} O oxidation with steam InAlN . Therefore, the value of Al / In ratio becomes high.

On the other hand, when InAlN is oxidized by O plasma oxidation, In (OH) ₃ is not generated, and In remains in the oxide film without being vaporized. For this reason, it is presumed that an oxide obtained by oxidizing InAlN by H ₂ O oxidation using water vapor has a higher Al / In ratio value than an oxide obtained by oxidizing InAlN by O plasma oxidation.

In this embodiment, when InAlN is oxidized by H ₂ O oxidation using water vapor, the substrate or the like is heated. At this time, in order to oxidize smoothly without damaging the nitride semiconductor layer, the temperature is preferably 150 ° C. or higher and 550 ° C. or lower, and more preferably 200 ° C. or higher and 400 ° C. or lower.

In the semiconductor device in the present embodiment, an oxide film 50 is formed by oxidizing a part of the surface of InAlN forming the electron supply layer 23, and an Al ₂ O film is formed on the formed oxide film 50. ₃ or the like. A method for oxidizing a part of the surface of InAlN forming the electron supply layer 23 may be H ₂ O oxidation using water vapor or O plasma oxidation. Therefore, H ₂ O oxidation using water vapor which can increase the Al composition ratio is more preferable.

As described above, the oxide film 50 is formed by oxidizing InAlN forming the electron supply layer 23. However, as the oxidation proceeds, In is released and the Al composition ratio is increased. When the oxide film 50 is formed, the oxidation proceeds gradually from the surface of InAlN. Therefore, as shown in FIG. 7, the surface of the oxide film 50 is larger than the portion deeper than the surface of the oxide film 50. And a large amount of Al ₂ O ₃ is formed.

Matching since the insulating film 60 is formed on the surface of the oxide film 50, when the insulating film 60 is _Al 2 _{O 3,} is the same, _Al 2 _{O 3,} based on are often formed on the surface of the oxide film 50 The interface trap is difficult to form at the interface between the oxide film 50 and the insulating film 60. For this reason, electrons are not easily trapped between the oxide film 50 and the insulating film 60, and generation of current collapse can be suppressed.

(Characteristics of semiconductor devices)
Next, characteristics of the semiconductor device in this embodiment will be described. 8 and 9 show the results of measuring the gate leakage current that flows when a voltage is applied between the gate electrode and the drain electrode. The horizontal axis represents the applied voltage, and the vertical axis represents the gate leakage current. FIG. 8 shows the characteristics of the semiconductor device in the present embodiment shown in FIG. 4, and FIG. 9 shows the characteristics of the semiconductor device having the structure shown in FIG. In the semiconductor device according to the present embodiment, as shown in FIG. 8, even if a voltage of up to 16 V is applied between the gate electrode and the drain electrode, no gate leakage current flows. On the other hand, in the semiconductor device having the structure shown in FIG. 1, when a voltage is applied between the gate electrode and the drain electrode as shown in FIG. 9, a gate leakage current flows. Thus, in the semiconductor device in this embodiment, generation of gate leakage current can be suppressed. The reason why the gate leakage current is lowered in the semiconductor device in the present embodiment is that the oxide film 50 and the insulating film 60 are formed immediately below the gate electrode 31 in the semiconductor device in the present embodiment.

Next, current collapse in the semiconductor device in this embodiment will be described in comparison with the semiconductor device having the structure shown in FIG. 10 and 11, a drain in the case of changing the gate voltage _{(V gs),} the case where the drain voltage _{(V ds)} is increased to 10V, a drain voltage _{(V ds)} in the case of increased to 20V The relationship with current (I _ds ) is shown. 10 shows the characteristics of the semiconductor device in the present embodiment shown in FIG. 4, and FIG. 11 shows the characteristics of the semiconductor device having the structure shown in FIG.

In the semiconductor device having the structure shown in FIG. 3, as shown in FIG. 11, when the drain voltage (V _ds ) is increased to 20 V, the drain current (I _ds ) decreases due to current collapse. . On the other hand, in the semiconductor device according to the present embodiment shown in FIG. 4, as shown in FIG. 10, even when the drain voltage (V _ds ) is increased to 20 V, the drain current (I _ds). ) Is not relatively decreased, and current collapse is suppressed.

  As described above, in the semiconductor device in this embodiment, the gate leakage current can be reduced. Moreover, since generation | occurrence | production of an electric current collapse can be suppressed, it can suppress that ON resistance becomes high.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 12A, a buffer layer (not shown), an electron transit layer 21, an intermediate layer 22, and an electron supply layer 23 are formed on the substrate 10 by epitaxial growth by MOVPE (Metal Organic Vapor Phase Epitaxy). Are sequentially stacked. In the present embodiment, the buffer layer, the electron transit layer 21, the intermediate layer 22, and the electron supply layer 23 (not shown) may be referred to as a nitride semiconductor layer. The electron transit layer 21 is made of i-GaN having a thickness of about 3 μm, the intermediate layer 22 is made of i-AlN having a thickness of about 1 nm, and the electron supply layer 23 has a thickness of about 10 nm. It is formed of i-In _0.17 Al _0.83 N. As a result, 2DEG 21 a is generated in the electron transit layer 21 in the vicinity of the interface between the electron transit layer 21 and the intermediate layer 22. The substrate 10 is a semi-insulating SiC substrate, and a buffer layer (not shown) is formed of GaN, AlGaN, or the like.

  Next, as illustrated in FIG. 12B, an element isolation region 61 is formed in the nitride semiconductor layer formed on the substrate 10. Specifically, by applying a photoresist on the electron supply layer 23 and performing exposure and development with an exposure apparatus, a resist pattern (not shown) having an opening in a region where the element isolation region 61 is formed is formed. Form. After that, ions such as Ar are ion-implanted into the nitride semiconductor layer in the opening of the resist pattern, thereby forming the element isolation region 61. When forming the element isolation region 61, ions such as Ar may be implanted up to a part of the substrate 10. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 12C, a resist pattern 71 having openings 71a and 71b in the region where the source electrode 32 and the drain electrode 33 are formed is formed on the electron supply layer 23, and then the openings are opened. Part of the surface of the electron supply layer 23 in the portions 71a and 71b is removed. Specifically, a photoresist is applied on the electron supply layer 23, and exposure and development are performed by an exposure apparatus. A resist pattern 71 having openings 71a and 71b is formed in a region where the source electrode 32 and the drain electrode 33 are formed. Thereafter, a region where the resist pattern 71 is not formed, that is, a part of the surface of the electron supply layer 23 exposed in the openings 71a and 71b of the resist pattern 71 is removed by RIE (Reactive Ion Etching) or the like. . In RIE performed at this time, a gas containing a chlorine component is used as an etching gas.

  Next, as shown in FIG. 13A, after removing the resist pattern 71 with an organic solvent or the like, a resist pattern 72 having openings 72a and 72b is formed in regions where the source electrode 32 and the drain electrode 33 are formed. To do. Specifically, after removing the resist pattern 71 with an organic solvent or the like, a photoresist is applied again on the electron supply layer 23, and exposure and development are performed by an exposure apparatus. Thus, a resist pattern 72 having openings 72a and 72b is formed in a region where the source electrode 32 and the drain electrode 33 are formed. As shown in the figure, the resist pattern 72 may be formed by laminating two resist layers.

  Next, as shown in FIG. 13B, a metal multilayer film 81 made of Ti / Al is formed on the surface on which the resist pattern 72 is formed by vacuum deposition. Specifically, a Ti film is formed by vacuum deposition on the surface on which the resist pattern 72 is formed, and an Al film is formed on the formed Ti film. In the present embodiment, the Ti film formed is about 20 nm thick, and the Al film is about 200 nm thick.

  Next, as shown in FIG. 13C, the metal multilayer film 81 formed on the resist pattern 72 is removed together with the resist pattern 72 by lift-off by being immersed in an organic solvent or the like. Thereby, the source electrode 32 and the drain electrode 33 are formed by the metal multilayer film 81 remaining in the region where the openings 72a and 72b of the resist pattern 72 were formed. Thereafter, an ohmic contact is established between the electron supply layer 23 and the source electrode 32 and the drain electrode 33 by performing a heat treatment at a temperature of 550 ° C.

  Next, as shown in FIG. 14A, a hard mask insulating film 73 for forming a hard mask, which will be described later, is formed on the electron supply layer 23, the source electrode 32, and the drain electrode 33. Specifically, an SiN film having a film thickness of about 20 nm is formed on the electron supply layer 23, the source electrode 32, and the drain electrode 33 by plasma CVD (Chemical Vapor Deposition), whereby an insulating film for a hard mask is formed. 73 is formed. When forming the hard mask insulating film 73 by plasma CVD, for example, silane, ammonia, or the like is used as a source gas. The deposited hard mask insulating film 73 has a refractive index of 2.0 at a wavelength of 633 nm, and is a stoichiometric film.

  Next, as shown in FIG. 14B, a resist pattern 74 having an opening 74 a is formed on the hard mask insulating film 73. Specifically, a photoresist is applied on the hard mask insulating film 73, and a resist pattern 74 having an opening 74a is formed by performing exposure and development with an exposure apparatus. The opening 74a in the resist pattern 74 has a width of about 0.5 μm and is the same size as the oxide film 50 formed by oxidizing the electron supply layer 23 described later.

  Next, as shown in FIG. 14C, the opening 73a is formed by removing the hard mask insulating film 73 in the opening 74a of the resist pattern 74 by RIE or the like. Thereby, a hard mask 73b having an opening 73a is formed by the remaining hard mask insulating film 73. Thereafter, the resist pattern 74 is removed with an organic solvent or the like.

Next, as shown in FIG. 15A, an oxide film 50 is formed by oxidizing the surface of the electron supply layer 23 exposed in the opening 73a of the hard mask 73b by H ₂ O oxidation using water vapor. To do. Specifically, using an ALD (Atomic Layer Deposition) apparatus, the substrate temperature is set to 300 ° C. and water vapor (H ₂ O) serving as an oxidation source is supplied, whereby electrons are supplied to the opening 73a of the hard mask 73b. The surface of the layer 23 is oxidized to form an oxide film 50. The oxide film 50 thus formed has a thickness of about 1.5 nm and a width D1 of about 0.5 μm.

  Next, as shown in FIG. 15B, a resist pattern 75 is formed on the oxide film 50. Specifically, a photoresist is applied on the electron supply layer 23, the oxide film 50, the source electrode 32, and the drain electrode 33, and exposure and development are performed by an exposure apparatus, whereby the resist is formed on the oxide film 50. A pattern 75 is formed.

  Next, as shown in FIG. 15C, the hard mask 73b in the region where the resist pattern 75 is not formed is removed using buffered hydrofluoric acid or the like. Thereafter, the resist pattern 75 is removed with an organic solvent or the like.

Next, as shown in FIG. 16A, an insulating film 60 to be a gate insulating film is formed on the electron supply layer 23, the oxide film 50, the source electrode 32, the drain electrode 33, and the like. Specifically, an Al ₂ O ₃ film having a thickness of about 2 nm is formed on the electron supply layer 23, the oxide film 50, the source electrode 32, the drain electrode 33, and the like by ALD (Atomic Layer. Deposition). Thereby, an insulating film 60 to be a gate insulating film is formed. When the insulating film 60 is formed by ALD, for example, TMA, H ₂ O, or the like is used as a source gas, and the film is formed at a substrate temperature of 300 ° C.

  Next, as shown in FIG. 16B, a resist pattern 77 for forming the gate electrode 31 is formed on the insulating film 60. The resist pattern 77 is formed by three stacked electron beam resist layers, and has an opening 77a in a region where the gate electrode 31 is formed. Specifically, a three-layer electron beam resist layer is formed on the insulating film 60 by repeatedly applying an electron beam resist and the like, and by repeating drawing and development with an electron beam drawing apparatus, the three-layer electron beam resist layer is formed. Openings 77a are formed in the electron beam resist layer. Thereby, a resist pattern 77 having an opening 77a is formed. The opening 77a in the resist pattern 77 is formed so as to have a width of 0.8 μm, 1.3 μm, and 0.2 μm in order from the top of the three-layer electron beam resist.

  Next, as shown in FIG. 16C, a metal multilayer film 82 made of Ni / Au is formed on the surface on which the resist pattern 77 is formed by vacuum deposition. Specifically, a Ni film is formed by vacuum deposition on the surface on which the resist pattern 77 is formed, and an Au film is formed on the formed Ni film. In the present embodiment, the Ni film formed is about 10 nm thick, and the Au film is about 300 nm thick.

  Next, as shown in FIG. 17, the metal multilayer film 82 formed on the resist pattern 77 is removed together with the resist pattern 77 by lift-off by being immersed in an organic solvent or the like. As a result, the gate electrode 31 is formed by the remaining metal multilayer film 82 in the region where the opening 77 a of the resist pattern 77 is formed on the insulating film 60.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

[Second Embodiment]
Next, a second embodiment will be described. The present embodiment is a semiconductor device having a structure similar to that of the semiconductor device in the first embodiment, and the steam oxidation time for forming the oxide film 50 is twice as long as that in the first embodiment. Formed. Thereby, an oxide film 50 having a thickness of about 3.0 nm is formed. Therefore, the film thickness of oxide film 50 formed in the semiconductor device in the present embodiment is double the film thickness of oxide film 50 formed in the semiconductor device in the first embodiment.

Further, in the steam oxidation, since the oxidation proceeds gradually from the surface of the electron supply layer 23, the In composition ratio on the surface of the oxide film 50 of the semiconductor device in the present embodiment is the same as that of the semiconductor in the first embodiment. This is lower than the In composition ratio on the surface of the oxide film 50 of the device. That is, the Al composition ratio on the surface of the oxide film 50 of the semiconductor device in the present embodiment is higher than the Al composition ratio on the surface of the oxide film 50 of the semiconductor device in the first embodiment. The ratio of Al ₂ O ₃ is higher than in the embodiment. In the present embodiment, by forming an Al ₂ O ₃ film as the insulating film 60 on the oxide film 50 having a high Al ₂ O ₃ ratio, the semiconductor device in the first embodiment can be obtained. Electrons trapped at the interface between the oxide film 50 and the insulating film 60 can be further reduced. Thereby, in the present embodiment, current collapse can be further suppressed.

(Characteristics of semiconductor devices)
Next, characteristics of the semiconductor device in this embodiment will be described. FIG. 18 shows the result of measuring the gate leakage current that flows when a voltage is applied between the gate electrode and the drain electrode in the semiconductor device of this embodiment. The horizontal axis represents the applied voltage, and the vertical axis represents the gate leakage current. In the semiconductor device according to the present embodiment, as shown in FIG. 18, even if a voltage of up to 16 V is applied between the gate electrode and the drain electrode, the gate leakage current does not flow. On the other hand, in the semiconductor device having the structure shown in FIG. 1, when a voltage is applied between the gate electrode and the drain electrode as shown in FIG. 9, a gate leakage current flows. Thus, in the semiconductor device in this embodiment, generation of gate leakage current can be suppressed. The reason why the gate leakage current is lowered in the semiconductor device in the present embodiment is that the oxide film 50 and the insulating film 60 are formed immediately below the gate electrode 31 in the semiconductor device in the present embodiment.

Next, current collapse in the semiconductor device in this embodiment will be described in comparison with the semiconductor device having the structure shown in FIG. FIG. 19 shows a case where the drain voltage (V _ds ) when the gate voltage (V _gs ) is changed to 10 V and the drain voltage (20 _g ) when the gate voltage (V _gs ) is increased to 20 V in the semiconductor device of this embodiment. The relationship between V _ds ) and drain current (I _ds ) is shown.

In the semiconductor device having the structure shown in FIG. 3, as shown in FIG. 11, when the drain voltage (V _ds ) is increased to 20 V, the drain current (I _ds ) decreases due to current collapse. . On the other hand, in the semiconductor device according to the present embodiment, as shown in FIG. 19, even when the drain voltage (V _ds ) is increased to 20 V, the drain current (I _ds ) decreases. The current collapse is suppressed. 19 is compared with the characteristics of the semiconductor device according to the first embodiment shown in FIG. 10 as compared with the characteristics of the semiconductor device according to the first embodiment. The current collapse is suppressed in the semiconductor device in this embodiment. This is because the time for oxidizing InAlN is longer in the present embodiment than in the first embodiment, so that the thickness of the oxide film 50 to be formed is thick, and the Al composition on the surface of the oxide film 50 is increased. This is probably due to the higher ratio.

  As described above, in the semiconductor device in this embodiment, the gate leakage current can be reduced. Further, since the occurrence of current collapse can be further suppressed, it is possible to suppress an increase in on-resistance.

  The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
(Semiconductor device)
Next, a semiconductor device according to the third embodiment will be described with reference to FIG. As shown in FIG. 20, the semiconductor device in the present embodiment includes a buffer layer (not shown), an electron transit layer 21 formed of i-GaN, an intermediate layer 22 formed of AlN, and InAlN on a substrate 10. The electron supply layer 23 formed by the above is laminated. A source electrode 32 and a drain electrode 33 are formed on the electron supply layer 23, and the electron supply layer 23 is formed on the surface of the electron supply layer 23 immediately below the region where the gate electrode 31 is formed. An oxide film 150 is formed by oxidizing the existing material. An insulating film 60 serving as a gate insulating film is formed of Al ₂ O ₃ or the like on the electron supply layer 23 and the oxide film 150, and on the insulating film 60 in a region where the oxide film 150 is formed. A gate electrode 31 is formed. In the present embodiment, the substrate 10 is formed of a semi-insulating SiC substrate, and 2DEG 21 a is generated in the electron transit layer 21 in the vicinity of the interface between the electron transit layer 21 and the intermediate layer 22.

  In the semiconductor device in the present embodiment, the oxide film 150 is formed by oxidizing the electron supply layer 23, but the gate electrode 31 and the drain electrode are not only directly under the gate electrode 31 but also directly under the gate electrode 31. It is also formed in the region up to the middle of 33. By forming such an oxide film 150, it becomes possible to further increase the output of the semiconductor device.

  By the way, since the oxide film 150 is formed by oxidizing the electron supply layer 23, the region where the oxide film 150 is formed is larger than the region where the oxide film 150 is not formed in the electron supply layer 23. The thickness is thin. As the thickness of the electron supply layer 23 decreases, the 2DEG 21a immediately below that region decreases. When the electron transit layer 21 is formed of i-GaN and the electron supply layer 23 is formed of InAlN as in the semiconductor device in the present embodiment, the electron transit layer in the vicinity of the interface between the electron transit layer 21 and the intermediate layer 22 is formed. 21 has a high concentration of 2DEG 21a. When the 2DEG 21a in the electron transit layer 21 has a high concentration, the drain current can be increased, but the gate breakdown voltage and the off breakdown voltage are reduced.

  Therefore, in the present embodiment, the oxide film 150 is formed in a region immediately below the gate electrode 31 and halfway between the gate electrode 31 and the drain electrode 33, whereby the electron supply layer 23 in the region where the oxide film 150 is formed. The thickness is reduced. As a result, the density of the generated 2DEG 21 a is lowered in the region from directly under the gate electrode 31 to the middle of the gate electrode 31 and the drain electrode 33. Thus, by reducing the density of the 2DEG 21a immediately below the region from the gate electrode 31 to the middle of the gate electrode 31 and the drain electrode 33, the gate breakdown voltage and the off breakdown voltage can be improved, and the semiconductor device can have high output. . Further, as shown in FIG. 21, the depletion layer region 151 can be expanded to a desired region, and high frequency characteristics can be improved.

  FIG. 21 shows the spread of the depletion layer region 151 generated when a voltage is applied to the gate electrode 31 in the semiconductor device according to the present embodiment by a two-dot chain line. As shown in FIG. 21, between the gate electrode 31 and the drain electrode 33, the depletion layer region 151 can be brought closer to the region where the 2DEG 21a is generated.

  In the present embodiment, as shown in FIG. 20, when the thickness T1 of the electron supply layer 23 in the region where the oxide film 150 is not formed is 10 nm and the thickness of the oxide film 150 is 3 nm, The thickness T2 of the electron supply layer 23 in the region where the oxide film 150 is formed is 7 nm.

(Characteristics of semiconductor devices)
Next, characteristics of the semiconductor device in this embodiment will be described. FIG. 22 shows the results of measuring the gate leakage current that flows when a voltage is applied between the gate electrode and the drain electrode in the semiconductor device of this embodiment. The horizontal axis represents the applied voltage, and the vertical axis represents the gate leakage current. In the semiconductor device according to the present embodiment, as shown in FIG. 22, even if a voltage of up to 16 V is applied between the gate electrode and the drain electrode, the gate leakage current does not flow. On the other hand, in the semiconductor device having the structure shown in FIG. 1, when a voltage is applied between the gate electrode and the drain electrode as shown in FIG. 9, a gate leakage current flows. Thus, in the semiconductor device in this embodiment, generation of gate leakage current can be suppressed. The reason why the gate leakage current is lowered in the semiconductor device in the present embodiment is that the oxide film 50 and the insulating film 60 are formed immediately below the gate electrode 31 in the semiconductor device in the present embodiment.

Next, characteristics of the semiconductor device according to the first embodiment and the semiconductor device according to the third embodiment will be described with reference to FIG. As shown in FIG. 23, the gate-source capacitance C _gs is the same between the semiconductor device in the first embodiment and the semiconductor device in the third embodiment, and is 500 (fF / mm). It is. The drain-source capacitance C _ds is the same for the semiconductor device in the first embodiment and the semiconductor device in the third embodiment, and is 150 (fF / mm).

On the other hand, the gate-drain capacitance C _gd is 130 (fF / mm) in the semiconductor device in the first embodiment, whereas 110 (fF / mm) in the semiconductor device in the third embodiment. mm). Therefore, the gate-drain capacitance C _gd is lower in the semiconductor device in the third embodiment than in the semiconductor device in the first embodiment.
The maximum transmission frequency f _max is 240 (GHz) in the semiconductor device in the first embodiment, whereas it is 250 (GHz) in the semiconductor device in the third embodiment. Therefore, the maximum transmission frequency f _max is higher in the semiconductor device in the third embodiment than in the semiconductor device in the first embodiment. Therefore, the frequency characteristics can be improved in the semiconductor device in the present embodiment.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 24A, a buffer layer (not shown), an electron transit layer 21, an intermediate layer 22, and an electron supply layer 23 are sequentially stacked on the substrate 10 by MOVPE epitaxial growth. . In the present embodiment, the buffer layer, the electron transit layer 21, the intermediate layer 22, and the electron supply layer 23 (not shown) may be referred to as a nitride semiconductor layer. The electron transit layer 21 is made of i-GaN having a thickness of about 3 μm, the intermediate layer 22 is made of i-AlN having a thickness of about 1 nm, and the electron supply layer 23 has a thickness of about 10 nm. It is formed of i-In _0.17 Al _0.83 N. As a result, 2DEG 21 a is generated in the electron transit layer 21 in the vicinity of the interface between the electron transit layer 21 and the intermediate layer 22. The substrate 10 is a semi-insulating SiC substrate, and a buffer layer (not shown) is formed of GaN, AlGaN, or the like.

  Next, as illustrated in FIG. 24B, the element isolation region 61 is formed in the nitride semiconductor layer formed on the substrate 10. Specifically, by applying a photoresist on the electron supply layer 23 and performing exposure and development with an exposure apparatus, a resist pattern (not shown) having an opening in a region where the element isolation region 61 is formed is formed. Form. After that, ions such as Ar are ion-implanted into the nitride semiconductor layer in the opening of the resist pattern, thereby forming the element isolation region 61. When forming the element isolation region 61, ions such as Ar may be implanted up to a part of the substrate 10. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as illustrated in FIG. 24C, a resist pattern 71 having openings 71 a and 71 b in the region where the source electrode 32 and the drain electrode 33 are formed is formed on the electron supply layer 23, Part of the surface of the electron supply layer 23 in the portions 71a and 71b is removed. Specifically, a photoresist is applied on the electron supply layer 23, and exposure and development are performed by an exposure apparatus. A resist pattern 71 having openings 71a and 71b is formed in a region where the source electrode 32 and the drain electrode 33 are formed. Thereafter, the region where the resist pattern 71 is not formed, that is, a part of the surface of the electron supply layer 23 exposed in the openings 71a and 71b of the resist pattern 71 is removed by RIE or the like. In RIE performed at this time, a gas containing a chlorine component is used as an etching gas.

  Next, as shown in FIG. 25A, after removing the resist pattern 71 with an organic solvent or the like, a resist pattern 72 having openings 72a and 72b is formed in regions where the source electrode 32 and the drain electrode 33 are formed. To do. Specifically, after removing the resist pattern 71 with an organic solvent or the like, a photoresist is applied again on the electron supply layer 23, and exposure and development are performed by an exposure apparatus. Thus, a resist pattern 72 having openings 72a and 72b is formed in a region where the source electrode 32 and the drain electrode 33 are formed. As shown in the figure, the resist pattern 72 may be formed by laminating two resist layers.

  Next, as shown in FIG. 25B, a metal multilayer film 81 made of Ti / Al is formed on the surface on which the resist pattern 72 is formed by vacuum deposition. Specifically, a Ti film is formed by vacuum deposition on the surface on which the resist pattern 72 is formed, and an Al film is formed on the formed Ti film. In the present embodiment, the Ti film formed is about 20 nm thick, and the Al film is about 200 nm thick.

  Next, as shown in FIG. 25C, the metal multilayer film 81 formed on the resist pattern 72 is removed together with the resist pattern 72 by lift-off by being immersed in an organic solvent or the like. Thereby, the source electrode 32 and the drain electrode 33 are formed by the metal multilayer film 81 remaining in the region where the openings 72a and 72b of the resist pattern 72 were formed. Thereafter, an ohmic contact is established between the electron supply layer 23 and the source electrode 32 and the drain electrode 33 by performing a heat treatment at a temperature of 550 ° C.

  Next, as shown in FIG. 26A, a hard mask insulating film 173 for forming a hard mask described later is formed on the electron supply layer 23, the source electrode 32, and the drain electrode 33. Specifically, a hard mask insulating film 173 is formed by forming a SiN film having a thickness of about 20 nm on the electron supply layer 23, the source electrode 32, and the drain electrode 33 by plasma CVD. When forming the hard mask insulating film 173 by plasma CVD, for example, silane, ammonia or the like is used as a source gas. The deposited hard mask insulating film 173 has a refractive index of 2.0 at a wavelength of 633 nm, and is a stoichiometric film.

  Next, as shown in FIG. 26B, a resist pattern 174 having an opening 174 a is formed on the hard mask insulating film 173. Specifically, a photoresist is applied on the hard mask insulating film 173, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern 174 having an opening 174a. The opening 174a in the resist pattern 174 has a width of about 1.0 μm and is the same size as the oxide film 150 formed by oxidizing the electron supply layer 23 described later. In the present embodiment, oxide film 150 is formed so as to partially extend from the region directly below gate electrode 31 to the drain electrode 33 side.

  Next, as shown in FIG. 26C, the opening 173a is formed by removing the hard mask insulating film 173 in the opening 174a of the resist pattern 174 by RIE or the like. Thus, a hard mask 173b having an opening 173a is formed by the remaining hard mask insulating film 173. Thereafter, the resist pattern 174 is removed with an organic solvent or the like.

Next, as shown in FIG. 27A, an oxide film 150 is formed by oxidizing the surface of the electron supply layer 23 exposed in the opening 173a of the hard mask 173b by H ₂ O oxidation using water vapor. To do. Specifically, the surface of the electron supply layer 23 in the opening 173a of the hard mask 173b is formed by supplying water vapor (H ₂ O) serving as an oxidation source by setting the substrate temperature to 300 ° C. using an ALD apparatus. Oxidation forms an oxide film 150. The oxide film 150 thus formed has a film thickness of about 1.5 nm, a width D3 of about 1.0 μm, and is formed so as to partially extend from directly below the gate electrode 31 to the drain electrode 33 side. The

  Next, as illustrated in FIG. 27B, a resist pattern 175 is formed on the oxide film 150. Specifically, a photoresist is applied on the electron supply layer 23, the oxide film 150, the source electrode 32, and the drain electrode 33, and exposure and development are performed by an exposure apparatus, whereby a resist is formed on the oxide film 150. A pattern 175 is formed.

  Next, as shown in FIG. 27C, the hard mask 173b in the region where the resist pattern 175 is not formed is removed using buffered hydrofluoric acid or the like. Thereafter, the resist pattern 175 is removed with an organic solvent or the like.

Next, as shown in FIG. 28A, an insulating film 60 to be a gate insulating film is formed on the electron supply layer 23, the oxide film 150, the source electrode 32, the drain electrode 33, and the like. Specifically, an Al ₂ O ₃ film having a thickness of about 2 nm is formed by ALD on the electron supply layer 23, the oxide film 150, the source electrode 32, the drain electrode 33, and the like, thereby forming a gate insulating film. An insulating film 60 is formed. When the insulating film 60 is formed by ALD, for example, TMA, H ₂ O, or the like is used as a source gas, and the film is formed at a substrate temperature of 300 ° C.

  Next, as shown in FIG. 28B, a resist pattern 77 for forming the gate electrode 31 is formed on the insulating film 60. The resist pattern 77 is formed by three stacked electron beam resist layers, and has an opening 77a in a region where the gate electrode 31 is formed. Specifically, a three-layer electron beam resist layer is formed on the insulating film 60 by repeatedly applying an electron beam resist and the like, and by repeating drawing and development with an electron beam drawing apparatus, the three-layer electron beam resist layer is formed. Openings 77a are formed in the electron beam resist layer. Thereby, a resist pattern 77 having an opening 77a is formed. The opening 77a in the resist pattern 77 is formed so as to have a width of 0.8 μm, 1.3 μm, and 0.2 μm in order from the top of the three-layer electron beam resist.

  Next, as shown in FIG. 28C, a metal multilayer film 82 made of Ni / Au is formed on the surface on which the resist pattern 77 is formed by vacuum deposition. Specifically, a Ni film is formed by vacuum deposition on the surface on which the resist pattern 77 is formed, and an Au film is formed on the formed Ni film. In the present embodiment, the Ni film formed is about 10 nm thick, and the Au film is about 300 nm thick.

  Next, as shown in FIG. 29, the metal multilayer film 82 formed on the resist pattern 77 is removed together with the resist pattern 77 by lift-off by being immersed in an organic solvent or the like. As a result, the gate electrode 31 is formed by the remaining metal multilayer film 82 in the region where the opening 77 a of the resist pattern 77 is formed on the insulating film 60.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

  The contents other than the above are the same as in the first embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high-frequency amplifier.

(Semiconductor device)
The semiconductor device according to the present embodiment is a discrete package of the semiconductor device according to the first to third embodiments. The semiconductor device thus discretely packaged will be described with reference to FIG. FIG. 30 schematically shows the inside of a discretely packaged semiconductor device. The arrangement of electrodes and the like are different from those shown in the first to third embodiments. Yes.

  First, the semiconductor device manufactured in the first to third embodiments is cut by dicing or the like to form a HEMT semiconductor chip 410 made of a GaN-based semiconductor material. The semiconductor chip 410 is fixed on the lead frame 420 with a die attach agent 430 such as solder. The semiconductor chip 410 corresponds to the semiconductor device in the first to third embodiments.

  Next, the gate electrode 411 is connected to the gate lead 421 by a bonding wire 431, the source electrode 412 is connected to the source lead 422 by a bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by a bonding wire 433. The bonding wires 431, 432, and 433 are formed of a metal material such as Al. In the present embodiment, the gate electrode 411 is a kind of gate electrode pad and is connected to the gate electrode 31 of the semiconductor device in the first to third embodiments. The source electrode 412 is a kind of source electrode pad, and is connected to the source electrode 32 of the semiconductor device according to the first to third embodiments. The drain electrode 413 is a kind of drain electrode pad, and is connected to the drain electrode 33 of the semiconductor device according to the first to third embodiments.

  Next, resin sealing with a mold resin 440 is performed by a transfer molding method. In this way, a HEMT discrete packaged semiconductor device using a GaN-based semiconductor material can be manufactured.

(PFC circuit, power supply and high frequency amplifier)
Next, a PFC circuit, a power supply device, and a high frequency amplifier in this embodiment will be described. The PFC circuit, the power supply device, and the high frequency amplifier in the present embodiment are a power supply device and a high frequency amplifier that use any one of the semiconductor devices in the first to third embodiments.

(PFC circuit)
Next, a PFC (Power Factor Correction) circuit according to the present embodiment will be described. The PFC circuit in the present embodiment has the semiconductor device in the first to third embodiments.

  Based on FIG. 31, the PFC circuit in the present embodiment will be described. The PFC circuit 450 in this embodiment includes a switch element (transistor) 451, a diode 452, a choke coil 453, capacitors 454 and 455, a diode bridge 456, and an AC power supply (not shown). As the switch element 451, the HEMT which is the semiconductor device in the first to third embodiments is used.

  In the PFC circuit 450, the drain electrode of the switch element 451, the anode terminal of the diode 452, and one terminal of the choke coil 453 are connected. The source electrode of the switch element 451 is connected to one terminal of the capacitor 454 and one terminal of the capacitor 455, and the other terminal of the capacitor 454 is connected to the other terminal of the choke coil 453. The other terminal of the capacitor 455 and the cathode terminal of the diode 452 are connected, and an AC power supply (not shown) is connected between both terminals of the capacitor 454 via a diode bridge 456. In such a PFC circuit 450, direct current (DC) is output from between both terminals of the capacitor 455.

(Power supply)
Next, the power supply device according to the present embodiment will be described. The power supply device in the present embodiment is a power supply device having a HEMT that is a semiconductor device in the first to third embodiments.

  The power supply device in the present embodiment will be described based on FIG. The power supply device in the present embodiment has a structure including the PFC circuit 450 in the present embodiment described above.

  Power supply device 470 in the present embodiment has a high-voltage primary circuit 461 and a low-voltage secondary circuit 462, and a transformer 463 disposed between primary circuit 461 and secondary circuit 462. ing.

  The primary circuit 461 includes the PFC circuit 450 in the present embodiment described above and an inverter circuit connected between both terminals of the capacitor 455 of the PFC circuit 450, for example, a full bridge inverter circuit 460. The full bridge inverter circuit 460 includes a plurality (here, four) of switch elements 464a, 464b, 464c, and 464d. The secondary side circuit 462 includes a plurality (three in this case) of switch elements 465a, 465b, and 465c. An AC power supply 457 is connected to the diode bridge 456.

  In the present embodiment, the HEMT that is the semiconductor device in the first to third embodiments is used in the switch element 451 of the PFC circuit 450 in the primary circuit 461. Furthermore, the HEMT that is the semiconductor device in the first to third embodiments is used in the switch elements 464a, 464b, 464c, and 464d in the full bridge inverter circuit 460. On the other hand, as the switch elements 465a, 465b, and 465c of the secondary side circuit 462, a normal MIS structure FET using silicon or the like is used.

(High frequency amplifier)
Next, the high frequency amplifier in the present embodiment will be described. The high-frequency amplifier in the present embodiment has a structure in which the HEMT that is the semiconductor device in the first to third embodiments is used.

  Based on FIG. 33, the high-frequency amplifier in the present embodiment will be described. The high frequency amplifier in this embodiment includes a digital predistortion circuit 471, mixers 472a and 472b, a power amplifier 473, and a directional coupler 474.

  The digital predistortion circuit 471 compensates for nonlinear distortion of the input signal. The mixer 472a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal, and includes the HEMT that is the semiconductor device according to the first to third embodiments. The directional coupler 474 performs monitoring of input signals and output signals. In FIG. 33, for example, by switching the switch, the signal on the output side can be mixed with the AC signal by the mixer 472b and sent to the digital predistortion circuit 471.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a material containing InAlN on the first semiconductor layer;
An oxide film formed by oxidizing a part of the surface of the second semiconductor layer;
An insulating film formed on the second semiconductor layer and the oxide film;
A gate electrode formed on the insulating film in a region where the oxide film is formed;
A source electrode and a drain electrode formed on the first semiconductor layer or the second semiconductor layer;
A semiconductor device comprising:
(Appendix 2)
The semiconductor device according to appendix 1, wherein the oxide film is formed by oxidizing a part of the surface of the second semiconductor layer with water vapor.
(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the oxide film is formed immediately below the gate electrode and in a partial region between the gate electrode and the drain electrode.
(Appendix 4)
4. The semiconductor device according to any one of appendices 1 to 3, wherein the oxide film contains more Al-O than In-O in the analysis by XPS.
(Appendix 5)
The supplementary note 1 to 4, wherein a third semiconductor layer formed of a nitride semiconductor is provided between the first semiconductor layer and the second semiconductor layer. Semiconductor device.
(Appendix 6)
The semiconductor device according to any one of appendices 1 to 5, wherein the third semiconductor layer is formed of a material containing AlN.
(Appendix 7)
The semiconductor device according to any one of appendices 1 to 6, wherein the first semiconductor layer is made of a material containing GaN.
(Appendix 8)
8. The semiconductor device according to any one of appendices 1 to 7, wherein the oxide film has a thickness of 1 nm or more and 5 nm or less.
(Appendix 9)
9. The semiconductor device according to any one of appendices 1 to 8, wherein the insulating film is any one of an oxide, a nitride, and an oxynitride containing Al.
(Appendix 10)
Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer on the first semiconductor layer from a material containing InAlN;
Forming a source electrode and a drain electrode on the first semiconductor layer or the second semiconductor layer;
Oxidizing a part of the surface of the second semiconductor layer with water vapor to form an oxide film;
Forming an insulating film on the second semiconductor layer and the oxide film;
Forming a gate electrode on the insulating film in a region where the oxide film is formed;
A method for manufacturing a semiconductor device, comprising:
(Appendix 11)
The method of manufacturing a semiconductor device according to appendix 10, wherein the step of forming the oxide film is performed at a temperature of the substrate of 150 ° C. or higher and 550 ° C. or lower.
(Appendix 12)
A step of forming a third semiconductor layer on the first semiconductor layer between the step of forming the first semiconductor layer and the step of forming the second semiconductor layer;
12. The method for manufacturing a semiconductor device according to appendix 10 or 11, wherein, in the step of forming the second semiconductor layer, the second semiconductor layer is formed on the third semiconductor layer.
(Appendix 13)
The step of forming the oxide film includes
Forming a hard mask having an opening in a region where an oxide film is formed on the second semiconductor layer;
After the step of forming the hard mask, a step of oxidizing part of the surface of the second semiconductor layer exposed at the opening of the hard mask with water vapor to form an oxide film;
Have
13. The method of manufacturing a semiconductor device according to any one of appendices 10 to 12, wherein the hard mask is formed of a material containing SiN.
(Appendix 14)
The step of forming the hard mask is performed after the step of forming the source electrode and the drain electrode,
14. The method of manufacturing a semiconductor device according to appendix 13, wherein the hard mask is also formed on the source electrode and the drain electrode.
(Appendix 15)
15. The method of manufacturing a semiconductor device according to appendix 13 or 14, further comprising a step of removing the hard mask by etching after the step of forming the oxide film.
(Appendix 16)
The step of forming the hard mask includes
Forming the hard mask insulating film;
Forming a resist pattern having an opening in a region to be an opening of the hard mask on the hard mask insulating film;
Removing the hard mask insulating film exposed in the opening of the resist pattern by etching;
Removing the resist pattern;
The method for manufacturing a semiconductor device according to any one of appendices 13 to 15, wherein the method includes:
(Appendix 17)
The method for manufacturing a semiconductor device according to any one of appendices 10 to 16, wherein the oxidation with water vapor is H ₂ O oxidation with water vapor.
(Appendix 18)
18. The method of manufacturing a semiconductor device according to any one of appendices 10 to 17, wherein the insulating film is any one of an oxide, a nitride, and an oxynitride containing Al.
(Appendix 19)
A power supply device comprising the semiconductor device according to any one of appendices 1 to 9.
(Appendix 20)
An amplifier comprising the semiconductor device according to any one of appendices 1 to 9.

10 Substrate 21 Electron travel layer (first semiconductor layer)
21a 2DEG
22 Intermediate layer (third semiconductor layer)
23 Electron supply layer (second semiconductor layer)
31 Gate electrode 32 Source electrode 33 Drain electrode 40 Protective film 50 Oxide film

Claims (10)

A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a material containing InAlN on the first semiconductor layer;
An oxide film formed by oxidizing a part of the surface of the second semiconductor layer;
An insulating film formed on the second semiconductor layer and the oxide film;
A gate electrode formed on the insulating film in a region where the oxide film is formed;
A source electrode and a drain electrode formed on the first semiconductor layer or the second semiconductor layer;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the oxide film is formed by oxidizing a part of the surface of the second semiconductor layer with water vapor.   3. The semiconductor device according to claim 1, wherein the oxide film is formed immediately below the gate electrode and in a partial region between the gate electrode and the drain electrode.   4. The semiconductor device according to claim 1, wherein the oxide film contains more Al-O than In-O in the analysis by XPS.   5. The semiconductor device according to claim 1, wherein a third semiconductor layer formed of a nitride semiconductor is provided between the first semiconductor layer and the second semiconductor layer. The semiconductor device described.   The semiconductor device according to claim 1, wherein the insulating film is any one of an oxide, a nitride, and an oxynitride containing Al. Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer on the first semiconductor layer from a material containing InAlN;
Forming a source electrode and a drain electrode on the first semiconductor layer or the second semiconductor layer;
Oxidizing a part of the surface of the second semiconductor layer with water vapor to form an oxide film;
Forming an insulating film on the second semiconductor layer and the oxide film;
Forming a gate electrode on the insulating film in a region where the oxide film is formed;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the oxide film is performed at a temperature of the substrate of 150 ° C. or higher and 550 ° C. or lower. A step of forming a third semiconductor layer on the first semiconductor layer between the step of forming the first semiconductor layer and the step of forming the second semiconductor layer;
9. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed on the third semiconductor layer. .   The method for manufacturing a semiconductor device according to claim 7, wherein the insulating film is any one of an oxide, a nitride, and an oxynitride containing Al.