JP2016157470A - Information recording system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent further deterioration in reliability of a nonvolatile storage device by constructing a system so as not to perform a writing operation to the nonvolatile storage device when the service life of the nonvolatile storage device gets closer to termination, and prevent data corruption of the nonvolatile storage device.SOLUTION: An information recording system comprises: a semiconductor storage device 2 which includes a nonvolatile semiconductor memory, a volatile semiconductor memory, a controller circuit, a temperature sensor and an interface circuit; and a host device 1 which transmits writing and reading commands. The nonvolatile semiconductor memory and the volatile semiconductor memory are configured to be able to record the first information designating the physical address corresponding to the logical address. The nonvolatile semiconductor memory is configured to store the second information, third information, fourth information, fifth information, sixth information and seventh information. The host device is configured to be able to display information based on the second or third information, information based on the fourth or fifth information and information based on the seventh information on a display device.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to an information recording system.

As an external storage device used in a computer system, an SSD (Solid State Drive) equipped with a nonvolatile semiconductor memory such as a NAND flash memory has attracted attention. The flash memory has advantages such as high speed and light weight compared with the magnetic disk device.
The SSD includes a plurality of flash memory chips, a controller that performs read / write control of each flash memory chip in response to a request from the host device, and a buffer that performs data transfer between each flash memory chip and the host device. A memory, a power supply circuit, a connection interface to the host device, and the like are provided.

JP 2009-217603 A JP 2008-090539 A JP 2002-351621 A JP 2006-18848 A Japanese Patent Application Laid-Open No. 07-78102 JP 2004-151785 A JP 2005-190075 A JP 2008-90539 A JP 2001-75813 A Patent No. 4489127 Japanese Patent No. 4635092

ATA / ATAPI Command Set-2 (ACS-2) d2015r6 Feb.22.2011http: //www.t13.org/Documents/UploadedDocuments/docs2011/d2015r6-ATAATAPI_Command_Set_-_2_ACS-2.pdf ・ Pages 73-74, Pages 290-306: SELF-MONITORING, ANALYSIS, AND REPORTING TECHNOLOGY (SMART) • Pages 98-99, Page 50: Data Set Management Command (trim command) • Pages 342-365: SCT Command Transport CrystalDiskInfo manual (Non-volatile storage device health monitoring software based on SMART information) http://crystalmark.info/software/CrystalDiskInfo/manual-en/http://crystalmark.info/software/CrystalDiskInfo/manual-en/ Smartmontools (Non-volatile storage device health monitoring software based on SMART information) http://sourceforge.net/apps/trac/smartmontools/wiki Samsung SSD Magician USER GUIDEhttp: //www.samsungssd.com/faq Intel Solid State Drive Toolbox http://downloadcenter.intel.com/Detail_Desc.aspx?lang=enu&DwnldID=18455http://downloadcenter.intel.com/Detail_Desc.aspx?lang=eng & DwnldId = 18455 S.M.A.R.T.attributes meaninghttp: //www.ariolic.com/activesmart/smart-attributes/ S.M.A.R.T.attributes meaninghttp: //www.siguardian.com/products/siguardian/on_line_help/s_m_a_r_t_attribute_meaning.html Self-Monitoring, Analysis and Reporting Technology :: Attributeshttp: //smartlinux.sourceforge.net/smart/attributes.php Serial ATA International Organization: Serial ATA Revision 3.1RC Clean DRAFT 2010.09.29 pp. 554-558 13.9 Phy Event Counters (Optional)

One embodiment of the present invention constructs a system so as not to perform a write operation to a nonvolatile storage device when the nonvolatile storage device approaches the end of its life, and prevents further deterioration of the reliability of the nonvolatile storage device, An object of the present invention is to provide an information recording system that prevents data destruction of a nonvolatile storage device.

In order to achieve the above object, an information recording system according to an embodiment includes a semiconductor memory device including a nonvolatile semiconductor memory, a volatile semiconductor memory, a controller circuit, a temperature sensor, and an interface circuit, and writing to the semiconductor memory device And a host device that transmits a read command. The nonvolatile semiconductor memory and the volatile semiconductor memory are
The first information designating the physical address of the nonvolatile semiconductor memory corresponding to the logical address information received from the host device via the interface circuit can be recorded. When the controller circuit receives a write command from the host device via the interface circuit, the controller circuit generates a correction code using the data received from the host device, and stores the data and the data in the nonvolatile semiconductor memory. When a correction code is recorded and a read command is received from the host device via the interface circuit, based on the data read from the nonvolatile semiconductor memory using the first information and the corresponding correction code Thus, the read data can be corrected. The nonvolatile semiconductor memory is configured to store second information, third information, fourth information, fifth information, sixth information, and seventh information. The second information is information based on the total amount of write data received according to the write command received from the host device. The third information is information based on the total amount of data read from the nonvolatile semiconductor memory in response to a read command received from the host device. The fourth information is information relating to the number of data that could not be corrected by using the correction code corresponding to the data read from the nonvolatile semiconductor memory by the controller. The fifth information is information according to the number of memory cells determined to be unable to write data in the nonvolatile semiconductor memory, and the first information
It is information indicated in units of. The sixth information is information according to the number of the memory cells determined to be able to write data in the nonvolatile semiconductor memory. The seventh information is information based on the temperature measured using the temperature sensor. The host device includes first status information of the nonvolatile semiconductor memory based on the second information or third information;
Display connected to the host device, the second status information of the nonvolatile semiconductor memory based on the fourth information or the fifth information, and the third status information of the nonvolatile semiconductor memory based on the seventh information It can be displayed on the device. The semiconductor storage device is configured to be able to change the sixth information by erasing data recorded at a corresponding physical address in the first unit based on a command and logical address information received from the host device. Is done.

FIG. 1 is a block diagram illustrating a functional configuration example of the computer system according to the first embodiment. FIG. 2 is a block diagram illustrating a functional configuration example of the computer system when the control tool is stored in the SSD. FIG. 3 is a block diagram illustrating a functional configuration example of the computer system when the control tool is stored in another external storage device. FIG. 4 is a block diagram illustrating a functional configuration example of the computer system when the control tool is installed from the WEB. FIG. 5 is a block diagram illustrating a functional configuration example of the computer system when the control tool is installed from the optical drive. FIG. 6 is a block diagram illustrating a functional configuration example of the computer system when the control tool is installed from the USB memory. FIG. 7 is a block diagram illustrating a functional configuration example of the computer system when the normal OS and the emergency OS are stored in the SSD. FIG. 8 is a block diagram illustrating a functional configuration example of a computer system when the normal-time OS and the emergency OS are stored in a nonvolatile storage device other than the SSD whose reliability has deteriorated. FIG. 9 is a block diagram illustrating a functional configuration example of a computer system when an emergency OS is installed from a storage medium on a WEB. FIG. 10 is a block diagram illustrating a functional configuration example of a computer system when an emergency OS is installed from an optical drive. FIG. 11 is a block diagram illustrating a functional configuration example of a computer system when an emergency OS is installed from a USB memory. FIG. 12 is a block diagram illustrating a hierarchical functional configuration example of the host. FIG. 13 is a diagram showing an external configuration of a computer system. FIG. 14 is a diagram showing another external configuration of the computer system. FIG. 15 is a block diagram illustrating an internal configuration example of the NAND memory chip. FIG. 16 is a circuit diagram showing a configuration example of one plane included in the NAND memory chip. FIG. 17 is a diagram showing a threshold distribution in the quaternary data storage system. FIG. 18 is a functional block diagram illustrating an internal configuration example of an SSD. FIG. 19 is a diagram showing SSD management information. FIG. 20 is a diagram showing the relationship between LBA and SSD management units. FIG. 21 is a flowchart showing a procedure for specifying a physical address from an LBA. FIG. 22 is a flowchart illustrating an example of an SSD read operation. FIG. 23 is a flowchart illustrating an example of an SSD read operation. FIG. 24 is a flowchart illustrating an example of an SSD write operation. FIG. 25 is a flowchart illustrating an example of an SSD write operation. FIG. 26 is a flowchart showing an operation example of organizing the SSD NAND memory. FIG. 27 is a flowchart illustrating an exemplary operation of the SSD when a deletion notification is received. FIG. 28 is a flowchart illustrating an operation example when an SSD error occurs. FIG. 29 is a flowchart showing the operation procedure of the control tool. FIG. 30 is a diagram illustrating an example of a management table of statistical information X01 to X19, X23, and X24. FIG. 31 is a graph showing a relationship between a raw value of statistical information and an SSD defect rate. FIG. 32 is a flowchart showing another operation procedure of the control tool. FIG. 33 is a flowchart showing another operation procedure of the control tool. FIG. 34 is a flowchart showing the process at the end of the life of the control tool. FIG. 35 is a flowchart showing another process at the end of the life of the control tool. FIG. 36 is a flowchart showing another process at the end of the life of the control tool. FIG. 37 is a flowchart showing an operation procedure when the computer system is activated. FIG. 38 is a diagram showing the configuration of the host when the emergency OS is equipped with a backup function. FIG. 39 is a flowchart showing an operation procedure including a backup operation when the computer system is activated. FIG. 40 shows the storage contents of the NAND memory and the storage contents of the file management table. FIG. 41 is a diagram illustrating a functional configuration example of a computer system when a USB storage is used as a backup storage device. FIG. 42 is a diagram illustrating a functional configuration example of a computer system when an optical storage medium is used as a backup storage device. FIG. 43 is a diagram illustrating a functional configuration example of a computer system when a storage server is used as a backup storage device. FIG. 44 is a diagram showing the concept of data movement when creating an emergency startup disk. FIG. 45 is a flowchart showing an operation procedure for creating an emergency start disk. FIG. 46 is a diagram showing a concept of data movement when an emergency start disk including an emergency tool is created. FIG. 47 is a flowchart showing an operation procedure when an emergency start disk including an emergency tool is created. FIG. 48 is a diagram showing an example of a screen for guiding the backup process to the user. FIG. 49 is a flowchart showing another operation procedure of the control tool. FIG. 50 is a flowchart showing another operation procedure when starting up the computer system. FIG. 51 is a diagram illustrating an example of time-series data of statistical information. FIG. 52 is a diagram showing the temporal change of statistical information. FIG. 53 is a diagram conceptually showing a process for obtaining a predicted life based on a change in statistical information over time. FIG. 54 is a diagram showing an example of a guidance screen to the user when the life of the SSD is reached. FIG. 55 is a block diagram illustrating a functional configuration example of the computer system when performing boot loader restoration processing. FIG. 56 is a flowchart showing the operation procedure of the boot loader restoration process at the end of life process. FIG. 57 is a diagram showing a rewrite difference log of the boot loader. FIG. 58 is a flowchart showing a backup operation procedure by the emergency OS. FIG. 59 is a block diagram illustrating a functional configuration example of the computer system when performing boot loader restoration processing. FIG. 60 is a flowchart showing an operation procedure of boot loader restoration processing by the emergency OS. FIG. 61 is a flowchart showing the overall operation procedure of the eighth embodiment.

Non-volatile semiconductor memory, such as NAND flash memory, erases data that is erased once in block units and then written, and data that is written / read out in page units. Some units have fixed / write / read units. On the other hand, a unit in which a host device such as a personal computer writes / reads data to / from a secondary storage device such as a hard disk is called a sector. The sector is determined independently of the unit of erasing / writing / reading of the semiconductor memory device. For example, the erase / write / read unit of the nonvolatile semiconductor memory may be larger than the write / read unit of the host device.

In addition, when configuring a secondary storage device of a personal computer using flash memory, blocks (bad blocks, bad blocks) that cannot be used as storage areas due to many errors, or areas that cannot be read (defective areas) Etc. may occur. If the number of defective blocks or defective areas exceeds the upper limit, new defective blocks or defective areas cannot be registered, so data stored in the buffer memory (cache memory) and write requests It is not possible to guarantee that both of the existing data are written to the flash memory. For this reason, when the number of defective blocks or the number of defective areas exceeds a predetermined value,
There was a problem that data could not be written suddenly even though the flash memory had free space.

As a solution to this, the number of bad clusters and the number of bad blocks generated in the NAND flash memory is managed, and data write from the host device to the NAND flash memory is performed according to the number of bad clusters and bad blocks. There is a method of switching the operation mode. A cluster is a management unit as a logical address in SSD. The cluster size is a natural number multiple of 2 or more of the sector size, and the cluster address is L
It consists of a high-order bit string from a predetermined bit of BA.

  In this method, the operation mode of the SSD is divided into the following three modes, for example.

WB mode (Write Back Mode): A normal operation mode in which data is once written in the cache memory and then evicted to the NAND flash memory based on a predetermined condition.

WT mode: (Write Through Mode): An operation mode in which data written to the cache memory with a single write request is written to the NAND flash memory each time. By writing to the NAND flash memory each time, data written from the host is guaranteed as much as possible. The SSD transitions to the WT mode when the number of remaining entries in the bad cluster table or the bad block table becomes a predetermined number or less.

RO mode (Read Only Mode): Mode in which all processes involving writing to the NAND flash memory are prohibited. By returning an error in response to all write requests from the host and not performing writing, it is possible to guarantee as much as possible the data already written from the host when the SSD is nearing the end of its life. The SSD transitions to the RO mode when the number of remaining entries in the bad cluster table or the bad block table falls below a predetermined number, or when there are insufficient free blocks.

In the WB mode and the WT mode, the SSD receives and processes both a read request and a write request from the host. On the other hand, in the RO mode, the SSD receives and processes a read request from the host, but returns an error without processing the write request from the host.

When an SSD is connected to a host equipped with an operating system (OS) such as Windows (registered trademark), the host sends a write request to the SSD, and when the write request is processed normally, the host The SSD is recognized as an external storage device that can be used.

On the other hand, when the SSD transitioned to the RO mode is connected to a host equipped with Windows (registered trademark) and the host sends a write request to the SSD, the SSD returns an error to the host. It may not be recognized as an external storage device that can be used. Therefore, even if an RO mode SSD capable of reading is connected to the host, there is a possibility that data recorded in the past cannot be read from the SSD.

In this way, when the SSD reaches the end of its life, or when the SSD is nearing the end of its life,
Writing to the SSD should be prohibited. However, in a normal operating system (OS) installed in a computer system, writing to the SSD occurs at the time of booting, and writing to the SSD unintended by the user occurs in the background. For this reason, when the SSD reaches the end of its life, or when the SSD is nearing the end of its life, the reliability of the SSD further deteriorates under the situation where a normal OS is installed in the computer system. May be destroyed.

Therefore, in this embodiment, when it is determined that the SSD has reached the end of its life, when the boot loader is rewritten and the system is restarted, for example, an emergency OS is started as emergency software that does not perform a write operation on the SSD 2. By doing so, the reliability of the SSD is prevented from being deteriorated, and the data already written is prevented from being destroyed. As an emergency OS,
A device that performs only a read operation on the SSD at the time of booting and does not write to the SSD in the background not intended by the user is employed.

Exemplary embodiments of an information processing apparatus will be explained below in detail with reference to the accompanying drawings. In addition,
The present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 shows the configuration of a first embodiment of a computer system. The computer system 1 includes an SSD 2 as a nonvolatile storage device, a host device 3, an SSD 2, and a host device 3.
The memory interface 19 is connected to In the present embodiment, an SSD (Solid State Drive) is used as a nonvolatile storage device. For example, a hard disk drive, a hybrid disk drive, an SD card, a USB memory, a NAND flash memory directly mounted on a motherboard, and the like. The non-volatile storage device may be used. In this embodiment, the interface 19 is an ATA (Advanced Technology At).
tachment) interface, but USB (Universal Serial Bus) or SAS (Seri)
al Attached SCSI), Thunderbolt (registered trademark), PCI Express, and other interfaces may be used. The CPU (control circuit) 4 is a central processing unit in the host device 3,
Various calculations and controls in the host device 3 are performed by the CPU 4. The CPU 4 controls the optical drive 10 such as the SSD 2 or DVD-ROM via the south bridge 7. The CPU 4 controls the main memory 6 via the north bridge 5. As the main memory 6, for example, a DRAM may be adopted.

The user controls the host device 3 through an input device such as a keyboard 14 and a mouse 15, and signals from the keyboard 14 and mouse 15 are processed by the CPU 4 via a USB (Universal Serial Bus) controller 13 and the south bridge 7. The The CPU 4 sends image data, text data, and the like to the display (display device) 9 via the north bridge 5 and the display controller 8. The user can visually recognize image data, text data, and the like from the host device 3 via the display 9.

The CPU 4 is a processor provided to control the operation of the computer system 1, and an operating system (OS) 100 loaded from the SSD 2 to the main memory 6.
Execute. Further, when the optical drive 10 enables execution of at least one of reading processing and writing processing with respect to the loaded optical disk, the CPU 4 executes those processing. The CPU 4 is a BIOS (Basic Input / Output System) -ROM 1
The system BIOS stored in 1 is also executed. The system BIOS is a program for controlling hardware in the computer system 1. In addition, the CPU 4 controls a LAN (Local Area Network) controller 12 via the south bridge 7.

The north bridge 5 is a bridge device connected to the local bus of the CPU 4. The north bridge 5 also includes a memory controller that controls access to the main memory 6. The north bridge 5 also has a function of executing communication with the display controller 8 and the like.

The main memory 6 temporarily stores programs and data and functions as a working memory for the CPU 4. The main memory 6 includes a storage area 6A for storing the OS 100 and a storage area 6B for storing the control tool 200. As generally known, the OS is the host device 3.
Is a program for managing the entire host device 3 such as managing the input / output devices, managing the disk and memory, and controlling the software so that the hardware of the host device 3 can be used.

The display controller 8 is a video playback controller that controls the display 9 of the computer system 1. The south bridge 7 is a bridge device connected to the local bus of the CPU 4. The south bridge 7 controls the SSD 2, which is a storage device that stores various software and data, via the ATA interface 19.

In the computer system 1, the SSD 2 is accessed in units of logical sectors. ATA
A write command (write request), a read command (read request), a flash command, and the like are input to the SSD 2 via the interface 19.

The south bridge 7 also has a function for controlling access to the BIOS-ROM 11, the optical drive 10, the LAN controller 12, and the USB controller 13. US
A keyboard 14 and a mouse 15 are connected to the B controller 13.

For example, as shown in FIG. 2, the control tool 200 is stored in the area 16B of the NAND flash memory (NAND memory) 16 of the SSD 2 when the host device 3 is powered off. At the time of start-up or program start-up, the area 16B of the NAND memory 16 is loaded into the area 6B on the main memory 6. On the other hand, when a plurality of non-volatile storage devices are connected to the host 3, as shown in FIG.
It is stored in the area 20B of the non-volatile storage device 20 different from SD2, and may be loaded from the area 20B to the area 6B on the main memory 6 when the host device 3 is activated or when the program is activated. In particular, when the nonvolatile storage device 20 is used as a system drive for storing the OS and the SSD 2 is used as a data drive for storing user data such as documents, still image data, and moving image data, the system drive 20 Is used as a drive that mainly stores the OS and application programs, and the data drive 2 is used as a drive that stores user data. It is desirable to store the control tool in the non-volatile storage device 20.

From the viewpoint of saving the user from setting up the control tool 200, the computer system 1 is shipped in a state where the control tool 200 is stored in the SSD 2 or the nonvolatile storage device 20, for example, as shown in FIGS. It is desirable to line up at the store and go into the hands of the user. On the other hand, from the viewpoint of allowing the user to select whether or not to install the control tool and providing the user with the latest control tool, the control tool 200 can be downloaded from the WEB, DVD-ROM, It is desirable that data can be stored in the SSD 2 or the nonvolatile storage device 20 by installation from an external storage medium such as a USB memory.

FIG. 4 shows an example of downloading from the WEB. The control tool 200 is a WEB server 21
The control tool 200 is stored in the area 16B on the NAND memory 16 of the SSD 2 via the LAN controller 12, for example, via the Internet, a local network, a wireless LAN, or the like. Downloaded (or installed). In the case of FIG. 3, the control tool 200 includes the nonvolatile storage device 20.
It is downloaded or installed in the upper area 20B.

FIG. 5 shows an example of installation from an optical medium such as a DVD-ROM or CD-ROM. The control tool 200 is stored in an optical medium 23 such as a DVD-ROM or a CD-ROM, and the control tool 20 is set when the optical medium 23 is set in the optical drive 10.
0 is installed in the area 16B (or area 20B) on the NAND memory 16 of the SSD 2 via the optical drive 10. FIG. 6 shows an example of installation from a USB memory. The control tool 200 is stored in the area 24B of the USB memory 24, and the USB memory 2
4 is connected to the USB controller 13, the control tool 200 is installed in the area 16B (or area 20B) on the NAND memory 16 of the SSD 2 via the USB controller 13. Of course, other external memories such as an SD card may be used instead of the USB memory 24. From the viewpoint of easy availability by the user, the optical medium 23
It is desirable that the USB memory 24 be sold together with the SSD 2 as an accessory when the SSD 2 is shipped. On the other hand, the optical media 23 and the USB memory 24 may be sold alone as software products, or may be attached as magazines or book appendices.

In the present embodiment, the OS 100 is a normal OS (first operating system) as the OS 100.
There are two types, 100A and emergency OS (second operating system) 100B. The normal-time OS 100A is an operating system used when the reliability of the SSD 2 is not deteriorated. As described above, in the normal OS, writing to the SSD occurs at the time of booting, and writing to the SSD not intended by the user occurs in the background.
As shown in FIG. 7, the normal-time OS 100A is stored in the area 16D of the NAND memory 16 when the host apparatus 3 is powered off. The emergency OS 100B is an operating system used when the reliability of the SSD 2 is deteriorated, and writing to the SSD 2 is not performed (writing not supported). That is, the emergency OS performs only a read operation on the SSD at the time of booting, and does not perform writing to the SSD in the background unintended by the user. Note that the emergency OS 100B may be able to write to a non-volatile storage device other than the SSD 2 when the reliability has deteriorated. In addition, the emergency OS 100B
When it is necessary to write some data such as system information of the emergency OS to the SSD 2, it may be permitted to write the data to the SSD 2 as an exception, but the data amount of the data is equal to the capacity of the NAND memory 16. It is desirable that it be sufficiently small. More preferably, in order to prevent a user from accidentally sending a write command and writing data to the SSD 2, the emergency OS 100B prohibits the normal write command for the SSD 2 from being sent to the SSD 2. If it is necessary to write data exceptionally, write to SSD2 is permitted only by commands using special commands such as SCT Command Transport described in INCITS ACS-2 and other vendor-specific commands. It is desirable to do so.

As shown in FIG. 7, the emergency OS 100B is stored in the area 16E of the NAND memory 16 when the host apparatus 3 is powered off. Since the emergency OS 100B is not used when the SSD 2 is in a normal state, the area 16E is set so that it cannot be rewritten from the host device 3 when the normal OS is used from the viewpoint of preventing the destruction of the emergency OS data in the area 16E. It is desirable. For example, during the operation of the normal time OS 100A, it is desirable that the LBA is not allocated to the area 16E in the management information of the SSD 2 described later. In this case, the LBA is stored in the area 16E after the emergency OS operation is required. Assigned. Alternatively, during the operation of the normal time OS 100A, the area 16E has the normal time OS 100A.
It is desirable that write protection is set by A.

From the viewpoint of reducing access to the SSD 2 as much as possible while the reliability of the SSD 2 is deteriorated, it is desirable that the data amount of the area 16E in which the emergency OS 100B is stored is significantly smaller than the capacity of the NAND memory 16. As an emergency OS100B, for example, MS-
Customization that prohibits writing to SSD2 in an OS such as DOS (trademark) or Linux (registered trademark), or a backup function of SSD2 may be adopted. It may be software developed in the past.

When the computer system 1 is started up, such as when the computer system 1 is turned on or when the OS is restarted, the host device 3 reads the boot loader 300 written in the area 16C of the NAND memory 16 and reads the boot loader. Based on 300 information,
It is determined which of the normal OS 100A and the emergency OS 100B is loaded into the area 6A in the host device 3. For this purpose, the boot loader 300 holds OS pointer information OSPT indicating the LBA of the OS to be read. When reading from the boot loader 300, the host device 3 may read the LBA indicated by the OS pointer information OSPT as a starting point and write the read data to the area 6A on the main memory 6. The boot loader 300 is configured to be loaded with the normal-time OS 100A in the initial state. After the reliability of the SSD 2 deteriorates, the control tool 200 stored in the area 6B on the main memory 6 rewrites the boot loader 300 stored in the area 16C on the NAND memory 16 to read the emergency OS 100B. Rebuild 300. For example, a master boot record (MBR) may be adopted as the boot loader 300,
A GUID partition table (GPT) may be adopted.

When a plurality of nonvolatile storage devices are connected to the host device 3, the OS may be stored in a nonvolatile storage device 20 different from the SSD 2. For example, as shown in FIG. 8, both the normal OS and the emergency OS may be stored in the nonvolatile storage device 20, or the normal OS is stored in the SSD 2, and the emergency OS is a nonvolatile storage device. 20, the normal-time OS may be stored in the nonvolatile storage device 20, and the emergency OS may be stored in the SSD 2. In particular, when the nonvolatile storage device 20 is used as a system drive for storing the OS and the SSD 2 is used as a data drive for storing user data such as documents, still image data, and moving image data, the system drive 20 Is used as a drive that mainly stores the OS and application programs, and the data drive 2 is used as a drive that stores user data. The nonvolatile storage device 20 is normally O
S is preferably stored, and more preferably, the emergency OS is also stored in the nonvolatile storage device 20 as the system drive.

From the viewpoint of saving the effort for the user to set up the emergency OS, for example, as shown in FIGS. 7 and 8, the computer system 1 is shipped with the emergency OS stored in the SSD 2 or the nonvolatile storage device 20, for example. It is desirable to line up at the store and go into the hands of the user. On the other hand, from the viewpoint of allowing the user to select whether or not the emergency OS can be installed and providing the user with the latest emergency OS, the emergency OS is downloaded from the WEB or DVD- It is desirable that data can be stored in the SSD 2 or the nonvolatile storage device 20 by installation from an external storage medium such as a ROM or a USB memory.

FIG. 9 shows an example of downloading from the WEB. The emergency OS is stored in the area 22E of the storage medium 22 in the WEB server 21, and the emergency OS is connected to the NAND of the SSD 2 via the LAN controller 12 via a network such as the Internet, a local network, or a wireless LAN. It is downloaded or installed in the area 16E on the memory 16. In the case of FIG. 8, it is downloaded or installed in the area 20E on the nonvolatile storage device 20.

FIG. 10 shows an example of installation from an optical medium such as a DVD-ROM or CD-ROM. The emergency OS is an area 23E of the optical medium 23 such as a DVD-ROM or CD-ROM.
When the optical medium 23 is set in the optical drive 10, the emergency OS is installed in the area 16E (or area 20E) on the NAND memory 16 of the SSD 2 via the optical drive 10. FIG. 11 shows an example of installation from a USB memory. The emergency OS is stored in the area 24E of the USB memory 24, and the USB memory 24
Is connected to the USB controller 13, the emergency OS is installed in the area 16E (or area 20E) on the NAND memory 16 of the SSD 2 via the USB controller 13. Of course, other external memories such as an SD card may be used instead of the USB memory 24. From the viewpoint of easy availability by the user, optical media 23 and USB
It is preferable that the memory 24 be sold together with the SSD 2 as an accessory when the SSD 2 is shipped. On the other hand, the optical media 23 and the USB memory 24 may be sold alone as software products, or may be attached as magazines or book appendices. The emergency OS and the control tool are preferably stored in the same external memory such as the optical medium 23 and the USB memory 24 from the viewpoint of ease of installation.

FIG. 12 shows a hierarchical structure at the software level of the computer system 1. The control tool 200 and other software (software other than the control tool 200) loaded on the main memory 6 normally do not directly communicate with the SSD 2 and are loaded on the main memory 6.
Communicate with SSD 2 via 100. Control tool 200 and other software is SSD
When it becomes necessary to transmit a command such as a read request or a write request to 2, the control tool 2
00 and other software transmit an access request for each file to the OS 100. O
S100 refers to the file management table included in OS 100, identifies the logical address (LBA) of SSD2 corresponding to the file for which access is requested, and transmits an instruction specific to the interface including the corresponding LBA to SSD2. When a response is returned from the SSD 2, the OS 100 identifies to which software the interface-specific response after conversion is a response, and returns a response to the identified software.

Next, a configuration example of the computer system 1 will be described. The computer system 1 can be realized, for example, as a desktop computer or a notebook portable computer. FIG. 13 is a schematic diagram of a desktop computer as the computer system 1. The desktop computer includes a computer main body 31, a display 9, a keyboard 14, a mouse 15, and the like. The computer main body 31 includes a mother board 30 on which main hardware is mounted, an SSD 2, a power supply device 32, and the like. The SSD 2 is physically connected to the mother board 30 via a SATA cable, and is electrically connected to the CPU 4 also mounted on the mother board via the south bridge 7 mounted on the mother board 30. The power supply device 32 generates various power sources used in the desktop computer and supplies power to the mother board 30 and the SSD 2 through a power cable.

FIG. 14 is a schematic diagram of a portable computer as the computer system 1.
The portable computer includes a computer main body 34, a display unit 35, and the like. The display unit 35 is, for example, an LCD (Liquid Crystal Display).
) Is incorporated. The display unit 35 is attached to the computer main body 34 so as to freely rotate between an open position where the upper surface of the main body 34 is exposed and a closed position covering the upper surface of the main body 34. The main body 34 has a thin box-shaped housing, and the power switch 36, the keyboard 14, the touch pad 33, and the like are disposed on the upper surface thereof. The main body 34 also includes an SSD 2, a motherboard, a power supply device, and the like, like the desktop computer.

As the information processing apparatus to which the present invention is applied, in addition to the computer system 1, an imaging apparatus such as a still camera or a video camera may be used. Also good.

Next, the NAND memory 16 which is a main component of the SSD 2 will be described. FIG.
1 shows an example of the internal configuration of the NAND memory chip 80 constituting the NAND memory 16. NAN
The D memory 16 includes one or more NAND memory chips 80. The NAND memory chip 80 has a memory cell array in which a plurality of memory cells are arranged in a matrix. A memory cell transistor constituting a memory cell array is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a semiconductor substrate.
). The stacked gate structure includes a charge storage layer (floating gate electrode) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate electrode formed on the floating gate electrode with an inter-gate insulating film interposed therebetween. It is out. The memory cell transistor changes the threshold voltage according to the number of electrons stored in the floating gate electrode, and stores data according to the difference in the threshold voltage. In this embodiment, each memory cell has 2bi using an upper page and a lower page.
The case of t / cell four-value storage method will be described. However, each memory cell uses a single page for 1 bit / cell binary storage method, or upper page and middle The essence of the present invention is in the case of a 3-bit / cell 8-level storage writing method using pages and lower pages, or even when a multi-value storage writing method of 4 bit / cell or more is adopted does not change. The threshold voltage can be adjusted by trapping electrons at the nitriding interface as a charge storage layer, such as a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type, as well as a structure having a floating gate electrode. It may be a simple structure. Similarly, the MONOS memory cell transistor may be configured to store one bit or may be configured to store multiple values. Further, the nonvolatile storage medium may be a semiconductor storage medium in which memory cells are arranged three-dimensionally as described in JP 2010-161199 A or JP 2011-29586 A.

As shown in FIG. 15, the NAND memory chip 80 includes a memory cell array 82 in which memory cells for storing data are arranged in a matrix. Memory cell array 82
Includes a plurality of bit lines, a plurality of word lines, and a common source line, and memory cells capable of electrically rewriting data are arranged in a matrix at intersections of the bit lines and the word lines. The memory cell array 82 is connected to a bit line control circuit 83 for controlling the bit lines and a word line control circuit 85 for controlling the word line voltage. That is, the bit line control circuit 83 reads the data of the memory cells in the memory cell array 82 via the bit lines, while applying a write control voltage to the memory cells in the memory cell array 82 via the bit lines. Write.

A column decoder 84, a data input / output buffer 89, and a data input / output terminal 88 are connected to the bit line control circuit 83. Data of the memory cell read from the memory cell array 82 is output from the data input / output terminal 88 to the outside via the bit line control circuit 83 and the data input / output buffer 89. Further, write data input from the outside to the data input / output terminal 88 is input to the bit line control circuit 83 by the column decoder 84 via the data input / output buffer 89, and writing to the designated memory cell is performed. .

Further, the memory cell array 82, the bit line control circuit 83, the column decoder 84, the data input / output buffer 89, and the word line control circuit 85 are connected to the control circuit 86. The control circuit 86 is responsive to the control signal input to the control signal input terminal 87 to provide a memory cell array 82.
A control signal and a control voltage for controlling the bit line control circuit 83, the column decoder 84, the data input / output buffer 89, and the word line control circuit 85 are generated. Of the NAND memory chip 80, circuit portions other than the memory cell array 82 are connected to a NAND controller (NAN).
DC) 81.

FIG. 16 shows a configuration of the memory cell array 82 shown in FIG. The memory cell array 82 is a NAND cell type memory cell array, and includes a plurality of NAND cells. One NAND cell is a memory string MS composed of memory cells connected in series.
And selection gates S1 and S2 connected to both ends thereof. Select gate S
1 is connected to the bit line BL, and the selection gate S2 is connected to the source line SRC. The control gates of the memory cells MC arranged in the same row are commonly connected to the word lines WL0 to WLm-1. The first selection gate S1 is commonly connected to the select line SGD, and the second selection gate S2 is commonly connected to the select line SGS.

The memory cell array 82 includes one or a plurality of planes, and the plane includes a plurality of blocks. Each block includes a plurality of NAND cells, and data is erased in units of blocks.

A plurality of memory cells connected to one word line constitute one physical sector. Data is written and read for each physical sector (this physical sector is an LB described later).
A has no relation to the logical sector of A). One physical sector stores, for example, data for two pages in the case of the 2-bit / cell write method (four values). On the other hand, in the case of the 1 bit / cell write method (binary), for example, one page of data is stored in one physical sector, and in the case of the 3 bit / cell write method (eight values), for example, three pages are stored in one physical sector. Data is stored.

In the read operation, the program verify operation, and the program operation, the SSD described later
One word line is selected according to the physical address received from C41, and one physical sector is selected. Switching of pages in the physical sector is performed by a physical address. In this embodiment, the NAND memory 16 is a 2-bit / cell write system, and the SSDC 41 treats that two pages of an upper page (Upper Page) and a lower page (Lower Page) are assigned as physical pages to the physical sector. Physical addresses are assigned to all pages.

The 4-bit NAND memory of 2 bits / cell is configured so that the threshold voltage in one memory cell can have four distributions. FIG. 17 shows two-bit quaternary data (data “11”, “01”, “10”) stored in the memory cell of the quaternary NAND cell type flash memory.
, “00”) and the threshold voltage distribution of the memory cell. In FIG. 17, V _A1 is a voltage applied to the selected word line when reading two data for a physical sector in which only the lower page has been written and the upper page has not been written, and V _A1V is
In the case of writing to A1, the verify voltage applied to check whether the writing is completed is shown.

_{Also, V A2, V B2, V} C2 , the lower page and upper page for written physical sector, a voltage applied to the selected word line when reading four data, V _A
2V , V _B2V , and V _C2V indicate verify voltages that are applied to check whether or not the writing is completed when writing to each threshold voltage distribution. Also,
Vread1 and Vread2 are read voltages that are applied to unselected memory cells in the NAND cell when data is read, and make the unselected memory cells conductive regardless of the retained data. Furthermore, Vev1 and Vev2 are erase verify voltages applied to the memory cells to confirm whether or not the erase has been completed when erasing the data in the memory cells, and have negative values. The size is determined in consideration of the influence of interference between adjacent memory cells. The magnitude relationship between the above voltages is as follows:
_{Vev1 <V A1 <V A1V <} Vread1
Vev2 <V _A2 <V _A2V <V _B2 <V _B2V <V _C2 <V _C2V <Vread2
It is.

Although the erase verify voltages Vev1, Vev2, and Vev3 are negative values as described above, the voltage actually applied to the control gate of the memory cell MC in the erase verify operation is
It is zero or positive, not negative. That is, in an actual erase verify operation, a positive voltage is applied to the back gate of the memory cell MC, and a positive voltage smaller than zero or the back gate voltage is applied to the control gate of the memory cell MC. In other words, the erase verify voltages Vev1, Vev2, and Vev3 are equivalently negative voltages.

The upper limit value of the threshold voltage distribution ER of the memory cell after the block erase is also a negative value, and data “11” is assigned. Lower page and upper page write state data “11”
”,“ 01 ”,“ 10 ”,“ 00 ”memory cells have positive threshold voltage distributions ER2,
A2, B2, and C2 (the lower limit values of A2, B2, and C2 are also positive values), and data “01”
The threshold voltage distribution A2 has the lowest voltage value, the threshold voltage distribution C2 of data “00” has the highest voltage value, and the voltage values of the various threshold voltage distributions have a relationship of A2 <B2 <C2. The memory cell of data “10” in the lower page write and upper page non-write state has a positive threshold voltage distribution A1 (the lower limit value of A1 is also a positive value). Note that the threshold voltage distribution shown in FIG. 17 is merely an example, and the present invention is not limited to this. For example, in FIG. 17, the threshold voltage distributions A2, B2, and C2 have been described as being positive threshold voltage distributions. However, the threshold voltage distribution A2 is a negative voltage distribution, and the threshold voltage distributions B2 and C2 are positive voltages. Such a distribution is also included in the scope of the present invention. Moreover, even if the threshold voltage distributions ER1 and ER2 are positive values, the present invention is not limited to this. In this embodiment, ER2, A
2, B2, C2 data corresponding to “11”, “01”, “10”, “00”, respectively.
However, other correspondence relationships such as “11”, “01”, “00”, and “10” may be used.

The 2-bit data of one memory cell includes lower page data and upper page data, and the lower page data and the upper page data are written into the memory cell by separate write operations, that is, two write operations. When data is marked as “* @”, * represents upper page data and @ represents lower page data.

First, writing of lower page data will be described with reference to the first to second stages in FIG.
All the memory cells have an erased threshold voltage distribution ER and store data “11”. As shown in FIG. 17, when lower page data is written, the threshold voltage distribution ER of the memory cell is divided into two threshold voltage distributions (“1” or “0”) according to the value (“1” or “0”) of the lower page data. ER1, A1). When the value of the lower page data is “1”, the threshold voltage distribution ER in the erased state is maintained, so ER1 = ER. However, ER1> ER may be satisfied.

On the other hand, when the value of the lower page data is “0”, a high electric field is applied to the tunnel oxide film of the memory cell, electrons are injected into the floating gate electrode, and the threshold voltage Vth of the memory cell.
Is raised by a predetermined amount. Specifically, the verify potential V _A1V is set, and the write operation is repeated until the threshold voltage becomes equal to or higher than the verify voltage V _A1V . As a result, the memory cell changes to a write state (data “10”). If the threshold voltage is not reached even after repeating the write operation a predetermined number of times (or if the number of memory cells that do not reach the threshold voltage is equal to or greater than the predetermined value), writing to the physical page is a “write error”.

Next, writing of upper page data will be described with reference to the second to third stages in FIG.
The upper page data is written based on write data (upper page data) input from the outside of the chip and lower page data already written in the memory cell.

That is, as shown in the second to third stages of FIG. 17, when the value of the upper page data is “1”, a high electric field is not applied to the tunnel oxide film of the memory cell, and the threshold voltage of the memory cell is set. Prevent rise in Vth. As a result, data “11” (threshold voltage distribution ER1 in the erased state)
The memory cell of “1” maintains the data “11” as it is (ER2), and the memory cell of the data “10” (threshold voltage distribution A1) maintains the data “10” as it is (B2). However, in terms of ensuring the voltage margin between the distribution, by adjusting the lower limit of the threshold voltage distribution with a large positive verify voltage V _B2V than above verify voltage V _A1V, thereby the width of the threshold voltage distribution It is desirable to form a threshold voltage distribution B2 with a narrowing. If the site voltage is not reached even after the lower limit adjustment is repeated a predetermined number of times (or if the number of memory cells that do not reach the threshold voltage is greater than or equal to the predetermined value), writing to the physical page becomes a “write error”.

On the other hand, when the value of the upper page data is “0”, a high electric field is applied to the tunnel oxide film of the memory cell, electrons are injected into the floating gate electrode, and the threshold voltage Vth of the memory cell.
Is raised by a predetermined amount. Specifically, the verify potentials V _A2V and V _C2V are set, and the write operation is repeated until the threshold voltage becomes equal to or higher than the verify voltage V _A1V . As a result, the memory cell with the data “11” (threshold voltage distribution ER1 in the erased state) changes to the data “01” with the threshold voltage distribution A2, and the memory cell with the data “10” (A1) has the threshold voltage distribution C2. The data changes to “00”. At this time, the verify voltages V _A2V and V _C2V are used to adjust the lower limit values of the threshold voltage distributions A2 and C2. If the site voltage is not reached even after repeating the write operation a predetermined number of times (or if the number of memory cells that do not reach the threshold voltage is equal to or greater than the predetermined value), writing to the physical page becomes a “write error”.

On the other hand, in the erase operation, the erase verify potential Vev is set, and the erase operation is repeated until the threshold voltage becomes equal to or lower than the verify voltage Vev. As a result, the memory cell changes to a write state (data “00”). If the site voltage is not reached even if the erase operation is repeated a predetermined number of times (or if the number of memory cells that do not reach the threshold voltage is greater than or equal to a predetermined value), the erase for the physical page is an “erase error”.

The above is an example of a data writing method in a general four-value storage method. Even in a multi-bit storage system of 3 bits or more, the basic operation is the same because only the operation of dividing the threshold voltage distribution into 8 or more types is added to the above operation according to the higher-order page data.

Next, a configuration example of the SSD 2 will be described. As shown in FIG. 18, the SSD 2 is a NAND flash memory (hereinafter abbreviated as a NAND memory) 1 as a nonvolatile semiconductor memory.
6 and an interface controller (IFC) 42 that transmits and receives signals to and from the host device 3 via the ATA interface 19, and a cache memory (CM) 46 that functions as an intermediate buffer between the interface controller 42 and the NAND memory 16. RAM (Random Access Memory) 40 as memory, NAND memory 16 and RAM 40
Management, control, and control of the interface controller 42 SSD controller (
SSDC) 41 and a bus 43 for connecting these components.

The RAM 40 includes DRAM (Dynamic Random Access Memory), SRAM (Static
Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MR
AM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Acc
ess Memory) or the like. The RAM 40 may be included in the SSDC 41.

The NAND memory 16 includes a plurality of NAND memory chips 80, stores user data designated by the host device 3, stores a management table for managing user data, and backups management information managed by the RAM 40. Or remember. NAND
The memory 16 has a memory cell array 82 in which a plurality of memory cells are arranged in a matrix, and each memory cell can store multiple values using an upper page and a lower page. N
The AND memory 16 is constituted by a plurality of memory chips, and each memory chip is constituted by arranging a plurality of blocks which are data erasing units. In the NAND memory 16,
Data writing and data reading are performed for each page. The block is composed of a plurality of pages.

The RAM 40 includes a cache memory (CM) 46 that functions as a cache for data transfer between the host device 3 and the NAND memory 16. The RAM 40 functions as a management information storage memory and a work area memory. The management table managed in the area 40A of the RAM 40 is the same as the various management tables stored in the area 40M of the NAND memory 16.
It is developed at the time of SD2 startup, etc., and the NAND memory 1 is periodically or when the power is turned off.
6 is saved in the area 40M.

The function of the SSDC 41 is realized by a processor that executes a system program (firmware) stored in the NAND memory 16 and various hardware circuits.
Data transfer control between the host device 3 and the NAND memory 16 in response to various commands such as a write request, a cache flush request, and a read request from the host device 3, the RAM 40, and the NA
Update and management of various management tables stored in the ND memory 16, ECC encoding of data written to the NAND memory 16, ECC decoding of data read from the NAND memory 16, and the like are executed.

When the host device 3 issues a read request or write request to the SSD 2, the AT 3
LBA (Logical Block Addressing) as a logical address via the A interface 19
). LBA is a logical address in which a serial number from 0 is assigned to a logical sector (size: for example, 512 B). Further, when issuing a read request or a write request to the SSD 2, the host device 3 inputs a logical sector size that is a target of the read request or the write request together with the LBA.

The IFC 42 has a function of receiving a read request, a write request, and other requests and data from the host device 3 and transmitting the received request and data to the SSDC 41 or transmitting data to the RAM 40 under the control of the SSDC 41.

FIG. 19 shows the configuration of management information used in SSD2. The management information is stored in a nonvolatile manner in the area 40M of the NAND memory 16 as described above. The management information stored in the area 40M is expanded and used in the area 40A of the RAM 40 when the SSD 2 is activated. The management information 44 in the area 40A is saved and saved in the area 40M periodically or when the power is turned off. RA
When M40 is a nonvolatile RAM such as MRAM or FeRAM, the management information 44 may be stored only in the RAM 40. In this case, the management information 44 is N
It is not stored in the AND memory 16. In order to reduce the amount of writing to the NAND memory 16, it is desirable that the data stored in the management information 45 is a compressed version of the data stored in the area 40 </ b> A of the RAM 40. In order to reduce the frequency of writing to the NAND memory 16, it is desirable to add update information (difference information) of the management information 44 stored in the area 40 </ b> A of the RAM 40 to the management information 45. .

As shown in FIG. 19, the management information includes free block table (FBT) 60, bad block table (BBT) 61, active block table (ABT) 62, and track table (logical / physical conversion table for each track) 63. And a cluster table (logical-physical conversion table for each cluster) 64 and statistical information 65.

As shown in FIG. 20, the LBA is a logical address in which a serial number from 0 is assigned to a logical sector (size: eg, 512B). In this embodiment, the management unit of the logical address (LBA) of SSD 2 is a cluster address composed of the upper bit string from the lower (s + 1) bit of the LBA and an upper bit string from the lower (s + t + 1) bit of the LBA. Define the track address to be configured. That is, the logical sector is the host device 3.
Is the minimum access unit from. The cluster is a management unit for managing “small data” in the SSD, and is determined so that a natural number multiple of the logical sector size becomes the cluster size. A track is a management unit for managing “large data” inside the SSD, and is determined so that a natural number multiple of 2 or more of the cluster size is the track size. Therefore, the track address is LBA divided by the track size, and the track address is L
BA is the remainder obtained by dividing the track size, the cluster address is obtained by dividing the LBA by the cluster size, and the intra-cluster address is the remainder obtained by dividing the LBA by the cluster size. In the following description, for the sake of convenience, the track size is equal to the size of data that can be recorded in one physical block (if the physical block includes redundant bits for ECC processing performed by the SSDC 41), the size of the cluster is assumed. The size is equal to the size of data that can be recorded on one physical page (if the physical page includes redundant bits for ECC processing performed by the SSDC 41, the size is excluded).

The free block table (FBT) 60 manages IDs of unassigned physical blocks (free blocks: FB) of the NAND memory that can be newly assigned for writing when writing to the NAND memory 16. In addition, the erase count is managed for each physical block ID, and when the physical block is erased, the erase count of the block is incremented.

The bad block table (BBT) 61 manages the ID of a bad block (BB) as a physical block (physical block) that cannot be used as a storage area due to many errors. F
Similar to BT60, the number of erasures may be managed for each physical block ID.

The active block table (ABT) 62 manages an active block (AB) that is a physical block to which a use is assigned. In addition, the erase count is managed for each physical block ID, and when the physical block is erased, the erase count of the block is incremented.

The track table 63 manages the correspondence between the track address and the physical block ID in which the track data corresponding to the track address is stored.

The cluster table 64 manages the correspondence between the cluster address, the physical block ID in which the cluster data corresponding to the cluster address is stored, and the page address in the physical block in which the cluster data corresponding to the cluster address is stored. .

The statistical information 65 stores various parameters (X01 to X24) related to the reliability of the SSD2.

The statistical information 65 includes the total number of bad blocks (statistical information X01), the total number of erasures (statistical information X02), the average number of erasures (statistical information X03), the cumulative number of times of occurrence of write errors in the NAND memory (statistical information X04), NAND memory erase error count cumulative value (statistical information X05), read logical sector count total (statistical information X06), write logical sector count total (statistical information X07), ECC uncorrectable count total (statistical information X08), n bits ~ M-bit ECC correction unit total count (statistical information X09), SATA communication R error occurrence count (statistical information X10), SATA communication error occurrence count (statistical information X11), RAM40 error occurrence count (statistical information X12), Total usage time of SSD2 (statistical information X13), cumulative time when temperature exceeded the maximum recommended operating temperature Statistical information X14), time accumulated when the temperature falls below the minimum recommended operating temperature (statistical information X15), command response time maximum value (statistical information X16), command response time average value (statistical information X17), NAND memory Response time maximum value (statistical information X18), NAND response time average value (statistical information X19), current temperature (statistical information X20)
), Maximum temperature (statistical information X21), minimum temperature (statistical information X22), statistical information increase rate (statistical information X23), NAND rearrangement failure flag (statistical information X24), and the like.

The total number of bad blocks (statistical information X01) will be described. Each time one physical block of the NAND memory 16 in the SSD 2 is added to the bad block, the statistical information X01 is incremented by one. It is desirable that the statistical information X01 is reset to zero at the time of manufacturing the SSD 2 (before the inspection process), and blocks in which an error has occurred in the inspection process or a margin between distributions of the threshold distribution is found to be bad in advance. It is more desirable to add it to the block. The statistical information X01 may be calculated directly from the BBT 61 without being stored in the statistical information 65. The larger the statistical information X01, the worse the reliability.

The total number of erasures (statistical information X02) will be described. Statistical information X02 is N in SSD2
The cumulative number of erase times of all blocks of the AND memory 16 is shown. NAND memory 1 in the SSD 2
Each time six physical blocks are erased, the statistical information X02 is incremented by one. The statistical information X02 is desirably reset to zero when the SSD 2 is manufactured (before the inspection process). The statistical information X02 may be directly calculated from the FBT 60, BBT 61, and ABT 62 without being stored in the statistical information 65. The larger the statistical information X02 is, the worse the reliability is.

The erase number average value (statistical information X03) will be described. The statistical information X03 indicates an average value per block of the number of erasures of all blocks of the NAND memory 16 in the SSD 2. Some blocks such as a block for storing management information may be excluded from the aggregation target of the statistical information X03. It is desirable that the statistical information X03 is reset to zero when the SSD 2 is manufactured (before the inspection process). Statistical information X03 is not stored in statistical information 65, but FBT60, BBT61, ABT
You may calculate directly from 62. The larger the statistical information X03, the worse the reliability.

A cumulative value of the number of occurrences of write errors in the NAND memory (statistical information X04) will be described. The statistical information X04 is incremented by 1 each time a write error occurs in the write unit in the NAND memory 16 in the SSD 2 (may be added in block units). Statistical information X04 is S
It is desirable to reset to zero at the time of manufacturing SD2 (before the inspection process). Statistical information X
The larger 04, the worse the reliability.

A cumulative value of the number of occurrences of erasure errors in the NAND memory (statistical information X05) will be described. It is desirable that the statistical information X05 is reset to zero when the SSD 2 is manufactured (before the inspection process). Each time an erase error occurs in one block in the NAND memory 16 in the SSD 2, the statistical information X05 is incremented by one. A plurality of blocks may be collectively set as an erasure unit, and 1 may be added to the statistical information X05 every time an erasure error occurs in one erasure unit. Statistical information X
The larger 05, the worse the reliability.

The total number of read logical sectors (statistical information X06) will be described. Statistical information X06 is I
This is the total number of logical sectors of data transmitted by the FC 42 to the host device 3 as read data. The statistical information X06 is desirably reset to zero when the SSD 2 is manufactured (before the inspection process). The larger the statistical information X06, the worse the reliability.

The total number of write logical sectors (statistical information X07) will be described. Statistical information X07 is I
This is the total number of logical sectors of data received from the host device 3 as write data by the FC 42. The statistical information X07 is desirably reset to zero when the SSD 2 is manufactured (before the inspection process). The larger the statistical information X07, the worse the reliability.

The total number of ECC uncorrectable times (statistical information X08) will be described. If the error bit cannot be repaired by the ECC correction, the statistical information X08 is incremented by 1 for each read unit. An estimated value of the number of error bits that could not be error-corrected may be added, or the number of blocks that could not be error-corrected may be added. Statistical information X0
8 is desirably reset to zero when the SSD 2 is manufactured (before the inspection process). The larger the statistical information X08, the worse the reliability.

The n-bit to m-bit ECC correction unit total count (statistical information X09) will be described. n,
m is a natural number, 0 ≦ n ≦ m ≦ maximum number of bits that can be corrected. When ECC correction is performed on an ECC correction unit (for example, a physical page), if all error bits are normally repaired and the number of repaired error bits is n or more and m or less, “ 1 is added to the “n-bit to m-bit ECC correction unit total count”. When a maximum of 64 bits can be corrected per ECC unit by ECC correction, for example, “1 to 8 bit ECC correction unit total count”, “9 to 16 bit ECC correction unit total count”, and “17 to 24 bit ECC correction” "Total unit count""25-bit to 32-bit ECC correction unit total count""33-bit to 40-bit ECC correction unit total count""41-bit to 48-bit ECC correction unit total count""49-bit to 56-bit ECC correction unit total Number ”“ 57-bit to 64-bit ECC correction unit total count ”is prepared, and when ECC correction is normally performed, one of these eight parameters is set per ECC correction of one ECC correction unit. 1 is incremented. The statistical information X09 is desirably reset to zero when the SSD 2 is manufactured (before the inspection process). The larger the statistical information X09, the worse the reliability.

The number of R error occurrences (statistical information X10) of SATA communication will be described. Statistical information X1
0 is 1 each time an R error (Reception Error, R_ERR) in the SATA standard occurs.
Incremented. If there is any error such as a CRC error in a frame transmitted and received between the host and the SSD, it is counted as an R error. Statistical information X10
As an alternative, any of the SATA standard Phy Event Counters counters may be employed. It is desirable that the statistical information X10 is reset to zero when the SSD 2 is manufactured (before the inspection process). The larger the statistical information X10, the worse the reliability.

The number of SATA communication errors (statistical information X11) will be described. Each time another abnormality (other than R error) in SATA communication occurs, it is incremented by one. For example, although the ATA interface 19, IFC 42, and SSDC 41 are designed as the SATA Generation 3 standard, the communication standard actually negotiated with the SSD 2 or the host device 3 is a slower communication standard such as Generation 2. If there is, SATA
Assuming a communication error, the statistical information X11 is incremented by one. Statistical information X11 is S
It is desirable to reset to zero at the time of manufacturing SD2 (before the inspection process). The larger this value, the worse the reliability.

The number of error occurrences (statistical information X12) in the RAM 40 will be described. For example, RAM
When the ECC circuit and the error detection circuit are mounted on 40, when the SSDC 41 receives from the RAM 40 a signal indicating that ECC correction has not been performed or a signal indicating that an error has been detected, the statistical information X12 is incremented by one. It is desirable that the statistical information X12 is reset to zero when the SSD 2 is manufactured (before the inspection process). The larger this value, the worse the reliability.

The total usage time (statistical information X13) of the SSD 2 will be described. SSD2 is powered on
The SSDC 41 increments the elapsed time by counting the clock or receiving the time information from the internal clock circuit. Alternatively, the SSDC 41 may periodically receive the time information of the host device 3 from the host device 3 and increment the difference of the time information. It is desirable that the statistical information X13 is reset to zero when the SSD 2 is manufactured (before the inspection process). The larger this value, the worse the reliability.

The accumulated time (statistical information X14) exceeding the maximum recommended operating temperature will be described. For example, when a thermometer is mounted in the SSD 2 such as in the SSDC 41 or in the NAND memory 16 on the board of the SSD 2, the SSDC 41 periodically receives temperature information from the thermometer. When the received temperature exceeds the recommended operating temperature (for example, 100 ° C.), the SSDC 41 calculates the number of hours of operation above the estimated operating temperature based on the clock, the internal clock, or time information acquired from the host device 3. Increment. It is desirable that the statistical information X14 is reset to zero when the SSD 2 is manufactured (before the inspection process). The larger this value, the worse the reliability.

The cumulative total time (statistical information X15) below the minimum recommended operating temperature will be described. SS
When a thermometer is mounted in D2, the SSDC 41 periodically receives temperature information from the thermometer. If the received temperature falls below the recommended operating temperature (eg -40 ° C), SSD
C41 increments the number of hours of operation above the estimated operating temperature based on the clock, the internal clock, and time information acquired from the host device 3. It is desirable to reset to zero at the time of manufacturing the SSD 2 (before the inspection process). The larger this value, the worse the reliability.

The command response time maximum value (statistical information X16) will be described. The statistical information X16 is the maximum value of the time (or the number of clocks) required from receiving a command from the host device 3 to responding to the host device 3 (or until command execution is completed). When a response time exceeding X16 occurs, this response time is overwritten on X16. Statistical information X16 may be held for each command. When manufacturing SSD2 (before inspection process) or SSD2
It is desirable that X16 is reset to zero at the time of shipment.

The command response time average value (statistical information X17) will be described. Statistical information X17
This is the average value of the time (or the number of clocks) required from receiving a command from the host device 3 to responding to the host device 3 (or until command execution is completed). For example, it is obtained by holding a certain number of response time lists in the RAM 40 and calculating the average value of the response time lists. Statistical information X17 may be held for each command. SS
It is desirable that X17 is reset to zero when D2 is manufactured (before the inspection process) or when SSD2 is shipped.

The response time maximum value (statistical information X18) of the NAND memory will be described. Statistical information X1
8 is the maximum value of the time (or the number of clocks) required from when the SSDC 41 instructs the NAND memory 16 to obtain a response (or to receive a command execution completion notification). X18
If a response time exceeding 1 is generated, this response time is overwritten in X18. Statistical information X18 may be held for each command. It is desirable that X18 is reset to zero when the SSD 2 is manufactured (before the inspection process) or when the SSD 2 is shipped.

The NAND response time average value (statistical information X19) will be described. Statistical information X19 is
This is an average value of the time (or the number of clocks) required from when the SSDC 41 instructs the NAND memory 16 to obtain a response (or to receive a command execution completion notification). For example, it is obtained by holding a certain number of response time lists in the RAM 40 and calculating the average value of the response time lists. Statistical information X19 may be held for each command. SS
It is desirable that X19 is reset to zero when D2 is manufactured (before the inspection process) or when SSD2 is shipped.

The current temperature (statistical information X20) will be described. When a thermometer is mounted in the SSD 2, the SSDC 41 periodically receives temperature information from the thermometer. The SSDC 41 holds the temperature received last from the thermometer as the current temperature in the statistical information X20. If this value is extremely large (for example, 85 ° C. or higher), the reliability of the SSD 2 is adversely affected. If the temperature is extremely small (for example, −10 ° C. or lower), the reliability of the SSD 2 is adversely affected. To do.

The maximum temperature (statistical information X21) will be described. The SSDC 41 holds the maximum value of the current temperature X20 in the statistical information X21 as the maximum temperature. If this value is extremely large (for example, 8
5 ° C. or higher), which has an adverse effect on the reliability of SSD2. When the SSDC 41 receives a current temperature higher than X21 from the thermometer, the SSDC 41 rewrites X21 to the current temperature. It is desirable that X21 is reset to a temperature (for example, −40 ° C.) sufficiently lower than the operating temperature of the SSD 2 at the time of manufacturing the SSD 2 (before the inspection process) or shipping the SSD 2.

The minimum temperature (statistical information X22) will be described. The SSDC 41 holds the minimum value of the current temperature X20 in the statistical information X22 as the lowest temperature. If this value is extremely small (for example-
40 ° C. or less), and the reliability of SSD 2 is adversely affected. When the SSDC 41 receives a current temperature smaller than X22 from the thermometer, the SSDC 41 rewrites X22 to the current temperature. When manufacturing SSD2 (
It is desirable that X22 is reset to a temperature sufficiently higher than the operating temperature of the SSD 2 (for example, 120 ° C.) before shipment of the SSD 2 or before the inspection process.

The statistical information increase rate (statistical information X23) will be described. Information that is not the latest of the statistical information X01 to X19 (for example, a value before a certain time, a value when the SSD 2 is powered on, a value when the SSD 2 is previously powered down, etc.) is held separately. The statistical information X23 is defined by any of the following, for example.

Statistical information increase rate = (latest statistical information)-(old information)
Statistical information increase rate = ((Latest statistical information)-(Old information)) / (Elapsed time since the acquisition of old information)
Statistical information increase rate = ((Latest statistical information)-(Old information)) / (NA after obtaining old information)
ND access count)
It is desirable to reset to zero at the time of manufacturing the SSD 2 (before the inspection process). The larger this value, the worse the reliability.

The NAND organization failure flag (statistical information X24) will be described. If the statistical information X24 is 1, a sufficient number of free blocks for operation cannot be secured even by NAND organization. It is desirable to reset to zero at the time of manufacturing the SSD 2 (before the inspection process). The larger this value, the worse the reliability.

As the statistical information 65, all the parameters described above may be stored, or a part or any one of them may be stored. It is desirable that the statistical information 65 holds the latest information in the area 40A on the RAM 40 and is periodically backed up in the area 40M on the NAND memory 16. On the other hand, it may be stored only in either the RAM 40 or the NAND memory 16, or the statistical information is transmitted to the host device 3 and stored in the host device 3 or a storage device connected to the host device 3. You may do it.

(LBA forward conversion)
Next, the procedure for identifying the physical address from the LBA in the SSD 2 with reference to FIG.
(BA forward conversion) will be described. When the LBA is designated, the SSDC 41 calculates a track address, a cluster address, and an intra-cluster address from the LBA.

The SSDC 41 first searches the track table 63 and identifies the physical block ID corresponding to the calculated track address (steps S100 and S101). SSDC 41
It is determined whether or not the identified physical block ID is valid (step S102). If the physical block ID is not null but a valid value (step S102: Yes), this physical block ID is entered in the ABT 62. It is searched whether or not (step S103)
. When the physical block ID is entered in the ABT 62 (step S104: Ye
s) The position shifted by the in-track address from the start position of the physical block designated by this physical block ID becomes the physical position on the NAND memory 16 corresponding to the designated LBA (step S105). In such a case, the cluster table 64 is not required for specifying the physical position on the NAND memory 16 corresponding to the LBA, and such an LBA
Is called “track-managed LBA”. In step S104, when the physical block ID is not entered in the ABT 62 (step S104: No), the designated LBA does not have a corresponding physical address, and such a state is referred to as an “unwritten state”. Call (step S106).

In step S102, when the physical address corresponding to the designated track address is null and an invalid value (step S102: No), the SSDC 41 calculates a cluster address from the LBA, searches the cluster table 64, and calculates The physical block ID corresponding to the cluster address and the corresponding intra-physical block page address are acquired from the cluster table 64 (step S107). The position shifted by the intra-cluster address from the start position of the physical page specified by the physical block ID and the intra-physical page address is the physical position on the NAND memory 16 corresponding to the specified LBA. In such a case, the physical position on the NAND memory 16 corresponding to the LBA cannot be specified only from the track table 63, and it is necessary to refer to the cluster table 64. This is referred to as “cluster-managed LBA” (step S108).

(Read operation)
Next, a read operation in the SSD 2 will be described with reference to FIGS. The read operation described in this embodiment is a 60h READ FPDMA described in INCITS ACS-2.
In the case of QUEUED, other write commands such as 25h READ DMA EXT may be adopted, and the difference in the type of read command does not affect the essence of the invention. SSD2 is host device 3
When the read command is received from the CPU 40 (step S110), the SSDC 41 adds the read command to the read command queue on the RAM 40 (step S111), and sends back to the host apparatus 3 that the read command has been accepted.

On the other hand, if there is an instruction in the read instruction queue on the RAM 40, the SSDC 41 determines whether or not the read process can be executed (step S120).
If it is determined that the read process is ready, the physical position of the data is specified from the LBA received from the host device 3 according to the LBA forward conversion procedure shown in FIG. 21 (step S121). The SSDC 41 reads data from the physical page at the specified position (step S123), and uses the ECC redundant bit in the read data to perform ECC.
The decrypted data is decrypted (step S124), the decrypted data is transmitted to the host apparatus 3 via the IFC 42 (step S125), and the statistical information 65 is updated. The data read from the NAND memory 16 may be once written in the RAM 40, and the data written in the RAM 40 may be decrypted and transmitted to the host device 3. Alternatively, the decrypted data is temporarily stored in the R memory.
The data written in the AM 40 and the data written in the RAM 40 may be transmitted to the host device 3.

In step S124, the SSDC 41 attempts to decode by ECC. If the decoding cannot be performed, the physical block including the page that could not be decoded is deleted from the ABT 62 and registered in the BBT 61, and the ECC of the statistical information 65 cannot be corrected. Total number of ECC correction units (
Statistical information X08) is added. At that time, the data of the block is copied to the free block allocated from the FBT 60, the physical block ID of the free block is registered in the ABT 62, and the physical blocks of the track table 63 and the cluster table 64 are copied from the copy source physical block ID to the copy destination. It is desirable to rewrite the physical block ID.

(Write operation)
Next, a write operation in the SSD 2 will be described with reference to FIGS. The write operation described in this embodiment is a 61h WRITE FPDM described in INCITS ACS-2.
In the case of A QUEUED, other write commands such as 35h WRITE DMA EXT may be adopted, and the difference in the type of write command does not affect the essence of the invention. When the SSD 2 receives a write command from the host device 3 (step S130), the SSDC 41 adds this write command to the read command queue on the RAM 40 (step S131), and notifies the host device 3 that the write command has been accepted. Send back.

On the other hand, if there is an instruction in the write instruction queue on the RAM 40, the SSDC 41 determines whether or not the write process can be executed (step S140).
If it is determined that the write process can be executed, the host apparatus 3 is notified that the write process is possible, the write data is received from the host apparatus 3, the received data is ECC-encoded, and the encoded data is stored in the RAM 40. Stored in the cache memory 46. Note that unencoded data may be stored in the cache memory 46 and encoded when written to the NAND memory 16.

Next, the SSDC 41 reads the FBT 60 (step S141), and acquires the physical block ID of the free block from the FBT 60. If there is no free block (step S142: No), the SSDC 41 arranges the NAND memory 16 described later (NAND
Organizing) (step S143), and after this organizing, the FBT 60 is read (step S).
144) The physical block ID of the free block is acquired from the FBT 60. SSDC41
Performs an erasing operation on the free block for which the physical block ID has been acquired. When an erasure error occurs, the physical block ID is added to the BBT 61, deleted from the FBT 60,
The process re-starts from S141 to reacquire the free block. Note that even if a physical block has an erasure error once, it can be erased normally without erasure if the erasure operation is performed again. From the viewpoint of preventing an unnecessary increase in the number of bad blocks. , FBT
60 or ABT 62 is provided with an item of erase error occurrence count for each block as statistical information X05 for each block. When a block erase error occurs, this is incremented, and the erase error occurrence count for each block exceeds a predetermined value. In this case, it is desirable to register the block in the BBT 61. More preferably, in order to convert only physical blocks in which erasure errors continuously occur into bad blocks, the SSDC 41 provides an item of “number of erasure errors per block” instead of the “number of erasure errors per block”. , If a block erase error occurs, increment this,
It is desirable to reset this to zero when erasing can be performed without error, and to register the block in the BBT 61 when the “number of consecutive erasure errors for each block” exceeds a predetermined value.

Next, the SSDC 41 searches for valid data corresponding to the LBA according to the forward conversion procedure shown in FIG. 21 in order to search whether the LBA specified by the write command is in an unwritten state. It is determined whether or not already stored in the NAND memory 16 (step S
145, S146).

When the LBA is in an unwritten state (step S146: Yes), the SSDC 41 writes the received data stored in the cache memory 46 to the free block (step S147), and the free block (new physical block) that has been written. And the erase count are registered in the ABT 62, and the ID of the written physical block is deleted from the FBT 60 (step S151). At this time, it is determined whether the track management or the cluster management is performed by dividing the LBA of the received data by a track unit (track partition) and determining whether or not the track partition is filled with data ( Step S152). That is, when the track section is filled with data, track management is performed, and when the track section is not filled with data, cluster management is performed. In the case of cluster management, the cluster table 64 is rewritten to associate the new physical block ID with the LBA (step S153), and the track table 63 is rewritten to associate the invalid physical block ID (for example, null) with the LBA. In the case of track management, the track table is rewritten and the new physical block ID is associated with the LBA (step S154).

On the other hand, if the LBA is not in an unwritten state in step S146, SSDC4
1 reads all the data in the corresponding physical block from the NAND memory 16 based on the physical block ID obtained by forward conversion, and writes it in the RAM 40 (step S148).
. Then, the data stored in the cache memory 46 and the data read from the NAND memory 16 and written to the RAM 40 are combined on the RAM 40 (step S149),
The synthesized data is written in the free block (step S150).

If a write error occurs in step S150, the physical block ID is added to the BBT 61, deleted from the FBT 60, and re-acquired from step S141. Note that even if a physical block has a write error once, it can be written normally without a write error if the write operation is performed again. Therefore, from the viewpoint of preventing an unnecessary increase in the number of bad blocks. , FBT60 and ABT6
2 is provided with an item of the number of write errors for each block as the statistical information X04 for each block. When a block write error occurs, this is incremented, and “the number of write errors for each block” exceeds a predetermined value. In this case, it is desirable to register the block in the BBT 61. More preferably, in order to convert only the physical blocks in which write errors continuously occur into bad blocks, the SSDC 41 provides an item of “number of consecutive write errors per block” instead of the above “number of write errors per block”. When a block write error occurs, this is incremented, and when the write can be performed without error, this is reset to zero, and the "number of consecutive write errors per block" exceeds the specified value. It is desirable to register the block in the BBT 61.

The SSDC 41 registers the ID of the free block (new physical block) that has been written and the number of times of erasure in the ABT 62, and deletes the ID of the physical block that has been written from the FBT 60 (step S151). When the LBA is cluster management, the old physical block ID in the cluster table 64 is rewritten to the new physical block ID (steps S152 and S1).
53). In the case of track management, the old physical block ID in the track table is rewritten to the new physical block ID (steps S152 and S154). Further, the SSDC 41 adds the old physical block ID and its erase count to the FBT 60, and deletes the old physical block ID and its erase count from the ABT 62 (step S155). The SSDC 41 reflects the contents of the above writing process in the statistical information 65.

(NAND organization)
Since the capacity of the entire LBA of the SSD 2 is designed to be smaller than the total capacity of the NAND memory 16 of the SSD 2, the free blocks will not be exhausted as long as the write operation continues to be written in track units. On the other hand, if a large number of cluster unit writes occur to an unwritten LBA, a physical block having a capacity larger than that of the cluster is allocated to one cluster unit write. NAN
D memory 16 physical blocks will be required, which can lead to depletion of free blocks. When free blocks are depleted, new free blocks can be secured by organizing the NAND memory 16 described below.

The NAND arrangement in the SSD 2 will be described with reference to FIG. Not all clusters stored in the physical block are valid clusters, and invalid clusters that do not correspond to valid clusters are not associated with LBAs. A valid cluster is a cluster that stores the latest data, and an invalid cluster is a cluster in which data of the same LBA is written to another location and is no longer referenced. The physical block has data for the invalid cluster, and the free block can be secured by executing the NAND organizing that collects the data of the valid cluster and rewrites the data to a different block.

First, the physical block IDi = 0 is set, and the free space accumulated amount S = 0 is set (step S160).
). The SSDC 41 determines whether or not the physical block whose ID is i = 0 is entered in the track table 63 (step S161). If it is entered in the track table, i is incremented by 1 (step S162), and the same determination is performed for the physical block having the next ID number (step S161). That is, when the physical block ID is included in the track table 63, the data of this physical block is track management and is not included in the NAND organizing target.

If the physical block with ID = i is not track management, the SSDC 41 (step S1
61: No) Next, referring to the cluster table 64, all the addresses of valid clusters included in the physical block with ID = i are acquired (step S163). And SSDC41
Obtains the size v for the total capacity of the acquired effective cluster (step S164), and if v <physical block size (step S165), the current physical block ID is NANDed.
It adds to the arrangement target block list (step S166). Further, the SSDC 41 adds the acquired cluster capacity v of the current physical block to the acquired cluster accumulated amount S, and updates the acquired cluster accumulated amount S (step S167).

If v <physical block size is not satisfied in step S165, or step S168
If the acquired cluster cumulative amount S has not reached the physical block size, the SSDC 41 increments i by 1 (step S162), and the procedure of steps S161 to S167 is the same as described above for the physical block having the next ID number. To run. In step S168,
Steps S161 to S16 are performed until the acquired cluster cumulative amount S reaches the physical block size.
Repeat step 7.

If the acquired cluster cumulative amount S reaches the physical block size in step S168, the SSDC 41 reads the data of all valid clusters for all physical blocks on the NAND organization target block list from the NAND memory 16 and stores them in the RAM 40. Write (step S169), and erase processing is performed on all physical blocks on the NAND rearrangement target block list (step S170).
It deletes from BT62 and adds to FBT60 (step S171). At that time, the erase count is incremented. The target of the erase operation performed in step S170 is step S17.
2 may be limited to a block to which data is written, and it is desirable to do so from the viewpoint of suppressing the number of block erases.

When an erasure error occurs, the physical block ID is added to the BBT 61, and the FBT 6
Delete from 0. Note that even if a physical block has an erasure error once, it can be erased normally without erasure if the erasure operation is performed again. From the viewpoint of preventing an unnecessary increase in the number of bad blocks. In the FBT 60 and ABT 62, an item “Number of occurrences of erasure error for each block” is provided for each block, and when a block erasure error occurs, this is incremented. In this case, it is desirable to register the block in the BBT 61. More preferably, in order to convert only physical blocks in which erasure errors continuously occur into bad blocks, the SSDC 41 provides an item of “number of erasure errors per block” instead of the “number of erasure errors per block”. When a block erase error occurs, this is incremented, and when erase is performed without error, it is reset to zero, and the "number of consecutive erase errors per block" exceeds a specified value. It is desirable to register the block in the BBT 61.

Then, the SSDC 41 acquires a new free block from the FBT 60, writes the data written in the RAM 40 to the acquired free block (step S172), and sets the physical block ID of the free block in which the data is written and the erase count of the block. AB
In addition to T62, the block ID of the block in which data is written is deleted from the FBT 60 (step S173). Furthermore, the SSDC 41 updates the cluster address, the physical block ID, and the page address in the physical block in the cluster table 64 so as to correspond to the current NAND arrangement (step S174). SSDC41 is the above NAN
The contents of the D organization process are reflected in the statistical information 65.

When a write error occurs in step S172, the physical block ID is added to the BBT 61, deleted from the FBT 60, and a free block is reacquired. Note that even if a physical block has a write error once, it can be written normally without a write error if the write operation is performed again. Therefore, from the viewpoint of preventing an unnecessary increase in the number of bad blocks. The FBT 60 and ABT 62 have an item “number of write errors per block” in each block so that if a block write error occurs, this is incremented. In this case, it is desirable to register the block in the BBT 61. More preferably, in order to convert only physical blocks in which write errors continuously occur into bad blocks, the SSDC 41 replaces “the number of write error occurrences for each block” with “
Create an item for `` Number of consecutive write errors for each block '', increment this if a block write error occurs, reset it to zero if there was no error in writing, It is desirable to register the block in the BBT 61 when the “number of errors” exceeds a predetermined value.

In the procedure of FIG. 26, NAND that prioritizes filling data into free blocks.
In step S164, v is obtained by subtracting the acquired cluster capacity from the physical block size. In step S165, it is determined whether v> 0. If v> 0, the process proceeds to step S168. If v> 0 is not satisfied, the process may be shifted to step S162 to perform NAND arrangement that prioritizes securing a free block.

Next, the deletion notification in the SSD 2 will be described with reference to FIG. The deletion notification is a command transmitted from the host device 3 to the external storage device when data is deleted by the OS 100 on the host device 3. As an example of deletion notification, for example, INCITS
Da described in ATA / ATAPI Command Set-2 (ACS-2)
ta Set Management Command (commonly known as a trim (TRIM) command). this is,
When data is deleted on the OS 100, a logical address area (LBA area) where the deleted data exists is changed to an LBA Range Entry consisting of a combination of the LBA and the number of sectors.
Is notified to the external storage device so that the area can be handled as a free area even on the external storage device. By the deletion notification, the SSD 2 can secure a new free block. The function of the trim command is Data Set Management.
In addition to the ment command, other commands such as an SCT Command Transport described in INCITS ACS-2 and other vendor-specific commands may be used. N if OS100 is an emergency OS
From the viewpoint of reducing writing to the AND memory, it is desirable that the emergency OS prohibits the issuance of the deletion notification. On the other hand, in the deletion notification process, only rewriting of the management information 45 at most occurs with respect to the NAND memory 16, and therefore the deletion notification may be permitted even in an emergency OS.

If the SSD 2 receives a deletion notification from the host device 3 (step S180), the SSD
C41 converts the LBA included in the deletion notification into LBA forward lookup according to the procedure shown in FIG. If the LBA included in the deletion notification is track management (step S181: Yes), the SSDC 41 adds the physical block ID to the FBT 60 and deletes it from the ABT 62 (step S184). On the other hand, if the LBA included in the deletion notification is cluster management (step S181: No), the SSDC 41 deletes all clusters corresponding to the physical block from the cluster table 64 (step S182), and the track table 63 stores the LBA. A valid value appropriate for the physical block ID corresponding to the track corresponding to (for example, FFF)
F) is entered (step S183), the physical block ID is added to the FBT 60, and the ABT 6
2 (step S184). In SSD2, a free block can be secured not only by NAND organizing but also by deletion notification processing.

Such a NAND arrangement usually ensures a sufficient number of free blocks for writing. If a sufficient number of free blocks for writing cannot be secured even by the NAND organizing, the NAND organizing failure flag of the statistical information 65 is set to 1, and the SSD 2 acquires a free block through the acquisition of the statistical information 65 by the host device 3. It is desirable to be able to notify the host device 3 that it has not been ensured. From the viewpoint of giving a grace period until the SSD 2 actually stops operating after the NAND rearrangement failure flag becomes 1.
(Number of free blocks secured by organizing NAND) <(Number of free blocks required for writing) + (Margin)
It is desirable to set the NAND rearrangement failure flag to 1 when the above condition is satisfied.

The NAND organizing is not only performed when a write request is received from the host device 3, but also when a predetermined time has elapsed since the last instruction was received from the host, or a command for shifting from the host device 3 to a standby, idle or sleep state. It may be executed when receiving AC, or AC
Through SCT Command Transport and other vendor commands described in S-2, NAN
The instruction to start D organization may be executed when the SSD 2 receives from the host device 3.
When the OS 100 is an emergency OS, from the viewpoint of reducing writing to the NAND memory, when a predetermined time has elapsed since the last instruction was received from the host device 3, the host device 3 is in a standby, idle, or sleep state. When a command to transition to is received,
It is desirable not to perform the NAND arrangement. Furthermore, when the OS 100 is an emergency OS, it is desirable that the emergency OS is prohibited from issuing an instruction to start NAND organizing from the viewpoint of reducing writing to the NAND memory 16.

(Error handling)
Next, error processing related to the NAND memory 16 in the SSD 2 will be described with reference to FIG. Various processes such as a process for a write request from the host device 3 and a NAND organizing process are normally performed as described above. However, if a write error occurs in a write operation (program operation) to the NAND memory 16, an erase to the NAND memory 16 is performed. When an erasure error occurs during an operation (erase operation), an ECC error (failure of error correction processing) may occur during a read operation on the NAND memory 16, and an exception process is required for these.

When any of the above errors occurs (step S190), the SSDC 41 adds the physical block in which the error has occurred to the BBT 61 (step S191), and deletes the physical block in which the error has occurred from the ABT 62 and the FBT 60 ( In step S192), the physical block in which the error has occurred is prevented from being accessed thereafter. At this time, the data of the physical block in which the error has occurred may be copied to another physical block. The SSDC 41 reflects the error processing in the statistical information 65.

In the above, an example of error processing has been described with respect to read processing, write processing, and NAND organizing processing. However, error processing is not limited to these examples, and all read processing, write processing, and erase processing for the NAND memory 16 are performed. Applicable.

(Control tool)
While the SSD 2 is used, the reliability of each block of the NAND memory 16 deteriorates, the number of bad blocks increases, and the sum of the number of free blocks and the number of active blocks decreases. Furthermore, if you use SSD2,
A sufficient number of free blocks for the writing process cannot be secured, which is the life of the SSD 2. In the following, the process of the control tool 200 when the life of the SSD 2 has been reached is shown.

When activated, the control tool 200 resides in the main memory 6 and monitors the statistical information 65 of the SSD 2. In order to constantly monitor the statistical information 65 of the SSD 2, the startup program of the control tool 200 is registered in the startup program of the normal OS 100A, and the normal OS 100A is read from the area 16D (or 20D) to the area 6A. It is desirable that the control tool 200 be read from the region 16B (or region 20B) at or shortly thereafter. For example, when the OS 100 is Windows (registered trademark), the control tool 200 is
For example, the control tool 200 is set as a resident program at startup by registering it in the Windows (registered trademark) startup menu, registering it as a service, or registering it in the Windows (registered trademark) registry. As a result, the control tool 200 can be automatically activated.

For example, as shown in FIG. 29, the control tool 200 is arranged at regular intervals (for example, every minute).
The statistical information 65 is acquired from the SSD 2. As a method for obtaining statistical information, for example, INCI
SMART (Self-Monitoring A), a memory self-diagnosis function described in TS ACS-2
nalysis and Reporting Technology) SMART READ DATA (B0h (D0h))
Alternatively, SCT Command Transport described in ACS-2 or other vendor-specific commands may be used.

FIG. 30 shows statistical information 65 (statistical information X01 to X19, X23, X23) managed by SSD2.
24 shows a table relating to 24). When using SMART, as shown in FIG. 30, for each component of the statistical information 65 (X01 to X19, X23, X24, etc.)
Although attribute ID (attribute ID) is assigned, it is needless to say that it may be assigned to only a part of these components. With regard to the constituent elements of the statistical information 65, SM is set as the best value after normalization.
Adopting AB, SMAL = SMAB * AMALR (0 ≦ AMALR <1) (SM
AL is an integer, and is converted from a decimal number to an integer by rounding, rounding up the decimal point, or rounding up the decimal point)
attribute value = SMAL + SMAB x (1-AMALR) x (RMAX-raw value) / RMAX
attribute Threshold = 30 (fixed value)
RMAX = upper limit of raw value of statistical information that can guarantee reliability
Based on the raw value = the raw value of the statistical information, the SSDC 41 calculates the attribute value of smart information (“Value” in FIG. 30) and transmits it to the control tool 200. The attribute Threshold is “Threshold” in FIG. 26, and the raw value is “Raw Data” in FIG.

The standardized best value SMAB may be any natural number. For example, SMAB = 100 may be adopted. The AMALR may be an arbitrary number satisfying 0 ≦ AMALLR <1, and for example, AMALR = 0.3 may be adopted. Also, RMAX, AMALR and SMAB
Can adopt different values for X01 to X19, X23, and X24. When SMAB = 100 and MALLR =; 0.3 is adopted, the best attribute value for the statistical information to be adopted is 100 (for example, 100 immediately after shipment), and gradually decreases as reliability deteriorates. When SSD2 can no longer guarantee reliability (
Attribute value is 3) when the raw value of the statistic is equal to or greater than RMAX)
A value of 0 or less will be reached. As a means for the host 3 to detect whether or not the attribute value exceeds the threshold, B0h / DAh SMA is a command described in ACS-2.
RT RETURN STATUS may be used to determine whether the Attribute Value exceeds the threshold from the output of the command.

For RMAX, for example, as shown in FIG. 31, it is desirable to derive the relationship between the raw value of statistical information and the failure rate of SSD2 to the development stage, and to adopt the raw value of statistical information when the failure rate exceeds an allowable value as RMAX. . For example, during the SSD2 development stage, a wear test is performed to verify whether the written data continues to be stored correctly for a certain time or more while repeating the write operation at a high temperature for a large number (for example, 100) of test SSD2 groups. At the same time, the statistical information may be continuously monitored, and the raw value of the statistical information at the time when the defect rate reaches a certain ratio may be adopted as RMAX. For example, the worn SSD 2 is allowed to stand for a long time at a high temperature, and then SS
If the temperature of D2 is lowered and a read operation is performed on SSD2, and the read data cannot be ECC-corrected (or if the data that cannot be ECC-corrected is more than a certain number), this is converted to SSD
2 is defined as a defect rate, and a value obtained by dividing the number of defects by the number of SSDs 2 that have undergone an equivalent test may be adopted as the defect rate. The raw value of statistical information whose statistical failure rate is significantly lower than the acceptable failure rate may be adopted as RMAX. Give RMAX some margin,
RMAX ′ with RMAX ′ = RMAX−margin may be adopted as RMAX.

“Worst” in FIG. 30 may be adopted as a specification for the control tool 200 to diagnose the life of the SSD 2. “Worst” is calculated by the SSDC 41 as the worst value of the attribute value. For example, in the case of X01 to X19 and X23, Worst is the minimum value of the attribute value after the SSD 2 is shipped (or manufactured), for example. Alternatively, the minimum value of the attribute value within a certain fixed time range may be adopted as the worst value as the worst, or the past is traced back to the past in which communication or processing was performed a certain number of times (a constant amount of data). The minimum value from the current to the present may be adopted as the worst value.

“Raw Data” (Raw Value) in FIG. 30 may be adopted as a specification for the control tool 200 to diagnose the life of the SSD 2. Raw values of statistical information (for example, X01 to X19, X23, X24) are transmitted as raw data from the SSD 2 to the control tool 200. In this case, the control tool 200 acquires RMAX by holding RMAX in the control tool 200, reading it separately from the SSD 2, or reading it from other storage devices, compares RMAX with Raw Data, and Raw Data> RMAX. Alternatively, when Raw Data ≧ RMAX, it is determined that the SSD 2 has reached the end of its life. For example, in the case of the NAND rearrangement failure flag, when this is 1, it is determined that the SSD 2 has reached the end of its life. For example, in the case of the total number of bad blocks, when this exceeds a predetermined value, it is determined that the SSD 2 has reached the end of its life. As raw data, it is not always necessary to output the raw value of statistical information. For example, Raw Da
The SSDC 41 may transmit to the control tool 200 as ta, and the determination may be performed by comparing RMAX with a value obtained by performing four arithmetic operations. In addition, the raw data encrypted statistical data
The SSDC 41 may transmit the data to the control tool 200, and the SSDC 41 may perform the determination by decrypting the data and comparing the decrypted data with the RMAX.

As described above, the control tool 200 determines whether the SSD 2 has reached the end of its life (SSD 2
Is determined to be abnormal or not, and it is determined that the SSD 2 has reached the end of its life (SS
(When it is determined that D2 is in an abnormal state), a process at the end of life described later (step S205)
). The statistical information 65 can take various forms other than the statistical information X01 to X19, X23, and X24, but the present invention is also applicable to these. X01 to X19
, X23, X24 and the defect rate have a positive correlation, but the present invention is also applicable to statistical information having a defect rate and a negative correlation. For example, the minimum temperature experienced by the SSD 2 after shipment. In that case, instead of RMAX, the lower limit value RMIN that can guarantee the reliability is adopted, and when the statistical information falls below RMIN, it may be determined that the SSD 2 has reached the end of its life.

In FIG. 29, when SMART is used, the control tool 200 acquires statistical information at regular time intervals (for example, every one minute) (step S200: Yes). Control tool 20
0 is B0h / D0h SMART R described in ACS-2 which is a statistical information acquisition command
EAD DATA is issued (step S201), data including statistical information is received from the SSD 2 (step S202), and the received data is diagnosed (step S203). The diagnostic method is as described above. In step S204, when the control tool 200 determines that the SSD 2 has reached the end of life (step S204: Yes), the control tool proceeds to the end of life process (step S205). Even if the SSD 2 has not reached the end of its service life, it is desirable to move to the processing of step S205 even when the statistical information exceeds a predetermined RMAX or indicates an abnormal value that cannot be a normal operation.

Information other than the statistical information 65 may be used to shift to the process at the end of life. For example, FIG.
2, the control tool 200 acquires (monitors) response information (see FIG. 12) received by the OS 100 from the SSD 2 from the OS 100 (step S210). If the error is a response (step S211), the control tool 200 It is determined that an abnormal state has been reached, and the process proceeds to the end of life process (step S212). The response to be monitored may be a response to any command, but for example, SS such as 61h WRITE FPDMA QUEUED or 35h WRITE DMA EXT described in ACS-2.
It is desirable from the viewpoint of reducing the load on the CPU 4 to monitor only the response to the write command to D2. In particular, Japanese Patent Application Laid-Open No. 2009-21 proposed by SSD2 as Patent Document 1.
In the case of an SSD adopting the invention of No. 7603, when the SSD 2 reaches the end of its life, the SSD 2
The response to the write command is returned with an error, so it is possible to determine the end of life without acquiring statistical information. Of course, the present invention can be applied even when the SSD 2 is not an SSD adopting the invention of Japanese Patent Laid-Open No. 2009-217603 presented as Patent Document 1.
When the SSD 2 is in a state of returning an error in response to a write command, when performing writing such as rewriting of the boot loader of the SSD 2 to be described later or writing in the emergency OS, a special write command is used in the ReadOnly mode state of Patent Document 1. (Eg ACS
It is desirable to configure the SSDC 41 so as not to return an error for the SCT Command Transport described in -2 and other vendor-specific commands, and to write to the SSD 2 using the special write command described above. . S
It is not necessary for writing to a storage device other than SD2. Alternatively, when the OS at normal time is an OS that uses only a write command (for example, 61h WRITE FPDMA QUEUED) as a write command, when the SSDC 41 reaches the ReadOnly mode of Patent Document 1, the write command (for example, 61h WRITE FPDMA QUEUED) is configured to return an error, and another write command (eg, 30h WRITE SECTOR (S)) is configured to return no error, and another write command is configured. (For example
30h WRITE SECTOR (S)) may be used to write the boot loader, emergency OS, etc. to SSD2.

Of course, the command to be monitored may be a command other than the write command. For example, B0H / D4H SMART EXECUTE OFF-LI described in ACS-2 as a command response
NE IMMEDIATE response (Outputs) and reports can be used, or 90h EXECUTE DEVICE DIAGNO
STIC responses may be used.

Even if a command response is an error, if the command is sent again, it may not be an error. In this case, SSD2 may not have reached its end of life, so if a reproducible command error occurs From the viewpoint of performing the process at the end of the lifetime only, it is desirable to perform the process at the end of the lifetime when a command error occurs a plurality of times. Furthermore, from the viewpoint of strictly determining the error reproducibility, it is desirable to perform the process at the end of life when a command error occurs continuously a plurality of times. Alternatively, as shown in FIG. 33, when a command response is returned as an error during command monitoring to the SSD 2 (steps S220 and S221: Yes), the control tool 200 or the OS 100 transmits the command to the SSD 2 again (command retry). (Step S222), and when the retried command has an error (Step S223:
Yes), a process at the end of the life may be performed (step S224).

(Processing at end of life)
Next, the process at the time of reaching the end of life (processing in the abnormal state) will be described. In the first embodiment,
A process at the end of the life when the normal-time OS and the emergency OS are already stored in the SSD 2 will be described. Normal OS 100A, emergency OS 100B, and boot loader 300
7 to 11, for example, the computer system 1 is written by the manufacturer of the computer system 1 on the SSD 2 before the shipment of the computer system 1, or the user can read the DVD-ROM or USB memory after the computer system 1 is shipped. It is written on the SSD 2 by performing installation using an installation disk such as or SSD, or by installing the installation image downloaded by the user after downloading the computer system 1 from the WEB. In the NAND memory 16,
As shown in FIG. 7, the boot loader 300 is in the area 16C, and the normal OS 100A is in the area 16C.
D, the emergency OS 100B is written in the area 16E, and LBAs are assigned to the areas 16C, 16D, and 16E, respectively, according to the management information 44 stored in the RAM 40. The area 16C has the LBA 16C, the area 16D has the LBA 16D, the area 16
Assume that L is assigned EBA16E. The aforementioned OS pointer information OSPT (pointer information indicating the LBA of the OS to be read) held in the boot loader 300
Similarly, LBA is assigned to the LBA assigned to OSPT.
This is called SPT. LBAOSPT is included in LBA16C.

The control tool 200 rewrites the boot loader 300 so that the emergency OS 100B is read into the area 6A on the main memory 6 of the host device 3 instead of the normal OS 100A when the computer system 1 is started next time. When the OS 100A is normally used by the CPU 4 as the OS 100, the host device 3 may perform a write operation on the SSD 2, thereby further shortening the life of the SSD 2, or the SSD 2
There is a possibility of destroying data written to or already written data. On the other hand, according to the present embodiment, the emergency OS 100B is not the main memory 6 but the normal OS 100A.
When reading to the upper area 6A and the CPU 4 is using the emergency OS 100B as an operating system, the host 3 is prohibited from performing a write operation on the SSD 2, so the data of the SSD 2 is destroyed or the SSD 2 is read. Before it becomes impossible, SS
It becomes possible to read the data of D2 and back up the user data stored in the SSD 2 to another storage medium.

For example, when the end-of-life process is called in step S205 of FIG. 29, as shown in FIG. 34, the control tool 200 rewrites the boot loader 300 and the next time the computer system 1 is started up, the emergency OS 100A is not used. The OS 100B is read to the area 6A on the main memory 6. For example, the control tool 200 is an LBA
LBA 16E is written as write data to OSPT. As a result, when the computer system 1 is started after the next time, the CPU 4 reads the OS pointer information OSPT and reads the emergency OS 100B by transmitting a read command to the LBA 16E which is the LBA indicated by the OS pointer information OSPT. Can do. Before and after the rewriting of the boot loader 300, the control tool 200 may display through the display 9 that “SSD has reached the end of its life.

In FIG. 34, only the boot loader 300 is rewritten as the process at the end of the life, but as shown in FIG. 35, the control tool 200 transmits a reset command to the computer system 1 after the boot loader rewrite in step S240. Alternatively, the computer system 1 may be restarted by transmitting a reset command to the normal OS (step S241).

As shown in FIG. 36, after rewriting the boot loader in step S250, through the display 9, "SSD has reached the end of life. Activate the emergency OS. Do you want to restart now?" Text display and OK button display are performed (step S2
51) When the OK button is pressed by, for example, the mouse 15 or the keyboard 14 (step S252: Yes), the computer system 1 may be restarted (step S253). Also, instead of displaying the OK button, “SS” is displayed on the command prompt screen.
D has reached the end of its life. Enable emergency OS. Do you want to restart now? y: Ye
The text “s, n: No” may be displayed, and the computer system 1 may be restarted when “y” and the enter key are input from the keyboard 14.

FIG. 37 shows an operation procedure when the computer system 1 is restarted. When the computer system 1 is restarted, the CPU 4 determines the LBA and LBA corresponding to the area 16C.
The boot loader 300 and the OS pointer information OSPT are read from the SSD 2 using the OSPT (step S260). Next, the CPU 4 performs a required boot process using the boot loader 300, analyzes the OS pointer information OSPT, and specifies the LBA indicated by the OS pointer information OSPT. Then, the CPU 4 transmits the read command for the specified LBA to the SSD 2, thereby setting the OS designated by the OS pointer information OSPT to the SSD.
Read from 2. Therefore, the LBA indicated by the OS pointer information OSPT is the normal time OS10.
When the area 16D which is the storage area of 0A is designated (step S261: Yes)
The normal time OA 100A is read from the area 16D and written to the area 6A on the main memory 6 (step S262), and the LBA indicated by the OS pointer information OSPT is the emergency OS 100B.
Is specified (step S261: No), the emergency OA 100B is read from the area 16E and written to the area 6A on the main memory 6 (
Step S263). As described above, when the OS pointer information OSPT of the boot loader 300 is rewritten so as to read the emergency OS 100B by the process at the end of life by the control tool 200, the emergency OA 100B is read from the area 16E and stored in the main memory 6. Is written in the area 6A.

(Backup function)
From the viewpoint of allowing the user to easily back up user data of the SSD 2 to another storage device, it is desirable to add a user data backup function to the emergency OS 100B. In a state where the SSD 2 is considered to have reached the end of its life, the data retention characteristics of the SSD 2 are considered to have deteriorated. Therefore, it is necessary to save the user data on the SSD 2 to another backup storage device as soon as possible. It is.

FIG. 38 is a diagram showing a configuration of the host device 3 when the emergency OS 100B has a backup function. The host device 3 has an interface 19 (SA in this embodiment).
A backup storage device (other SSD, hard disk drive, etc.) 150 is connected via a TA interface. The backup storage device 150 does not need to be installed when the computer system 1 is shipped. For example, when an SSD purchased separately by the user is used as the backup storage device 150, the SATA port of the SSD is connected to the motherboard via the SATA cable. 30 (see FIG. 13) and SSD2
Is preferably connected to the power source 32 via a power cable.

FIG. 39 shows an emergency OS 10 when a backup function is added to the emergency OS 100B.
An example of the start procedure of 0B is shown. The operations in steps S270 to S273 in FIG. 39 are the same as the operations in steps S260 to S263 in FIG. In FIG. 39, steps S274 to S276 are added to the startup procedure of the computer system 1 shown in FIG. After the emergency OS 100B is activated, the processes in and after step S274 are automatically performed when, for example, the user selects a backup function from the program menu of the emergency OS 100B via the keyboard 14 or the mouse 15, or when the emergency OS 100B is activated. To begin.
Before the backup process, it is desirable to display a message “Do you want to backup?” And an OK button on the display 9 so that the user can freely select the backup timing. When the OK button is selected with the mouse 15 or the keyboard 14,
Proceed to Yes in step S275. Alternatively, a message “Do you want to back up? Yes: Y, No: N” is displayed on the display 9 via the command prompt, and the Y button and the enter key are pressed from the keyboard 14 to proceed to Yes in step S275. Good. When the backup function is selected in this way (step S2
75: Yes), the emergency OS 100B starts backup processing.

As the contents of the backup processing, for example, the emergency OS 100B writes the data read from the SSD 2 to the same LBA (LBA on the backup storage device 150) as the LBA of the data read from the SSD 2 (LBA of the SSD 2) ( LBA backup). For example, the data of LBA = 0h on the SSD 2 is stored in the backup storage device 150.
The upper LBA = 0h is copied (step S276). In addition, LBA = 2 on SSD2
The data 34c5h is copied to LBA = 234c5h on the backup storage device 150. Copy data to SSD2, for example 60h READ FPDMA described in ACS-2
Send QUEUED or 25h READ DMA EXT command with LBA and sector length specified, SSD
2 receives the read data and writes it to the main memory 6, for example 61h described in ACS-2
WRITE FPDMA QUEUED or 35h WRITE DMA EXT is transmitted by specifying the LBA and sector length to the backup storage device 150, and the data written in the main memory 6 is transmitted to the backup storage device 150. The backup process may be performed for all LBA areas, but may be performed only for some LBA areas.

In this backup process, the emergency OS 100B may copy all the files of the SSD 2 to the backup storage device 150. In many OSs, a user does not access data by directly specifying an LBA, but accesses data using a file ID (file name). For example, as shown in FIG. 40, the SSD 2 stores a file management table 140 that associates file IDs with LBAs and sector lengths. The LBA is also assigned to the file management table 140 by the management information 44. The normal-time OS 100A converts the file ID received from the other software shown in FIG. 12 into an LBA based on the file management table 140 and transmits it to the SSD 2, or stores the LBA received from the SSD 2 in the file management table 140. Or convert it into a file ID and send it to other software. In the backup process, the emergency OS 100B reads the file management table 140 from the SSD 2, and reads the LBA data corresponding to each file ID in the file management table 140 (60h READ FPD
MA QUEUED, 25h READ DMA EXT command, etc.) are transmitted to SSD 2, read data is received from SSD 2 and written to main memory 6. Further, the emergency OS 100B reads a file management table (not shown) in the backup storage device 150 and still has a file ID.
The data written to the main memory 6 is written to the LBA to which no data is assigned, all the LBAs of all the files of the SSD 2 are acquired so that the written LBAs are associated with the file names, all the data of the acquired LBAs are read, and the read data Backup storage device 150
And the file management table (not shown) of the backup storage device 150 is rewritten so that the written LBA and the file ID are associated with each other. The backup process may be performed for all files, but may be performed for only some files.

Further, when the backup data is written to the backup storage device 150, the data read from the SSD 2 may be compressed and written. Also, read the management information of SSD2 including the file management table 140, acquire the information of the used area and file, create the ROM image for the data of SSD2 based on the acquired information, create The ROM image may be stored in another backup storage device 150.

In the above description, the backup storage device is a SATA device connected via the SATA interface, but other backup storage devices may be used. For example, as shown in FIG. 41, a USB storage device 151 such as a USB memory or a USB-compatible SSD may be adopted as a backup storage device. As shown in FIG. 42, a DVD-R or DVD is used as a backup storage device. A writable optical drive 152 such as RW or Blu-ray (registered trademark) Disc
As shown in FIG. 43, a network storage server 153 connected via the Internet or a LAN may be used as a backup storage device. The backup function can also be applied to other embodiments.

As shown in FIG. 7, the storage area 16E of the emergency OS 100B is associated with the LBA in the management information 44. On the other hand, in order to prevent the user from inadvertently rewriting the data in the area 16E, the emergency OS is recorded in the storage area 16E without allocating the LBA when the SSD 2 is shipped, and the life is reached. Control tool 20 during processing
0 is SCT Command Transport or a vendor-specific command SSD2
, The SSDC 41 may rewrite the management information 44 and assign an LBA to the area 16E. Alternatively, the LB of the area 16E to which the LBA is allocated
When the control tool 200 sends an SCT Command Transport including A Range and a vendor-specific command to the SSD 2, the SSDC 41 rewrites the management information 44 so that the area 16E is not allocated to the LBA, and the control tool When 200 sends SCT Command Transport or a vendor-specific command to SSD 2, SSDC 41 rewrites management information 44 and stores area 16E.
An LBA may be assigned to the.

Thus, according to the first embodiment, the control tool 200 determines whether or not the SSD 2 has reached the end of its life, whether or not the SSD 2 is in a normal state, and is determined that the SSD 2 has reached the end of its life. Or when it is determined that the SSD 2 is in an abnormal state, the boot loader 300 is rewritten so that an emergency OS that does not support the writing operation is started, and when the computer system 1 is restarted, the emergency OS Is activated to prohibit the write operation to the SSD 2 or to prevent the write operation to the SSD 2 from being performed explicitly, thereby preventing the reliability of the SSD 2 from being deteriorated. Prevents data being written from being destroyed and allows users to easily access user data.
Reading from D2 or backing up to another storage device is realized.

(Second Embodiment)
In the first embodiment, both the normal OS 100A and the emergency OS 100B are both SSD2
The case where the data is stored in the NAND memory 16 has been described. In the second embodiment, a case where the normal-time OS 100A is stored in the SSD 2 and the emergency OS 100B is not stored in the SSD 2 will be described. In the second embodiment, the control tool 200 sets the emergency OS 100B before and after the boot loader 300 rewriting process (see step S240 in FIG. 34 and FIG. 35) at the end of life process shown in step S224 in FIG. Then, the external storage device 20 (see FIG. 8) different from the SSD 2 is installed in the area 16E of the NAND memory 16 of the SSD 2. From the viewpoint of preventing the emergency OS data from being destroyed by inadvertently rewriting the area 16E in which the emergency OS of the SSD 2 is stored, the free area of the SSD 2 is reduced by securing the area 16E. From the viewpoint of prevention, it is desirable to adopt the second embodiment.

For example, as shown in FIG. 9, the control tool 200 downloads the emergency OS 100B data or the installation program from the WEB server 21 before and after rewriting the boot loader 300, and based on the downloaded data, the NAND memory of the SSD 2 The emergency OS 100B is installed in the 16 area 16E. Alternatively, the control tool 200 may display the emergency OS data or the address of the WEB server storing the installation program to the user through the display 9.

Alternatively, as illustrated in FIGS. 10 and 11, the control tool 200 may include a boot loader 300.
Before and after rewriting, the emergency OS 100B may be installed in the area 16E of the NAND memory 16 of the SSD 2 from the external storage medium (optical medium such as DVD-ROM, USB memory, SD card, SSD, etc.) 23, 24. Good. Alternatively, the control tool 20
0 is an external storage medium (optical medium such as a DVD-ROM, USB memory, etc.) in which the installation program of the emergency OS 100B is stored before and after the boot loader 300 is rewritten.
A message may be displayed to the user through the display 9 so as to set an SD card, SSD, etc.

Since the writing to the NAND memory 16 occurs when the emergency OS 100B is installed in the NAND memory 16, the data amount of the emergency OS is the same as that of the NAND memory 16 from the viewpoint of preventing the reliability deterioration and the data destruction of the NAND memory 16. It is desirable to be significantly smaller than the capacity.

(Third embodiment)
In the third embodiment, a process at the end of life when the normal-time OS 100A and the emergency OS 100B are stored in a non-volatile storage device 20 different from the SSD 2 will be described. FIG.
As shown in FIG. 5, when the normal OS 100A and the emergency OS 100B are stored in the non-volatile storage device 20 different from the SSD 2 and are not stored in the SSD 2, or one of them is the SS
The present invention is also applicable to the case where the other is stored in the nonvolatile storage device 20 while being stored in D2. In that case, the control tool 200 is not only an SSD2 boot loader,
It may be necessary to rewrite the boot loader of the nonvolatile storage device 20.

The non-volatile storage device 2 in which the normal time OS 100A and the emergency OS 100B are different from the SSD 2
When stored in 0, the control tool 200 rewrites the boot loader 300 stored in the nonvolatile storage device 20, and does not rewrite the boot loader of the SSD2.

When the normal OS 100A is stored in the SSD 2 and the emergency OS 100B is stored in the nonvolatile storage device 20, the control tool 200 uses the SSD 2 and the nonvolatile storage device 2.
It is desirable to rewrite both 0 boot loaders. When the computer system 1 is started with the nonvolatile storage device 20 removed from the host device 3, the SSD
From the viewpoint of preventing inadvertent write access to 2, it is desirable that the boot loader be configured so that the OS does not start up at normal times.

When the emergency OS 100B is stored in the SSD 2 and the normal OS 100A is stored in the nonvolatile storage device 20, it is desirable to rewrite the boot loaders of both the SSD 2 and the nonvolatile storage device 20. It is only necessary to rewrite the boot loader of the storage device 20. In this case, even when the computer system 1 is started in a state where the nonvolatile storage device 20 is removed from the host device 3, the boot loader 300 of the SSD 2 is read and the emergency is read from the area 16E of the NAND memory 16 of the SSD 2. You can start the OS.

(Fourth embodiment)
In the fourth embodiment, a case where the normal-time OS 100A is installed in the SSD 2 but the emergency OS is not installed in the SSD 2 will be described. From the viewpoint of suppressing access to the SSD 2 whose reliability has deteriorated as much as possible, the activation of the emergency OS 100B is performed by the SSD 2
It is desirable to perform from a different storage device. The control tool 200 of the present embodiment has a function of creating an emergency startup boot disk in which an emergency OS is installed during the life end process.

Various non-volatile storage devices such as an optical medium such as a USB memory, an SD card, a CD / DVD, an SSD, and a hard disk drive can be adopted as an emergency startup disk. In this embodiment, among these, USB is used as a startup disk for emergency startup.
A case where a memory is employed will be described.

Data (image data) including emergency OS data for creating a startup disk for emergency startup is, for example, SSD2, other SSD, USB memory, SD card,
It may be stored in an optical medium such as a DVD-ROM drive or a storage medium of a WEB server. In the present embodiment, a case where the SSD 2 is adopted as a storage medium for storing image data for emergency OS installation will be introduced. In other words, SSD with degraded reliability
2 itself stores installation source image data.

At the time of installation of the emergency OS, image data is read from the SSD 2, but once installed, the image data is not read. Further, it is desirable that the control tool 200 has a function that allows the user to arbitrarily create a startup disk for emergency startup from a stage before the SSD 2 reaches the end of its life.

FIG. 44 shows a conceptual diagram of data movement when creating an emergency start disk. FIG. 45 shows an operation procedure of the control tool 200 when an emergency start disk is created. The control tool 200 sends a US to the USB controller 13 of the host device 3 at the start of the end of life process.
Check if the B memory is connected. If not, connect the display 9 with a message stating "Create an emergency OS startup USB memory. Please connect the USB memory." It is desirable to display it to the user.

As shown in FIG. 44, when the USB memory 24 is connected, the control tool 200
The emergency OS data is extracted from the installation image data 400 stored in the area 16Q of the NAND memory 16 of the SSD 2 (if the emergency OS data is compressed / encrypted, it is decrypted), and the USB memory 24 Is copied (installed) into the area 24R (step S280). Next, the control tool 200 refers to the storage area 24R of the emergency OS 100B so that the emergency OS 100B installed in the USB memory 24 is read when the boot loader 310 stored in the USB memory 24 is read. The boot loader 310 is rewritten (step S281). Specifically, the control tool 20
0 is stored in the storage area 24 in the OS pointer information OSPT 311 of the boot loader 310, for example.
Write LBA corresponding to R.

When both the USB memory 24 and the SSD 2 are connected to the host device 3, the boot loader 310 and the boot loader 310 are rewritten so that the boot loader 310 of the USB memory 24 is preferentially started, or the setting of the BIOS-ROM 11 is changed. It is desirable to be performed (step S282). Note that step S282 need not be executed.

When the USB memory 24 is not connected to the host device 3, the normal time OS is started from the SSD 2.
From the viewpoint of preventing inadvertent write access to the SSD 2 due to the activation of the 100A, it is desirable to rewrite the boot loader 300 of the SSD 2 so that the normal-time OS 100A is not activated from the SSD 2 in step S282. For example, by writing an LBA other than the storage area 16D of the normal OS 100A or writing an invalid LBA to the OS pointer information OSPT301 of the boot loader 300, the normal OS 100A is loaded even if the boot loader 300 of the SSD 2 is read. Can be prevented. Alternatively, the data of the OS 100A during normal times may be rewritten.

In this way, when the SSD 2 reaches the end of its life or when the SSD 2 is in an abnormal state, the SSD 2 data can be read or the SSD 2 data can be read from other data while suppressing the deterioration of the SSD 2 reliability or the SSD 2 data destruction. O that can be backed up to non-volatile storage
A startup disk for starting up S can be created.

In addition, as shown in FIG. 46, MS-DOS (trademark) or Lin as the emergency OS 100B.
An emergency tool 210 that employs an OS such as ux (registered trademark) or Windows (registered trademark) PE (trademark) and installs the emergency OS in the USB memory 24 and has a function of backing up the data of the SSD 2 at the same time. It may be installed in the area 24S of the USB memory 24 so that the emergency tool 210 can be executed from the emergency OS 100B. The emergency tool 210 preferably has a backup function similar to that described in the first embodiment.

FIG. 47 shows the operation when the host apparatus 3 is activated. When the host device 3 starts up, U
The emergency OS 100B is read from the SB memory 24 and written to the main memory 6, whereby the emergency OS 100B is activated from the USB memory 24 (step S290). Next, the emergency tool 210 is read from the USB memory 24 and written to the main memory 6, whereby the emergency tool 210 is activated from the USB memory 24 (step S291). It is desirable that the emergency tool 210 is automatically started after the emergency OS 100B is started, such as by registering the emergency tool 210 in the startup of the emergency OS 100B.

As shown in FIG. 48, the emergency OS 100B displays a backup menu as one of menu items selectable by the user, a message “Do you want to backup?” And an OK button via the display 9. Or "Do you want to backup?"
It is desirable that the user arbitrarily activates the backup function by displaying the message and making the keyboard 14 ready for input (step S292).
Note that the emergency OS 100B may automatically start backup.

When the backup function activation is selected by the keyboard 14 or the mouse 15 (step S293), the emergency tool 210 is activated. The emergency tool 210 copies the SSD2 data to the backup storage device 150 (step S293). As a backup method, a method similar to that described in the first embodiment may be employed. For example, LBA unit backup or file unit backup may be employed.

(Fifth embodiment)
According to the above-described embodiment, it is possible to easily read out user data from the SSD 2 or back up to another storage device after suppressing deterioration in reliability of the SSD 2 and data destruction of the SSD 2. The fifth embodiment further provides a method for suppressing deterioration in reliability of the SSD 2. The SSD 2 may be equipped with a function of performing a refresh process in the background in order to repair data corruption due to aging degradation or read disturb. In this function, the block of the NAND memory 16 is periodically read, and the data of the block with a large number of data errors is written to another block. This
Although it is possible to reduce the effects of aging and read disturb, there is also a problem that reliability of the SSD 2 is accelerated because unnecessary blocks are erased and written.

In this embodiment, the control tool 200 or the emergency OS 100B uses the refresh control command (SCT Command Transport described in ACS-2, other vendor-specific commands, and other commands) to stop performing the refresh. Command SSDC 41. In response to the refresh control command, the SSDC 41 stops the refresh process or sets a long refresh execution interval (for example, 1 minute) (for example, 2 minutes).
When the SSDC 41 is set to have a long refresh execution interval, it is desirable to explicitly specify the refresh execution interval in the refresh control command.

FIG. 49 shows an operation when the control tool 200 issues a refresh control command. In this case, the control tool 200 may issue a refresh control command during the end-of-life process shown in step S205 of FIG. The control tool 200 is shown in FIG.
4 is rewritten (step S300), and then a refresh control command is transmitted to the SSD 2 (step S301).

FIG. 50 shows an operation when the emergency OS 100B issues a refresh control command. In this case, the CPU 4 starts up the SSD as shown in FIG.
The boot loader 300 including the OS pointer information OSPT is read from the second NAND memory 16 (step S310), and the LBA indicated by the OS pointer information OSPT is specified. Then, the CPU 4 transmits a read command for the specified LBA to the SSD 2, whereby the OS 4
The OS specified by the pointer information OSPT is read from the SSD 2. OS pointer information OSP
When the LBA indicated by T designates the area 16D which is the storage area of the normal time OS 100A (step S311: Yes), the normal time OA 100A is read from the area 16D and written to the area 6A on the main memory 6 ( In step S312), when the LBA indicated by the OS pointer information OSPT designates the area 16E that is the storage area of the emergency OS 100B (step S312).
In step S311: No), the emergency OA 100B is read from the area 16E and written to the area 6A on the main memory 6 (step S313). When the emergency OA 100B is activated, the emergency OA 100B transmits a refresh control command to the SSD 2 (
Step S314).

As described above, in the fifth embodiment, the control tool controls the background writing process in the SSD 2 such as the refresh process in the prohibition direction during the process at the end of the life. It is possible to suppress the deterioration of sex.

(Sixth embodiment)
In the first embodiment, the control tool 200 periodically acquires statistical information as shown in FIG. 29, and when the SSD 2 reaches the end of its life or immediately before the SSD 2 reaches the end of its life, Went. The control tool 200 may predict the life of the SSD 2 based on the acquired statistical information and notify the user through the display 9, which will be described below.

When the control tool 200 periodically acquires statistical information in accordance with the processing procedure shown in FIG. 29, the acquired data is stored in the main memory 6 in the format shown in FIG. I will add. The statistical information time series data may be periodically backed up in a nonvolatile storage device such as SSD2. Further, the statistical information time-series data may be deleted from the old data every time the latest data is added.

Further, the control tool 200 may display the statistical information time-series data in the main memory 6 in a graph for the user via the display 9 in a display format as shown in FIG.

In the present embodiment, SSD 2 life prediction is performed based on the statistical information time-series data. As shown in FIG. 53, the control tool 200 sets the Attribute Value of a certain Attribute ID as a variable Y, sets the time as a variable X, and is the current time from the time A that is a predetermined time T before the current time. Using all the data (X, Y) in the period up to time C, the fitting function Y =
Find f (X). That is, the predicted value from X to Y = f (X)) is obtained using f). There are various methods for deriving f. For example, f (X) = aX + b using parameter a and parameter b, and a minimum of two for all data of (X, Y) from time A to time C. You may determine f by calculating | requiring a and b using a multiplication method.

Then, f ⁻¹ (Y), which is an inverse function of f (X), is obtained. When f (X) = aX + b, f
⁻¹ (Y) = (Y · b) / a is obtained. The predicted lifetime arrival time of SSD2 is f ⁻¹ (Y = Th
reshold). Note that the fitting function X = g (Y) is obtained for all the data (X, Y) from time A to time C, and the predicted life arrival time of the SSD 2 is g (Y = Threshol).
d). Further, f (X) and g (Y) may be fitted to a function other than a linear function such as a quadratic function.

In this embodiment, the life is predicted using SMART Attribute Value (= Y) and Threshold, but f (X) and g (Y) are obtained by using Raw Value as raw data as Y, and the expected life is reached. The time is f ⁻¹ (Y = RMAX) or g (Y = RMAX), or f ⁻¹ (Y = RM).
IN) or g (Y = RMIN). Further, the lifetime may be predicted based on statistical information obtained by using means other than SMART information.

The control tool 200 notifies the user of the predicted life arrival time obtained in this way through the display 9. As a notification method, for example, “predicted life arrival time: 1999 0”
The text may be displayed as "September 09" or as shown in Fig. 54, "SSD life is less than 30 days. SSD data is backed up immediately and a new SS
Please replace it with D. May be displayed. Or, when the remaining life of the SSD reaches a predetermined number of days, the color of the icon of the control tool 200 is changed, etc.
You may change the color of the icon displayed on a display.

(Seventh embodiment)
In the first embodiment, as shown in FIG. 38, when the normal OS 100A and the emergency OS 100B are stored in the NAND memory 16 of the SSD 2, the data of the SSD 2 is backed up to the backup storage device 150. Explained. The control tool 200 rewrites the boot loader 300 as a process at the end of life (step S205 in FIG. 29) and rewrites the boot loader 300 (step S230 in FIG. 34).
When adopting BA unit backup, disconnect SSD2 from host device 3 after that,
In order for the OS 100A to start normally when the computer system 1 is powered on with the backup storage device 150 connected to the host device 3,
It is desirable that the boot loader copied to the backup storage device 150 by the backup process is restored to the state of the boot loader 300 of the SSD 2 before the end of life process. In the present embodiment, a method for rewriting the boot loader of the backup storage device 150 during the backup operation will be described.

FIG. 55 shows functional configurations of the computer system 1 and the backup storage device 150 before and after the backup operation. The boot loader restoration information 350 for returning the boot loader 300 to the state before rewriting by the control tool 200 is stored in the restoration boot loader area 16V of the NAND memory 16 of the SSD2. The area 16V may be assigned by the control tool 200 at the time of end of life processing, may be assigned when the control tool 200 is activated, or may be assigned when the control tool 200 is installed in the SSD 2. An LBA is allocated to the allocated area 16V by the management information 45 (see FIG. 18) of the SSD 2.

FIG. 56 shows the operation procedure of the process at the end of the life in the present embodiment. In the life end process, the backup storage device 150 may not be connected to the host device 3. The control tool 200 writes the backup information of the boot loader 300, that is, the boot loader restoration information 350 in the restoration boot loader area 16V during the process at the end of the life, that is, before rewriting the boot loader 300 (step S320). As information to be written in the area 16V, for example, data (image) of the boot loader 300 stored in the area 16C may be copied as it is, or rewrite difference information of the boot loader may be recorded.

When the difference information is recorded in the area 16V, a rewrite difference log in which the correspondence between the pre-rewrite data and the rewritten LBA as shown in FIG. 57 may be employed as the difference information. When adopting the rewrite difference log, the control tool 200 uses the region 1
Of the boot loader 300 stored in 6C, the rewritten LBA is written to “rewritten LBA” of the rewrite difference log, and the data before rewriting of the LBA is written to “data before rewriting” of the rewrite difference log. For example, if the logical sector that is the smallest unit of LBA is 512 bytes, 1 of “data before rewriting” of the rewriting difference log
The element may be 512-byte data, or may be data other than 512 bytes obtained by compressing or reversibly converting data before rewriting. When the boot loader 300 is restored from the new boot loader to the old boot loader using the rewrite difference log, the area 16C
On the other hand, it is possible to restore the old boot loader by writing “data before rewriting” to the LBA indicated by “rewritten LBA” in the rewriting difference log.

After that, the control tool 200 rewrites the boot loader 300, and when the computer system 1 is started next time, as in the case described in the first embodiment, the normal time OS 1
Instead of 00A, the emergency OS 100B is read out to the main memory 6 (step S
321).

In order to facilitate the search of the restoration boot loader area 16V during a backup operation described later, the control tool 200 stores the restoration boot loader area 16V in the boot loader area 16C.
Is preferably written (step S322). It is not always necessary to write the first LBA of the boot loader area for restoration 16V in the boot loader area 16C. A specific data pattern is written at the beginning of the area 16V, and the area is obtained by searching for this specific data pattern at the time of backup described later. 16V may be specified, or the region 16V may be fixedly associated with a predetermined specific LBA.
The area 16V may be specified by accessing the specific LBA at the time of backup described later, or the area 16V may be specified by other methods.

After step S321, the computer system 1 may be restarted as in the first embodiment, or an SSD2 refresh control command may be transmitted as in the fifth embodiment. The restoration boot loader area 16V may be secured in a storage device other than the SSD 2.

FIG. 58 shows a backup operation by the emergency OS 100B. When the backup storage device 150 is not connected to the host device 3 at the time of backup, the user connects the backup storage device 150 to the host device 3. At that time, the control tool 200
May display a message “Please connect backup device” on the display 9 to the user.

Emergency OS loaded from area 16E of NAND memory 16 to area 6A of main memory 6
In the same manner as in the first embodiment, the SSD2 data is copied to the backup storage device 150 (step S330). For example, when the LBA unit backup is adopted as a backup method and the entire LBA area of the SSD 2 is copied to the backup storage device 150, the normal-time OS 100A stored in the area 16D uses the area 150D of the backup storage device 150. The other user data copied to the area 16U is copied to the area 150U. The boot loader 300 stored in the boot loader area 16C may be copied to the area 100C of the backup storage device 150 or may not be copied. The emergency OS 100B stored in the area 16E may be copied to the area 150E of the backup storage device 150 or may not be copied. Further, the boot loader restoration information 350 stored in the restoration boot loader area 16V may not be copied to the backup storage device 150.

The emergency OS 100B creates a boot loader 320 to be stored in the backup storage device 150 based on the boot loader restoration information 350 and the data of the boot loader 300, and writes the created boot loader 320 in the area 150C of the backup storage device 150. If the boot loader 320 is loaded when the computer system 1 is started next time or later, the normal time OS 100A is loaded into the area 6A of the main memory 6 (step S).
331).

In the boot loader backup process in step S320 of FIG.
When the data (image) of the boot loader 300 stored in is restored to the restoration boot loader area 16V as it is, the boot loader restoration information 350 in the restoration boot loader area 16V is directly used as the backup storage device 15 in step S331 of FIG.
You may copy to 0 area | region 150C.

Also, in the boot loader backup process in step S320 of FIG. 56, when rewrite difference information of the boot loader area 16C is recorded in the restoration boot loader area 16V, that is, the boot loader area 16C is rewritten from the old boot loader data to the new boot loader data. 58, when the difference information for rewriting the new and old boot loader data at the time is recorded in the restoration boot loader area 16V, the emergency OS 100B determines that step S331 in FIG.
, The boot loader area 16C data (new boot loader data) and the boot loader restoration information 350, which is the difference data stored in the restoration boot loader area 16V, are read into the main memory 6, and the new boot loader data is read based on the boot loader restoration information 350. Is restored to the old boot loader data, and the restored old boot loader data is stored in the backup storage device 15.
Write to 0 area 150C.

After performing the above backup processing, the SSD 2 that has reached the end of its life is detached from the host device 3 by removing the SSD 2 from the IF 0, and the backup storage device 150 is stored in the IF 1.
When the computer system 1 is started in a state where the backup storage device 150 is connected to the host device 3, the host device 3 reads the boot loader 320 of the backup storage device 150, and the host device 3 is read based on the information of the boot loader 320. Loads the area 150D of the backup storage device 150 into the area 6A of the main memory 6, thereby starting up the normal-time OS. When the backup storage device 150 is compatible with the interface IF0, the backup storage device 150 may be replaced with the SSD 2, and the backup storage device 150 may be connected to the interface IF0. If the backup storage device 150 does not support the interface IF0, the backup storage device 150 may be replaced with the SSD 2, and the backup storage device 150 may be connected to the interface IF0 via the interface conversion device.

Thus, even when the SSD 2 reaches the end of its life, the computer system 1
Can restore user data and normal-time OS stored in SSD2 to the backup storage device, and the user can use the SS without performing extra settings or reinstalling the normal-time OS.
D2 can be replaced with a backup storage device 150, and the backup storage device 150 can be used as a system drive instead of SSD2.

(Eighth embodiment)
In the present embodiment, when the host device connected to the SSD 2 is started when the SSD 2 returns from the abnormal state (life reached state) to the normal state (health state), the normal time OS is started instead of the emergency OS. Like that.

As statistical information, for example, the current temperature X20 and the maximum temperature X21 indicate that the larger the numerical value is, the lower the reliability is. When adopting parameters having characteristics that can be recovered, for those statistical information, for example, RMAX = 85 ° C. is adopted as RMAX,
Statistical information value> RMAX
Or statistical information value ≧ RMAX
When a condition that results in a temperature outside the operation guarantee is satisfied, the control tool 200 sets the boot loader 3
By rewriting 00, the emergency OS 100B is read to the main memory 6 instead of the normal OS 100A the next time the computer system 1 is activated.

The emergency OS 100B monitors the value of statistical information after startup,
When the statistical information value ≦ RMAX-MAX margin or the statistical information value <RMAX-MAX margin and the statistical information returns to the normal value again, the boot loader 300 is rewritten to start the computer system 1 from the next time. In some cases, a boot loader restoration process is executed so that not the emergency OS 100B but the normal OS 100A is read into the main memory 6.

The MAX margin is a value greater than or equal to zero. However, in order to prevent frequent rewriting of the boot loader 300, it is desirable that the MAX margin be a value greater than zero.
When the statistical information is the current temperature or the maximum temperature, for example, MAX margin = 5 ° C. When using SMART information for statistical information acquisition and condition judgment, Attribute Value and Thresho
ld may be used, or Raw Value and RMAX may be used. In addition, normal OS
When the statistical information returns from the abnormal state to the normal state during startup, the control tool 200 may perform the boot loader restoration process.

As the statistical information, the smaller the numerical value, such as the current temperature X20 and the minimum temperature X22, the lower the reliability, and even if the numerical value decreases to a value that adversely affects the reliability, it is restored to a normal value again. When adopting a parameter having a characteristic that can be used, RMIN = −10 ° C. is adopted as RMIN,
Statistical information value <RMIN
Or statistical value ≤ RMIN
For example, the control tool 200 rewrites the boot loader 300 when the condition that the temperature is not guaranteed, for example, is satisfied, so that when the computer system 1 is started next time, the emergency OS 100B is not the main memory but the emergency OS 100B. To be read.

The emergency OS 100B monitors the value of statistical information after startup,
When the statistical information value ≧ RMIN + MIN margin or the statistical information value> RMIN + MIN margin and the statistical information returns to the normal value again, the boot loader 300 is rewritten, and the next time the computer system 1 is started, the emergency A boot loader restoration process is executed so that not the OS 100B but the normal-time OS 100A is read into the main memory 6.

The MIN margin is a value greater than or equal to zero. However, in order to prevent frequent rewriting of the boot loader 300, it is desirable that the MIN margin be greater than zero.
When the statistical information is the current temperature or the minimum temperature, for example, MIN margin = 5 ° C. When SMART information is used for statistical information acquisition and condition judgment, Attribute Value and T
hreshold may be used, or Raw Value and RMIN may be used.

Next, details of the operation of the control tool 200 in the life end process will be described. When returning from the abnormal state (life reaching state) to the normal state (healthy state), it is desirable that the boot loader 300 is restored to the boot loader before being rewritten in the life reaching process by the boot loader restoring process. FIG. 59 shows a functional configuration of the computer system 1 before and after the boot loader restoration process. The boot loader restoration information 350 for returning the boot loader 300 to the state before rewriting by the control tool 200 is stored in the restoration boot loader area 16V of the NAND memory 16 of the SSD2. The area 16V may be assigned by the control tool 200 at the time of end of life processing, may be assigned when the control tool 200 is activated, or may be assigned when the control tool 200 is installed in the SSD 2. An LBA is allocated to the allocated area 16V by the management information 45 (see FIG. 18) of the SSD 2. Further, the area 16V of the present embodiment may be used for boot loader restoration at the time of backup as the same as the area 16V shown in FIG. 55, or may be different from the area 16V shown in FIG. Good.

The procedure of the process at the end of the lifetime is the same as that shown in FIG. That is, control tool 2
00 writes the backup information of the boot loader 300, that is, the boot loader restoration information 350, in the restoration boot loader area 16V during the life end process (step S320).
). As information to be written in the area 16V, for example, data (image) of the boot loader 300 stored in the area 16C may be copied as it is, or rewrite difference information of the boot loader may be recorded. Thereafter, the control tool 200 rewrites the boot loader 300 so that the emergency OS 100B is read into the main memory 6 instead of the normal OS 100A when the computer system 1 is started up next time (step S321).

Furthermore, in order to facilitate the retrieval of the restoration boot loader area 16V during a backup operation described later, it is desirable that the control tool 200 writes the first LBA of the restoration boot loader area 16V in the boot loader area 16C (step S322). ). It is not always necessary to write the first LBA of the boot loader area for restoration 16V in the boot loader area 16C. A specific data pattern is written at the beginning of the area 16V, and the area is obtained by searching for this specific data pattern at the time of backup described later. 16V may be specified, or the area 16V may be fixedly associated with a predetermined specific LBA, and the area 16V may be specified by accessing the specific LBA during backup described later. The region 16V may be specified by other methods.

After step S321, the computer system 1 may be restarted as in the first embodiment, or an SSD2 refresh control command may be transmitted as in the fifth embodiment. The restoration boot loader area 16V may be secured in a storage device other than the SSD 2.

FIG. 60 shows boot loader restoration processing by the emergency OS 100B. After the end of life processing (after abnormal processing), when the computer system 1 is activated using the emergency OS, the emergency OS 100B monitors the statistical information using, for example, the above-mentioned SMART READ DATA, and the statistical information It is determined whether or not has returned to a normal value (step S340). When the statistical information returns to the normal value based on the above-described determination criteria (step S340: Yes), the emergency OS 100B sets the boot loader restoration information 35 stored in the restoration boot loader area 16V.
Based on 0 and the data of the boot loader 300 stored in the boot loader area 16C, a boot loader for processing so that the normal time OS 100A is loaded into the area 6A of the main memory 6 is created, and the created boot loader is written in the boot loader area 16C. (Step S341).
Thereby, when the boot loader 300 is loaded when the computer system 1 is started next time or later, the normal-time OS 100A is loaded into the area 6A of the main memory 6.

In the boot loader backup process in step S320 of FIG.
When the data (image) of the boot loader 300 stored in is restored to the restoration boot loader area 16V as it is, the boot loader restoration information 350 in the restoration boot loader area 16V is directly used as the backup storage device 15 in step S341 in FIG.
You may copy to 0 area | region 150C.

Also, in the boot loader backup process in step S320 of FIG. 56, when rewrite difference information of the boot loader area 16C is recorded in the restoration boot loader area 16V, that is, the boot loader area 16C is rewritten from the old boot loader data to the new boot loader data. When the difference information for rewriting the new and old boot loader data at the time is recorded in the restoration boot loader area 16V, the emergency OS 100B determines that step S341 in FIG.
, The boot loader area 16C data (new boot loader data) and the boot loader restoration information 350, which is the difference data stored in the restoration boot loader area 16V, are read into the main memory 6, and the new boot loader data is read based on the boot loader restoration information 350. Is restored to the old boot loader data, and the restored old boot loader data is stored in the backup storage device 15.
Write to 0 area 150C.

As described above, in this embodiment, as shown in FIG. 61, when the statistical information changes from the normal state to the abnormal state, the abnormal time arrival process is performed so that the abnormal time OS is activated, and the statistical information is When the abnormal state returns to the normal state, a boot loader restoration process that operates so as to start the OS at the normal time is executed.

In this way, even if the SSD 2 temporarily becomes abnormal, after the SSD 2 returns to the normal state (healthy state), the computer system 1 starts the OS at the normal time, and the user SSD without extra configuration or re-installing OS during normal operation
2 can be handled in the same way as before the process at the end of life.

Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 computer system, 3 host device, 6 main memory, 16 NAND memory,
20 Nonvolatile storage device, 100A Normal OS, 100B Emergency OS, 200 Control tool, 210 Emergency tool, 300 Boot loader, 350 Boot loader restoration information.

Claims (14)

A non-volatile semiconductor memory comprising a memory cell for storing data, and capable of electrically erasing data recorded in the memory cell using a plurality of the memory cells as a first unit;
Volatile semiconductor memory,
A controller circuit;
A temperature sensor;
An interface circuit;
A semiconductor memory device comprising:
A host device that transmits write and read commands to the semiconductor memory device;
An information recording system comprising:
The nonvolatile semiconductor memory and the volatile semiconductor memory can each record first information that designates a physical address of the nonvolatile semiconductor memory corresponding to logical address information received from the host device via the interface circuit. Configured,
When the controller circuit receives a write command from the host device via the interface circuit, it generates a correction code using the data received from the host device,
When the data and the correction code are recorded in the nonvolatile semiconductor memory, and when a read command is received from the host device via the interface circuit, the nonvolatile semiconductor memory uses the first information. Based on the read data and the corresponding correction code, the read data is configured to be correctable,
The nonvolatile semiconductor memory further includes second information based on a total amount of write data received in response to a write command received from the host device,
Third information based on the total amount of data read from the nonvolatile semiconductor memory in response to a read command received from the host device;
The controller reads the data read from the non-volatile semiconductor memory, using the corresponding correction code, fourth information regarding the number of data that could not be corrected;
Fifth information indicating, in the first unit, information corresponding to the number of memory cells determined to be unable to write data in the nonvolatile semiconductor memory;
Sixth information according to the number of the memory cells determined to be able to write data in the nonvolatile semiconductor memory;
7th information based on the temperature measured using the temperature sensor, and configured to store,
The host device includes: first status information of the nonvolatile semiconductor memory based on the second information or third information; second status information of the nonvolatile semiconductor memory based on the fourth information or fifth information; Third status information of the nonvolatile semiconductor memory based on seventh information is configured to be displayed on a display device connected to the host device,
The semiconductor memory device is configured to erase the data recorded in the corresponding physical address in the first unit and change the sixth information based on the command and logical address information received from the host device. An information recording system characterized by that. The information recording according to claim 1, wherein a color of an icon included in the first status information is changed when specific information of the second information or the third information exceeds a corresponding threshold value. system. 2. The information recording according to claim 1, wherein the second status information indicates a remaining life of the semiconductor memory device, and displays a warning screen on the display device when the remaining life falls below a predetermined value. system. 5. The information recording system according to claim 3, wherein the warning screen includes a message prompting backup of data stored in the semiconductor storage device. The information recording system according to any one of claims 1 to 4, wherein each of the second to seventh information includes an attribute ID. 6. The information recording system according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory. The information recording system according to claim 6, wherein 2-bit data can be stored in the memory cell. The information recording system according to claim 6, wherein 3-bit data can be stored in the memory cell. 9. The information recording system according to claim 1, wherein the volatile semiconductor memory is a DRAM (Dynamic Random Access Memory) and functions as a buffer between the interface circuit and the nonvolatile semiconductor memory. . The information recording system according to claim 1, wherein a capacity of the semiconductor memory device is larger than a data capacity accessible from the host device. 11. The host device according to claim 1, wherein the host device further includes a memory, and is configured to record at least one of the second to seventh information acquired from the semiconductor storage device in the memory. The information recording system described in one. The information recording system according to claim 11, wherein the host device is configured to be able to display time series data of the at least one information recorded in the memory on the display device. The information recording system according to claim 11 or 12, wherein the host device further includes a nonvolatile memory, and is configured to back up the at least one information recorded in the memory to the nonvolatile memory. 14. The information recording system according to claim 13, wherein the host device is configured to erase old data among the data recorded in the nonvolatile manner when backing up to the nonvolatile memory.

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