JP2016154194A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the formation of a side wall insulation film on a side face of a peripheral gate electrode from being disabled by making an etchant for removing a silicon oxide film within a memory cell area reach a peripheral circuit area, to prevent no LDD diffusion layer from being residual after implementation of ion implantation for forming a source/drain diffusion layer, and to prevent the provision of the LDD diffusion layer in a peripheral transistor from being disabled as a result.SOLUTION: A semiconductor device 1 comprises: a semiconductor substrate 2 in which a memory cell area MC and a peripheral circuit area PA are defined; a plurality of first distribution lines (bit lines BL and dummy bit lines DBL) disposed within the memory cell area MC and extending in an (x) direction; and a guard line GL which is provided for each of the plurality of first distribution lines and disposed within the memory cell area MC while including a plurality of projections P each having an end E2 that faces one end E1 of the first distribution line in the (x) direction, and extends in a (y) direction.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which an LDD diffusion layer is provided in a transistor in a peripheral circuit region and a manufacturing method thereof.

  A peripheral transistor provided in a peripheral circuit region of a semiconductor device such as a DRAM (Dynamic Randam Access Memory) may be provided with an LDD (Lightly Dosed Drain) diffusion layer as an electric field relaxation layer (see, for example, Patent Document 1). . The LDD diffusion layer is disposed between a gate electrode (hereinafter referred to as “peripheral gate electrode”) formed on the surface of the semiconductor substrate and each of the two source / drain diffusion layers formed in the surface of the semiconductor substrate. Is done.

  The formation of the LDD diffusion layer is performed as follows. First, an active region is defined by a so-called STI (Shallow Trench Isolation) method by embedding an insulating film for element isolation in a semiconductor substrate. Subsequently, after covering the surface of the active region with a gate insulating film, a conductive film is formed and patterned to form a peripheral gate electrode. Next, an LDD diffusion layer is formed in the surface of the active region by first forming a thin liner insulating film and then ion-implanting impurities into the semiconductor substrate. At this stage, the LDD diffusion layer is widely distributed over the entire active region except the portion covered by the peripheral gate electrode. Subsequently, the side surface of the peripheral gate electrode is covered with a sidewall insulating film, and impurity ion implantation is performed again in that state. At this time, since the sidewall insulating film functions as a mask, impurities are not implanted into a region near the peripheral gate electrode, and impurities are implanted only into a region far from the peripheral gate electrode. As a result, the LDD diffusion layer formed in the region far from the peripheral gate electrode is replaced with the source / drain diffusion layer containing impurities at a high concentration, while the LDD diffusion layer remains in the region near the peripheral gate electrode. It will be. Thus, as described above, it is possible to obtain a configuration in which the LDD diffusion layer is disposed between the peripheral gate electrode and each of the two source / drain diffusion layers.

  A semiconductor device having a structure in which a word line is embedded in a semiconductor substrate is known (see, for example, Patent Document 2). In this type of semiconductor device, since the word line is buried in a trench provided on the surface of the semiconductor substrate, as shown in Patent Document 1, the bit line and the peripheral gate electrode are manufactured in the same process. It becomes possible.

  In addition, Patent Document 3 discloses an etching solution used for forming a peripheral gate electrode in a semiconductor device in which a word line is formed on a surface of a semiconductor substrate and a bit line and a cell capacitor are formed above the word line. A structure for protecting the structure in the memory cell region from the above is disclosed.

  More specifically, in the method of manufacturing a semiconductor device described in Patent Document 3, after a word line is formed in a memory cell region by patterning a conductive film formed on the entire surface, a semiconductor is formed in a region between the word lines. A cell contact pad for connecting the surface of the substrate (source / drain diffusion layer) and each of the bit line and the cell capacitor is formed. Then, a peripheral gate electrode is formed by patterning a portion of the conductive film formed in the peripheral circuit region with the memory cell region covered with an interlayer insulating film. Here, as the miniaturization progresses, the interval between the word lines becomes very narrow. As a result, when the interlayer insulating film covering the memory cell region is formed, a situation may occur in which the interlayer insulating film is not sufficiently embedded in the region between the word lines. In this case, voids are generated in the interlayer insulating film, and the etching solution used to form the peripheral gate electrode penetrates into the memory cell region through the voids. Thus, the etchant that enters the memory cell region corrodes the cell contact pad formed in the memory cell region. The technique of Patent Document 3 is to provide a dummy cell contact pad extending in a direction intersecting the word line between the peripheral circuit region and the memory cell region in order to prevent this corrosion. Since the dummy cell contact pad serves as a breakwater for the etching solution, according to the technique of Patent Document 3, corrosion of the cell contact pad is prevented.

International Publication No. 2014/072210 JP 2012-099793 A JP 2010-199613 A

  Incidentally, FIG. 7 of Patent Document 1 discloses an example of a process for forming the above-described sidewall insulating film on the side surface of the peripheral gate electrode. In this example, after a silicon oxide film as a material for the sidewall insulating film is formed, the silicon oxide film is etched back to form a sidewall insulating film on the side surface of the peripheral gate electrode. At this point, the silicon oxide film in the memory cell region (region between bit lines) remains. After the formation of the sidewall insulating film, ion implantation of impurities is performed in the same manner as described above to form a source / drain diffusion layer. In the process shown in FIG. 7 of Patent Document 1, after forming the source / drain diffusion layers in this manner, wet etching of the silicon oxide film is performed in a state where the peripheral circuit region is covered with a resist, thereby forming a memory cell region (bit). The silicon oxide film in the region between the lines is removed.

  Here, it is also conceivable to remove the silicon oxide film in the memory cell region before forming the sidewall insulating film by etch back. In this case, after the silicon oxide film is formed on the entire surface, the peripheral circuit region is covered with a mask film such as a resist, and wet etching of the silicon oxide film is performed in that state. The sidewall insulating film is formed by etching back the silicon oxide film remaining in the peripheral circuit region thereafter.

  However, when such a process is employed, there is a risk that a sidewall insulating film cannot be formed on the side surface of the peripheral gate electrode, particularly in a highly miniaturized semiconductor device. In other words, since wet etching is isotropic, the etching solution used in wet etching also goes to some extent below the mask film covering the peripheral circuit region. When the peripheral circuit area and the memory cell area come close to each other due to advanced miniaturization, the etching solution that wraps around below the mask film may reach the peripheral circuit area. Further, when the interval between the bit lines becomes narrow due to advanced miniaturization, a region between the bit lines cannot be sufficiently filled with the silicon oxide film, and seams and voids are generated in the silicon oxide film. These seams and voids play a role of guiding the etching solution toward the peripheral circuit region. As described above, in a highly miniaturized semiconductor device, the etching solution for removing the silicon oxide film in the memory cell region reaches the peripheral circuit region, and the silicon oxide film formed on the side surface of the peripheral gate electrode is used. There is a high possibility of removal. When the silicon oxide film formed on the side surface of the peripheral gate electrode is removed, the sidewall insulating film described above is not formed on the side surface of the peripheral gate electrode. As a result, the LDD diffusion layer does not remain after the ion implantation for forming the source / drain diffusion layer, and the LDD diffusion layer cannot be provided in the peripheral transistor.

  A semiconductor device according to the present invention includes a semiconductor substrate in which a memory cell region and a peripheral circuit region are partitioned, a plurality of first wirings that are respectively disposed in the memory cell region and extend in a first direction, In each of the plurality of first wirings, each of the corresponding first wirings has a plurality of protrusions each having an end facing the one end in the first direction. And a guard line extending in a second direction orthogonal to the first direction.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an interlayer insulating film on a surface corresponding to the memory cell region of a semiconductor substrate in which a memory cell region and a peripheral circuit region are partitioned; Forming a first conductive film on the surface; a plurality of first wiring patterns extending in a first direction in the memory cell region on the surface of the first conductive film; Provided in each of the first wirings and having a plurality of protrusions each having an end opposite to one end of the corresponding first wiring in the first direction, and disposed in the memory cell region Forming a mask pattern including a guard line pattern extending in a second direction orthogonal to the first direction, and patterning the first conductive film by etching using the mask pattern as a mask. By grayed, characterized in that it comprises a step of forming a plurality of first wiring and the guard line.

  According to the present invention, the guard line serves to prevent the etching solution from entering the peripheral circuit region. Accordingly, since the source / drain diffusion layer of the peripheral transistor can be formed with the side surface of the peripheral gate electrode covered with the sidewall insulating film, the LDD diffusion layer can be provided in the peripheral transistor.

(A) is a figure which shows the plane layout of the semiconductor device 1 by the preferable 1st Embodiment of this invention, (b) is sectional drawing of the semiconductor device 1 corresponding to the AA line of (a). It is. (A) is a top view of the semiconductor device 1 in the middle of manufacture, and (b) is a cross-sectional view of the semiconductor device 1 corresponding to the AA line of (a). (A) is a top view of the semiconductor device 1 during manufacturing (step following FIG. 2), and (b) is a cross-sectional view of the semiconductor device 1 corresponding to the AA line of (a). (A) is a top view of the semiconductor device 1 in the middle of manufacture (step following FIG. 3), and (b) is a cross-sectional view of the semiconductor device 1 corresponding to the AA line of (a). (A) is a top view of the semiconductor device 1 in the middle of manufacturing (step following FIG. 4), and (b) is a cross-sectional view of the semiconductor device 1 corresponding to the AA line of (a). (A) is a top view of the semiconductor device 1 in the middle of manufacturing (step following FIG. 5), and (b) is a cross-sectional view of the semiconductor device 1 corresponding to the AA line of (a). (A) is sectional drawing corresponding to the AA of FIG. 1 (a) of the semiconductor device 1 in the middle of manufacture (process following FIG. 6). (A) is sectional drawing corresponding to the AA line of FIG. 1 (a) of the semiconductor device 1 in the middle of manufacture (process following FIG. 7). (A) is sectional drawing corresponding to the AA line of FIG. 1 (a) of the semiconductor device 1 in the middle of manufacture (process following FIG. 8). (A) is sectional drawing corresponding to the AA line of FIG. 1 (a) of the semiconductor device 1 in the middle of manufacture (process following FIG. 9). (A) is sectional drawing corresponding to the AA line of Fig.1 (a) of the semiconductor device 1 in the middle of manufacture (process following FIG. 10). (A) is a top view of the semiconductor device 1 in the middle of manufacture (step following FIG. 11), and (b) is a cross-sectional view of the semiconductor device 1 corresponding to the AA line of (a). (A) is a top view of the semiconductor device 1 in the middle of manufacturing (step following FIG. 12), and (b) is a cross-sectional view of the semiconductor device 1 corresponding to the AA line of (a). (A) is sectional drawing corresponding to the AA line of FIG. 1 (a) of the semiconductor device 1 in the middle of manufacture (process following FIG. 13). (A) is the top view in the process corresponding to FIG. 6 of the semiconductor device 1 by preferable 2nd Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  The semiconductor device 1 according to the present embodiment is a DRAM, and has a configuration in which a memory cell region MC and a peripheral circuit region PA are partitioned on the main surface of a semiconductor substrate 2 as shown in FIG. Note that the scope of application of the present invention is not limited to DRAM, and the present invention is not limited to, for example, ReRAM (Resistance Random Access Memory) using a resistance change type element as a memory element, or PRAM (phase change element as a memory element). (Phase change Random Access Memory) can be suitably applied.

  The memory cell region MC has a rectangle having a first side 10X extending in the x direction (first direction) and a second side 10Y extending in the y direction (second direction) orthogonal to the x direction. (Rectangular) area. The memory cell region MC shown in FIG. 1 is a part of the actual memory cell region, and the actual memory cell region is formed so as to further expand in the right direction of the drawing.

  In the memory cell area MC, a rectangular (rectangular) active cell area AC and a dummy cell area arranged so as to surround the active cell area AC are arranged. The dummy cell region includes two first dummy cell regions DC1 extending in the y direction (however, only one first dummy cell region DC1 is shown in FIG. 1) and two first dummy cell regions DC1 extending in the x direction. 2 dummy cell regions DC2. The first dummy cell region DC1 is disposed in contact with the end portion in the x direction of the active cell region AC, and the second dummy cell region DC2 is disposed in contact with the end portion in the y direction of the active cell region AC.

  The active cell region AC includes memory cell element isolation regions 3a and 3b formed by embedding an insulating film such as a silicon oxide film in the semiconductor substrate 2, and a plurality of memory cell element isolation regions 3a and 3b surrounded by the memory cell element isolation regions 3a and 3b, respectively. A cell active region k is disposed. FIG. 1A shows only eight cell active regions k, but more cell active regions k are actually arranged. The memory cell element isolation region 3a (first element isolation region) is formed to extend in the w direction (third direction) inclined with respect to each of the x direction and the y direction, and the memory cell element isolation region 3b The (second element isolation region) is formed to extend in the y direction. Since the memory cell element isolation regions 3a and 3b have such a shape, the planar shape of each cell active region k is parallel in which one opposite side is parallel to the y direction and the other opposite side is parallel to the w direction. It becomes a quadrilateral. Each cell active region k is arranged in a matrix along each of the x direction and the y direction. Two DRAM memory cells are arranged in each cell active region k.

  On the other hand, in the first dummy cell region DC1, a plurality of dummy cell active regions Dk are arranged along the second side 10Y. These dummy cell active regions Dk are separated from each other by a memory cell element isolation region 3a extending from the active cell region AC into the first dummy cell region DC1, and in the active cell region AC by the memory cell element isolation region 3b. Are isolated from each cell active region k. Similarly, a plurality of dummy cell active regions Dk are arranged along the first side 10X in the second dummy cell region DC2. These dummy cell active regions Dk are separated from each other by memory cell element isolation regions 3a and 3b extending from the active cell region AC into the second dummy cell region DC2, and active by the memory cell element isolation regions 3a and 3b. It is isolated from each cell active region k in the cell region AC. No memory cell is arranged in the dummy cell active region Dk. Therefore, the dummy cell active region Dk does not contribute to the operation of the semiconductor device 1 as a DRAM.

  The peripheral circuit area PA is an area disposed around the memory cell area MC. The peripheral element isolation area 3c is formed by embedding an insulating film such as a silicon oxide film in the semiconductor substrate 2; And at least one peripheral active region surrounded by the region 3c. In the peripheral circuit area PA, a first peripheral circuit area PC1 in which a word driver is installed and a second peripheral circuit area PC2 in which a sense amplifier is installed are arranged. In the first peripheral circuit region PC1, a plurality of peripheral active regions 20a extending in the x direction are juxtaposed in the y direction. On the other hand, in the second peripheral circuit region PC2, a plurality of peripheral active regions 20b extending in the y direction are juxtaposed in the x direction. In the actual peripheral circuit area PA, a large number of peripheral circuit areas are arranged in addition to the illustrated first and second peripheral circuit areas PC1 and PC2. The peripheral element isolation region 3c communicates with the memory cell element isolation regions 3a and 3b in the memory cell region MC at the boundary between the memory cell region MC and the peripheral circuit region PA.

  A first peripheral gate electrode PG1 is arranged in the first peripheral circuit region PC1. The first peripheral gate electrode PG1 is formed so as to extend in the y direction, and intersects each of the plurality of peripheral active regions 20a arranged in the first peripheral circuit region PC1. One peripheral transistor having the first peripheral gate electrode PG1 as a gate electrode is disposed in each of the plurality of peripheral active regions 20a.

  As shown in FIG. 1B, the source / drain diffusion layers D5 constituting the controlled electrodes of the corresponding peripheral transistors are formed in the regions in the peripheral active region 20a located on both sides of the first peripheral gate electrode PG1, respectively. Is placed. In addition, an LDD diffusion layer D4 is formed in a region in the peripheral active region 20a located between each source / drain diffusion layer D5 and the first peripheral gate electrode PG1. Both the source / drain diffusion layer D5 and the LDD diffusion layer D4 are impurity diffusion layers formed by ion-implanting n-type impurities such as phosphorus into the surface of the semiconductor substrate 2. The impurity concentration of the LDD diffusion layer D4 is It is lower than the impurity concentration of the source / drain diffusion layer D5.

  As shown in FIG. 1B, the first peripheral gate electrode PG1 is composed of a laminated film of a silicon film 21 and a metal film 22. The upper surface of the metal film 22 is covered with a cover film 23. The cover film 23 is the one in which the silicon nitride film used as a mask when the first peripheral gate electrode PG1 is formed is left. Further, the side surfaces (including the side surfaces 24a and 24b in the x direction shown in FIG. 1B) of the first peripheral gate electrode PG1 are arranged in order from the side closer to the side surfaces, the first liner film 11, the spacer insulating film 12, And the second liner film 13. The first and second liner films 11 and 13 are made of a silicon nitride film, and the spacer insulating film 12 is made of a silicon oxide film. The spacer insulating film 12 has a sidewall shape formed to leave a part of the LDD diffusion layer D4 previously formed when ion implantation of impurities is performed to form the source / drain diffusion layer D5. This is an insulating film. Details of this point will be described later when a method for manufacturing the semiconductor device 1 is described.

  An interlayer insulating film 14 made of a silicon oxide film is formed on the upper surface of the second liner film 13. The upper surface of the interlayer insulating film 14 is flattened so as to form the same plane as the upper surface of the cover film 23. One of the two source / drain diffusion layers D5 formed in each peripheral active region 20a is connected via a contact plug 15a penetrating the first and second liner films 11 and 13 and the interlayer insulating film 14. It is connected to a wiring 16 a formed on the upper surface of the interlayer insulating film 14. Similarly, the other of the two source / drain diffusion layers D5 formed in each peripheral active region 20a has a contact plug 15b penetrating the first and second liner films 11 and 13 and the interlayer insulating film 14. The wiring 16b is formed on the upper surface of the interlayer insulating film 14 through the wiring 16b.

  An interlayer insulating film 17 made of a silicon oxide film is formed on the upper surface of the interlayer insulating film 14. An interlayer insulating film 34 made of a silicon oxide film is further formed on the upper surface of the interlayer insulating film 17. The wiring 16 a is connected to a wiring 36 a formed on the upper surface of the interlayer insulating film 34 through a via plug 35 a penetrating the interlayer insulating films 17 and 34.

  The wiring 16b is connected to one of the plurality of bit lines BL formed in the memory cell region MC. This will be described in detail below.

  A plurality of first wirings each extending in the x direction are formed in the memory cell region MC. The first wiring has a bit line BL used for transferring data stored in the memory cell and the same structure as the bit line BL, but transfers data stored in the memory cell. Includes dummy bit lines DBL (dummy wiring) that are not used. The bit line BL is formed so as to pass through the active cell region AC, and the dummy bit line DBL is formed so as to pass through the second dummy cell region DC2. In the example of FIG. 1A, two first wirings located at both ends in the y direction of a plurality of first wirings are dummy bit lines DBL. Each bit line BL intersects each of a plurality of cell active regions k arranged in the x direction. The arrangement of each bit line BL is determined so that one bit line BL passes through one cell active region k.

  Each of the plurality of first wirings is composed of a metal film 22 common to the first peripheral gate electrode PG1, and is disposed on the surface of the interlayer insulating film 9 shown in FIG. The interlayer insulating film 9 is a silicon oxide film formed on the surface of the semiconductor substrate 2 with a film thickness similar to that of the silicon film 21 and covers almost the entire memory cell region MC. Each bit line BL is connected to a diffusion layer D1 (described later) of the corresponding cell transistor through a bit line contact plug 9a penetrating the interlayer insulating film 9.

  The upper surfaces of the plurality of first wirings are covered with the cover film 23 in the same manner as the upper surface of the first peripheral gate electrode PG1. Further, the side surfaces (including the side surfaces 26a and 26b shown in FIG. 1B) of each of the plurality of first wirings are the same as the side surfaces of the first peripheral gate electrode PG1, and the first liner film 11 and the second Covered by the liner film 13. However, the spacer insulating film 12 is not formed on the side surface of the first wiring. Since the first and second liner films 11 and 13 are both silicon nitride films as described above, the side surface of the first wiring is covered with a sidewall insulating film made of a single-layer silicon nitride film. I can also say.

  Each bit line BL is connected to a wiring 16b formed on the interlayer insulating film 14 by a bit line contact plug BC penetrating the cover film 23 in the first dummy cell region DC1. The wiring 16b is formed for each bit line BL, and the bit line BL and the other source / drain diffusion layer D5 in each peripheral active region 20a are connected one-to-one via the wiring 16b.

  A second peripheral gate electrode PG2 is disposed in the second peripheral circuit region PC2. The second peripheral gate electrode PG2 is formed so as to extend in the x direction, and intersects each of the plurality of peripheral active regions 20b arranged in the second peripheral circuit region PC2. One peripheral transistor having the second peripheral gate electrode PG2 as a gate electrode is disposed in each of the plurality of peripheral active regions 20b. Although the detailed structure of the peripheral transistor (including the second peripheral gate electrode PG2 and its peripheral structure) is not shown, the peripheral transistor described with reference to FIG. 1B (arranged in the peripheral active region 20a) This is the same as the structure of the peripheral transistor).

  One of the two source / drain diffusion layers D5 formed in each peripheral active region 20b includes the first and second liner films 11 and 13 and the interlayer insulating film 14 as in the peripheral active region 20a. It is connected to a wiring 16a formed on the upper surface of the interlayer insulating film 14 through a contact plug 15a that penetrates. On the other hand, the other of the two source / drain diffusion layers D5 formed in each peripheral active region 20b is connected one-to-one with a plurality of word lines WL1 to WL4 formed in the memory cell region MC.

  Hereinafter, the word lines WL1 to WL4 will be collectively referred to as word lines WL (second wiring) and the description will be continued. Each word line WL is formed so as to extend in the y direction from the peripheral circuit area PA to the memory cell area MC. In the memory cell area MC, each word line WL is connected to each of the plurality of cell active areas k arranged in the y direction. Crossed. The arrangement of each word line WL is determined so that two word lines WL pass through one cell active region k.

  As shown in FIG. 1B, each word line WL is a buried word line constituted by a conductive film buried under a trench provided in the semiconductor substrate 2 via a gate insulating film 5. A cap insulating film 6 made of a silicon nitride film is embedded in the upper portion of the trench, thereby ensuring insulation between the upper layer wiring such as the bit line BL and the word line WL.

  Focusing on one cell active region k, a diffusion layer D1 is disposed in a region between two corresponding word lines WL. Further, a diffusion layer D2 is disposed on the opposite side of the diffusion layer D1 (between one word line WL and the memory cell element isolation region 3b) across one word line WL, and diffused across the other word line WL. A diffusion layer D3 is arranged on the opposite side of the layer D1 (between the other word line WL and the memory cell element isolation region 3b). The diffusion layers D1 to D3 are all impurity diffusion layers formed by ion-implanting n-type impurities such as phosphorus into the surface of the semiconductor substrate 2. One cell transistor is constituted by the diffusion layers D1, D2 and the word line WL therebetween, and the other cell transistor is constituted by the diffusion layers D1, D3 and the word line WL therebetween.

  As described above, the diffusion layer D1 is connected to the bit line BL passing right above via the bit line contact plug 9a penetrating the interlayer insulating film 9. On the other hand, the diffusion layers D2 and D3 are respectively formed on the interlayer insulating film 17 via the interlayer insulating film 9, the first and second liner films 11 and 13, and the capacitor contact plug 30 penetrating the interlayer insulating films 14 and 17. A plurality of lower electrodes 31 formed on the upper surface are connected one-on-one.

  The lower electrode 31 constitutes a cell capacitor C together with the capacitive insulating film 32 and the upper electrode 33. Note that a silicon nitride film layer as an etching stopper is actually formed on the upper surface of the interlayer insulating film 17, but is not shown in FIG. The cell capacitor C is provided in one-to-one correspondence with the cell transistor. The lower electrode 31 is provided independently for each cell capacitor C, while the upper electrode 33 is provided in common for the plurality of cell capacitors C. The upper surface of the interlayer insulating film 34 is located higher than the upper surface of the upper electrode 33, and the upper electrode 33 is connected to a wiring 36 b formed on the upper surface of the interlayer insulating film 34 by a via plug 35 b penetrating the interlayer insulating film 34. .

  In addition to the configuration described above, the semiconductor device 1 is provided with a guard line GL shown in FIG. In the guard line GL, an etching solution used to remove a portion formed in the memory cell region MC in the silicon oxide film formed to form the spacer insulating film 12 enters the peripheral circuit region PA. This is to prevent this and is arranged in the first dummy cell region DC1. Hereinafter, the configuration of the guard line GL will be described first, and the effect of using the guard line GL will be described in detail later when the method for manufacturing the semiconductor device 1 is described. In the following description, the description will be given focusing on the first dummy cell region DC1 shown in FIG. 1, but another first dummy cell region DC1 (not shown) provided in one memory cell region MC. A similar guard line GL is also arranged.

  Each of the guard lines GL protrudes in the active cell region AC direction and extends in the x direction on a straight line portion that extends in the y direction along the second side 10Y of the memory cell region MC. The protrusion P is provided. The plurality of protrusions P are provided for each first wiring (bit line BL and dummy bit line DBL), and each end E2 is opposed to one end E1 in the x direction of the corresponding first wiring. have. The center line in the y direction of the protrusion P matches the center line in the y direction of the corresponding first wiring. Moreover, in this Embodiment, regarding all the projection parts P, the edge part E1 and the edge part E2 are spaced apart. The guard line GL is composed of the same metal film 22 as that of the bit line BL, and the guard line GL and the bit line BL are formed simultaneously as will be described later. Further, the width W3 in the x direction of the straight line portion (the portion that is not the protrusion P) of the guard line GL is the sum of the widths W4 of the two first wires arranged adjacent to each other in the y direction. It is 1/3 or more and 2/3 or less of the value W1 obtained by adding the distance W2 between the first wirings.

  Many portions of the side surface (second side surface, including the side surface 25b shown in FIG. 1B) on the active cell region AC side of the guard line GL are formed on the bit line BL as illustrated in FIG. 1B. Like the above, the two layers of the first liner film 11 and the second liner film 13 are covered in order from the side closer to the side surface. The spacer insulating film 12 described above is not formed in these portions. On the other hand, the side surface (first side surface, including the side surface 25a shown in FIG. 1B) of the guard line GL on the peripheral circuit region PA side is the same as the first peripheral gate electrode PG1 from the side close to the side surface. The first liner film 11, the spacer insulating film 12, and the second liner film 13 are sequentially covered with a three-layer film.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.

  First, a p-type silicon single crystal substrate is prepared as the semiconductor substrate 2, and a trench is provided on the surface, and an insulating film such as a silicon oxide film is embedded therein, whereby the memory cell element isolation regions 3a and 3b and the periphery are provided. An element isolation region 3c is formed. Thus, each active region (cell active region k, dummy cell active region Dk, peripheral active regions 20a, 20b) shown in FIG. 1 is partitioned on the surface of the semiconductor substrate 2. Note that a semiconductor substrate other than the p-type silicon single crystal substrate can also be used as the semiconductor substrate 2.

  Next, the gate insulating film 10 is formed on the surfaces of the peripheral active regions 20a and 20b by thermal oxidation, and further, a silicon film 21A (second conductive film) that becomes a part of the first and second peripheral gate electrodes PG1 and PG2. ) In the peripheral circuit area PA. Thereafter, two cell transistors are formed in each cell active region k by forming the word line WL and the diffusion layers D1 to D3. After the cell transistor is formed, a silicon oxide film is formed and the upper surface is flattened to form an interlayer insulating film 9 covering the memory cell region MC. A bit line contact plug 9a connected to the diffusion layer D1 is formed.

  Next, as shown in FIG. 2, a metal film 22A (first conductive film) including a titanium nitride film and a tungsten film, a silicon nitride film, on a plane composed of the upper surface of the interlayer insulating film 9 and the upper surface of the silicon film 21A. A cover film 23A and a hard mask film 43 are sequentially formed. The hard mask film 43 is a laminated film in which a carbon film 40A, a silicon nitride film 41A, and a silicon film 42A are laminated in order.

  Next, a first lithography process is performed to form a first organic film 44A constituting the first pattern 45 on the hard mask film 43 as shown in FIG. The first pattern 45 extends in the y direction and extends in the x direction, and two first side surfaces S1 facing each other (however, only one first side surface S1 is shown in FIG. 2). A plurality of first line patterns 45A extending in the x direction and arranged at equal intervals in the y direction inside a rectangular opening as a whole surrounded by the two second side surfaces S2 facing each other. And a plurality of first space patterns 45B arranged between the first line patterns 45A. The width of the first space pattern 45B in the y direction (= W1 shown in FIG. 1) is, for example, 70 nm, and the width of the first line pattern 45A in the y direction (= W2 shown in FIG. 1) is, for example, 30 nm. . The first pattern 45 also has a groove 45C that is disposed along the first side surface S1. Both end portions in the x direction of the first line pattern 45A are separated from the first side surface S1 by the groove 45C. The width in the x direction of the groove 45C (= W3 shown in FIG. 1) is in the range of 1/3 to 2/3 of the value W1.

  Next, as shown in FIG. 3, a sidewall insulating film 50 made of a silicon oxide film is formed on the side surface of the first pattern 45. The sidewall insulating film 50 is formed around the first line pattern 45A, the first side surface S1, and the second side surface S2. The width of the sidewall insulating film 50 (= W4 shown in FIG. 1) is, for example, 20 nm. Thus, the groove 45C having a width W3 of 30 nm is buried with the silicon oxide film. Accordingly, the plurality of sidewall insulating films 50 extending in the x direction are connected by the sidewall insulating films 50 formed along the first side surface S1.

  Next, as shown in FIG. 4, the first organic film 44A is removed. Thereby, only the sidewall insulating film 50 remains on the upper surface of the silicon film 42 </ b> A, and the remaining sidewall insulating film 50 constitutes the second pattern 51. The second pattern 51 includes a plurality of second line patterns 51A extending in the x direction and arranged at equal intervals in the y direction, and a plurality of second lines arranged between the second line patterns 51A. The space pattern 51B and two groove line patterns 51C extending in the y direction and connected to the end portions of the plurality of second line patterns 51A in the x direction (however, only one groove line pattern 51C is shown in FIG. 4) Are shown). When the width W1 and the width W2 shown in FIG. 2 are 70 nm and 30 nm, respectively, and the width W4 shown in FIG. 3 is 20 nm, the pitch of the second line pattern 51A (= P1 shown in FIG. 1) is 50 nm. It becomes. Note that the method of making a fine pattern (second pattern 51) using the sidewall insulating film 50 in this way is usually a method called a double patterning (DPT) method.

  Next, a second organic film 52 having an opening 52a is formed by performing a second lithography process as shown in FIG. The opening 52a is an opening that extends in the y direction, and is formed at a position that does not overlap the groove line pattern 51C on the first dummy cell region DC1. The width of the opening 52a in the x direction is, for example, 30 nm. Further, the end of the opening 52a in the y direction is arranged so that the second line pattern 51A located at both ends in the y direction is exposed. As a result, the upper surface of the second line pattern 51A made of a silicon oxide film and the upper surface of the silicon film 42A are alternately exposed in the y direction in the opening 52a.

  Here, if the conventional DPT method is applied to the above process, the opening 52a is formed so as to expose the entire groove line pattern 51C. The manufacturing method according to the present embodiment differs from the conventional DPT method in that the opening 52a is formed at a position where the groove line pattern 51C is not exposed as described above.

  Next, by selectively etching the silicon oxide film with respect to the silicon film 42A using the second organic film 52 as a mask, the second pattern 51 is changed into the wiring mask pattern 53 and the guard line as shown in FIG. Separated into mask patterns 54. This etching is preferably performed using fluorine (F) -containing plasma. Subsequently, the second organic film 52 used as a mask is removed. The wiring mask pattern 53 is composed of a plurality of linear patterns extending in the x direction. On the other hand, the guard line mask pattern 54 includes a linear pattern extending in the y direction and a plurality of protrusion patterns Pa protruding from the linear pattern in the active cell region AC direction and extending in the x direction. The projection pattern Pa has a one-to-one correspondence with the wiring mask pattern 53, and the end portion E2a in the x direction of each projection pattern Pa faces the one end portion E1a in the x direction of the corresponding wiring mask pattern 53 on a straight line. ing.

  Next, by performing a third lithography step, a third organic film constituting the peripheral gate mask pattern 55 is formed as shown in FIG. Through the steps so far, the third pattern 56 including the wiring mask pattern 53, the guard line mask pattern 54, and the peripheral gate mask pattern 55 is formed on the silicon film 42A. This third pattern 56 becomes the final mask pattern in the present manufacturing method.

  Next, dry etching using hydrogen bromide (HBr) -containing plasma is performed using the third pattern 56 as a mask, thereby transferring the third pattern 56 to the silicon film 42A as shown in FIG. Subsequently, by sequentially etching the silicon nitride film 41A and the carbon film 40A using the silicon film 42A as a mask, the third pattern 56 is transferred to the silicon nitride film 41A and the carbon film 40A as shown in FIG. The silicon film 42A used as a mask is removed after the transfer to the carbon film 40A is completed.

  Next, as shown in FIG. 9, the third pattern 56 is transferred to the cover film 23A made of a silicon nitride film by etching using the silicon nitride film 41A and the carbon film 40A as a mask. The silicon nitride film 41A and the carbon film 40A used as the mask are removed after the transfer to the cover film 23A is completed. Thereafter, the metal film 22A and the silicon film 21A are sequentially etched using the cover film 23 as a mask. As a result, the third pattern 56 is transferred to the metal film 22 and the silicon film 21. As a result, as shown in FIG. 1, the first wiring (bit line BL and dummy bit line DBL) made of the metal film 22 and the guard line GL are formed in the memory cell region MC, and the peripheral circuit region PA is formed in the peripheral circuit region PA. First and second peripheral gate electrodes PG1 and PG2 made of a laminated film of the silicon film 21 and the metal film 22 are formed.

  Next, as shown in FIG. 10, a first liner film 11 made of a silicon nitride film having a thickness of, for example, 5 nm is formed on the entire surface by a deposition method, and further, arsenic that becomes an n-type impurity is formed by an ion implantation method. (As) is introduced into the surface of the semiconductor substrate 2 (first ion implantation). Thereby, the LDD diffusion layer D4 is formed on the surfaces of the peripheral active regions 20a and 20b. Although the first liner film 11 is also formed on the upper surface of the cover film 23, these are made of the same silicon nitride film and are not shown.

  Next, as shown in FIG. 11, a spacer insulating film 12a made of a silicon oxide film having a thickness of, for example, 15 nm is formed on the entire surface by a deposition method. Here, the interval W2 (see FIG. 1) between the adjacent first wirings is set to 30 nm as described above. Therefore, by forming the first liner film 11 having a thickness of 5 nm and the spacer insulating film 12a having a thickness of 15 nm, the space between the first wirings is buried by these. However, as shown in FIG. 11, the space between the first wirings is originally very narrow and is further narrowed after the first liner film 11 is formed, so that the inside thereof is completely covered by the silicon oxide film. It is difficult to embed. As a result, a void 12b as shown in FIG. 11 is formed in a portion of the spacer insulating film 12a located between the first wirings. Even if a deposition method having excellent step coverage is used, the void 12b is inevitably generated in a seam shape extending in the x direction as shown in FIG. If the spacer insulating film 12a is formed using a fluid thin film, the generation of voids 12b can be avoided. However, in this case, the first and second peripheral gate electrodes PG1 and PG2 in the spacer insulating film 12a respectively. The shape of the portion formed on the side surface of the metal becomes irregular. Then, since it becomes difficult to process the spacer insulating film 12a into a sidewall shape, it is inappropriate to form the spacer insulating film 12a using a fluid thin film.

  Next, by performing a fourth lithography step, as shown in FIG. 12, a fourth organic film 60 (mask film) having an opening 60a is formed. The opening 60a is formed so as to expose the active cell region AC. The opening 60a is formed such that the end in the x direction is located between the cell active region k and the dummy cell active region Dk (that is, directly above the memory cell element isolation region 3b).

  Next, as shown in FIG. 13, the spacer insulating film exposed in the opening 60a by wet etching using a hydrofluoric acid (HF) -containing solution (wet etching using the fourth organic film 60 as a mask). 12a is removed. Since this etching is wet etching, it proceeds in the lateral direction unlike dry etching. Further, as described above, the void 12b exists in the spacer insulating film 12a, and this void 12b acts to further diffuse the etching solution in the lateral direction. Therefore, in the wet etching performed in this step, the portion of the spacer insulating film 12a formed in the first dummy cell region DC1 is also etched. The fourth organic film 60 is removed after the wet etching.

  As a result of the wet etching also proceeding in the lateral direction, as shown in FIG. 13, the end portion 12c in the x direction of the spacer insulating film 12a after the wet etching is retracted to the upper surface position of the guard line GL. Conversely, the recession of the spacer insulating film 12a stops at the upper surface position of the guard line GL. If the guard line GL does not exist, the etching solution may enter the peripheral circuit area PA and may be removed to the spacer insulating film 12a in the vicinity of the peripheral gate electrode PG1. In the semiconductor device 1, since the guard line GL functions as a prevention wall that stops the diffusion of the etching solution through the void 12b, the backward movement of the spacer insulating film 12a is stopped at the upper surface position of the guard line GL. Therefore, the spacer insulating film 12a in the peripheral circuit area PA is prevented from being removed.

  Next, the entire spacer insulating film 12a is etched back by a dry etching method, thereby forming a sidewall-like spacer insulating film 12 on the side surface of the first peripheral gate electrode PG1, as shown in FIG. To do. Although not shown in FIG. 14, a sidewall-like spacer insulating film 12 is similarly formed on the side surface of the second peripheral gate electrode PG2 (see FIG. 1) by this step. The spacer insulating film 12 is also formed on the side surface 25a of the guard line GL on the peripheral circuit region PA side. Since the spacer insulating film 12 is not formed on the side surface 25b on the active cell region AC side of the guard line GL, the shape of the sidewalls formed on both side surfaces in the x direction of the guard line GL is asymmetric.

  After forming the spacer insulating film 12 in this way, phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 2 by ion implantation, whereby the source / drain diffusion layers are formed in the peripheral active regions 20a and 20b. D5 is formed (second ion implantation). At this time, since the spacer insulating film 12 is formed on the side surfaces of the first and second peripheral gate electrodes PG1 and PG2, the LDD diffusion layer D4 remains in a region below the spacer insulating film 12. Subsequently, a second liner film 13 made of a silicon oxynitride film (SiON) having a thickness of 3 nm is deposited on the entire surface. Thereafter, a silicon oxide film having a film thickness exceeding the upper surface of the cover film 23 is formed by using a fluid thin film deposition method, and the upper surface is planarized by a CMP method, whereby an interlayer insulating film 14 is formed as shown in FIG. Form.

  Thereafter, as shown in FIG. 1, formation of contact plugs 15a and 15b and bit line contact plug BC, formation of wiring 16b, formation of interlayer insulating film 17, formation of capacitive contact plug 30, formation of cell capacitor C, The semiconductor device 1 is completed by sequentially forming the interlayer insulating film 34, the via plugs 35a and 35b, and the wirings 36a and 36b.

  As described above, according to the semiconductor device 1 and the manufacturing method thereof according to the present embodiment, the guard line GL plays a role of preventing the etchant from entering the peripheral circuit area PA. Therefore, the source / drain diffusion layer D5 of the peripheral transistor can be formed in a state where the side surfaces of the first peripheral gate electrodes PG1 and PG2 are covered with the sidewall-like spacer insulating film 12, and thus the LDD is formed in the peripheral transistor. The diffusion layer D4 can be provided. In addition, it is possible to reduce the variation in the performance of the peripheral transistors and improve the controllability of the characteristics of the peripheral transistors.

  Even when the guard line GL is provided, there remains a possibility that the etching solution may enter the peripheral circuit region PA through the region between the upper surface of the guard line GL and the lower surface of the fourth organic film 60. However, compared with the case where the guard line GL is not provided, the amount of intrusion can be greatly reduced.

  Next, a semiconductor device 1 according to a second embodiment of the present invention will be described with reference to FIG.

  The semiconductor device 1 according to the present embodiment is different from the semiconductor device 1 according to the first embodiment in that a part of the plurality of protrusions P corresponding to the dummy bit line DBL is connected to the corresponding dummy bit line DBL. The other points are the same as those of the semiconductor device 1 according to the first embodiment. Therefore, the same components as those of the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the following, attention is focused on differences from the semiconductor device 1 according to the first embodiment. I will explain.

  As can be understood by comparing FIG. 15 and FIG. 6, in the manufacturing process of the semiconductor device 1 according to the present embodiment, two of the plurality of protrusion patterns Pa provided on the guard line mask pattern 51 are positioned at both ends in the y direction. Are connected to the corresponding linear patterns 53a and 53b in the wiring mask pattern 53. On the other hand, the other protrusion patterns Pa are spaced apart from the corresponding linear patterns as in the first embodiment. This configuration is realized by forming the second organic film 52 so that the openings 52a shown in FIG. 5 do not overlap the second line patterns 51A located at both ends in the y direction. Thereby, although not illustrated, two of the plurality of protrusions P provided on the guard line GL located at both ends in the y direction are connected to the corresponding dummy bit line DBL, and the other protrusions P are connected. And the corresponding first wiring (bit line BL or dummy bit line DBL). As a result, the guard line GL forms a guard ring surrounding the four sides of the memory cell region MC together with the two dummy bit lines DBL located at both ends in the y direction.

  According to the semiconductor device 1 and the manufacturing method thereof according to the present embodiment, the peripheral circuit region PA and the memory cell region MC are completely divided by the guard ring configured as described above, so that the diffusion of the etchant is more efficient. Can be avoided.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in each of the above embodiments, the example in which the cell active regions k are arranged in a matrix has been described. However, the present invention can also be suitably applied to a semiconductor device in which the cell active regions k have other arrangements. It is.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3a, 3b Memory cell element isolation region 3c Peripheral element isolation region 5 Gate insulating film 6 Cap insulating film 9, 14, 17, 34 Interlayer insulating film 9a, BC Bit line contact plug 10 Gate insulating film 10X Memory First side 10Y of the cell region MC Second side 11 of the memory cell region MC First liner film 12, 12a Spacer insulating film 12b Void 12c formed in the spacer insulating film 12a End 13 of the spacer insulating film 12a Second liner films 15a, 15b Contact plugs 16a, 16b, 36a, 36b Wirings 20a, 20b Peripheral active regions 21, 21A Silicon films 22, 22A Metal films 23, 23A Cover films 24a, 24b First peripheral gate electrode PG1 Side surface 25a in the x direction Side of the peripheral circuit area PA side of the guard line GL 25b Side surfaces 26a, 26b on the active cell region AC side of the guard line GL Side surfaces 30 of the first wiring Capacitor contact plug 31 Lower electrode 32 Capacitor insulating film 33 Upper electrode 35a, 35b Via plug 40A Carbon film 41A Silicon nitride film 42A Silicon film 43 Hard mask film 44A First organic film 45 First pattern 45A First line pattern 45B First space pattern 45C Groove 50 Side wall insulating film 51 Second pattern 51A Second line pattern 51B Second space pattern 51C Groove Line Pattern 52 Second Organic Film 52a Opening 53 Wiring Mask Patterns 53a, 53b Linear Pattern 54 in Wiring Mask Pattern 53 Guard Line Mask Pattern 55 Peripheral Gate Mask Pattern 56 Third Pattern 60 Fourth Pattern Organic film 60a Opening AC Active cell region BL Bit line C Cell capacitors D1 to D3 Diffusion layer D4 LDD diffusion layer D5 Source / drain diffusion layer DBL Dummy bit line DC1 First dummy cell region DC2 Second dummy cell region Dk Dummy cell active region E1 x-direction end E1a of the first wiring E2 direction end E2 of the wiring mask pattern 53 x-direction end E2a of the projection P Pa-pattern end GL guard line k cell active region MC Memory cell region P Projection portion Pa Projection pattern PA Peripheral circuit region PC1 First peripheral circuit region PC2 Second peripheral circuit region PG Peripheral gate electrode PG1 First peripheral gate electrode PG2 Second peripheral gate electrode S1 First pattern 45 in the x-direction side of the opening included in the opening 45 included in the first pattern 45 Side surface WL, WL1-WL4 of y direction

Claims (16)

A semiconductor substrate in which a memory cell region and a peripheral circuit region are partitioned;
A plurality of first wirings each disposed in the memory cell region and extending in a first direction;
In each of the plurality of first wirings, each of the corresponding first wirings has a plurality of protrusions each having an end facing the one end in the first direction. And a guard line extending in a second direction orthogonal to the first direction. Among the plurality of first wires, the plurality of first wires located at both ends in the second direction are dummy wires,
A part of the plurality of protrusions each corresponding to the dummy wiring is connected to the corresponding dummy wiring,
2. The semiconductor device according to claim 1, wherein each of the guard lines forms a guard ring that surrounds four sides of the memory cell region together with the two first wirings that are the dummy wirings. The semiconductor device according to claim 2, wherein the first wiring that is not the dummy wiring is a bit line. The semiconductor device according to any one of claims 1 to 3, wherein the guard line and the plurality of first wirings are made of the same material. A spacer insulating film that covers a first side surface that is a side surface of the guard line on the peripheral circuit region side;
5. The semiconductor device according to claim 1, wherein the spacer insulating film is not disposed on a second side surface of the guard line located on the opposite side of the first side surface. 6. The memory cell region has an active cell region in which a plurality of memory cells are disposed, and a dummy cell region disposed so as to surround the active cell region,
The semiconductor device according to claim 1, wherein the guard line is disposed in the dummy cell region. The active cell region includes a first element isolation region extending in a third direction inclined with respect to each of the first and second directions, and a second element extending in the second direction. A plurality of active regions surrounded by the element isolation region are formed,
The semiconductor device is embedded in the semiconductor substrate and extends in the second direction so as to intersect with each of the plurality of active regions arranged along the second direction. The semiconductor device according to claim 1, further comprising: a wiring. The width of the portion of the guard line that is not the protrusion in the first direction is the sum of the widths of the two first wires arranged adjacent to each other in the second direction. The semiconductor device according to any one of claims 1 to 7, wherein the value is 1/3 or more and 2/3 or less of a value obtained by adding a distance between the first wirings. In the peripheral circuit region, a peripheral active region surrounded by a peripheral element isolation region is formed,
The semiconductor device includes:
A peripheral gate electrode formed on the semiconductor substrate so as to intersect the peripheral active region;
Two source / drain diffusion layers respectively formed in regions located on both sides of the peripheral gate electrode in the peripheral active region;
9. The method further comprising: two LDD diffusion layers formed in a region located between each of the two source / drain diffusion layers in the peripheral active region and the peripheral gate electrode. The semiconductor device according to any one of the above. A spacer insulating film covering a side surface of the peripheral gate electrode;
The semiconductor device according to claim 9, wherein each of the two LDD diffusion layers is formed below the spacer insulating film. Forming an interlayer insulating film on a surface corresponding to the memory cell region of the semiconductor substrate in which the memory cell region and the peripheral circuit region are partitioned;
Forming a first conductive film on the surface of the interlayer insulating film;
A plurality of first wiring patterns extending in the first direction in the memory cell region and provided on the surface of the first conductive film for each of the plurality of first wirings. A plurality of protrusions each having an end opposite to one end in the first direction of the first wiring, the second wiring being disposed in the memory cell region and orthogonal to the first direction; Forming a mask pattern including a pattern of guard lines extending in a direction;
And forming the plurality of first wirings and the guard lines by patterning the first conductive film by etching using the mask pattern as a mask. The step of forming the mask pattern includes:
By forming and patterning a first organic film, two first side surfaces extending in the second direction and facing each other, and two second side surfaces extending in the first direction and facing each other A plurality of first line patterns extending in the first direction and arranged at equal intervals in the second direction inside the generally rectangular opening surrounded by the side surface of A first pattern having a shape in which a plurality of first space patterns arranged between the first line patterns and a groove portion arranged along each of the two first side surfaces are formed. Forming, and
After the side wall insulating film is formed on the side surface of the first organic film, the first organic film is removed to extend in the first direction and be arranged at equal intervals in the second direction. A plurality of second line patterns, a plurality of second space patterns arranged between the plurality of second line patterns, and the plurality of second lines extending in the second direction. Forming a second pattern having two groove line patterns connected to the ends of each pattern in the first direction;
Forming a second organic film having an opening extending in the second direction at a position where the upper surface of each of the plurality of second line patterns is exposed while the groove line pattern is not exposed;
The method according to claim 11, further comprising: etching the sidewall insulating film by etching using the second organic film as a mask. The step of forming the mask pattern includes:
By forming and patterning a first organic film, two first side surfaces extending in the second direction and facing each other, and two second side surfaces extending in the first direction and facing each other A plurality of first line patterns extending in the first direction and arranged at equal intervals in the second direction inside the generally rectangular opening surrounded by the side surface of A first pattern having a shape in which a plurality of first space patterns arranged between the first line patterns and a groove portion arranged along each of the two first side surfaces are formed. Forming, and
After the side wall insulating film is formed on the side surface of the first organic film, the first organic film is removed to extend in the first direction and be arranged at equal intervals in the second direction. A plurality of second line patterns, a plurality of second space patterns arranged between the plurality of second line patterns, and the plurality of second lines extending in the second direction. Forming a second pattern having two groove line patterns connected to the ends of each pattern in the first direction;
An opening extending in the second direction at a position where the upper surface of the plurality of second line patterns other than those located at both ends in the second direction is exposed and the groove line pattern is not exposed. Forming a second organic film having:
The method according to claim 11, further comprising: etching the sidewall insulating film by etching using the second organic film as a mask. Forming a second conductive film on a surface corresponding to the peripheral circuit region of the semiconductor substrate;
The first conductive film is also formed on the surface of the second conductive film,
The mask pattern further includes a pattern of a peripheral gate electrode disposed in the peripheral circuit region,
14. The step of forming the plurality of first wirings and the guard line also forms the peripheral gate electrode made of a laminated film of the first and second conductive films. The manufacturing method as described in any one. Forming a LDD diffusion layer on a surface of a peripheral active region disposed in the peripheral circuit region by performing a first ion implantation after the peripheral gate electrode is formed;
Forming a spacer insulating film;
Forming a mask film having an opening exposing at least an active cell region in the memory cell region;
Etching the spacer insulating film by wet etching using the mask film as a mask;
Etching the spacer insulating film, removing the mask film, and further performing etch back of the spacer insulating film;
The method according to claim 14, further comprising: forming a source / drain diffusion layer on a surface of the peripheral active region by performing second ion implantation after the etch back. . Forming a first liner film covering the entire surface after the peripheral gate electrode is formed and before performing the first ion implantation;
The method according to claim 15, further comprising: forming a second liner film covering the entire surface after forming the source / drain diffusion layer.

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