JP2016152578A - Esd protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ESD protection circuit of small layout area, which does not become a load during normal operation of a differential output buffer.SOLUTION: In an ESD protection circuit, a common mode voltage detection circuit detects the common mode voltage of a differential output signal from a differential output buffer, and outputs a common mode voltage detection signal. An overvoltage detection circuit detects whether the voltage of a common mode voltage detection signal is a common mode voltage at the time of normal operation, or an overvoltage at the time of ESD event occurrence, higher than the common mode voltage at the time of normal operation, and generates a detection signal. When the detection signal indicates that the voltage of a common mode voltage detection signal is overvoltage, an off circuit turns the protected element of the differential output buffer off at the time of ESD event occurrence.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an ESD protection circuit that protects an internal circuit of a semiconductor integrated circuit from being destroyed by an overvoltage when an ESD (electrostatic discharge) event occurs.

  FIG. 7 is a circuit diagram illustrating an example of a configuration of a differential output buffer to which a conventional ESD protection circuit is applied. A differential output buffer 10 shown in FIG. 1 is mounted on a semiconductor integrated circuit, and includes two PMOS (P-type MOS transistors) P1 and P2 serving as load resistors and an NMOS (N-type MOS transistor serving as a current source). ) N1, two NMOSs N2 and N3 serving as differential switches, two resistance elements R1 and R2, and an operational amplifier OP.

  Further, the ESD protection circuit includes a first protection circuit 12 and a second protection circuit 14, and the first protection circuit 12 includes four diodes D1, D2, D3, and D4.

During normal operation, the voltage at the external output terminal of the differential output signals OUTP and OUTN is a voltage from the ground voltage VSS to the power supply voltage VDD. Therefore, the four diodes D1, D2, D3, and D4 of the first protection circuit 12 are Both are off.
When the voltage VDD of the power supply node is the power supply voltage VDD during normal operation, the second protection circuit 14 is in an off state.

  Thus, during normal operation, both the first protection circuit 12 and the second protection circuit 14 are in an off state, and the ESD protection circuit has no influence on the normal operation of the differential output buffer 10.

  Subsequently, when an ESD event occurs and an overcurrent due to ESD is applied to the differential output signal OUTP with reference to the external ground terminal, the diode D1 of the first protection circuit 12 is turned on, and the voltage VDD of the power supply node is It sharply rises above the power supply voltage VDD during normal operation.

  When the voltage VDD of the power supply node steeply rises above the power supply voltage VDD during normal operation, the second protection circuit 14 is turned on. As a result, the ESD current is released from the external output terminal of the differential output signal OUTP to the external ground terminal via the first diode D1, the power supply node, the second protection circuit 14, and the ground node. As a result, the voltage VDD of the power supply node is clamped, and the internal circuit of the semiconductor integrated circuit operating at the power supply voltage VDD during normal operation is protected.

  Thus, when an ESD event occurs, the first protection circuit 12 and the second protection circuit 14 are turned on, and the internal circuit of the semiconductor integrated circuit that operates at the power supply voltage VDD during normal operation is protected.

  As described above, when an overcurrent due to ESD is applied to the external output terminal of the differential output signal OUTP with reference to the external ground terminal, the overcurrent flows through the ESD protection element, thereby causing the differential output signal OUTP to flow. When the voltage between the external connection terminal and the external power supply terminal is Vdio and the voltage between the external power supply terminal and the external ground terminal is Vpc, the differential output signal OUTP is connected between the external connection terminal and the external ground terminal. Generates voltage Vclamp = voltage Vdio + voltage Vpc.

  As shown in FIG. 8, the voltage Vclamp is applied to both ends of the NMOSs N2 and N1 stacked in the differential output buffer 10. When this voltage Vclamp exceeds the ESD withstand voltage of the vertically stacked NMOSN2 and N1, the NMOSN2 and N1 may be destroyed. However, the ESD withstand voltage of the vertically stacked NMOSN2 and N1 is It turns out that it changes with the ON state (ON) and the OFF state (OFF) of NMOSN2 and N1.

In this example, the ESD withstand voltage (allowable voltage Vclamp) is maximized when both NMOSN2 and N1 are off as shown in Table 1.
In general, as an ESD protection circuit, if it is possible to add a circuit that detects that an overvoltage due to ESD is applied without interfering with normal operation and controls the state of a MOS transistor so that the ESD withstand voltage is maximized, an ESD protection circuit can be added. The breakdown voltage can be improved.

  Patent Document 1, Non-Patent Documents 1 and 2 have been proposed as an ESD protection circuit that improves the ESD withstand voltage by controlling the state of the MOS transistor.

However, as shown in FIG. 9, Patent Document 1 presupposes the existence of a level shift circuit driven by a different power supply system for detection of application of an overvoltage by ESD and state control of a MOS transistor. It cannot be used in the differential output buffer of the power supply system.
As shown in FIG. 10, Non-Patent Document 1 uses an RC filter for detection of overvoltage application by ESD and state control of a MOS transistor. Generally, an RC filter for detection of application of overvoltage by ESD is sized. Is considerably large, and the layout area increases.
In Non-Patent Document 2, as shown in FIG. 11, a diode string is added to an output node for detection of application of overvoltage by ESD and state control of a MOS transistor. For this reason, there is a concern that the parasitic capacitance of the output node increases and the operation speed during normal operation becomes slow.

JP 2008-205782 A

S. Cao et al., "Investigation on Output Driver with Stacked Devices for ESD Design Window Engineering", EOS / ESD 2010, pp. 203-210 M. Okumura et al., "CDM Secondary Clamp of RX and TX for High Speed SerDes Application in 40 nm CMOS Technology", EOS / ESD 2011, pp. 94-99

  An object of the present invention is to solve the above-described problems of the prior art, and to provide an ESD protection circuit that does not become a load during normal operation of a differential output buffer and has a small layout area.

In order to achieve the above object, the present invention provides an ESD protection circuit for protecting a differential output buffer from being destroyed by an overvoltage when an ESD event occurs,
A common mode voltage detection circuit that detects a common mode voltage of a differential output signal of the differential output buffer and outputs a common mode voltage detection signal; and
A detection signal is generated by detecting whether the voltage of the common mode voltage detection signal is a common mode voltage during normal operation or an overvoltage when the ESD event is higher than the common mode voltage during normal operation. An overvoltage detection circuit;
An off circuit that turns off the protected element of the differential output buffer when the ESD event occurs when the common signal detection signal indicates that the voltage of the common mode voltage detection signal is the overvoltage. An ESD protection circuit is provided.

Here, the differential output buffer is
A first differential switch and a second differential switch, one of which is turned on and the other is turned off in response to a differential input signal;
The power supply node is connected between the first differential switch and the second differential switch, and the resistance value changes according to the voltage of the first bias signal, so that the power supply voltage supplied to the power supply node A load resistor for supplying a lower voltage to the differential output buffer;
A current source connected between the first differential switch and the second differential switch and a ground node, and flowing a constant current corresponding to the voltage of a second bias signal to the differential output buffer;
The differential output signal is output from a first internal node between the load resistor and the first differential switch and a second internal node between the load resistor and the second differential switch. It is preferable.

Further, the common mode voltage detection circuit includes:
A first resistance element and a second resistance element connected in series between the first internal node and the second internal node and having the same resistance value;
In the current source, a reference voltage of a reference voltage signal is equal to a voltage of the common mode voltage detection signal output from a third internal node between the first resistance element and the second resistance element. It is preferable to provide an operational amplifier that adjusts the voltage of the second bias signal that controls the flowing current.

  Further, the overvoltage detection circuit includes a first MOS transistor having a gate oxide film having a thickness that is not destroyed even when the voltage of the common mode voltage detection signal becomes the overvoltage when the ESD event occurs, The threshold voltage of the first inverter formed of the first MOS transistor is preferably set to a voltage higher than the voltage during the normal operation.

Further, the overvoltage detection circuit includes the first MOS transistor, the first inverter that inverts and outputs the common mode voltage detection signal,
It is preferable to provide a second inverter that inverts an output signal of the first inverter and outputs the inverted signal as the detection signal.

Further, the protected element is the first differential switch, the second differential switch, and the current source configured by a second MOS transistor,
The off circuit controls the gate voltage of the second MOS transistor to turn off the second MOS transistor when the detection signal indicates that the voltage of the common mode voltage detection signal is the overvoltage. It is preferable.

The second MOS transistor is an N-type MOS transistor,
The off-circuit pulls down the voltage of the gate of the N-type MOS transistor to the ground voltage when the detection signal indicates that the voltage of the common-mode voltage detection signal is the overvoltage, and the N-type MOS transistor Is preferably turned off.

  In the present invention, the voltage of the common mode voltage detection signal is utilized in order to detect the application of overvoltage due to ESD. In many cases, the differential output buffer originally includes a common mode voltage detection circuit. Therefore, according to the present invention, this common mode voltage detection circuit is also used to detect the application of overvoltage by ESD, thereby preventing the application of overvoltage by ESD without increasing the layout area and the parasitic capacitance of the output node. Detection can be performed.

  Further, according to the present invention, the ESD withstand voltage can be improved by turning off the protected element of the differential output buffer when an ESD event occurs by utilizing the detection result of the overvoltage applied by the ESD. Can do. In addition, the present invention is not premised on the presence of a level shift circuit driven by a different power supply system in detecting the application of overvoltage by ESD, and therefore can be applied to a differential output buffer of a single power supply system.

It is a circuit diagram of one Embodiment showing the composition of the differential output buffer to which the ESD protection circuit of the present invention is applied. FIG. 3 is a circuit diagram illustrating an example of a configuration of a second protection circuit illustrated in FIG. 1. It is a conceptual diagram of an example showing the state at the time of ESD event generation | occurrence | production of the 3rd protection circuit shown in FIG. (A) And (B) is an example timing chart showing the operation | movement at the time of normal operation of the differential output buffer shown in FIG. It is a conceptual diagram of another example showing the state at the time of ESD event generation | occurrence | production of the 3rd protection circuit shown in FIG. (A), (B), (C), and (D) are timing charts showing an example of the operation of the differential output buffer shown in FIG. 1 when an ESD event occurs. It is an example circuit diagram showing the structure of the differential output buffer to which the conventional ESD protection circuit is applied. FIG. 8 is a circuit diagram of an example in which the vertically stacked NMOSs N2 and N1 of the differential output buffer shown in FIG. 7 are extracted and represented. This is an ESD protection circuit described in Patent Document 1. This is an ESD protection circuit described in Non-Patent Document 1. This is an ESD protection circuit described in Non-Patent Document 2.

  Hereinafter, an ESD protection circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a circuit diagram of an embodiment showing a configuration of a differential output buffer to which an ESD protection circuit of the present invention is applied. A differential output buffer 10 shown in the figure is mounted on a semiconductor integrated circuit, operates in response to differential input signals INN and INP input from a preceding circuit (not shown), and corresponds to the differential input signals INN and INP. Differential output signals OUTN and OUTP to be output, and includes two PMOSs P1 and P2, NMOS N1, two NMOSs N2 and N3, two resistance elements R1 and R2, and an operational amplifier OP.

PMOS P 1 and P 2 are load resistors of the differential output buffer 10. The sources of the PMOSs P1 and P2 are connected to the power supply node, and the first bias signal Pbias is input to the gates thereof.
In the differential output buffer 10, the resistance values of the load resistors of the PMOSs P1 and P2 change according to the voltage Pbias of the first bias signal, and a voltage lower than the power supply voltage VDD supplied from the external power supply terminal to the power supply node is Supplied.

The NMOS N1 is a current source that allows a constant current to flow through the differential output buffer 10. The source of the NMOS N1 is connected to the ground node, and the second bias signal Nbias is input from the operational amplifier OP to the gate thereof.
In the differential output buffer 10, a constant current flows to the ground node via the NMOS N1 according to the voltage Nbias of the second bias signal.

The NMOSs N2 and N3 are a first differential switch and a second differential switch in which one is turned on and the other is turned off according to the differential input signals INN and INP. The NMOSs N2 and N3 are connected between the PMOSs P1 and P2 and the NMOS N1, respectively, and differential input signals INN and INP are input to the gates thereof.
Differential output signals OUTP and OUTN are output from a first internal node between PMOSP1 and NMOSN2 and a second internal node between PMOSP2 and NMOSN3, and are connected to external output terminals, respectively.

The resistance elements R1 and R2 have the same resistance value, and are connected in series between the first internal node and the second internal node.
From the third internal node between the two resistance elements R1 and R2, a common mode voltage detection signal having a voltage that is ½ of the voltage of the differential output signal OUTP and the voltage of the differential output signal OUTN is output.

The operational amplifier OP generates a second bias signal. A reference voltage signal is input to the + terminal of the operational amplifier OP, and a common mode voltage detection signal is input to the − terminal.
The operational amplifier OP adjusts the voltage Nbias of the second bias signal that controls the current flowing through the NMOS N1 so that the reference voltage VREF of the reference voltage signal is equal to the voltage Vcom of the common mode voltage detection signal.

  Here, the resistance elements R1 and R2 and the operational amplifier OP detect the common mode voltage Vcom of the differential output signals OUTP and OUTN of the differential output buffer 10, and output the common mode voltage detection signal of the present invention. A detection circuit is configured.

  Subsequently, the ESD protection circuit protects the internal circuit of the semiconductor integrated circuit from being destroyed by an overvoltage at the time of occurrence of the ESD event, and includes a first protection circuit 12, a second protection circuit 14, and a third protection circuit. Circuit 16.

  The first protection circuit 12 causes an ESD current applied to the external output terminals of the differential output signals OUTP and OUTN to flow to the power supply node or the ground node when an ESD event occurs, and includes four diodes D1, D2, D3, D4 is provided.

  The diode D1 is connected in the forward direction from the differential output signal OUTP to the power supply node, and the diode D2 is connected in the forward direction from the ground node to the differential output signal OUTP. The diode D3 is connected in the forward direction from the differential output signal OUTN to the power supply node, and the diode D4 is connected in the forward direction from the ground node to the differential output signal OUTN.

  The second protection circuit 14 clamps the voltage VDD of the power supply node by causing an ESD current applied to the external output terminals of the differential output signals OUTP and OUTN to flow from the power supply node to the ground node when an ESD event occurs.

  FIG. 2 is a circuit diagram illustrating an example of the configuration of the second protection circuit illustrated in FIG. The second protection circuit 14 shown in the figure is an active clamp type, and includes an overvoltage detection circuit 18 and a clamp circuit 20.

  The overvoltage detection circuit 18 detects whether the voltage VDD of the power supply node is the power supply voltage VDD during normal operation or the power supply voltage VDD higher than that during normal operation, and outputs a detection signal. The RC time constant circuit 22 and the inverter 24 are included.

The RC time constant circuit 22 includes a resistance element R and a capacitance element C.
Resistive element R and capacitive element C are connected in series between the power supply node and the ground node. An output signal n1 of the RC time constant circuit 22 is output from the fourth internal node between the resistance element R and the capacitance element C.

The inverter 24 inverts and outputs the output signal n1 of the RC time constant circuit 22, and includes a PMOS P9 and an NMOS N9.
The PMOS P9 and the NMOS N9 are connected in series between the power supply node and the ground node, and the output signal n1 of the RC time constant circuit 22 is input to the gate thereof. A detection signal n0 that is an output signal of the inverter 24 is output from the fifth internal node between the PMOS P9 and the NMOS N9.

When the detection signal n0 indicates that the overcurrent is applied to the power supply node and, as a result, the voltage of the power supply node has risen sharply, the clamp circuit 20 is turned on to connect the power supply node and the ground node. An overcurrent applied to the power supply node is caused to flow to the ground node to clamp the voltage VDD of the power supply node, and includes an NMOS N10.
The NMOS N10 is connected between a power supply node and a ground node, and a detection signal n0 is input to its gate.

In the second protection circuit 14, during the normal operation, the capacitor C is charged to the power supply voltage VDD when the power supply voltage VDD is supplied to the power supply node. Therefore, the output signal n1 of the RC time constant circuit 22 is high level (H), the PMOS P9 of the inverter 24 is off, the NMOS N9 is on, the detection signal n0 is low level (L), and the NMOS N10 is off.
Therefore, the second protection circuit 14 does not affect the operation of the internal circuit that operates at the power supply voltage VDD during normal operation.

On the other hand, when an overcurrent is applied to the power supply node when an ESD event occurs, the voltage of the power supply node rises sharply, whereas the output signal n1 of the RC time constant circuit 22 is caused by the action of the RC time constant circuit 22. It rises more slowly than the power supply node. Therefore, the output signal n1 of the RC time constant circuit 22 is set to L during the time until the capacitive element C is charged to an overvoltage via the resistance element R, that is, the time corresponding to the time constant RC of the RC time constant circuit 22. Thus, the detection signal n0 becomes H for a time corresponding to the time constant RC, and the NMOS N10 is turned on.
Therefore, when an ESD event occurs, an ESD current applied to the power supply node flows to the ground node via the NMOS N10, and the voltage VDD of the power supply node is clamped, so that an internal circuit that operates at the power supply voltage VDD during normal operation is Can be protected.

  Subsequently, the third protection circuit 16 protects the NMOSs N1, N2, and N3 serving as the protected elements of the differential output buffer 10 from being destroyed by an overvoltage at the time of occurrence of the ESD event. And an off circuit.

  The overvoltage detection circuit 26 detects whether the voltage Vcom of the common mode voltage detection signal is the common mode voltage Vcom during normal operation or an overvoltage at the occurrence of an ESD event that is higher than the common mode voltage Vcom during normal operation. Output a detection signal INV_out, and includes a first inverter 28 and a second inverter 30.

The first inverter 28 inverts and outputs the common mode voltage detection signal, and includes a PMOS P4 and an NMOS N4.
The PMOS P4 and the NMOS N4 are connected in series between the power supply node and the ground node, and a common mode voltage detection signal is input to the gate thereof. The output signal INV_hvt_out of the first inverter 28 is output from the sixth internal node between the PMOSP4 and the NMOS N4 of the first inverter 28.
The PMOS P4 and the NMOS N4 constituting the first inverter 28 have a gate oxide film having a thickness (thick film) that is not destroyed even when the voltage Vcom of the common mode voltage detection signal becomes an overvoltage when an ESD event occurs. It is desirable to be composed of 1 MOS transistor. The threshold voltage Vth of the first inverter 28 is set to a voltage higher than the common mode voltage Vcom during normal operation.

Similarly, the second inverter 30 inverts and outputs the output signal INV_hvt_out of the first inverter 28, and includes a PMOS P5 and an NMOS N5.
The PMOS P5 and the NMOS N5 are connected in series between the power supply node and the ground node, and the output signal INV_hvt_out of the first inverter 28 is input to the gate thereof. A detection signal INV_out that is an output signal of the second inverter 30 is output from a seventh internal node between the PMOSP5 and the NMOS N5 of the second inverter 30.

  When the detection signal INV_out indicates that the voltage Vcom of the common mode voltage detection signal is an overvoltage, the off circuit includes gates of NMOS N1, N2, and N3 that are protected elements of the differential output buffer 10 when an ESD event occurs. Is forcibly turned off, and includes three NMOSs N6, N7, and N8 serving as pull-down circuits.

  The NMOSs N6 and N7 are respectively connected between the differential input signals INN and INP and the ground node, and the NMOS N8 is connected between the second bias signal and the ground node. The detection signal INV_out is input to the gates of the NMOSs N6, N7, and N8.

  Next, the operation of the differential output buffer 10 will be described.

First, with reference to FIGS. 3, 4A and 4B, operations of the differential output buffer 10 and the ESD protection circuit during normal operation will be described.
As shown in FIG. 4A, the power supply voltage VDD during normal operation is VDD = 1.2V and the ground voltage VSS = 0V, and the common mode voltage detection circuit uses the common mode voltage detection signal voltage Vcom = (1.2V + 0V). ) / 2 is assumed to be controlled to 0.6V. Further, it is assumed that the threshold voltage Vth of the first inverter 28 of the third protection circuit 16 is set to 0.7V.

  In this case, since the voltages of the external output terminals of the differential output signals OUTP and OUTN are voltages from the ground voltage VSS = 0V to the power supply voltage VDD = 1.2V, the four diodes D1 and D2 of the first protection circuit 12 are used. , D3, and D4 are all off.

  When the voltage VDD of the power supply node is the power supply voltage VDD at normal operation = 1.2V, the NMOS N10 of the clamp circuit 20 of the second protection circuit 14 is in an off state.

  The voltage Vcom = 0.6V of the common mode voltage detection signal is lower than the threshold voltage Vth = 0.7V of the first inverter 28 of the third protection circuit 16. Therefore, as shown in FIG. 4B, the output signal INV_hvt_out of the first inverter 28 becomes high level (High) = 1.2 V, and the detection signal INV_out output from the second inverter 30 is low level (Low) = 0V. As a result, the NMOSs N6, N7, and N8 in the off circuit are all turned off.

  Thus, during normal operation, all of the first protection circuit 12, the second protection circuit 14, and the third protection circuit 16 are in an off state, and the ESD protection circuit has no influence on the normal operation of the differential output buffer 10. Don't give.

  During normal operation, a voltage lower than the power supply voltage VDD = 1.2V is supplied from the power supply node via the load resistors PMOSP1 and P2 in accordance with the voltage Pbias of the first bias signal. Is output.

  Further, the operational amplifier OP generates a second bias signal for controlling the current flowing through the differential output buffer 10 so that the reference voltage VREF of the reference voltage signal is equal to the voltage Vcom of the common mode voltage detection signal. That is, a current corresponding to the voltage Nbias of the second bias signal flows through the differential output buffer 10 via the NMOS N1 as the current source. As a result, the voltage Vcom of the common mode voltage detection signal is equal to the reference voltage of the reference voltage signal. Controlled to a voltage equal to VREF.

  When the differential input signal INN is at a high level, that is, when the differential input signal INP is at a low level, the NMOS N2 of the first differential switch is turned on and the NMOS N3 of the second differential switch is turned off. In this case, a current flows from the power supply node to the ground node via the PMOSs P1 and P2, the resistance elements R1 and R2, and the NMOSs N2 and N1. As a result, the differential output signal OUTP is at a low level and the differential output signal OUTN is at a high level.

  The operation is the same when the differential input signal INP is at high level, that is, when the differential input signal INN is at low level.

Next, operations of the differential output buffer 10 and the ESD protection circuit when an ESD event occurs will be described with reference to FIGS. 5 and 6A, 6B, 6C, and 6D.
When an ESD event occurs, as shown in FIG. 6A, when an overcurrent due to ESD is applied to the differential output signal OUTP at time 1 ns with reference to the external ground terminal, the ESD current is As a voltage drop occurs through the second protection circuit 14, the voltage Vclamp = between the external output terminal and the external ground terminal of the differential output signal OUTP at time 10ns as shown in FIG. 6B. It shall be 6.9V.

  In this case, the diode D1 of the first protection circuit 12 is turned on, and the overcurrent generated in the power supply node due to the ESD current flowing through the first protection circuit 12 causes the first diode D1 as shown in FIG. For example, the voltage VDD of the power supply node becomes 4.8V.

  When the voltage VDD of the power supply node becomes 4.8 V, the rise is steep, so that the NMOS N10 of the clamp circuit 20 of the second protection circuit 14 is turned on. As a result, the ESD current is released from the external output terminal of the differential output signal OUTP to the external ground terminal via the first diode D1, the power supply node, the second protection circuit 14, and the ground node. As a result, the voltage VDD of the power supply node is clamped, and the internal circuit of the semiconductor integrated circuit operating at the power supply voltage VDD during normal operation is protected.

  Thus, when an ESD event occurs, the first protection circuit 12 and the second protection circuit 14 are turned on, and the internal circuit of the semiconductor integrated circuit that operates at the power supply voltage VDD during normal operation is protected.

  In addition, when an overvoltage due to ESD occurs at the external output terminal of the differential output signal OUTP, the voltage Vcom of the common mode voltage detection signal becomes the minimum value because both the NMOS N3 and N1 are strongly on. This is a case where the dynamic output signal OUTN is at a low level (= 0V). At this time, if the voltage between the external output terminal and the external power supply terminal of the differential output signal OUTP is Vdio, and the voltage between the external power supply terminal and the external ground terminal is Vpc, Vcom≈ (Vclamp + 0V) / 2 = ( Vdio + Vpc) / 2.

  Therefore, if Vdio / 2 is largely adjusted within a range that does not exceed the breakdown voltage of the MOS transistor due to a voltage drop due to the first diode D1 of the first protection circuit 12, Vcom ≧ Vpc / 2 can always be established when an overvoltage is applied. . In the present embodiment, when an overvoltage is applied by ESD, the voltage Vcom of the common mode voltage detection signal is at least Vcom = (Vclamp + 0V) / 2 = (6.9V + 0V) /, as shown in FIG. It takes a value of 2 ≧ 3.8V.

  When the voltage VDD of the power supply node when the ESD event occurs is 4.8V, the threshold voltage Vth of the first inverter 28 of the third protection circuit 16 is 4.8V * 0.7V as shown in FIG. /1.2V=2.83V or so.

  Therefore, when Vcom ≧ 3.8V is input to the first inverter 28, as shown in FIG. 6C, when Vcom = Vth = 2.83V, the output signal INV_hvt_out of the first inverter 28 is low level. The detection signal INV_out output from the second inverter 30 is at a high level. As a result, the NMOSs N6, N7, and N8 in the off circuit are turned on, and the NMOSs N1, N2, and N3 are, as shown in FIG. 6D, the voltage Nbias of the second bias signal and the voltages of the differential input signals INN and INP. Is pulled down to the ground voltage VSS and becomes a low level, so that it is forcibly turned off.

  As a result, as shown in Table 1, the ESD withstand voltage of the NMOSs N2 and N1 is improved to 9.6V. Therefore, when the voltage Vclamp = 6.9V, the NMOSs N1, N2, and N3 are protected against the overvoltage applied by the ESD. can do.

Here, when the ESD event occurs, the time Toff is estimated from when the overvoltage due to ESD is applied until the NMOSs N1, N2, and N3 are turned off.
Since the delay time of the first inverter 28 and the second inverter 30 is small, the time required for the voltage Vcom of the common mode voltage detection signal to rise is dominant. Considering the RC time constant of the voltage Vcom of the common mode voltage detection signal, the time Toff is estimated to be about Toff≈ (resistance value of the resistance elements R1 and R2) × (capacitance value of the capacitive component that appears in the common mode voltage detection signal). It is.

In this embodiment, assuming that the resistance values of the resistance elements R1 and R2 are 30 kΩ and the capacitance value of the capacitive component that appears in the common mode voltage detection signal is 30 pF, it is estimated that Toff = 30 kΩ × 50 pF = 900 ps. The gate of the first inverter 28 can be controlled sufficiently faster than the rise time of the overvoltage application due to the ESD.
Further, the time Toff can be further reduced by adjusting the resistance values of the resistance elements R1 and R2 and the capacitance value of the capacitance component that appears in the common mode voltage detection signal.

  The ESD protection circuit of the present embodiment uses the voltage Vcom of the common mode voltage detection signal in order to detect application of an overvoltage due to ESD. In many cases, the differential output buffer originally includes a common mode voltage detection circuit. Therefore, by utilizing this common mode voltage detection circuit for detection of overvoltage application by ESD, it is possible to detect application of overvoltage by ESD without increasing the layout area and the parasitic capacitance of the output node. .

  Then, by utilizing the detection result of the overvoltage applied by the ESD, the ESD withstand voltage is improved by turning off the NMOS N1, N2, and N3 which are the protected elements of the differential output buffer 10 when the ESD event occurs. Can be made. In addition, the ESD protection circuit of the present embodiment does not assume the presence of a level shift circuit driven by a different power supply system in detecting the application of overvoltage by ESD, and therefore can be applied to a differential output buffer of a single power supply system. Is possible.

Note that the ESD protection circuit of this embodiment operates in the same manner when an overvoltage at the time of occurrence of an ESD event is applied to the external output terminal of the differential output signal OUTN with the external ground terminal as a reference.
Further, the differential output buffer is not limited to the one shown in FIG. 1, and any of various configurations including a load resistor, a differential switch, and a current source can be used.
The overvoltage detection circuit and the off-circuit of the third protection circuit are not limited to those shown in FIG. 1, and can be configured by circuits having various configurations that perform the same function.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 Differential output buffer 12 1st protection circuit 14 2nd protection circuit 16 3rd protection circuit 18, 26 Overvoltage detection circuit 20 Clamp circuit 22 RC time constant circuit 24 Inverter 28 1st inverter 30 2nd inverter P1, P2, P4, P5, P9 PMOS
N1, N2, N3, N4, N5, N6, N7, N8, N9, N10 NMOS
R1, R2, R Resistance element OP Operational amplifier D1, D2, D3, D4 Diode C Capacitance element

Claims (7)

An ESD protection circuit for protecting a differential output buffer from being destroyed by an overvoltage at the time of occurrence of an ESD event,
A common mode voltage detection circuit that detects a common mode voltage of a differential output signal of the differential output buffer and outputs a common mode voltage detection signal; and
A detection signal is generated by detecting whether the voltage of the common mode voltage detection signal is a common mode voltage during normal operation or an overvoltage when the ESD event is higher than the common mode voltage during normal operation. An overvoltage detection circuit;
An off circuit that turns off the protected element of the differential output buffer when the ESD event occurs when the common signal detection signal indicates that the voltage of the common mode voltage detection signal is the overvoltage. A featured ESD protection circuit. The differential output buffer is
A first differential switch and a second differential switch, one of which is turned on and the other is turned off in response to a differential input signal;
The power supply node is connected between the first differential switch and the second differential switch, and the resistance value changes according to the voltage of the first bias signal, so that the power supply voltage supplied to the power supply node A load resistor for supplying a lower voltage to the differential output buffer;
A current source connected between the first differential switch and the second differential switch and a ground node, and flowing a constant current corresponding to the voltage of a second bias signal to the differential output buffer;
The differential output signal is output from a first internal node between the load resistor and the first differential switch and a second internal node between the load resistor and the second differential switch. The ESD protection circuit according to claim 1, wherein The common mode voltage detection circuit includes:
A first resistance element and a second resistance element connected in series between the first internal node and the second internal node and having the same resistance value;
In the current source, a reference voltage of a reference voltage signal is equal to a voltage of the common mode voltage detection signal output from a third internal node between the first resistance element and the second resistance element. The ESD protection circuit according to claim 2, further comprising an operational amplifier that adjusts a voltage of a second bias signal that controls a flowing current.   The overvoltage detection circuit includes a first MOS transistor having a gate oxide film having a thickness that is not destroyed even when the voltage of the common mode voltage detection signal becomes the overvoltage when the ESD event occurs. 4. The ESD protection circuit according to claim 3, wherein a threshold voltage of the first inverter configured by 1 MOS transistor is set to a voltage higher than the voltage during the normal operation. The overvoltage detection circuit is composed of the first MOS transistor, the first inverter that inverts and outputs the common mode voltage detection signal,
The ESD protection circuit according to claim 4, further comprising: a second inverter that inverts an output signal of the first inverter and outputs the inverted signal as the detection signal. The protected element is the first differential switch, the second differential switch, and the current source configured by a second MOS transistor,
The off circuit controls the gate voltage of the second MOS transistor to turn off the second MOS transistor when the detection signal indicates that the voltage of the common mode voltage detection signal is the overvoltage. The ESD protection circuit according to claim 4 or 5, wherein the ESD protection circuit is one. The second MOS transistor is an N-type MOS transistor,
The off-circuit pulls down the voltage of the gate of the N-type MOS transistor to the ground voltage when the detection signal indicates that the voltage of the common-mode voltage detection signal is the overvoltage, and the N-type MOS transistor 7. The ESD protection circuit according to claim 6, wherein the ESD protection circuit is turned off.