JP2016151830A - Design support device, design support method and design support program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow an interface or bridge connecting among hardware modules to be inserted.SOLUTION: A function model analysis unit 2 is configured to analyze a function program 5, and extract input/output relations among hardware modules in a plurality of hardware modules. An I/F library 4 is configured to store, as modular interfaces, a plurality of descriptions each in a format capable of a high-level synthesis encapsulating interface functions of interfaces or bridges among the hardware modules, and input/output ports. An I/F insertion unit 3 is configured to select the modular interfaces for each input/output relation among the hardware modules extracted by the function model analysis unit 2. Further, the I/F insertion unit 3 is configured to insert the descriptions of the selected modular interfaces into the function model program 5 to convert the function program 5 to a program 8 capable of the high-level synthesis.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technology for supporting LSI (Large Scale Integration) design.

Conventionally, in LSI development, design using a hardware description language such as Verilog-HDL or VHDL has been mainly performed.
However, with the recent increase in scale of integrated circuits, it takes a lot of time to design hardware description, and C language, C ++ language, and System C language, which have a higher level of abstraction than hardware description language, have become a problem. A technique for shortening design time by applying a high-level design in which a hardware description language is automatically generated using a high-level synthesis tool is designed.
Normally, in LSI development, first, in order to confirm the algorithm of calculation and control, an algorithm description written in C language or C ++ language is prepared, or a calculation function or control function to be realized by hardware is implemented by hardware. In order to confirm the operation in accordance with the processing unit, a function program description written in C language or C ++ language is prepared.
However, these program descriptions do not include the concept of hardware such as the concept of time or parallel operation.
Therefore, in the high-level design, in order to confirm the operation including the time concept and the parallel operation between hardware modules (also referred to as modules), the program can be verified by changing to a program in which the hardware concept is inserted at the transaction level. In order to generate a hardware description by a high-level synthesis tool, a high-level synthesis is performed by changing to a program in which a hardware concept at a cycle level is inserted.
At this time, in order to change from the algorithm description or the function program description, it is necessary to manually insert a description of an interface (also referred to as I / F) for connecting a circuit and a bus and rewrite the program.

  Patent Document 1 performs a conversion process from an algorithm description to a description capable of high-level synthesis. In the algorithm description, by specifying a parameter to be an input / output port, the description of the input / output port is inserted, and high-level synthesis is performed. It describes automatic conversion into a possible hardware description.

JP 2013-20329 A

In the technique of Patent Document 1, it is possible to insert a description of an input / output port by instructing a parameter existing in the original description as an input / output.
However, the algorithm description and the function program description do not describe input / output and variables that are not related to the operation and control of the module, and therefore do not describe various control signals included in the interface.
Therefore, the technique of Patent Document 1 cannot automatically insert an interface.

  The present invention has been made in view of such circumstances, and a main object of the present invention is to make it possible to insert an interface or a bridge for connecting hardware modules.

A design support apparatus according to the present invention includes:
An analysis extraction unit that analyzes a function program and extracts an input / output relationship between hardware modules in a plurality of hardware modules;
A modular interface storage unit for storing a plurality of high-level synthesizable descriptions in which interface functions between hardware modules or bridge interface functions and input / output ports are encapsulated as modular interfaces;
A selection unit that selects a modular interface for each input / output relationship between the hardware modules extracted by the analysis extraction unit;
A program conversion unit for inserting a description of the modular interface selected by the selection unit into the function program and converting the function program into a program capable of high-level synthesis.

In the present invention, for each input / output relationship between hardware, a modular interface described in a high-level synthesizable form in which an interface function or an interface function of a bridge or an input / output port is encapsulated is selected, and the description of the selected modular interface is performed. Is inserted into the function program.
Therefore, according to the present invention, an interface or a bridge can be inserted into a function program by inserting a description of a modular interface into the function program.

FIG. 3 is a diagram illustrating a functional configuration example of an inter-module I / F design support apparatus according to the first embodiment. FIG. 3 shows a configuration example of a modular I / F according to the first embodiment. FIG. 3 is a diagram illustrating a description example of a modular I / F according to the first embodiment. FIG. 3 is a diagram showing a schematic configuration example of an LSI according to the first embodiment. FIG. 6 is a diagram showing a description example of top description of a function program according to the first embodiment. FIG. 6 is a diagram showing a description example of a YUV → RGB format conversion module and a screen composition module of the function program according to the first embodiment. FIG. 6 is a diagram illustrating a description example of I / F selection information according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of an LSI in which a modular I / F is inserted into an inter-module I / F according to the first embodiment. The figure which shows the example of description of the top description of the high level synthesis | combination possible program which concerns on Embodiment 1. FIG. FIG. 6 is a diagram illustrating a description example of a YUV → RGB format conversion module and a screen composition module of a program capable of high-level composition according to Embodiment 1; FIG. 3 is a diagram showing an LSI configuration example in which different bus protocols are connected according to the first embodiment. The figure which shows the example of description of I / F selection information and top description which connect between the different bus protocols which concern on Embodiment 1 concerning Embodiment 1. FIG. FIG. 10 is a diagram illustrating an example of a functional configuration of an inter-module I / F design support apparatus according to the second embodiment. FIG. 9 is a flowchart showing performance improvement steps according to the second embodiment. FIG. 3 is a diagram illustrating a hardware configuration example of an inter-module I / F design support apparatus according to the first embodiment and the second embodiment.

Embodiment 1 FIG.
In this embodiment, in LSI development, I / Fs and bridges that connect hardware modules to which each function is assigned are automatically inserted based on a C / C ++ description program created for function confirmation. A configuration for supporting conversion to a transaction level program description used in high-level verification or a cycle-level program description capable of high-level synthesis will be described.

*** Explanation of configuration ***
FIG. 1 shows a configuration of an inter-module I / F design support apparatus 1 according to the first embodiment.
The inter-module I / F design support apparatus 1 includes a functional model analysis unit 2, an I / F insertion unit 3, and an I / F library 4.
The inter-module I / F design support apparatus 1 corresponds to an example of the design support apparatus of the present application.

The function model analysis unit 2 analyzes the function program and extracts an input / output relationship between hardware modules in a plurality of hardware modules.
The function model analysis unit 2 corresponds to an example of an analysis extraction unit.
The function program 5 is a program in which LSI functions are described in C or C ++.
The functional model analysis unit 2 includes a top configuration analysis unit 2a, a module input / output analysis unit 2b, and an inter-module connection analysis unit 2c.
The top configuration analysis unit 2 a analyzes the top configuration of hardware from the top description of the function program 5.
The module input / output analysis unit 2b analyzes and extracts input / output signals of each hardware module.
The inter-module connection analysis unit 2c analyzes and extracts information on the connection relationship between module inputs and outputs, and outputs input / output signal / connection information 6 representing the analysis and extraction results.

The I / F library 4 stores a plurality of modular interfaces (also referred to as modular I / Fs) that are insertion candidates.
The modular I / F is a description of a high-level synthesizable form in which interface functions between modules or bridge interface functions and input / output ports are encapsulated.
Details of the modular I / F will be described later.
The I / F library 4 corresponds to an example of a modular interface storage unit.

The I / F insertion unit 3 acquires interface selection information 7 (also expressed as I / F selection information 7).
In the I / F selection information 7, a plurality of input / output relationships are described, and a modular I / F to be selected is described for each described input / output relationship.
The I / F insertion unit 3 selects the corresponding modular I / F described in the I / F selection information 7 for each input / output relationship between the hardware modules extracted by the functional model analysis unit 2. To do.
Also, the I / F insertion unit 3 uses the description of the selected modular I / F to include a module description describing the function of the module included in the function program 5 and a function of a circuit composed of a plurality of modules. By rewriting the top description in which is described, the description of the selected modular I / F is inserted into the function program 5 to convert the function program 5 into a program 8 capable of high-level synthesis.
The high-level synthesizable program 8 is described in SystemC.
The I / F insertion unit 3 corresponds to an example of a selection unit and a program conversion unit.
The I / F insertion unit 3 includes an I / F selection information analysis unit 3a, a module description generation unit 3b, and a top description generation unit 3c.
The I / F selection information analysis unit 3a analyzes and associates signal names between modules and modular I / F names from the I / F selection information 7.
The module description generation unit 3b acquires a modular I / F from the I / F library 4 and converts the module description into a program description that can be synthesized at a high level.
The top description generation unit 3 c inserts a modular I / F into the top description of the function program 5.

Here, the modular I / F will be described.
2 shows a configuration example of the modular I / F stored in the I / F library 4, and FIG. 3 shows a description example of the modular I / F.
2 and 3, the modular I / F is a class that encapsulates an I / F function and an input / output port. The module instantiates a class of the modular I / F to be used, and the I / F function. Can be accessed without being aware of input / output ports and protocols.

*** Explanation of operation ***
Next, a method for inserting a modular I / F between modules by the inter-module I / F design support apparatus 1 according to the present embodiment will be described with reference to FIGS.
The following method corresponds to an example of the design support method and design support program of the present application.

FIG. 4 shows a schematic configuration example of an LSI.
5 and 6 show a description example of the function program 5 representing the LSI configuration of FIG.
FIG. 7 shows a description example of the I / F selection information 7.
FIG. 8 shows a schematic configuration example of an LSI after a modular I / F is inserted between modules.
9 and 10 show a description example of the program 8 that can be synthesized at a high level obtained by the inter-module I / F design support apparatus 1.

In the case of the LSI shown in FIG. 4, the YUV format pixel data input from the “preprocessing module” is converted into RGB format pixel data by the “YUV → RGB conversion module” and output.
Then, the pixel data is input and the “screen composition module” generates and outputs pixel data synthesized by two systems, and the “RGB → YUV conversion module” converts the pixel data into pixel data in the YUV format. Output to “Post-processing module”.
When this is described in the function program 5, as shown in FIGS. 5 and 6, only data necessary for the function (arithmetic processing) of each module is transferred between the modules as input / output of the module.

  Taking the LSI configuration of FIG. 4 as an example, a procedure for inserting a modular I / F between modules will be described.

First, the top configuration analysis unit 2a analyzes the top configuration from the top description of FIG. 5A (FIG. 5 (1)), and the module input / output analysis unit 2b analyzes each module of FIGS. 6B and 6C. Input / output signals are extracted from the description ((2) in FIG. 6) (analysis extraction step).
More specifically, the module input / output analysis unit 2b extracts the argument and return value of the function in the top function inside the class (the top function is designated from the outside).
This is an input / output signal.
The return value is an output signal.
Arguments are input signals except for pointers.
In the case of a pointer, if there is only a pointer reference inside the function, it becomes an input signal.
In addition, when assigning to a pointer, it becomes an output signal.
It should be noted that the case where pointer reference and substitution are performed is not supported in this specification.

Subsequently, the inter-module connection analysis unit 2c analyzes the connection relation between the module inputs and outputs based on the input / output signal information of the top function of each class extracted by the module input / output analysis unit 2b (FIG. 5). (3)), the input / output signal / connection information 6 is output (analysis extraction step).
That is, the inter-module connection analysis unit 2c extracts connection information from the top description ((3) in FIG. 5) of the function program 5.
The inter-module connection analysis unit 2c interprets the functions having the same signal name as the return value and argument in the return value and argument to the top function of each class as connected.
The inter-module connection analysis unit 2c interprets that “pre-processing 0” and “YUV → RGB conversion (m_Fmt0)” are connected in the configuration of FIG. .
Further, “preprocessing 1” and “YUV → RGB conversion (m_Fmt1)” are connected, and it is interpreted that these two modules have an input / output relationship.
Similarly, the inter-module connection analysis unit 2c interprets that there is an input / output relationship between modules connected by arrows in FIG.

Next, the I / F selection information analysis unit 3a analyzes the signal name between modules and the modular I / F name from the input / output signal / connection information 6 and the I / F selection information 7 of FIG. 7 (FIG. 7). (4))), the association is performed (selection step).
The input / output signal / connection information 6 includes an input / output relationship between modules, that is, a signal shown on the left side of FIG. 7 (for example, s_yuv0), an output source module of the signal (for example, preprocessing 0), and an input The previous module (YUV → RGB conversion (m_Fmt0)) is described.
The I / F selection information analysis unit 3a converts the modular I / F (Mif_BusYuv) corresponding to the signal (for example, s_yuv0) indicated by the input / output signal / connection information 6 to the output source indicated by the input / output signal / connection information 6. Are associated with an input destination module (YUV → RGB conversion (m_Fmt0)).
As described above, the modular I / F is a class that encapsulates an I / F function and an input / output port. Therefore, if the class name of the modular I / F used as shown in FIG. A modular I / F can be uniquely determined from within.

Next, the module description generation unit 3b acquires the modular I / F from the I / F library 4 based on the association by the I / F selection information analysis unit 3a, and the module description I / F of the function program 5 The description portion is rewritten ((5) in FIG. 10) (program conversion step).
Further, the top description generation unit 3c inserts a modular I / F instance and connection into the top description of the function program 5 ((6) in FIG. 9), and outputs a program 8 capable of high-level synthesis of the SystemC description (program) Conversion step).

FIG. 8 is a configuration example of an LSI corresponding to the high-level synthesizable program 8 output from the top description generation unit 3c.
In FIG. 8, the modular I / F (m_mif_yuv0 etc.) selected by the I / F selection information analysis unit 3a is inserted between the modules.
Note that “m_mif_yuv0”, “m_mif_yuv”, and “m_mif_yuv2” in FIG. 8 are instances of “Mif_BusYuv” in FIG.
Also, “m_mif_rgb0”, “m_mif_rgb1”, and “m_mif_rgb2” in FIG. 8 are instances of “Mif_BusRgb” in FIG.
In FIG. 8, “M” means a master and “S” means a slave.

*** Explanation of effects ***
As described above, if the inter-module I / F design support apparatus 1 according to the present embodiment is used, it is possible to generate an I / F that connects modules of C language descriptions that do not include protocol information and the like. The design procedure can be made more efficient.

FIG. 11 shows an example of LSI configuration when different bus protocols are connected.
More specifically, FIG. 11A shows an LSI configuration example before the modular I / F is inserted, and FIG. 11B shows an LSI configuration example after the modular I / F is inserted.
FIG. 12 shows an example of I / F selection information and a top description example of a high-level synthesizable program obtained from the LSI function program of FIG.
As shown in the LSI configuration of FIG. 11A, for example, when pixel data after RGB → YUV conversion is stored in an external memory, the master side and the slave side of the inter-module I / F as shown in FIG. When the protocols are different, the master side and slave side buses are designated as I / F selection information as shown in FIG.
In this case, a modular I / F including a bus bridge capable of connecting both protocols is selected from the I / F library 4 to generate a top description as shown in FIG.

  As described above, by using the inter-module I / F design support apparatus 1 of the present invention, it is possible to insert a bridge that connects different bus protocols, and the high-level design procedure can be made efficient.

  In the above description, the case where a program description capable of high-level synthesis is obtained has been described. If a transaction level modular I / F is selected based on I / F selection information, a transaction level program description used for high-level verification can be obtained. You can also.

Embodiment 2. FIG.
*** Explanation of configuration ***
FIG. 13 shows the configuration of the inter-module I / F design support apparatus 1 according to the second embodiment.
The inter-module I / F design support apparatus 1 according to this embodiment includes a functional model analysis unit 2, an I / F insertion unit 3, an I / F library 4, and a performance improvement unit 9.

The function model analysis unit 2, the I / F library 4, the function program 5, the I / F selection information 7, and the program 8 capable of high-level synthesis are the same as those shown in the first embodiment.
Also in the present embodiment, the function model analysis unit 2 corresponds to an example of an analysis extraction unit, and the I / F library 4 corresponds to an example of a modular I / F storage unit.

The I / F insertion unit 3 has the same configuration as that of the first embodiment, but in this embodiment, the I / F insertion unit 3 is connected to the I / F via the performance improvement unit 9. The selection information 7 is acquired, and the modular I / F is acquired from the I / F library 4 via the performance improvement unit 9.
In the present embodiment, the I / F insertion unit 3 corresponds to an example of a program conversion unit.

The performance improvement unit 9 performs high-level synthesis (or high-level synthesis + logic synthesis) and performance analysis using the outputted program 8 capable of high-level synthesis.
The performance improvement unit 9 can change the parameter of the modular I / F used for the conversion to the program 8 capable of high-level synthesis when the performance in the high-level synthesis execution result does not satisfy the required performance, or high-level synthesis is possible. A process for switching the modular I / F used for the conversion to the correct program 8 to another modular I / F is performed.
Specifically, the performance improvement unit 9 uses the modular I / O used for conversion to the program 8 capable of high-level synthesis when the transfer bit amount in the high-level synthesis execution result does not satisfy the required performance for the transfer bit amount. Processing for changing the data width of F is performed.
The performance improvement unit 9 also has a circuit scale larger than the modular I / F used for conversion to the program 8 capable of high-level synthesis when the circuit scale in the high-level synthesis execution result does not satisfy the required performance for the circuit scale. A process of switching to another modular I / F having a small value is performed.
The performance improvement unit 9 corresponds to an example of a selection unit and an adjustment processing unit.

  In the present embodiment, the I / F insertion unit 3 writes the description of the modular I / F after the parameter is changed by the performance improvement unit 9 or the description of the modular I / F after the switching by the performance improvement unit 9. The function program 5 is inserted into the function program 5 and converted into a program 8 capable of high-level synthesis.

*** Explanation of operation ***
FIG. 14 is a flowchart showing the performance improvement steps in the performance improvement unit 9.

In S <b> 0, the performance improvement unit 9 acquires various modular I / Fs indicated by the I / F selection information 7 from the I / F library 4.
Next, in S1, the performance improvement unit 9 inserts a transfer bit amount counter in the descriptions of various modular I / Fs acquired in S0.
Next, in S2, the performance improvement unit 9 passes the I / F selection information 7 and the modular I / F rewritten in S1 to the I / F insertion unit 3.
Next, in S <b> 3, the performance improvement unit 9 acquires the high-level synthesizable program 8 generated by the I / F insertion unit 3.

Next, in S4, the performance improvement unit 9 performs high-level synthesis (+ logical synthesis) using the program 8 capable of high-level synthesis acquired in S3, and estimates the circuit scale.
Next, in S5, the performance improvement unit 9 compares the required circuit scale indicated by the required performance information 10 with the circuit scale estimation result obtained in S4.
In the comparison of S5, if the circuit scale estimation does not satisfy the required circuit scale (NO in S6), the performance improvement unit 9 selects a modular I / F having a smaller circuit scale in the I / F library 4 in S7. The I / F selection information 7 is rewritten as described above.
Further, the performance improvement unit 9 records in the I / F change record 11 that the I / F selection information 7 has been rewritten.
On the other hand, if the circuit size estimate satisfies the required circuit size in the comparison in S5 (YES in S6), the performance improvement unit 9 executes a simulation in S8 using the high-level synthesizable program 8 acquired in S3. The transfer bit amount of each modular I / F is counted.
Next, in S9, the performance improvement unit 9 compares the requested transfer bit amount of each modular I / F indicated by the required performance information 10 with the count result obtained in S8.
If the transfer bit count amount does not satisfy the requested transfer bit amount in the comparison in S9 (NO in S10), the performance improvement unit 9 determines the data width of the modular I / F acquired from the I / F library 4 in S11. change.
Further, the performance improvement unit 9 records in the I / F change record 11 that the data width of the modular I / F has been changed.
On the other hand, if the transfer bit count amount satisfies the required transfer bit amount in the comparison of S9 (YES in S0), the performance improvement is terminated.

*** Explanation of effects ***
As described above, when the inter-module I / F design support apparatus 1 according to the second embodiment is used, even when the modular I / F assumed by the user cannot satisfy the performance, an appropriate modular I / F is automatically obtained. Since it can be inserted, the high-level design procedure can be made efficient.

*** Explanation of hardware configuration ***
Finally, a hardware configuration example of the inter-module I / F design support apparatus 1 will be described with reference to FIG.
The inter-module I / F design support apparatus 1 is a computer.
The inter-module I / F design support apparatus 1 includes hardware such as a processor 901, an auxiliary storage device 902, a memory 903, a communication device 904, an input interface 905, and a display interface 906.
The processor 901 is connected to other hardware via the signal line 910, and controls these other hardware.
The input interface 905 is connected to the input device 907.
The display interface 906 is connected to the display 908.

The processor 901 is an IC (Integrated Circuit) that performs processing.
The processor 901 is, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or a GPU (Graphics Processing Unit).
The auxiliary storage device 902 is, for example, a ROM (Read Only Memory), a flash memory, or an HDD (Hard Disk Drive).
The memory 903 is, for example, a RAM (Random Access Memory).
The communication device 904 includes a receiver 9041 that receives data and a transmitter 9042 that transmits data.
The communication device 904 is, for example, a communication chip or a NIC (Network Interface Card).
The input interface 905 is a port to which the cable 911 of the input device 907 is connected.
The input interface 905 is, for example, a USB (Universal Serial Bus) terminal.
The display interface 906 is a port to which the cable 912 of the display 908 is connected.
The display interface 906 is, for example, a USB terminal or an HDMI (registered trademark) (High Definition Multimedia Interface) terminal.
The input device 907 is, for example, a mouse, a keyboard, or a touch panel.
The display 908 is, for example, an LCD (Liquid Crystal Display).

The auxiliary storage device 902 includes a function model analysis unit 2 and an I / F insertion unit 3 shown in FIG. 1, and a performance improvement unit 9 (hereinafter, function model analysis unit 2, I / F insertion unit 3 and performance improvement shown in FIG. A program for realizing the function of the part 9 is collectively described as “part” is stored.
This program is loaded into the memory 903, read into the processor 901, and executed by the processor 901.
Further, the auxiliary storage device 902 also stores an OS (Operating System).
Then, at least a part of the OS is loaded into the memory 903, and the processor 901 executes a program that realizes the function of “unit” while executing the OS.
Although one processor 901 is illustrated in FIG. 15, the inter-module I / F design support apparatus 1 may include a plurality of processors 901.
A plurality of processors 901 may execute a program for realizing the function of “unit” in cooperation with each other.
In addition, information, data, signal values, and variable values indicating the processing results of “unit” are stored in the memory 903, the auxiliary storage device 902, or a register or cache memory in the processor 901.

Further, “part” may be read as “circuit”, “step”, “procedure”, or “processing”.
The “circuit” is a concept that includes not only the processor 901 but also other types of processing circuits such as a logic IC, GA (Gate Array), ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array). .

  1 Inter-module I / F design support device, 2 function model analysis unit, 2a top configuration analysis unit, 2b module input / output analysis unit, 2c inter-module connection analysis unit, 3 I / F insertion unit, 3a I / F selection information analysis Part, 3b module description generation part, 3c top configuration description generation part, 4 I / F library, 5 function program, 6 I / O signal / connection information, 7 I / F selection information, 8 high-level synthesis program, 9 performance improvement Part, 10 required performance information, 11 I / F change record.

Claims (7)

An analysis extraction unit that analyzes a function program and extracts an input / output relationship between hardware modules in a plurality of hardware modules;
A modular interface storage unit for storing a plurality of high-level synthesizable descriptions in which interface functions between hardware modules or bridge interface functions and input / output ports are encapsulated as modular interfaces;
A selection unit that selects a modular interface for each input / output relationship between the hardware modules extracted by the analysis extraction unit;
A design support apparatus comprising: a program conversion unit that inserts a description of the modular interface selected by the selection unit into the functional program and converts the functional program into a program that can be synthesized at a high level. The program conversion unit
Using the description of the modular interface selected by the selection unit, the module description describing the function of the hardware module included in the function program, and the function of the circuit composed of the plurality of hardware modules are described. The design support according to claim 1, wherein a description of a modular interface selected by the selection unit is inserted into the function program by rewriting the top description to be converted into the program capable of high-level synthesis. apparatus. The selection unit includes:
A plurality of input / output relationships are described, and for each described input / output relationship, interface selection information that describes the modular interface to be selected is acquired.
The design support apparatus according to claim 1, wherein a corresponding modular interface described in the interface selection information is selected for each input / output relationship between hardware modules extracted by the analysis extraction unit. The design support device further includes:
The high-level synthesis is executed using the program capable of high-level synthesis, and the modular interface parameters used for the conversion to the program capable of high-level synthesis are changed when the performance in the high-level synthesis execution result does not satisfy the required performance. An adjustment processing unit for performing processing or processing for switching the modular interface used for conversion into the program capable of high-level synthesis to another modular interface;
The program conversion unit
The description of the modular interface after the parameter is changed by the adjustment processing unit or the description of the modular interface after the switching by the adjustment processing unit is inserted into the function program to convert the function program into a program capable of high-level synthesis. The design support apparatus according to claim 1. The adjustment processing unit
When the transfer bit amount in the high-level synthesis execution result does not satisfy the required performance for the transfer bit amount, a process of changing the data width of the modular interface used for the conversion to the program capable of high-level synthesis is performed,
Processing for switching to another modular interface having a smaller circuit scale than the modular interface used for conversion to the program capable of high-level synthesis when the circuit scale in the high-level synthesis execution result does not satisfy the required performance for the circuit scale The design support apparatus of Claim 4 which performs. An analysis extraction step in which the computer analyzes the function program and extracts an input / output relationship between the hardware modules in the plurality of hardware modules;
The computer extracts the analysis and extraction by referring to an interface library that stores a plurality of descriptions in a form capable of high-level synthesis in which interface functions between hardware modules or bridge interface functions and input / output ports are encapsulated as modular interfaces. A selection step of selecting a modular interface for each input / output relationship between the hardware modules extracted in the step;
A design support method comprising: a program conversion step in which the computer converts the functional program into a program capable of high-level synthesis by inserting the modular interface selected in the selection step into the functional program. An analysis and extraction step of analyzing a functional program and extracting an input / output relationship between hardware modules in a plurality of hardware modules;
A description of a format capable of high-level synthesis in which interface functions between hardware modules or bridge interface functions and input / output ports are encapsulated is extracted as a modular interface by referring to an interface library that stores a plurality of descriptions. A selection step for selecting a modular interface for each input / output relationship between the hardware modules;
A design support program for causing a computer to execute a program conversion step of inserting a description of the modular interface selected in the selection step into the function program and converting the function program into a program capable of high-level synthesis.

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