JP2016148964A - Calculating device, calculation method, and protection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability in data by providing a simple and more accurate determination method of a memory inspection target.SOLUTION: A calculating device includes: a CPU for outputting an access request; a cache memory for outputting data corresponding the access request to the CPU, a main memory for receiving the access request from the cache memory and outputting the data corresponding to the access request to the cache memory, an access control part for inspecting the main memory, a cache access range storage part for storing an address accessed within a predetermined range in the cache memory, and a main memory inspection target address determination part that is the main memory inspection target address determination part for outputting an inspection target range of the main memory to the access control part and omits the address accessed within the predetermined range recorded in the cache access range storage part from the inspection target range.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a calculation device, a calculation method, and a security device.

  In a memory mounted on an information processing apparatus, data may become an incorrect value due to a soft error or the like while data is being stored. Memory patrol performs this error correction independently of normal access. Since memory patrol does not use OS or CPU resources, it is possible to detect and correct data errors easily and at high speed. In recent years, there is a technique described in Japanese Patent Application Laid-Open No. 2014-59821 (Patent Document 1) in order to detect and correct data errors earlier and maintain high data reliability. In this publication, “a CPU, a memory composed of a plurality of memory blocks, a memory patrol unit that periodically detects and corrects errors in the memory block, a memory patrol control unit that controls execution of the memory patrol, And an access frequency calculation unit that counts the number of accesses from the CPU to the memory block, and reduces the number of memory patrols for the memory block when the number of accesses exceeds a predetermined value.

JP 2014-59821 A

Patent Document 1 is based on the fact that an error occurrence probability is low in a memory block in which data is frequently rewritten. That is, memory patrols can be omitted because there are few errors in memory blocks that are frequently accessed from the CPU. Omission reduces the probability of competing memory patrol and access by the CPU. In addition, the resources that are floated by omission can be used for memory patrol strengthening for memory blocks with a high error occurrence probability (low access). As a result, the reliability of the data is improved.
However, in the technique of Patent Document 1, there are two problems in determining the size of each memory block subject to memory patrol.
The first point is that if the size of the memory block is set larger than necessary, a bit having a low data rewrite frequency and a bit having a high data rewrite frequency are generated in the memory block.
The second point is that setting the memory block size smaller than necessary increases the amount of hardware for storing and calculating the memory block number and access frequency of the access frequency calculation means. .
Therefore, the present invention provides a calculation device, a calculation method, and a security device capable of simpler memory inspection. In particular, the reliability of data can be further improved by performing a memory test on a range where the error occurrence probability of the memory is high.

  In order to solve the above problems, one of the representative computing devices of the present invention includes a CPU that outputs an access request, a cache memory that outputs data corresponding to the access request to the CPU, and an access request from the cache memory. A main memory that receives and outputs data corresponding to the access request to the cache memory, an access control unit that inspects the main memory, a cache access range storage unit that records addresses accessed by the cache memory within a predetermined period, and an access A main memory test target address determination unit for outputting a main memory test target range to the control unit, wherein an address accessed in a predetermined period recorded in the cache access range storage unit is omitted from the test target range. A target address determination unit.

  According to the present invention, it is possible to provide a calculation device, a calculation method, and a security device that can perform a simpler memory test.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

1 is a block diagram of a computing device having a memory inspection method according to an embodiment of the present invention. FIG. It is an image figure of the memory test object range of this invention. 3 is a flowchart of a memory inspection method of the present invention. It is the figure which showed the order of the address storage to the memory area of the cache access range memory | storage part of this invention. It is the figure which showed the inside of the cache access range memory | storage part with the fast search method of this invention. It is the block diagram which added the initialization timer of the cache access range memory | storage part to the computer apparatus which had the memory test | inspection method of one Example of this invention. 1 is a block diagram of a computing device having a memory checking method and a data matching function according to an embodiment of the present invention. FIG.

  Hereinafter, examples will be described with reference to the drawings.

  The present invention focuses on the fact that the area read into the cache memory by the read request is less likely to cause a memory failure than the area that has not been read for a while, within the range in which the memory check (memory patrol) of the main memory is performed. However, the memory inspection is appropriately omitted depending on the region, thereby improving the efficiency of the memory inspection or improving the reliability of the memory. For example, if it is applied to a railway security device, the memory inspection can be made more efficient while ensuring reliability.

FIG. 1 is a block diagram of a computing device that performs high-efficiency memory inspection according to an embodiment of the present invention.
The computing device 100 includes a CPU 101, a cache memory 102, a main memory 103, an access control unit 104 with an error detection function, a cache access range storage unit 105, and a main memory inspection target address determination unit 106.

Next, processing of each device or unit will be described.
The CPU 101 requests access to the cache memory 102 (hereinafter, the access request is a read request or a write request, the read request is a signal including a read instruction and an address, and the write request is a signal including a write instruction, an address, and data. When the access request is a read request, the cache memory 102 receives data for the read request. When an error detection input is received from the access control unit 104 with an error detection function, an interrupt process is performed.
When the cache memory 102 receives an input of an access request from the CPU 101, the cache memory 102 compares the address in the access request with the address stored in the cache memory 102.
If the comparison between the address in the access request and the address stored in the cache memory 102 matches and the access request is a read request, data for the read request is output to the CPU 101.
If the comparison between the address in the access request and the address stored in the cache memory 102 does not match, the access request is output to the access control unit 104 with error detection function. If the above comparison does not match and the access request is a read request, the read instruction and address in the read request are output to the cache access range storage unit 105. Then, it receives data in response to the read request from the access control unit 104 with error detection function, and outputs data in response to the read request to the CPU 101.
Regardless of whether the comparison between the address in the access request and the address stored in the cache memory 102 is coincident or inconsistent, if the access request is a write request, the address and data in the access request are stored, and an error detection function is performed in a timely manner. To the attached access control unit 104.

  When the cache access range storage unit 105 receives an input of a read instruction in the read request from the cache memory 102, the cache access range storage unit 105 stores an address in the read request. When there is no more storage area for storing the address in the read request, the address in the read request is overwritten from the storage area of the address in the read request stored most recently. When the main memory test target address determining unit 106 receives the input of the main memory test target candidate address, the cache memory 102 accesses the address with the error detection function from the address stored in the cache access range storage unit 105. A search is made as to whether the data corresponds to a read request received from the control unit 104 within the data length (eg, cache line size). If applicable, a signal indicating the corresponding is output to the main memory inspection target address determination unit 106. If not applicable, a signal indicating non-applicability is output to the main memory inspection target address determination unit 106.

  When the main memory inspection target address determination unit 106 outputs the main memory inspection target candidate address to the cache access range storage unit 105, the main memory inspection target address determination unit 106 receives a signal indicating corresponding or non-applicable from the cache access range storage unit 105. . If it is a signal indicating the corresponding, the next main memory inspection target candidate address is output to the cache access range storage unit 105. If the signal means non-applicable, the main memory test target address is output to the access control unit 104 with error detection function.

  When the access control unit 104 with an error detection function receives an input of an access request from the cache memory 102, the access control unit 104 outputs the access request to the main memory 103. If the access request is a read request, data input to the read request is received from the main memory 103 and the data corresponding to the read request is output to the cache memory 102. When receiving the main memory test target address from the main memory test target address determining unit 106, the read request is output to the main memory 103. Data input to the read request is received from the main memory 103 and the data corresponding to the read request is inspected. When it is detected that there is an error in the data, an error detection is output to the CPU 101. In the present invention, the access control unit 104 with an error detection function only needs to function as an access control unit as a main body that performs memory detection.

  When the access request is input from the access control unit 104 with error detection function, the main memory 103 outputs data for the read request to the access control unit 104 with error detection function if the access request is a read request. If the access request is a write request, a code for checking the main memory is added to the data in the write request and stored. When an input of a read request is received from the access control unit 104 with error detection function, data for the read request is output to the access control unit 104 with error detection function.

Next, the highly efficient memory inspection method will be described more specifically with reference to FIGS.
FIG. 2 is an image showing how to obtain the memory inspection target range 200 in the main memory 103. The memory test is performed in order from the first memory test position 202 to the last memory test position 203. In the present invention, by omitting and skipping the inspection of the non-memory inspection target range 201, a simpler memory inspection can be performed. The target range of the memory inspection target range 200 may be the entire area of the main memory, or the area may be appropriately divided into blocks according to the size of the memory area.

FIG. 3 shows a flowchart of memory inspection in this embodiment.
Step 300: Start memory test.
Step 301: Set the pointer to the first address. In FIG. 2, this corresponds to setting the pointer to the first memory check position 202.
Step 302: Check whether the address indicated by the pointer is in the memory inspection target range. In FIG. 2, it corresponds to checking whether or not the area 201 is not in the memory inspection target range. If yes, then go to step 303, otherwise go to step 304.
Step 303: Memory check.
Step 304: Check whether the pointer indicates the last address. In FIG. 2, it is checked whether the last memory inspection position 203 is indicated. If YES, the process proceeds to step 305, and if NO, the process proceeds to step 301.
Step 305: Set the pointer to the next address. In FIG. 2, this corresponds to moving the pointer 204 to the next address. Then, it progresses to step 302.

Next, a formula for calculating the capacity of the cache access range storage unit is shown. The maximum memory inspection exclusion rate is
It depends on the capacity of the cache access range storage unit.
[Capacity of cache access range storage] =
[Number of stored addresses] x [address length] =
[Memory inspection target range] × [Maximum memory inspection target nonexistence rate] ÷ [Data length received by cache memory 102 from access control unit 104 with error detection function] × [Address length]
Note that the memory inspection non-target range 201 may be skipped every time the memory test is performed, or the first test for inspecting the entire memory test target range 200 and the memory inspection non-target range 201 are omitted as described above. The second inspection may be selected and performed. If more reliability is required, the frequency of the first inspection may be increased, and if more importance is placed on the efficiency, the second frequency may be set higher.

Next, the cache access range storage unit 105 in FIG. 1 will be described with reference to FIGS. 4 and 5.
As an example, it is assumed that there is a storage area 400 of the cache access range storage unit 105 as shown in FIG. The first received address is to the storage area 401, the second received address is to the storage area 402, the third received address is to the storage area 403, in the order of the storage area 401, the storage area 402, and the storage area 403. Remembered. When the storage area 401, the storage area 402, and the storage area 403 are all stored, the next received address is overwritten in the storage area 401. That is, the addresses received in the order of the storage area 401, the storage area 402, the storage area 403, the storage area 401, the storage area 402, and the storage area 403 are continuously overwritten.

FIG. 5 shows the data length that the cache memory 102 including the address stored in the storage area 500 of the cache access range storage unit 105 receives the input from the access control unit 104 with error detection function. The method of searching at high speed whether it corresponds to the range is shown.
The comparison unit 501 receives an input of the main memory inspection target candidate address 503 and an address of the storage area 500 of the cache access range storage unit 105. Then, a comparison is made as to whether or not the cache memory 102 including the address of the storage area 500 of the cache access range storage unit 105 corresponds to the data length range in which the main memory inspection target candidate address 503 is input from the access control unit 104 with error detection function To do.
If applicable, output corresponding to the logical sum 502. If not applicable, the non-applicability is output to the logical sum 502. The logical sum 502 receives relevant or non-relevant inputs from the plurality of comparison units 501. When even one corresponding input is received, the logical sum 502 outputs the corresponding, and the cache access range storage unit 105 outputs the corresponding to the main memory inspection target address determining unit 106. If all are not applicable, the logical sum 502 outputs “not applicable”, and the cache access range storage unit 105 outputs “not applicable” to the main memory check target address determination unit 106.
By using such a memory inspection method that excludes the data length of data corresponding to the read request from the address in the read request output from the cache memory 102 to the access control unit 104 with error detection function as described above. Therefore, it is possible to more easily and accurately determine a memory inspection target. Memory inspection can be performed by narrowing the memory error occurrence probability to a high range, and data reliability can be further improved by detecting errors early.
In this embodiment, the three storage areas of the cache access range storage unit 105 have been described. However, the number of storage areas may be determined according to the capacity of the cache access range storage unit 105, and the cache area may be cached within the most recent predetermined period. What is necessary is just to detect whether the address recorded in the access range storage unit 105 is relevant or not. Further, in the case where there are three storage areas, it has been described that the memory inspection of the area for which the last three read requests have been requested can be omitted. If these are held, the memory test may be omitted only for the addresses that have been input up to the first or second most recently among the three storage areas.

  FIG. 6 is a block diagram in which an initialization timer of a cache access range storage unit is added to a computing device that performs high-efficiency memory checking according to an embodiment of the present invention. A computing device 600 to which an initialization timer for a cache access range storage unit is added includes a CPU 601, a cache memory 602, a main memory 603, an access control unit with error detection function 604, a cache access range storage unit 605, and a main memory inspection target address determination unit. 606 and an initialization timer 607.

  Next, differences from the first embodiment will be described. The initialization timer 607 measures time. When a certain time elapses, an initialization request is output to the cache access range storage unit 605. When receiving an initialization request input from the initialization timer 607, the cache access range storage unit 605 initializes all the storage areas 400 of the cache access range storage unit of FIG.

  By periodically initializing the storage area 400 of the cache access range storage unit as described above, the storage information in the storage area 400 of the cache access range storage unit is out of date, and a range that requires a memory check is excluded from the memory check target It is possible to solve the problem of the range.

  FIG. 7 is a block diagram of a computing device having a highly efficient memory inspection method and data collation function according to an embodiment of the present invention.

  A computing device 700 having a highly efficient memory inspection method and a data collation function includes a CPU 701, a cache memory 702, a main memory 703, an access control unit 704, a cache access range storage unit 705, a main memory inspection target address determination unit 706, and a CPU 707. A cache memory 708, a main memory 709, an access control unit 710, and a data comparison unit 711.

Next, input / output of each device or unit will be described.
The CPU 701 inputs / outputs an access request or a response to the cache memory 702, the CPU 707, and the cache memory 708, and the CPU 701 and the CPU 707 receive an error detection input from the data comparison unit 711.
The cache memory 702 inputs and outputs access requests or responses to the CPU 701 and access control unit 704, and the cache memory 708 inputs and outputs access requests or responses thereto, and the cache memory 702 performs read requests to the cache access range storage unit 705. Outputs the read instruction and address. In the following, although FIG. 7 shows an example of output from the cache memory 702 to the cache access range storage unit 705, output from the cache memory 708 to the cache access range storage unit 705 is also possible.
The cache access range storage unit 705 inputs / outputs a search target or search result to / from the main memory inspection target address determination unit 706, and receives a read instruction and an address in a read request from the cache memory 702.
The main memory test target address determination unit 706 inputs / outputs the search target or the search result to / from the cache access range storage unit 705, and outputs the main memory test target address to the access control unit 704 and the access control unit 710.
The access control unit 704 inputs / outputs an access request or a response to / from the cache memory 708 and the data comparison unit 711, and the main memory inspection target address determination unit 706 inputs and outputs the cache memory 702 and the data comparison unit 711. Receives the address of the main memory test target.
The data comparison unit 711 inputs and outputs access requests or responses to the access control unit 704, access control unit 710, main memory 703, and main memory 709, and outputs error detection to the CPU 701 and the CPU 707.
The main memory 703 and the main memory 709 input / output an access request or a response to the data comparison unit 711.

  Next, processing of each device or unit will be described. Here, the CPU 707 operates in the same manner as the CPU 701, the cache memory 708 in the cache memory 702, the main memory 709 in the main memory 703, and the access control unit 710 in the same manner as the access control unit 704. .

  The CPU 701 outputs an access request to the cache memory 702, and when the access request is a read request, the CPU 701 receives data input for the read request from the cache memory 702. When the CPU 701 receives an error detection input from the data comparison unit 711, it performs an interrupt process.

  When the cache memory 702 receives an input of an access request from the CPU 701, the cache memory 702 compares the address in the access request with the address stored in the cache memory 702. If the comparison between the address in the access request and the address stored in the cache memory 702 matches and the access request is a read request, the cache memory 702 outputs data for the read request to the CPU 701. If the comparison between the address in the access request and the address stored in the cache memory 702 does not match and the read request is issued, a read request is output to the access control unit 705, and only the cache memory 702 is read from the cache access range storage unit 705. Outputs the read instruction and address. In response to the input of data for the read request from the access control unit 705, the data for the read request is output to the CPU 701. Regardless of whether the address in the access request and the address stored in the cache memory 702 match or not, if the access request is a write request, the address and data of the write request are stored. Output.

  When receiving a read instruction and a write instruction in the access request from the cache memory 702, the cache access range storage unit 705 stores the address in the access request. When there is no more storage area for storing the address in the access request, the address in the access request is overwritten from the storage area of the address in the access request stored most recently. When the main memory test target address determination unit 706 receives the input of the main memory test target candidate address, the cache memory 702 is transferred from the access control unit 705 from the address stored in the cache access range storage unit 705. A search is performed to determine whether the data corresponds to the data length (for example, cache line size) of the data corresponding to the read request received (or data in the write request output to the access control unit 705). If applicable, a signal indicating the corresponding is output to the main memory inspection target address determination unit 206. If not applicable, a signal indicating non-applicability is output to the main memory inspection target address determination unit 206.

  When the main memory test target address determination unit 706 outputs the main memory test target candidate address to the cache access range storage unit 705, the main memory test target address determination unit 706 receives a signal indicating corresponding or non-applicable from the cache access range storage unit 705. . If it is a signal indicating the corresponding, the next main memory inspection target candidate address is output to the cache access range storage unit 705. If the signal means non-applicable, the main memory test target address is output to the access control unit 704 and the access control unit 710.

  When the access control unit 704 receives an access request input from the cache memory 702, the access control unit 704 outputs the access request to the data comparison unit 711. If the access request is a read request, data input for the read request is received from the data comparison unit 711, and the data for the read request is output to the cache memory 702. When receiving the main memory test target address from the main memory test target address determination unit 706, it outputs a read request to the data comparison unit 711 and receives data input from the data comparison unit 711 in response to the read request.

The data comparison unit 711 receives input of access requests from the access control unit 704 and the access control unit 710. If the access request is a read request, the read request from the access control unit 704 is output to the main memory 703, the data input to the read request from the access control unit 704 is received from the main memory 703, and the access control unit is stored in the main memory 709. The read request from the access control unit 710 is received from the main memory 709.
Then, the data for the read request from the access control unit 704 is compared with the data for the read request from the access control unit 710. If they match, the data for the read request from the access control unit 704 is output to the access control unit 704, and the data for the read request from the access control unit 710 is output to the access control unit 710. If they do not match, error detection is output to CPU 701 and CPU 707. If the access request is a write request, the data in the write request from the access control unit 704 is compared with the data in the write request from the access control unit 710. If they match, the data in the write request from the access control unit 704 is output to the main memory 703, and the data in the write request from the access control unit 710 is output to the main memory 709. If they do not match, error detection is output to CPU 701 and CPU 707.

The main memory 703 receives an access request input from the data comparison unit 711. If the access request is a read request, data corresponding to the read request is output to the data comparison unit 711. If the access request is a write request, the data in the write request is stored.
The description of the highly efficient memory inspection method using FIGS. 2 and 3 and the description of the cache access range storage unit 105 of FIG. 1 using FIGS. 4 and 5 are the same as in the first embodiment.

  By using the computing device having the data collation function as described above, not only the data length of the data for the read request from the address in the read request output from the cache memory 702 to the access control unit 704, but also the write request The data length of the data in the write request from the address in can also be excluded from the latest memory check. Other effects are equivalent to those of the first embodiment.

DESCRIPTION OF SYMBOLS 101 ... CPU, 102 ... Cache memory, 103 ... Main memory, 104 ... Access control unit with error detection function, 105 ... Cache access range storage unit, 106 ... Main memory test target address determination unit, 201 ... Memory test target non-target range, 202 ... First memory test position, 203 ... Last memory test position, 204 ... Move to next address, 400 ... Storage area of cache access range storage unit, 401 ... Storage area, 402 ... Storage area, 403 ... Storage area, 500 ... Storage area of cache access range storage unit, 501 ... Comparison unit, 502 ... OR, 601 ... CPU, 602 ... Cache memory, 603 ... Main memory, 604 ... Access control unit with error detection function, 605 ... Cache access range Storage unit, 606... Main memory inspection target address determination 607 ... initialization timer, 701 ... CPU, 702 ... cache memory, 703 ... main memory, 704 ... access control unit, 705 ... cache access range storage unit, 706 ... main memory inspection target address determination unit, 707 ... CPU, 708 ... Cache memory, 709 ... Main memory, 710 ... Access control unit, 711 ... Data comparison unit.

Claims (6)

A CPU that outputs an access request;
A cache memory that outputs data corresponding to the access request to the CPU;
A main memory that receives the access request from the cache memory and outputs data corresponding to the access request to the cache memory;
An access control unit for inspecting the main memory;
A cache access range storage unit for recording addresses accessed by the cache memory within a predetermined period;
A main memory test target address determination unit that outputs a test target range of the main memory to the access control unit, wherein an address accessed within the predetermined period recorded in the cache access range storage unit is the test target range. The main memory inspection target address determination unit omitted from,
A computing device. The computing device according to claim 1,
The cache access range storage unit records a predetermined number of the addresses, and when the cache memory is accessed beyond the predetermined number, the predetermined number of addresses recorded in the past A computing device that overwrites and records addresses. The computing device according to claim 1,
The access control unit
A first inspection for inspecting the entire inspection target range of the main memory;
A second test in which the address accessed by the main memory test target address determination unit within the predetermined period is omitted from the test target range;
A computing device that performs. The computing device according to claim 1, further comprising:
A computing device comprising an initialization timer for outputting an initialization request for initializing the recorded address to the cache access range storage unit when a certain time has elapsed.   A security device comprising the calculation device according to claim 1. A CPU that outputs an access request;
A cache memory that outputs data corresponding to the access request to the CPU;
A main memory that receives the access request from the cache memory and outputs data corresponding to the access request to the cache memory;
An access control unit for inspecting the main memory;
A cache access range storage unit for recording addresses accessed by the cache memory within a predetermined period,
When inspecting the inspection target range of the main memory, it is detected whether the address is accessed within the predetermined period recorded in the cache access range storage unit, and is an address accessed within the predetermined period. If the calculation method omits the inspection.

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