JP2016148868A - Driving method of electro-optical device, electro-optical device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an influence of photo-deterioration of a liquid crystal panel.SOLUTION: The present driving method is a driving method of an electro-optical device comprising a plurality of pixel electrodes, an opposing electrode corresponding to the plurality of pixel electrodes, and an electro-optical layer held between the plurality of pixel electrodes and the opposing electrode, the method including the step of, for each of a plurality of sub field periods obtained by dividing one frame period, applying a voltage corresponding to either one of a first gradation value or a second gradation value to between each of the plurality of pixel electrodes and the opposing electrode, where the time length of all of the plurality of sub field periods is 2.78 milliseconds or less.SELECTED DRAWING: Figure 9

Description

  The present invention relates to driving of an electro-optical device.

Patent Document 1 discloses a liquid crystal panel in which a circuit for driving a liquid crystal layer is formed on a quartz substrate. Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for expressing halftones by dividing one frame into a plurality of subframes and applying a voltage of 0 V or 5 V to each subframe.
Patent Documents 3 and 4 disclose techniques for reversing the polarity of the applied voltage for each subfield. Patent Document 5 discloses a technique for equalizing the time of a subfield to which a positive voltage is applied and the time of a subfield to which a negative voltage is applied in one frame.

JP-A-10-293320 JP 2001-100180 A JP 2010-191038 A JP 2002-169517 A JP 2010-85955 A

Patent Documents 1 to 5 do not disclose a technique for suppressing the influence of light deterioration of the liquid crystal panel.
On the other hand, this invention provides the technique which suppresses the influence of the optical deterioration of a liquid crystal panel.

The present invention is a driving method of an electro-optical device, which includes a plurality of pixel electrodes, a counter electrode facing the plurality of pixel electrodes, and an electro-optical layer sandwiched between the plurality of pixel electrodes and the counter electrode. For each of a plurality of subfield periods obtained by dividing one frame period, a voltage corresponding to either the first gradation value or the second gradation value between each of the plurality of pixel electrodes and the counter electrode. The driving method is characterized in that, for all of the plurality of subfield periods, the time length of the subfield period is 2.78 milliseconds or less.
According to this driving method, a change in display characteristics due to light degradation of the electro-optic layer can be suppressed as compared with a case where the time length of the subfield period exceeds 2.78 milliseconds.

In a preferred embodiment, a time length of the plurality of subfield periods is any one of k different time lengths t _i (i is an integer satisfying 1 ≦ i ≦ k), and the k time lengths t _{i are set.} is a t _i <t _{i + 1} in 1 ≦ i ≦ k-1 in the range in the sub-field period of the time length t _i, the opposite polarity voltage to the time length t _{i + 1} of the subfield period The electro-optical layer may be applied.
According to this driving method, in the subfield period having the time length ti, the electro-optical layer is compared with the case where a voltage having a polarity opposite to that of the subfield period having the time length t _{i + 1} is applied to the electrooptical layer. Changes in display characteristics due to light degradation of the layer can be suppressed.

In another preferred embodiment, a time length of the plurality of subfield periods is any one of k different time lengths t _i (i is an integer satisfying 1 ≦ i ≦ k), and the k time lengths t _i may be 40 microseconds ≦ (t _i + t _{i + 2} ) ≦ 2.78 milliseconds in the range of 1 ≦ i ≦ k−2.
According to this driving method, a change in display characteristics due to light degradation of the electro-optic layer can be suppressed as compared with a case where the sum of time lengths (t _i + t _{i +2} ) exceeds 2.78 milliseconds. .

In still another preferred embodiment, in one frame period, a total time length of a subfield period in which a positive voltage is applied to the electro-optic layer, and a subfield in which a negative voltage is applied to the electro-optic layer. The difference from the total time length of the period may be 2.78 milliseconds or less.
According to this driving method, the sum of the time lengths of the subfield period in which the positive voltage is applied to the electro-optic layer, and the sum of the time lengths of the sub-field period in which the negative voltage is applied to the electro-optic layer, Compared with the case where the difference between the two exceeds 2.78 milliseconds, a change in display characteristics due to light degradation of the electro-optic layer can be suppressed.

In addition, the present invention provides a plurality of pixel electrodes, a counter electrode facing the plurality of pixel electrodes, an electro-optical layer sandwiched between the plurality of pixel electrodes and the counter electrode, and a plurality of divided one frame periods For each of the subfield periods, a signal for applying a voltage corresponding to either the first gradation value or the second gradation value is output between each of the plurality of pixel electrodes and the counter electrode. There is provided an electro-optical device including a data line driving circuit, wherein a time length of a subfield period is 2.78 milliseconds or less for all of the plurality of subfield periods.
According to this electro-optical device, a change in display characteristics due to light degradation of the electro-optical layer can be suppressed as compared with a case where the time length of the subfield period exceeds 2.78 milliseconds.

Furthermore, the present invention provides an electronic apparatus having the above electro-optical device.
According to this electronic apparatus, it is possible to suppress a change in display characteristics due to light degradation of the electro-optic layer as compared with a case where the time length of the subfield period exceeds 2.78 milliseconds.

It is a block diagram which shows the structure of the electronic device 1 which concerns on one Embodiment. 2 is a diagram showing a structure of a liquid crystal panel 100. FIG. 1 is a diagram illustrating a configuration of an element substrate 101. FIG. 2 is a diagram illustrating an equivalent circuit of a pixel 110. FIG. 3 is a timing chart illustrating a method for driving the liquid crystal panel 100. FIG. 4 is a diagram illustrating a voltage-transmittance characteristic (VT characteristic) of the liquid crystal panel 100. It is a figure explaining the mechanism in which the characteristic of the liquid crystal layer 105 deteriorates. It is a figure which shows the transient characteristic of the transmittance | permeability at the time of polarity reversal. It is a figure which illustrates the structure of a subfield. It is a figure which illustrates the structure of the subfield concerning the modification 1. It is a figure explaining the modification 5. FIG. It is a figure explaining the modification 6. FIG.

1. Configuration FIG. 1 is a block diagram illustrating a configuration of an electronic apparatus 1 according to an embodiment. In this example, the electronic device 1 is a so-called rear type projector. The electronic device 1 includes a liquid crystal panel 100, a light source 11, an optical system 12, a reflecting mirror 13, a reflecting mirror 14, and a screen 15. The liquid crystal panel 100 functions as a light valve. The light source 11 outputs light. The light emitted from the light source 11 passes through the liquid crystal panel 100 and is given image information. The optical system 12 controls the light beam transmitted through the liquid crystal panel 100 and emits the light beam toward the reflecting mirror 13. The reflecting mirror 13 and the reflecting mirror 14 guide the light beam to the screen 15. An image controlled by the liquid crystal panel 100 is displayed on the screen 15.

  FIG. 2A is a perspective view showing the structure of the liquid crystal panel 100. FIG. 2B is a schematic diagram illustrating a cross section taken along the line Hh in FIG. The liquid crystal panel 100 includes an element substrate 101, a counter substrate 102, and a liquid crystal layer 105. The element substrate 101 and the counter substrate 102 are bonded together with a sealant 90 including a spacer (not shown) so that the electrode formation surfaces face each other while maintaining a certain gap. The liquid crystal layer 105 is sealed in this gap. The liquid crystal layer 105 is, for example, a VA (Vertical Alignment) type liquid crystal.

  The element substrate 101 and the counter substrate 102 each have a transparent substrate such as quartz. The element substrate 101 is longer in the Y direction than the counter substrate 102. Since the back side (h side) is aligned, one side of the front side (H side) of the element substrate 101 protrudes from the counter substrate 102. A plurality of connectors 107 are provided in the protruding region along the X direction. The plurality of connectors 107 are terminals for supplying various signals, various voltages, image signals, and the like from an external circuit.

  A pixel electrode 118 is formed on a surface of the element substrate 101 facing the counter substrate 102. The pixel electrode 118 is obtained by patterning a transparent conductive layer such as ITO (Indium Tin Oxide). A data line driving circuit 140 is formed on the element substrate 101. In the counter substrate 102, the counter electrode 108 provided on the surface facing the element substrate 101 is a conductive layer having transparency such as ITO.

  FIG. 3 is a diagram illustrating a configuration of the element substrate 101. The element substrate 101 has a drive circuit formed on a quartz substrate. This driving circuit includes m scanning lines 103, n data lines 104, pixels 110 arranged in m rows and n columns, a timing control circuit 120, a scanning line driving circuit 130, and a data line driving circuit. 140. The pixel 110 is provided corresponding to the intersection of the scanning line 103 and the data line 104. A display region 150 is formed by the pixels 110 arranged in m rows and n columns. The timing control circuit 120 outputs signals for controlling the timing at which the scanning line driving circuit 130 and the data line driving circuit 140 operate, for example, a start signal DY and an inversion signal FR. The scanning line driving circuit 130 supplies a scanning signal to the m scanning lines 103. The scanning signal is a signal for sequentially and exclusively selecting one scanning line 103 from the m scanning lines 103. The data line driving circuit 140 supplies a data signal corresponding to the image signal input via the connector 107 to the n data lines 104. The data signal indicates a voltage (hereinafter referred to as “data voltage”) corresponding to the gradation value of the pixel 110. A counter electrode 108 is formed on the counter substrate 102. The counter electrode 108 is common to all the pixels 110. The liquid crystal layer 105 is an example of an electro-optic element that exhibits an optical state in accordance with an applied voltage.

  FIG. 4 is a diagram illustrating an equivalent circuit of the pixel 110. The pixel 110 includes a transistor 111, a capacitor 112, a pixel electrode 118, and a counter electrode 108. The transistor 111 is an example of a switching unit that controls a conduction state between the data line 104 and the pixel electrode 118 in accordance with a scanning signal. In this example, the transistor 111 is an n-channel TFT (Thin Film Transistor). The gate and source of the transistor 111 are connected to the scanning line 103 and the data line 104. The drain of the transistor 111 is connected to the pixel electrode 118. One pixel electrode 118 is provided for each pixel 110. A liquid crystal layer 105 is sandwiched between the pixel electrode 118 and the counter electrode 108. A common potential LCcom is applied to the counter electrode 108. When the transistor 111 is in a conductive state, a voltage corresponding to the difference between the data voltage and the common potential LCcom is applied to the liquid crystal layer 105. The liquid crystal layer 105 shows an optical state corresponding to the data voltage. The capacitor element 112 is a storage capacitor for storing a data voltage. One end of the capacitor 112 is connected to the drain of the transistor 111. A common potential Vcom is applied to the other end of the capacitor 112. In this example, Vcom = LCcom.

2. Operation FIG. 5 is a timing chart showing a method for driving the liquid crystal panel 100. The image is rewritten every frame. For example, the frame rate is 60 frames / second, that is, the frequency of the vertical synchronization signal (not shown) is 60 Hz, and one frame period (hereinafter simply referred to as “one frame”) is 16.7 milliseconds. The liquid crystal panel 100 is driven by subfield driving. In subfield driving, one frame is divided into a plurality of subfield periods (hereinafter simply referred to as “subfields”). The start signal DY is a signal indicating the start of the subfield. When an H (High) level pulse is supplied as the start signal DY, the scanning line driving circuit 130 starts scanning the scanning line 103, that is, the scanning signal Gi (1 ≦ i ≦ m) is supplied to the m scanning lines 103. ) Is output. In one subfield, the scanning signal G is a signal that sequentially becomes an H level voltage. An H level scanning signal is called a selection signal, and an L (Low) level scanning signal is called a non-selection signal. The supply of the selection signal to the i-th scanning line 103 is referred to as “the i-th scanning line 103 is selected”. The transistor 111 is in an insulated state (off state) when a non-selection signal is input, and is in a conductive state (on state) when a selection signal is input. The output data signal Sj supplied to the j-th column data line 104 is synchronized with the scanning signal. For example, when the i-th row scanning line 103 is selected, a signal indicating a voltage corresponding to the gradation value of the pixel 110 in the i-th row and j-th column is supplied as the data signal Sj.

  The data signal Sj is a signal indicating one of the binary values of the first gradation value and the second gradation value (for example, 0V or 5V). A subfield having an applied voltage of 0V is referred to as “off subfield”, and applying a voltage of 0V in a certain subfield is referred to as “turning off the subfield”. Similarly, a subfield whose applied voltage has an absolute value of 5V is referred to as “on subfield”, and application of a voltage having an absolute value of 5V in a certain subfield is referred to as “turning on the subfield”. . In subfield driving, intermediate gray levels in one frame are expressed by controlling the ratio of subfields to be turned on and subfields to be turned off.

  The inversion signal FR is a signal indicating the polarity of the data voltage. For example, a positive data voltage (for example, + 5V) is applied in a subfield where the inverted signal FR is at an H level, and a negative data voltage (for example, −5V) is applied in a subfield where the inverted signal FR is at an L level. The The inversion signal FR is a signal that switches between the H level and the L level in synchronization with the start signal DY. That is, the polarity of the data voltage is switched for each subfield.

FIG. 6 is a diagram illustrating the voltage-transmittance characteristics (VT characteristics) of the liquid crystal panel 100. The problem of the prior art will be described with reference to this figure. In FIG. 5, the horizontal axis represents the voltage applied to the liquid crystal layer 105, and the vertical axis represents the transmittance of the liquid crystal layer 105. A broken line indicates an initial characteristic (for example, when not in use), and a solid line indicates a characteristic after deterioration (for example, after light irradiation for a certain period of time). In the electronic device 1, a light source 11 with higher luminance is used to brighten an image projected on the screen 15. The characteristics of the liquid crystal panel 100 deteriorate due to the light emitted from the light source 11.
In the example of FIG. 5, the VT curve is generally shifted to the higher voltage side than the initial state after deterioration. For example, considering the case where a voltage of 3 V is applied to the liquid crystal layer 105, the transmittance is lower than the initial value after deterioration. That is, after the deterioration, the image becomes darker than the initial stage.

  FIG. 7 is a diagram for explaining the mechanism by which the characteristics of the liquid crystal layer 105 deteriorate. FIG. 7A is a schematic diagram illustrating a state of the liquid crystal layer 105 in an initial state. In the initial state, a voltage applied from the outside of the liquid crystal layer 105 is applied to the liquid crystal layer 105. When light is irradiated from the light source 11, impurity ions are generated in the liquid crystal layer 105. As the impurity ions, impurities contained in the liquid crystal layer 105 are ionized by light irradiation, liquid crystal molecules are decomposed and ionized by light irradiation, or impurities mixed from the sealing material 90 or the sealing material are irradiated by light irradiation. Ionized can be considered. FIG. 7B is a diagram illustrating the influence of impurity ions. Among the impurity ions, there are movable ions that move in the liquid crystal layer 105. For example, when voltages of 0 V and −3 V are applied to the counter electrode 108 and the pixel electrode 118, negative impurity ions move to the counter electrode 108 side, and positive impurity ions move to the pixel electrode 118 side. . Due to these impurity ions, an internal electric field Ei is generated in the liquid crystal layer 105. The internal electric field Ei is an electric field in a direction that cancels an electric field corresponding to a potential difference between the counter electrode 108 and the pixel electrode 118 (hereinafter referred to as “external electric field Ee”). That is, the effective voltage applied to the liquid crystal layer 105 is a voltage corresponding to an electric field obtained by subtracting the internal electric field Ei from the external electric field Ee. That is, the absolute value of the effective voltage applied to the liquid crystal layer 105 is lower than 3V.

  In a liquid crystal panel, in general, polarity inversion driving is performed in order to prevent the panel from burning. Polarity inversion driving refers to applying a voltage of -3V and a voltage of + 3V alternately in order to obtain a transmittance corresponding to a voltage of 3V, for example. When the polarity inversion driving frequency is sufficiently lower than the mobility of impurity ions, the impurity ions move following the polarity inversion of the applied voltage.

  FIG. 8 is a diagram showing a transient characteristic of transmittance at the time of polarity reversal. The horizontal axis represents time, and the vertical axis represents transmittance. A broken line indicates an initial characteristic, and a solid line indicates a characteristic after deterioration. At the moment when the polarity of the applied voltage is reversed, the directions of the external electric field Ee and the internal electric field Ei are aligned (FIG. 7C). At this moment, the absolute value of the effective voltage applied to the liquid crystal layer 105 becomes higher than 3V. That is, at this time, the transmittance of the liquid crystal layer 105 is higher than that in the initial state. Thereafter, the impurity ions move with time. As the impurity ions move, the internal electric field Ei becomes zero, and finally turns to cancel the external electric field (FIG. 7D). That is, the transmittance of the liquid crystal layer 105 converges to a value lower than the initial state. Thereafter, when the polarity is reversed again, the directions of the external electric field Ee and the internal electric field Ei are aligned, and the transmittance increases. The transmittance decreases with time and converges to a lower value than the initial state.

  According to the mechanism described with reference to FIG. 7, if the frequency of polarity reversal is increased, the movement of impurity ions cannot follow the polarity reversal, and the influence should be reduced. According to the study by the inventors of the present application, by setting the frequency of polarity reversal to 360 Hz or more (that is, the period of polarity reversal is 2.78 milliseconds or less), the influence on the transmittance of impurity ions can be ignored. It was found that it can be reduced. By performing polarity inversion at a high frequency of 360 Hz or higher, even if impurity ions are generated in the liquid crystal layer 105 due to light degradation, the influence on the transmittance can be reduced.

  FIG. 9 is a diagram illustrating the configuration of subfields. In this example, one frame is composed of 20 subfields SF1 to SF20. The time length (width) is uniform at ts for all subfields. For example, when one frame is 16.7 milliseconds (when the vertical synchronization frequency is 60 Hz), ts = 0.833 milliseconds. That is, the cycle in which the polarity of the data voltage switches is shorter than 2.78 milliseconds. Therefore, according to the liquid crystal panel 100, it is possible to perform driving in which the influence of the impurity ions on the transmittance is reduced as compared with the case where the cycle of switching the polarity of the data voltage exceeds 2.78 milliseconds. The polarity inversion period, that is, the subfield time length is preferably 20.0 microseconds or more. This is because when the time length of the subfield is less than 20.0 microseconds, the liquid crystal molecules hardly respond at this speed.

3. Other Embodiments The present invention is not limited to the above-described embodiments, and various modifications can be made. Hereinafter, some modifications will be described. Two or more of the following modifications may be used in combination.

3-1. Modification 1
FIG. 10 is a diagram illustrating the configuration of subfields according to the first modification. The time length of the plurality of subfields may not be uniform. In the first modification, the time length of the subfield is one of four types (t ₁ <t ₂ <t ₃ <t ₄ ), t1, t2, t3, and t4. One frame is divided into a plurality of (in this example, five) blocks. One block is divided into a plurality (four in this example) of subfields. The time lengths of the four subfields in one block are t ₁ , t ₂ , t ₃ , and t ₄ . In this example, the time length of the subfield is 20.0 microseconds ≦ t ₁ <t ₂ <t ₃ <t ₄ ≦ 2.78 milliseconds. Even in the subfield having the longest time length t ₄ , it is possible to perform driving in which the influence of the impurity ions on the transmittance is reduced.

3-2. Modification 2
In the example of FIG. 10, the polarity of the data voltage applied in the subfield of time length t _i and the polarity of the data voltage applied in the subfield of time length t _{i−1 and} the subfield of time length t _{i + 1.} The opposite is true. With this configuration, the polarity of the data voltage applied in the subfield of time length t _i and the polarity of the data voltage applied in the subfield of time length t _{i−1 and} the subfield of time length t _{i + 1.} As compared with the configuration in which the same is applied, the polarity difference of the data voltage (the difference between the time when the positive voltage is applied and the time when the negative voltage is applied) can be reduced. For example, consider an example in which SF1 to SF5 are turned on in FIG. At this time, the polarity difference Δt is Δt = t ₁ −t ₂ + t ₃ −t ₄ + t ₁ .
Considering an example in which the polarity of the data voltage applied in the subfield of time length t _{i-1 and} the subfield of time length t _{i + 1} is the same, the polarity difference Δtc is Δtc = t ₁ + t ₂ + T ₃ + t ₄ −t ₁ . It can be seen that the polarity difference can be reduced by the configuration of FIG.
However, the polarity of the data voltage applied in the subfield of time length t _{i-1 and} the subfield of time length t _{i + 1} may be the same.

ここで、Δｔｆは、１ブロック内における極性差の代表値であり、次式（２）で表される。

Δｔｆは、１ブロック内のすべてのサブフィールドがオンである場合の極性差に相当する。式（１）の条件を採用することにより、１ブロック内のすべてのサブフィールドがオンである場合も、不純物イオンの影響を低減することができる。 3-3. Modification 3
In the example of FIG. 10, one block is composed of k (k = 4) subfields having different time lengths. The total number of subfields in one frame is represented as _{SF total (SF total = 20)} , in the modified example 3, the number k of types of total SF _total subfield of subfields, the following relationship (1) Fulfill.

Here, Δtf is a representative value of the polarity difference in one block, and is expressed by the following equation (2).

Δtf corresponds to a polarity difference when all subfields in one block are on. By adopting the condition of Expression (1), the influence of impurity ions can be reduced even when all subfields in one block are on.

3-4. Modification 4
In the fourth modification, the sum of the time lengths t _i and t _{i + 2} , that is, the sum of the time lengths of two adjacent subfields having the same polarity is 2.78 milliseconds or less. In order to express halftone, not only a subfield adjacent to a certain subfield but also two adjacent subfields may be turned on. For example, consider the case of turning on SF1 to SF5 and SF7 in the example of FIG. In the second block, SF5 and SF7 are of the same polarity and SF6 of opposite polarity is off, so the polarity difference depends on the sum of t ₁ and t ₃ . Therefore, the influence of impurity ions can be reduced by adopting the condition of t _i + t _{i + 2} ≦ 2.78 milliseconds. In consideration of the response speed of the liquid crystal molecules, the lower limit of t _i + t _{i + 2} is 40.0 microseconds (20.0 microseconds per subfield). That is, 40.0 microseconds ≦ t _i + t _{i + 2} ≦ 2.78 milliseconds.

3-5. Modification 5
FIG. 11 is a diagram for explaining the fifth modification. In the fifth modification, when there are a plurality of SF codes that express a certain gradation, the liquid crystal panel 100 uses an SF code having a polarity difference of 2.78 milliseconds or less. “SF code” refers to a combination of subfields to be turned on. For example, when the three SF codes of FIGS. 11A to 11C exist to express a certain gradation, the data line driving circuit 140 has a polarity difference of 2.78 milliseconds or less. The data voltage according to the SF code is output to the data line 104. In another example, the data line driving circuit 140 may output a data voltage to the data line 104 according to the SF code that minimizes the polarity difference.

3-6. Modification 6
FIG. 12 is a diagram illustrating the sixth modification. In the embodiment, the polarity of the subfield in one frame or the configuration of the SF code has been described. In addition to the above contents, the sixth modification uses so-called frame inversion driving in which the polarity of the data voltage is inverted every frame. In FIG. 12, the polarities of the subfields in the first frame and the subsequent second frame are shown. For example, considering the case where the same image is continuously displayed over a plurality of frames, the polarity difference generated in one frame can be canceled in the next frame.

3-7. Modification 7
The upper limit value of the time length of the subfield is not limited to 2.78 milliseconds. In short, it is only necessary to switch the polarity of the data voltage at such a speed that impurity ions cannot follow. That is, the upper limit value may be changed according to conditions such as impurity ion mobility, temperature, and liquid crystal layer viscosity. The upper limit value of the time length of the subfield is more preferably 1 millisecond or less.
Further, the liquid crystal layer 105 is not limited to a transmissive type, and may be a reflective type. The liquid crystal layer 105 is not limited to the normally black mode, and may be a normally white mode in which the liquid crystal layer 120 is in a white state when no voltage is applied, for example, as a TN mode. Further, an electro-optical element other than liquid crystal may be used.
The pixel circuit is not limited to that illustrated in FIG. As long as a desired voltage can be applied to the liquid crystal layer 105, a circuit having any configuration may be used.
The electronic device 1 is not limited to a rear projector. The electronic device 1 may be a projector, a personal computer, a PDA (Personal Digital Assistant), a mobile phone, a smartphone, a tablet terminal, or a portable game machine.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 11 ... Light source, 12 ... Optical system, 13 ... Reflecting mirror, 14 ... Reflecting mirror, 15 ... Screen, 90 ... Sealing material, 100 ... Liquid crystal panel, 101 ... Element substrate, 102 ... Opposite substrate, 103 ... Scanning line, 104 ... data line, 105 ... liquid crystal layer, 107 ... connector, 108 ... counter electrode, 110 ... pixel, 111 ... transistor, 112 ... capacitive element, 118 ... pixel electrode, 120 ... timing control circuit, 130 ... scanning line Drive circuit, 140... Data line drive circuit, 150... Display area.

Claims (6)

A driving method for an electro-optical device, comprising: a plurality of pixel electrodes; a counter electrode facing the plurality of pixel electrodes; and an electro-optical layer sandwiched between the plurality of pixel electrodes and the counter electrode.
For each of a plurality of subfield periods obtained by dividing one frame period, a voltage corresponding to either the first gradation value or the second gradation value is applied between each of the plurality of pixel electrodes and the counter electrode. The step of
The driving method, wherein a time length of the subfield period is 2.78 milliseconds or less for all of the plurality of subfield periods. A time length of the plurality of subfield periods is any one of k different time lengths t _i (i is an integer satisfying 1 ≦ i ≦ k);
The k time lengths t _i satisfy t _i <t _{i + 1} in the range of 1 ≦ i ≦ k−1.
In the subfield period duration t _i, The method according to claim 1, characterized in that the opposite polarity voltage is applied to said electro-optic layer and the length of time t _{i + 1} of the subfield period. A time length of the plurality of subfield periods is any one of k different time lengths t _i (i is an integer satisfying 1 ≦ i ≦ k);
3. The k time lengths ti are 40 microseconds ≦ (t _i + t _{i + 2} ) ≦ 2.78 milliseconds in the range of 1 ≦ i ≦ k−2. The driving method described. In one frame period, a sum of time lengths of subfield periods in which a positive voltage is applied to the electro-optic layer, and a sum of time lengths of subfield periods in which a negative voltage is applied to the electro-optic layer, The driving method according to claim 1, wherein the difference is less than or equal to 2.78 milliseconds. A plurality of pixel electrodes;
A counter electrode facing the plurality of pixel electrodes;
An electro-optic layer sandwiched between the plurality of pixel electrodes and the counter electrode;
For each of a plurality of subfield periods obtained by dividing one frame period, a voltage corresponding to either the first gradation value or the second gradation value is applied between each of the plurality of pixel electrodes and the counter electrode. And a data line driving circuit for outputting a signal for
The electro-optical device, wherein a time length of the subfield period is 2.78 milliseconds or less for all of the plurality of subfield periods.   An electronic apparatus comprising the electro-optical device according to claim 5.

Images