JP2016143782A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device capable of appropriately protecting an electronic element.SOLUTION: An electronic device A1 comprises: a substrate 1 that has a principal face 111 and a rear face 112 which face the sides opposite to each other in a thickness direction, and that is made of a semiconductor material; an electronic element 7 arranged on the substrate 1; and a conductive layer 3 conductive with the electronic element 7. The substrate 1 is formed with an element arrangement recessed part 14 recessed from the principal face 111. At the element arrangement recessed part 14, the electronic element 7 is arranged. The electronic device A1 comprises a sealing chip 4 that has a sealing chip principal face 41 that faces a side opposite to the element arrangement recessed part 14 in the thickness direction and a sealing chip rear face 42 that faces a side opposite to the sealing chip principal face 41, and that covers at least a part of the element arrangement recessed part 14 at the principal face 111 side.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic device.

  Various types of electronic devices having a specific function with respect to input / output of current from the outside have been proposed. Generally, in order to fulfill the function of this electronic device, a plurality of electronic elements each constituting a part of an electric circuit are incorporated. Metal leads are used for the purpose of supporting these electronic elements and conducting them. The number, shape and size of the leads are determined according to the function, shape and size of the plurality of electronic elements. The plurality of electronic elements mounted on the leads are covered with a sealing resin. The sealing resin is for protecting these electronic elements and part of the leads. Such an electronic device is used by being mounted on a circuit board of an electronic device, for example. In the electronic device, it is important to appropriately protect the electronic element. Note that Patent Document 1 is cited as a document related to the electronic device.

JP 2012-99673 A

  The present invention has been conceived under the circumstances described above, and an object thereof is to provide an electronic device capable of appropriately protecting an electronic element.

  An electronic device provided by the present invention has a main surface and a back surface that face opposite sides in the thickness direction, and is electrically connected to a substrate made of a semiconductor material, an electronic element disposed on the substrate, and the electronic element. An electronic device comprising a conductive layer, wherein the substrate is provided with an element placement recess that is recessed from the main surface, and the element placement recess is provided with the electronic element, A seal chip main surface facing away from the element placement recess in the thickness direction; and a seal chip back surface facing away from the seal chip principal surface; and the element placement on the main surface side. A seal tip covering at least a part of the recess is provided.

  In a preferred embodiment of the present invention, the bottom surface of the element placement recess is a surface orthogonal to the thickness direction.

  In a preferred embodiment of the present invention, the side surface of the element placement recess is inclined with respect to the thickness direction.

  In a preferred embodiment of the present invention, an angle of the element placement recess side surface with respect to the element placement recess bottom surface is 55 degrees.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface and the back surface are orthogonal to the thickness direction of the substrate and are flat.

  In a preferred embodiment of the present invention, the main surface is a (100) surface.

  In a preferred embodiment of the present invention, the side surface of the recess for element arrangement is connected to the main surface.

  In a preferred embodiment of the present invention, the seal tip is joined to the main surface.

  In a preferred embodiment of the present invention, the seal tip is made of Si.

  In a preferred embodiment of the present invention, an integrated circuit is built in the seal chip.

  In a preferred embodiment of the present invention, a gap region is provided in the element placement recess.

  In a preferred embodiment of the present invention, the gap region is in contact with the electronic element.

  In a preferred embodiment of the present invention, the electronic element and the seal chip are separated via the gap region.

  In a preferred embodiment of the present invention, the gap region occupies all of the element placement recesses.

  In preferable embodiment of this invention, the sealing resin part which occupies at least one part of the said recessed part for element arrangement | positioning is provided.

  In a preferred embodiment of the present invention, the sealing resin portion is in contact with the electronic element.

  In a preferred embodiment of the present invention, the sealing resin portion covers all of the electronic elements.

  In a preferred embodiment of the present invention, the sealing resin portion and the seal chip are separated via the gap region.

  In a preferred embodiment of the present invention, a buffer member interposed between the electronic element and the seal chip is provided.

  In a preferred embodiment of the present invention, the buffer member is made of a material that is more easily elastically deformed than the electronic element.

  In a preferred embodiment of the present invention, the buffer member is made of a material that is more easily elastically deformed than the seal tip.

  In a preferred embodiment of the present invention, the buffer member is made of a silicone resin.

  In a preferred embodiment of the present invention, the buffer member is larger than the electronic element in the thickness direction view.

  In a preferred embodiment of the present invention, the buffer member includes the electronic element in the thickness direction view.

  In a preferred embodiment of the present invention, the buffer member is partitioned into a plurality of small regions spaced from each other when viewed in the thickness direction.

  In a preferred embodiment of the present invention, the plurality of small regions overlap an end portion of the electronic element in the thickness direction view.

  In preferable embodiment of this invention, the sealing resin part which occupies all the said recessed parts for element arrangement | positioning is provided.

  In a preferred embodiment of the present invention, a seal chip electrode pad formed on the main surface of the seal chip is provided.

  In a preferred embodiment of the present invention, the seal chip has a seal chip side surface that is inclined so as to be located inward in the thickness direction view from the back surface of the seal chip toward the main surface of the seal chip. The conductive layer includes a seal chip side surface connecting portion formed on the side surface of the seal chip.

  In a preferred embodiment of the present invention, the seal tip side surface connecting portion reaches the edge of the main surface.

  In a preferred embodiment of the present invention, the conductive layer includes a main surface side connecting portion formed on the main surface of the substrate.

  In a preferred embodiment of the present invention, the conductive layer includes a recess side surface connecting portion formed on the element arranging recess side surface of the substrate.

  In a preferred embodiment of the present invention, the substrate is formed with a through hole penetrating from the element placement recess to the back surface, the through hole having a through hole inner surface, and the conductive layer And from the concave portion for element arrangement to the back surface through the inner surface of the through hole.

  In a preferred embodiment of the present invention, the semiconductor device further includes an insulating layer formed on the substrate, and the insulating layer is interposed between the conductive layer and the substrate.

  In a preferred embodiment of the present invention, the insulating layer is made of SiO2 or SiN.

  In a preferred embodiment of the present invention, the insulating layer includes a recess inner surface insulating portion formed on an inner surface of the element arranging recess.

  In a preferred embodiment of the present invention, the insulating layer includes a through hole inner surface insulating portion formed on the inner surface of the through hole.

  In a preferred embodiment of the present invention, the through hole has a cross-sectional dimension that increases from the main surface side toward the back surface side.

  In a preferred embodiment of the present invention, the recessed portion inner surface insulating portion has an auxiliary through hole positioned as an edge on the main surface side of the through hole in the thickness direction view.

  In a preferred embodiment of the present invention, the auxiliary through hole has a constant cross-sectional shape in the thickness direction.

  In a preferred embodiment of the present invention, the insulating layer includes an auxiliary through hole inner surface insulating portion formed on the inner surface of the auxiliary through hole and connected to the through hole inner surface insulating portion.

  In a preferred embodiment of the present invention, the conductive layer includes an auxiliary through-hole blocking portion that closes the auxiliary through-hole in the element placement recess.

  In a preferred embodiment of the present invention, the conductive layer includes a through hole inner surface conductive portion at least partially formed on the through hole inner surface insulating portion and in contact with the auxiliary through hole blocking portion.

  In a preferred embodiment of the present invention, a back electrode pad formed on the back surface is further provided, the back electrode pad being in contact with the conductive layer and electrically connected to the electronic element.

  In a preferred embodiment of the present invention, a seal chip shield layer made of a conductive material is formed on the seal chip.

  In a preferred embodiment of the present invention, the seal chip shield layer is formed on the back surface of the seal chip.

  In a preferred embodiment of the present invention, the seal chip shield layer covers the entire back surface of the seal chip.

  In a preferred embodiment of the present invention, a substrate shield layer is formed on the back surface of the substrate.

  In a preferred embodiment of the present invention, the substrate shield layer covers all of the back surface.

  According to the present invention, the recess for element arrangement is covered with the seal chip. Thereby, the said electronic element accommodated in the said recessed part for element arrangement | positioning can be protected more appropriately by the said seal chip.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is sectional drawing which shows the electronic device based on 1st Embodiment of this invention. FIG. 2 is an enlarged cross-sectional view of a main part showing the electronic device of FIG. 1. It is principal part sectional drawing which shows the electronic device of FIG. It is sectional drawing which shows an example of the manufacturing method of the electronic device of FIG. It is sectional drawing which shows an example of the manufacturing method of the electronic device of FIG. It is sectional drawing which shows an example of the manufacturing method of the electronic device of FIG. It is sectional drawing which shows an example of the manufacturing method of the electronic device of FIG. It is sectional drawing which shows an example of the manufacturing method of the electronic device of FIG. It is sectional drawing which shows an example of the manufacturing method of the electronic device of FIG. It is sectional drawing which shows an example of the manufacturing method of the electronic device of FIG. It is sectional drawing which shows the electronic device based on 2nd Embodiment of this invention. It is a top view which shows the buffer member and electronic element of the electronic device of FIG. FIG. 12 is a plan view illustrating another example of the buffer member and the electronic element of the electronic device of FIG. 11. It is sectional drawing which shows the modification of the electronic device based on 2nd Embodiment of this invention. It is a top view which shows the buffer member and electronic element of the electronic device of FIG. It is sectional drawing which shows the electronic device based on 3rd Embodiment of this invention. It is sectional drawing which shows the electronic device based on 4th Embodiment of this invention. It is sectional drawing which shows the electronic device based on 5th Embodiment of this invention. It is sectional drawing which shows the electronic device based on 6th Embodiment of this invention. It is a principal part expanded sectional view which shows the electronic apparatus of FIG. It is sectional drawing which shows the electronic device based on 7th Embodiment of this invention. It is sectional drawing which shows the modification of the electronic device based on 7th Embodiment of this invention. It is sectional drawing which shows the electronic device based on 8th Embodiment of this invention. It is sectional drawing which shows the modification of the electronic device based on 8th Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

  1 to 3 show an electronic device according to a first embodiment of the present invention. The electronic device A1 of this embodiment includes a substrate 1, an insulating layer 2, a conductive layer 3, a seal chip 4, a seal chip electrode pad 341, and an electronic element 7. FIG. 1 is a cross-sectional view showing the electronic device A1. FIG. 2 is an enlarged cross-sectional view of a main part showing the electronic device A1. FIG. 3 is a cross-sectional view of a main part showing the electronic device A1.

  The substrate 1 is made of a single crystal of a semiconductor material. In the present embodiment, the substrate 1 is made of Si single crystal. The material of the board | substrate 1 is not limited to Si, For example, SiC may be sufficient. The thickness of the substrate 1 is, for example, 200 to 550 μm. An electronic element 7 is disposed on the substrate 1.

  The substrate 1 has a main surface 111 and a back surface 112.

  The main surface 111 faces one side in the thickness direction. The main surface 111 is flat. The main surface 111 is orthogonal to the thickness direction. The main surface 111 is a (100) plane or a (110) plane. In the present embodiment, the main surface 111 is a (100) plane.

  The back surface 112 faces the other side in the thickness direction. That is, the back surface 112 and the main surface 111 face opposite to each other. The back surface 112 is flat. The back surface 112 is orthogonal to the thickness direction.

  The substrate 1 is provided with a recess 14 for element arrangement.

  The element placement recess 14 is recessed from the main surface 111. The electronic element 7 is arranged in the element arranging recess 14. The depth of the element placement recess 14 (the separation dimension in the thickness direction between the main surface 111 and the element placement recess bottom 142 described later) is, for example, 100 to 300 μm. The element placement recess 14 has a rectangular shape when viewed in the thickness direction. The shape of the element placement recess 14 depends on the adoption of the (100) plane as the main surface 111.

  The element placement recess 14 has an element placement recess side surface 141 and an element placement recess bottom surface 142.

  The element placement recess bottom surface 142 faces the same side as the main surface 111 in the thickness direction of the substrate 1. The element placement recess bottom surface 142 has a rectangular shape when viewed in the thickness direction. The electronic element 7 is arranged on the element arrangement recess bottom surface 142. The element placement recess bottom surface 142 is a surface orthogonal to the thickness direction.

  The element arrangement recess side surface 141 rises from the element arrangement recess bottom surface 142. The element arrangement recess side surface 141 is connected to the element arrangement recess bottom surface 142. The element arrangement concave side surface 141 is inclined with respect to the thickness direction. The angle of the element placement recess side surface 141 with respect to the plane orthogonal to the thickness direction is 55 degrees. This is because the (100) plane is adopted as the main surface 111. The element arrangement recess side surface 141 has four flat surfaces.

The insulating layer 2 is interposed between the conductive layer 3 and the substrate 1. The thickness of the insulating layer 2 is, for example, about 0.1 to 1.0 μm. The insulating layer 2 is made of, for example, SiO ₂ or SiN.

  The insulating layer 2 has a recessed inner surface insulating portion 21 and a back surface insulating portion 24.

The recess inner surface insulating portion 21 is formed in the element placement recess 14 of the substrate 1. In the present embodiment, the concave portion inner surface insulating portion 21 is formed on all of the element arrangement concave side surface 141 and the element arrangement concave bottom surface 142. The recess inner surface insulating portion 21 is formed by, for example, thermal oxidation. The recess inner surface insulating portion 21 is made of, for example, SiO ₂ .

At least a part of the back surface side insulating portion 24 is formed on the back surface 112 of the substrate 1. The back surface side insulating part 24 is formed by thermal oxidation. The back side insulating part 24 is made of, for example, SiO ₂ . In the present embodiment, the back surface side insulating portion 24 covers the entire back surface 112.

  The seal chip 4 has a seal chip main surface 41 facing the same side as the main surface 111 in the thickness direction and a seal chip back surface 42 facing the opposite side to the seal chip main surface 41. The seal chip 4 covers at least a part of the element placement recess 14 on the main surface 111 side. In the present embodiment, the seal chip 4 covers all of the element placement recesses 14. The seal tip 4 is made of Si, for example. The seal chip 4 may be integrated with an integrated circuit that performs a part of the function of the electronic device A1.

  The seal tip 4 has a seal tip side surface 43. The seal chip side surface 43 is inclined so as to be located inward in the thickness direction view from the seal chip back surface 42 toward the seal chip main surface 41. When the seal chip main surface 41 and the seal chip back surface 42 are (100) surfaces, the angle formed between the seal chip side surface 43 and the seal chip main surface 41 or the seal chip back surface 42 is 55 degrees. The seal chip 4 is bonded to the main surface 111 with a bonding layer 45. The bonding layer 45 may be a conductive material or an insulating material.

  In the present embodiment, the element placement recess 14 is sealed by the seal chip 4. In addition, the element placement recess 14 includes a void region 145. The void region 145 is a space such as an inert gas or a vacuum. In the present embodiment, all of the element placement recesses 14 are occupied by the gap regions 145. The void area 145 is in contact with the electronic element 7. In addition, a gap region 145 is interposed between the electronic element 7 and the seal chip 4.

  The thickness of the seal chip 4 may be a thickness that can appropriately protect the electronic element 7. Further, the thickness of the seal chip 4 may be set for the purpose of adjusting the thickness of the entire electronic device A1 when the thickness of the substrate 1 is fixed.

  The conductive layer 3 is electrically connected to the electronic element 7. The conductive layer 3 is for configuring a current path for inputting and outputting to the electronic element 7. The conductive layer 3 is formed on the element placement recess side surface 141, the element placement recess bottom surface 142 and the seal chip 4.

  The conductive layer 3 includes a seed layer 31 and a plating layer 32.

  The seed layer 31 is a so-called underlayer for forming a desired plating layer 32. The seed layer 31 is interposed between the substrate 1 and the plating layer 32. The seed layer 31 is made of Cu, for example. The seed layer 31 is formed by sputtering, for example. The thickness of the seed layer 31 is, for example, 1 μm or less.

  The plating layer 32 is formed by electrolytic plating using the seed layer 31. The plating layer 32 is made of, for example, a layer in which Cu, Ti, Ni, Cu, or the like is laminated. The thickness of the plating layer 32 is, for example, about 3 to 10 μm. The plating layer 32 is thicker than the seed layer 31.

  The conductive layer 3 includes an element arrangement recessed pad 33, a seal chip side surface connecting portion 37, and a main surface side connecting portion 38.

  The element placement recess pad 33 is formed in the element placement recess 14, and particularly includes those formed on the element placement recess bottom surface 142. The element placement recess pad 33 formed on the element placement recess bottom surface 142 is used for mounting the electronic element 7 on the element placement recess bottom surface 142.

  The seal chip side surface connecting portion 37 is formed on the seal chip side surface 43 of the seal chip 4, and is located on the side of the seal chip back surface 42 and the portion of the conductive layer 3 formed on the seal chip main surface 41. Contact with the part. Further, in the present embodiment, the seal chip side surface connecting portion 37 reaches the end edge of the main surface 111. The seal chip side surface connecting portion 37 is configured by the seed layer 31 and the plating layer 32, but may have a layer structure other than this.

  The main surface side communication portion 38 is formed on the main surface 111, and communicates a portion of the conductive layer 3 formed in the element placement concave portion 14 with the seal chip side surface communication portion 37. In the present embodiment, most of the main surface side communication portion 38 is covered with the seal chip 4. In the case where conduction between the main surface side connecting portion 38 and the seal chip 4 is not preferable, an insulating material is selected for the bonding layer 45.

  The seal tip electrode pad 341 is formed on the seal tip main surface 41 of the seal tip 4. The seal chip electrode pad 341 is in contact with the conductive layer 3 and is electrically connected to the electronic element 7. The seal chip electrode pad 341 has a structure in which, for example, a Ni layer, a Pd layer, and an Au layer are stacked in the order close to the seal chip main surface 41 of the seal chip 4. In the present embodiment, the seal chip electrode pad 341 has a rectangular shape.

  The electronic element 7 is mounted on the element arrangement recess bottom surface 142. An example of the electronic element 7 is, for example, an integrated circuit element, and specifically, a so-called ASIC (Application Specific Integrated Circuit) element. Alternatively, other examples of the electronic element 7 include passive elements such as inductors and capacitors.

  Next, an example of a method for manufacturing the electronic device A1 will be described below with reference to FIGS.

  First, a substrate 1 is prepared as shown in FIG. The substrate 1 is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. The thickness of the substrate 1 is, for example, about 200 to 550 μm. The substrate 1 is sized to obtain a plurality of substrates 1 of the electronic device A1 described above. That is, the subsequent manufacturing process is based on a technique for manufacturing a plurality of electronic devices A1 in a lump. Although a method of manufacturing one electronic device A1 may be used, in consideration of industrial efficiency, a method of manufacturing a plurality of electronic devices A1 at once is realistic. Although the substrate 1 shown in FIG. 4 is strictly different from the substrate 1 in the electronic device A1, for convenience of understanding, any substrate is represented as the substrate 1.

  The substrate 1 has a main surface 111 and a back surface 112 facing opposite to each other. In the present embodiment, a plane having a crystal orientation (100), that is, a (100) plane is adopted as the main surface 111.

Next, a mask layer made of SiO ₂ is formed by oxidizing the main surface 111, for example. The thickness of this mask layer is, for example, about 0.7 to 1.0 μm.

  Next, the mask layer is patterned by etching, for example. Thereby, for example, a rectangular opening is formed in the mask layer. The shape and size of the opening are set according to the shape and size of the element placement recess 14 to be finally obtained.

  Next, the substrate 1 is subjected to anisotropic etching using, for example, KOH. KOH is an example of an alkaline etching solution that can realize good anisotropic etching for a Si single crystal. As a result, as shown in FIG. The element placement recess 14 has an element placement recess side surface 141 and an element placement recess bottom surface 142, and is recessed from the main surface 111. The element placement recess 14 has a rectangular shape in the thickness direction.

  Next, as shown in FIG. 6, the insulating layer 2 is formed on the main surface 111, the element arrangement concave side surface 141, and the element arrangement concave bottom surface 142 and the back surface 112 by thermal oxidation. The insulating layer 2 includes a portion that becomes the concave inner surface insulating portion 21 described above.

  Next, as shown in FIG. 7, the conductive layer 3 is formed. Formation of the conductive layer 3 includes formation of a seed layer 31 and a plating layer 32. The seed layer 31 is formed, for example, by performing patterning after performing sputtering using Cu. The plating layer 32 is formed by electrolytic plating using the seed layer 31, for example. As a result, a plated layer 32 made of a layer in which, for example, Cu, Ti, Ni, Cu or the like is laminated is obtained. The seed layer 31 and the plating layer 32 form a conductive layer 3 by being laminated. At this time, the conductive layer 3 has a shape including, for example, the element placement recessed pad 33 and the main surface side connecting portion 38.

  Next, as shown in FIG. 8, the electronic device 7 is placed in the device placement recess 14. More specifically, the electronic element 7 is mounted on the element arrangement recess bottom surface 142. For example, solder balls are formed on the electronic element 7. A flux is applied to the solder balls. The electronic element 7 is mounted using the adhesiveness of the flux.

  Next, the seal chip 4 is joined as shown in FIG. The sealing chip 4 is bonded by applying a conductive or insulating paste constituting the bonding layer 45 to a bonding portion between the sealing chip 4 and the main surface 111 and curing it. Thereby, in the present embodiment, all of the element placement recesses 14 are covered with the seal chip 4. Further, a void region 145 that occupies all of the element placement recesses 14 is formed. From the seal chip 4, the main surface side communication portion 38 is exposed.

  Next, as shown in FIG. 10, the seal chip side surface connecting portion 37 is formed. For example, the seed chip 31 is formed in a region where the seal chip side contact part 37 is to be formed, and the plating layer 32 is laminated using the seed layer 31. In the example shown in the figure, the portion of the conductive layer 3 connected to the seal chip side surface connecting portion 37 is formed on the seal chip main surface 41 of the seal chip 4. As a result, the seal chip side surface contact portion 37 contacts the main surface side contact portion 38. In the present embodiment, the seal chip side surface connecting portion 37 is made to reach the end edge of the main surface 111. This may be realized by collectively cutting the seal chip side surface connecting portion 37 and the substrate 1 after the subsequent steps are finished.

  Next, a seal chip electrode pad 341 is formed. Seal chip electrode pad 341 is formed, for example, by electroless plating a metal such as Ni, Pd, or Au.

  Then, by cutting the substrate 1 with, for example, a dicer, the electronic device A1 shown in FIGS. 1 to 3 is obtained.

  Next, the operation of the electronic device A1 will be described.

  According to the present embodiment, the element placement recess 14 is covered by the seal chip 4. Thereby, the electronic element 7 accommodated in the element arrangement recess 14 can be more appropriately protected by the seal chip 4.

  The element placement recess 14 includes a void region 145. The void area 145 is in contact with the electronic element 7. The void region 145 does not transmit force to the electronic element 7. For this reason, it is possible to suppress an external force from acting on the electronic element 7, which is preferable for protecting the electronic element 7.

  A gap region 145 is interposed between the seal chip 4 and the electronic element 7. Thereby, this force can be prevented from being transmitted from the seal chip 4 that can receive an external force or the like to the electronic element 7.

  In the present embodiment, all of the element placement recesses 14 are occupied by the gap region 145. Thereby, it can avoid more suitably that external force is transmitted to the electronic element 7. FIG.

  The void region 145 is sealed by the seal tip 4. Thereby, it is possible to prevent moisture or the like from the outside from entering the element placement recess 14 and affecting the electronic element 7.

  The seal chip 4 is provided with a seal chip side surface 43. The seal chip side surface 43 is inclined so as to be located inward in the thickness direction view from the seal chip back surface 42 toward the seal chip main surface 41. For this reason, it is possible to easily form the seal chip side surface connecting portion 37 by a technique such as plating. Thereby, the sealing chip electrode pad 341 provided on the sealing chip main surface 41 of the sealing chip 4 and the electronic element 7 can be appropriately conducted.

  The seal tip electrode pad 341 can be provided at a position overlapping the main surface 111 and the element placement recess 14 in plan view. Thereby, the planar view dimension of electronic device A1 can be reduced in size.

  FIG. 3 shows a state in which the electronic device A1 is mounted on the circuit board 8. The seal chip electrode pad 341 is bonded to the mounting pattern 81 of the circuit board 8 by solder 82. A seal chip side surface connecting portion 37 is formed on the seal chip side surface 43 of the seal chip 4. The seal tip side surface connecting portion 37 reaches the end edge of the main surface 111. As a result, the solder 82 has a so-called fillet shape that spreads outward from the edge of the seal chip side surface connecting portion 37, that is, the edge of the main surface 111. In such a form, it is possible to easily determine whether or not the electronic device A1 is appropriately mounted on the circuit board 8 by visually confirming the extent of spread of the solder 82.

  11 to 24 show another embodiment of the present invention. In these drawings, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

  FIG. 11 shows an electronic device according to a second embodiment of the present invention. The electronic device A2 of this embodiment includes a buffer member 5. FIG. 12 is a plan view showing the buffer member 5 and the electronic element 7.

  The buffer member 5 is interposed between the electronic element 7 and the seal chip 4 and is in contact therewith. The buffer member 5 is made of a material that is more easily elastically deformed than the electronic element 7. The buffer member 5 is made of a material that is more easily elastically deformed than the seal tip 4. In the present embodiment, the buffer member 5 is made of a silicone resin.

  As shown in FIG. 7, in the present embodiment, the buffer member 5 is larger than the electronic element 7 in the thickness direction view. The buffer member 5 includes the electronic element 7 as viewed in the thickness direction.

  Also in such an embodiment, the electronic element 7 accommodated in the element disposition recess 14 can be more appropriately protected by the seal chip 4. Further, by interposing the buffer member 5 between the electronic element 7 and the seal chip 4, an external force is transmitted to the electronic element 7 as compared with, for example, the case where the entire element arranging recess 14 is filled with hard resin or the like. This can be suppressed.

  Forming the buffer member 5 using a silicone resin that is more easily elastically deformed than the seal chip 4 or the electronic element 7 is preferable for protecting the electronic element 7.

  FIG. 13 shows a modification of the buffer member 5. In this modification, the buffer member 5 is annular when viewed in the thickness direction. Further, the buffer member 5 has a rectangular ring shape corresponding to the rectangular electronic element 7. Further, the buffer member 5 overlaps the end portion 71 of the electronic element 7 in the thickness direction view. In the present embodiment, the buffer member 5 overlaps all of the end portion 71.

  Also according to such a modification, the electronic element 7 can be appropriately protected.

  FIG. 14 shows a modification of the electronic device A2. FIG. 15 shows the buffer member 5 and the electronic element 7 of this modification.

  In the present modification, the buffer member 5 is partitioned into a plurality of small regions 51. The plurality of small regions 51 are separated from each other when viewed in the thickness direction. The small region 51 overlaps the end 71 when viewed in the thickness direction. In the present modification, the small region 51 overlaps the corner of the electronic element 7.

  Also according to such a modification, the electronic element 7 can be appropriately protected.

  FIG. 16 shows an electronic device according to a third embodiment of the present invention. The electronic device A3 of this embodiment includes a sealing resin portion 6.

  The sealing resin portion 6 is filled in the element placement recess 14 and covers the electronic element 7. Examples of the material of the sealing resin portion 6 include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The sealing resin portion 6 may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable. In this modification, the sealing resin portion 6 covers all of the electronic elements 7. A gap region 145 is interposed between the seal chip 4 and the sealing resin portion 6. In other words, in the present embodiment, the element placement recess 14 is occupied by the gap region 145 and the sealing resin portion 6.

  Also in such an embodiment, the electronic element 7 accommodated in the element disposition recess 14 can be more appropriately protected by the seal chip 4.

  FIG. 17 shows an electronic device according to a fourth embodiment of the present invention. The electronic device A4 of this embodiment includes a sealing resin portion 6. In the present embodiment, the sealing resin portion 6 occupies all of the element placement recesses 14. That is, in the present embodiment, the void area 145 does not exist in the element placement recess 14. The sealing resin portion 6 is in contact with both the electronic element 7 and the seal chip 4.

  Also in such an embodiment, the electronic element 7 accommodated in the element disposition recess 14 can be more appropriately protected by the seal chip 4.

  FIG. 18 shows an electronic device according to a fifth embodiment of the present invention. In the electronic device A5 of this embodiment, the seal chip shield layer 44 is formed on the seal chip 4. A substrate shield layer 18 is formed on the substrate 1.

  The seal chip shield layer 44 is a layer made of a conductive material such as a metal represented by Cu, for example. In the present embodiment, the seal chip shield layer 44 is formed on the seal chip back surface 42 of the seal chip 4. Further, the seal chip shield layer 44 covers the entire seal chip back surface 42. The seal chip shield layer 44 is preferably conducted to a ground line provided in the electronic device A1.

  The substrate shield layer 18 is a layer made of a conductive material such as a metal typified by Cu. The substrate shield layer 18 is formed on the back surface 112 of the substrate 1. The substrate shield layer 18 covers the entire back surface 112. The substrate shield layer 18 is preferably conducted to a ground line provided in the electronic device A1.

  Also in such an embodiment, the electronic element 7 accommodated in the element disposition recess 14 can be more appropriately protected by the seal chip 4. Further, the substrate shield layer 18 and the seal chip shield layer 44 can prevent the electromagnetic wave emitted from the electronic element 7 from leaking to the outside and the electromagnetic wave as noise from the outside reaching the electronic element 7. .

  19 and 20 show an electronic device according to a sixth embodiment of the present invention. The electronic device A6 of this embodiment includes a substrate 1, an insulating layer 2, a conductive layer 3, a seal chip 4, a back electrode pad 342, and an electronic element 7. FIG. 19 is a cross-sectional view of a cross section along the thickness direction of the electronic device A6. FIG. 20 is an enlarged cross-sectional view of a main part of the electronic device A6.

  The substrate 1 is made of a single crystal of a semiconductor material. In the present embodiment, the substrate 1 is made of Si single crystal. The material of the board | substrate 1 is not limited to Si, For example, SiC may be sufficient. The thickness of the substrate 1 is, for example, 200 to 550 μm. An electronic element 7 is disposed on the substrate 1.

  The substrate 1 has a main surface 111 and a back surface 112.

  The main surface 111 faces one side in the thickness direction. The main surface 111 is flat. The main surface 111 is orthogonal to the thickness direction. The main surface 111 is a (100) plane or a (110) plane. In the present embodiment, the main surface 111 is a (100) plane.

  The back surface 112 faces the other side in the thickness direction. That is, the back surface 112 and the main surface 111 face opposite to each other. The back surface 112 is flat. The back surface 112 is orthogonal to the thickness direction.

  The substrate 1 is provided with a recess 14 for element arrangement and two through holes 17.

  The element placement recess 14 is recessed from the main surface 111. The electronic element 7 is arranged in the element arranging recess 14. The depth of the element placement recess 14 (the separation dimension in the thickness direction between the main surface 111 and the element placement recess bottom 142 described later) is, for example, 100 to 300 μm. The element placement recess 14 has a rectangular shape when viewed in the thickness direction. The shape of the element placement recess 14 depends on the adoption of the (100) plane as the main surface 111.

  The element placement recess 14 has an element placement recess side surface 141 and an element placement recess bottom surface 142.

  The element placement recess bottom surface 142 faces the same side as the main surface 111 in the thickness direction of the substrate 1. The element placement recess bottom surface 142 has a rectangular shape when viewed in the thickness direction. The electronic element 7 is arranged on the element arrangement recess bottom surface 142. The element placement recess bottom surface 142 is a surface orthogonal to the thickness direction.

  The element arrangement recess side surface 141 rises from the element arrangement recess bottom surface 142. The element arrangement recess side surface 141 is connected to the element arrangement recess bottom surface 142. The element arrangement concave side surface 141 is inclined with respect to the thickness direction. The angle of the element placement recess side surface 141 with respect to the plane orthogonal to the thickness direction is 55 degrees. This is because the (100) plane is adopted as the main surface 111. The element arrangement recess side surface 141 has four flat surfaces.

  The through-hole 17 penetrates a part of the substrate 1 from the bottom surface 142 for element placement to the back surface 112. In the present embodiment, the number of through holes 17 is plural (two). The depth of the through hole 17 is, for example, 10 to 50 μm. The maximum opening dimension of the through hole 17 in the thickness direction of the substrate 1 is, for example, 10 to 50 μm. The ratio of the depth of the through hole 17 to the maximum opening size of the through hole 17 in the thickness direction of the substrate 1 is 0.2 to 5. In the present embodiment, the through hole 17 has a rectangular shape when viewed in the thickness direction. In the present embodiment, the through-hole 17 has a larger cross-sectional dimension from the main surface 111 side toward the back surface 112 side in the thickness direction.

  The through hole 17 has a through hole inner surface 171.

  The through hole inner surface 171 is inclined with respect to the thickness direction of the substrate 1. The through-hole inner surface 171 has four flat surfaces. In the present embodiment, the through-hole inner surface 171 is connected to the element placement recess bottom surface 142 and the back surface 112. The angle of the through-hole inner surface 171 with respect to the plane orthogonal to the thickness direction is 55 degrees. This is because the (100) plane is adopted as the main surface 111.

The insulating layer 2 is interposed between the conductive layer 3 and the substrate 1. The thickness of the insulating layer 2 is, for example, about 0.1 to 1.0 μm. The insulating layer 2 is made of, for example, SiO ₂ or SiN.

  The insulating layer 2 has a concave inner surface insulating part 21, a through hole inner surface insulating part 22, an auxiliary through hole inner surface insulating part 23, and a back surface side insulating part 24.

The recess inner surface insulating portion 21 is formed in the element placement recess 14 of the substrate 1. In the present embodiment, the concave portion inner surface insulating portion 21 is formed on all of the element arrangement concave side surface 141 and the element arrangement concave bottom surface 142. The recess inner surface insulating portion 21 is formed by, for example, thermal oxidation. The recess inner surface insulating portion 21 is made of, for example, SiO ₂ .

  An auxiliary through hole 211 is formed in the recess inner surface insulating portion 21. The auxiliary through hole 211 penetrates the recessed portion inner surface insulating portion 21 in the thickness direction. Further, the auxiliary through hole 211 is located in the through hole 17 in the thickness direction view. The auxiliary through hole 211 has a constant cross-sectional shape in the thickness direction.

The through hole inner surface insulating portion 22 is formed on the through hole inner surface 171 of the through hole 17. The through hole inner surface insulating portion 22 is formed by, for example, CVD (Chemical Vapor Deposition). The through hole inner surface insulating portion 22 is made of, for example, SiO ₂ or SiN.

The auxiliary through hole inner surface insulating portion 23 is formed on the inner surface of the auxiliary through hole 211 of the concave portion inner surface insulating portion 21. The auxiliary through hole inner surface insulating portion 23 is formed by, for example, CVD (Chemical Vapor Deposition). The auxiliary through hole inner surface insulating portion 23 is made of, for example, SiO ₂ or SiN.

At least a part of the back surface side insulating portion 24 is formed on the back surface 112 of the substrate 1. The back surface side insulating part 24 is formed by thermal oxidation. The back side insulating part 24 is made of, for example, SiO ₂ . In the present embodiment, the back surface side insulating portion 24 covers the entire back surface 112.

  The seal chip 4 has a seal chip main surface 41 facing the same side as the main surface 111 in the thickness direction and a seal chip back surface 42 facing the opposite side to the seal chip main surface 41. The seal chip 4 covers at least a part of the element placement recess 14 on the main surface 111 side. In the present embodiment, the seal chip 4 covers all of the element placement recesses 14. The seal tip 4 is made of Si, for example. Further, an integrated circuit that performs a part of the function of the electronic device A6 may be built in the seal chip 4. The seal chip 4 is bonded to the main surface 111 with a bonding layer 45. The bonding layer 45 may be a conductive material or an insulating material.

  In the present embodiment, the element placement recess 14 is sealed by the seal chip 4. In addition, the element placement recess 14 includes a void region 145. The void region 145 is a space such as an inert gas or a vacuum. In the present embodiment, all of the element placement recesses 14 are occupied by the gap regions 145. The void area 145 is in contact with the electronic element 7. In addition, a gap region 145 is interposed between the electronic element 7 and the seal chip 4.

  The thickness of the seal chip 4 may be a thickness that can appropriately protect the electronic element 7. Further, the thickness of the seal chip 4 may be set for the purpose of adjusting the thickness of the entire electronic device A6 when the thickness of the substrate 1 is fixed.

  The conductive layer 3 is electrically connected to the electronic element 7. The conductive layer 3 is for configuring a current path for inputting and outputting to the electronic element 7. The conductive layer 3 is formed on the element arrangement recess side surface 141, the element arrangement recess bottom surface 142, the through-hole inner surface 171, and the back surface 112. More specifically, the conductive layer 3 is formed from the element placement recess 14 to the back surface 112 via the through hole inner surface 171.

  The conductive layer 3 includes a seed layer 31 and a plating layer 32.

  The seed layer 31 is a so-called underlayer for forming a desired plating layer 32. The seed layer 31 is interposed between the substrate 1 and the plating layer 32. The seed layer 31 is made of Cu, for example. The seed layer 31 is formed by sputtering, for example. The thickness of the seed layer 31 is, for example, 1 μm or less.

  The plating layer 32 is formed by electrolytic plating using the seed layer 31. The plating layer 32 is made of, for example, a layer in which Cu, Ti, Ni, Cu, or the like is laminated. The thickness of the plating layer 32 is, for example, about 3 to 10 μm. The plating layer 32 is thicker than the seed layer 31.

  The conductive layer 3 includes a device placement recess pad 33, a through hole inner surface conductive portion 35, and an auxiliary through hole blocking portion 36.

  The element placement recess pad 33 is formed in the element placement recess 14, and particularly includes those formed on the element placement recess bottom surface 142. The element placement recess pad 33 formed on the element placement recess bottom surface 142 is used for mounting the electronic element 7 on the element placement recess bottom surface 142.

  The through hole inner surface conductive portion 35 includes a portion formed on the through hole inner surface 171 of the through hole 17. In the present embodiment, as shown in FIG. 20, the through hole inner surface conductive portion 35 includes a portion of the through hole inner surface 171 of the through hole 17 laminated on the through hole inner surface insulating portion 22 and the auxiliary through hole. Part formed in the inner surface insulating part 23. Furthermore, the through-hole inner surface conductive portion 35 includes a portion that is disposed so as to form the bottom surface of the through-hole 17 and is perpendicular to the thickness direction.

  The auxiliary through-hole blocking part 36 closes the through-hole 17 from the main surface 111 side, and forms the same layer as that formed on the element placement recess bottom surface 142 of the element placement recess pad 33. The auxiliary through hole blocking portion 36 and the through hole inner surface conductive portion 35 are in contact with each other.

  At least a part of the back surface side insulating film 25 is formed on the back surface 112. The back side insulating film 25 has a portion formed in the through hole 17. The conductive layer 3 is interposed between the back side insulating film 25 and the substrate 1. The back side insulating film 25 is made of SiN, for example. The back side insulating film 25 is formed by, for example, CVD.

  The back electrode pad 342 is formed on the back surface 112. The back electrode pad 342 is in contact with the conductive layer 3 and is electrically connected to the electronic element 7. The back electrode pad 342 has a structure in which, for example, a Ni layer, a Pd layer, and an Au layer are stacked in the order closer to the substrate 1. In the present embodiment, the back electrode pad 342 has a rectangular shape.

  The electronic element 7 is mounted on the element arrangement recess bottom surface 142. An example of the electronic element 7 is, for example, an integrated circuit element, and specifically, a so-called ASIC (Application Specific Integrated Circuit) element. Alternatively, other examples of the electronic element 7 include passive elements such as inductors and capacitors.

  Also in such an embodiment, the electronic element 7 accommodated in the element disposition recess 14 can be more appropriately protected by the seal chip 4.

  In addition, a through hole 17 is formed in the substrate 1 so as to penetrate from the element placement recess 14 to the back surface 112. The conductive layer 3 is formed from the element placement recess 14 to the back surface 112 via the through hole inner surface 171. According to such a configuration, it is possible to form a current path from the element arrangement recess 14 side to the back surface 112 side. As a result, a configuration is realized in which a conduction path necessary for operating the electronic element 7 is overlapped with the electronic element 7 in a thickness direction view, for example. Therefore, it is suitable for reducing the size of the electronic device A6 when viewed in the thickness direction.

  In the present embodiment, the through hole inner surface 171 is inclined with respect to the thickness direction Z. According to such a configuration, the through-hole inner surface 171 can be formed relatively flat. Therefore, the advantage that it is easy to form the seed layer 31 (that is, the conductive layer 3) can be enjoyed.

  The auxiliary through-hole blocking portion 36 and the through-hole inner surface conductive portion 35 are in contact with each other at the boundary portion between the element placement recess 14 (element placement recess bottom surface 142) and the through-hole 17. This contact is made in an area corresponding to the area of the bottom of the through hole 17. Therefore, conduction between the auxiliary through hole blocking portion 36 and the through hole inner surface conductive portion 35, that is, a portion formed on the back surface 112 side of the conductive layer 3, and a portion formed on the element placement concave portion 14 side of the conductive layer 3. The portion can be more reliably conducted.

  FIG. 21 shows an electronic device according to a seventh embodiment of the present invention. The electronic device A7 of the present embodiment includes a buffer member 5.

  The buffer member 5 is interposed between the electronic element 7 and the seal chip 4 and is in contact therewith. The buffer member 5 is made of a material that is more easily elastically deformed than the electronic element 7. The buffer member 5 is made of a material that is more easily elastically deformed than the seal tip 4. In the present embodiment, the buffer member 5 is made of a silicone resin.

  In the present embodiment, the buffer member 5 is larger than the electronic element 7 in the thickness direction view. The buffer member 5 includes the electronic element 7 as viewed in the thickness direction.

  Also in such an embodiment, the electronic element 7 accommodated in the element disposition recess 14 can be more appropriately protected by the seal chip 4.

  FIG. 22 shows a modification of the electronic device A7.

  In the present modification, the buffer member 5 is partitioned into a plurality of small regions 51. The plurality of small regions 51 are separated from each other when viewed in the thickness direction. The small region 51 overlaps the end 71 when viewed in the thickness direction. In the present modification, the small region 51 overlaps the corner of the electronic element 7.

  Also according to such a modified example, the electronic element 7 accommodated in the element arranging recess 14 can be more appropriately protected by the seal chip 4.

  FIG. 23 shows an electronic device according to an eighth embodiment of the present invention. In the electronic device A8 of this embodiment, the seal chip shield layer 44 is formed on the seal chip 4.

  The seal chip shield layer 44 is a layer made of a conductive material such as a metal represented by Cu, for example. In the present embodiment, the seal chip shield layer 44 is formed on the seal chip back surface 42 of the seal chip 4. Further, the seal chip shield layer 44 covers the entire seal chip back surface 42. The seal chip shield layer 44 is preferably conducted to a ground line provided in the electronic device A1.

  Also in such an embodiment, the electronic element 7 accommodated in the element disposition recess 14 can be more appropriately protected by the seal chip 4.

  FIG. 24 shows a modification of the electronic device A8. In this modification, a seal chip shield layer 44 is formed on the seal chip main surface 41 of the seal chip 4.

  Also according to such a modified example, the electronic element 7 accommodated in the element arranging recess 14 can be more appropriately protected by the seal chip 4.

  The electronic device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the electronic device according to the present invention can be varied in design in various ways.

A1 to A8 Electronic device 1 Substrate 111 Main surface 112 Back surface 14 Element placement concave portion 142 Element placement concave bottom surface 141 Element placement concave side surface 145 Air gap region 17 Through hole 171 Through hole inner surface 18 Substrate shield layer 2 Insulating layer 21 Recess inner surface insulation Portion 211 auxiliary through hole 22 through hole inner surface insulating portion 23 auxiliary through hole inner surface insulating portion 24 back surface side insulating portion 25 back surface side insulating film 3 conductive layer 31 seed layer 32 plated layer 33 element placement recess pad 35 through hole inner surface conductive portion 36 Auxiliary through hole sealing part 37 Seal chip side surface connection part 38 Main surface side communication part 341 Seal chip electrode pad 342 Back surface electrode pad 4 Seal chip 41 Seal chip main surface 42 Seal chip back surface 43 Seal chip side surface 44 Seal chip shield layer 45 Bonding layer 5 Buffer member 51 Small region 6 Sealing resin portion 7 Electronic element 71 End portion 8 Circuit base Board 81 Mounting pattern 82 Solder

Claims (53)

A substrate having a main surface and a back surface facing opposite sides in the thickness direction, and made of a semiconductor material;
An electronic element disposed on the substrate;
An electronic device comprising a conductive layer conducting to the electronic element,
The substrate is formed with a concave portion for element arrangement that is recessed from the main surface,
The electronic element is arranged in the concave portion for element arrangement,
A seal chip main surface facing away from the element placement recess in the thickness direction; and a seal chip back surface facing away from the seal chip principal surface; and the element placement on the main surface side. An electronic device comprising a seal chip covering at least a part of the recess. The element placement recess has an element placement recess bottom surface facing the thickness direction,
The electronic device according to claim 1, wherein the electronic element is disposed on a bottom surface of the element disposing recess.   The electronic device according to claim 2, wherein the element placement recess has an element placement recess side surface that rises from the element placement recess bottom surface.   The electronic device according to claim 3, wherein the bottom surface of the concave portion for element arrangement is a surface orthogonal to the thickness direction.   The electronic device according to claim 4, wherein the side surface of the concave portion for element arrangement is inclined with respect to the thickness direction.   The electronic device according to claim 5, wherein an angle of the element arrangement recess side surface with respect to the element arrangement recess bottom surface is 55 degrees.   The electronic device according to claim 6, wherein the substrate is made of a single crystal of a semiconductor material.   The electronic device according to claim 7, wherein the semiconductor material is Si.   The electronic device according to claim 8, wherein the main surface and the back surface are orthogonal to the thickness direction of the substrate and are flat.   The electronic device according to claim 9, wherein the main surface is a (100) surface.   11. The electronic device according to claim 3, wherein the side surface of the concave portion for element arrangement is connected to the main surface.   The electronic device according to claim 3, wherein the seal chip is bonded to the main surface.   The electronic device according to claim 12, wherein the seal chip is made of Si.   The electronic device according to claim 13, wherein an integrated circuit is built in the seal chip.   The electronic device according to claim 3, wherein a gap region is provided in the element placement recess.   The electronic device according to claim 15, wherein the void region is in contact with the electronic element.   The electronic device according to claim 16, wherein the electronic element and the seal chip are separated via the gap region.   The electronic device according to claim 17, wherein the gap region occupies all of the element placement recesses.   The electronic device according to claim 17, further comprising a sealing resin portion that occupies at least a part of the element placement recess.   The electronic device according to claim 19, wherein the sealing resin portion is in contact with the electronic element.   The electronic device according to claim 20, wherein the sealing resin portion covers all of the electronic elements.   The electronic device according to claim 21, wherein the sealing resin portion and the seal chip are separated via the gap region.   The electronic device according to claim 17, further comprising a buffer member interposed between the electronic element and the seal chip.   The electronic device according to claim 23, wherein the buffer member is made of a material that is more easily elastically deformed than the electronic element.   25. The electronic device according to claim 24, wherein the buffer member is made of a material that is more easily elastically deformed than the seal tip.   26. The electronic device according to claim 25, wherein the buffer member is made of a silicone resin.   27. The electronic device according to claim 23, wherein the buffer member is larger than the electronic element in the thickness direction view.   28. The electronic device according to claim 27, wherein the buffer member includes the electronic element in the thickness direction view.   27. The electronic device according to claim 23, wherein the buffer member is partitioned into a plurality of small regions that are separated from each other when viewed in the thickness direction.   30. The electronic device according to claim 29, wherein the plurality of small regions overlap an end portion of the electronic element when viewed in the thickness direction.   The electronic device according to claim 3, further comprising a sealing resin portion that occupies all of the element arrangement recesses.   32. The electronic device according to claim 3, further comprising a seal tip electrode pad formed on the seal tip main surface. The seal chip has a seal chip side surface that is inclined so as to be located inward in the thickness direction view from the back surface of the seal chip toward the main surface of the seal chip.
The electronic device according to claim 32, wherein the conductive layer includes a seal chip side surface connecting portion formed on the side surface of the seal chip.   The electronic device according to claim 33, wherein the seal chip side surface connecting portion reaches an end edge of the main surface.   The electronic device according to claim 33 or 34, wherein the conductive layer includes a main surface side connecting portion formed on the main surface of the substrate.   36. The electronic device according to any one of claims 33 to 35, wherein the conductive layer includes a concave side surface connecting portion formed on a side surface of the concave portion for element arrangement of the substrate. In the substrate, a through-hole penetrating from the element placement recess to the back surface is formed,
The through hole has a through hole inner surface;
32. The electronic device according to claim 3, wherein the conductive layer is formed from the element placement recess to the back surface via the through hole inner surface.   38. The electronic device according to claim 37, further comprising an insulating layer formed on the substrate, wherein the insulating layer is interposed between the conductive layer and the substrate.   39. The electronic device according to claim 38, wherein the insulating layer is made of SiO2 or SiN.   40. The electronic device according to claim 38 or 39, wherein the insulating layer includes a recessed portion inner surface insulating portion formed on an inner surface of the element arranging recessed portion.   41. The electronic device according to claim 40, wherein the insulating layer includes a through hole inner surface insulating portion formed on an inner surface of the through hole.   42. The electronic device according to claim 41, wherein the through hole has a cross-sectional dimension that increases from the main surface side toward the back surface side.   43. The electronic device according to claim 42, wherein the recessed portion inner surface insulating portion has an auxiliary through hole positioned as an edge on the main surface side of the through hole in a thickness direction view.   44. The electronic device according to claim 43, wherein the auxiliary through hole has a constant cross-sectional shape in the thickness direction.   45. The electronic device according to claim 44, wherein the insulating layer includes an auxiliary through hole inner surface insulating portion formed on an inner surface of the auxiliary through hole and connected to the through hole inner surface insulating portion.   46. The electronic device according to claim 45, wherein the conductive layer includes an auxiliary through hole blocking portion that closes the auxiliary through hole in the element arrangement recess.   47. The electronic device according to claim 46, wherein the conductive layer includes a through hole inner surface conductive portion at least partially formed in the through hole inner surface insulating portion and in contact with the auxiliary through hole blocking portion. A back electrode pad formed on the back surface;
48. The electronic device according to claim 37, wherein the back electrode pad is in contact with the conductive layer and is electrically connected to the electronic element.   49. The electronic device according to claim 3, wherein a seal chip shield layer made of a conductive material is formed on the seal chip.   50. The electronic device according to claim 49, wherein the seal chip shield layer is formed on a back surface of the seal chip.   51. The electronic device according to claim 50, wherein the seal chip shield layer covers all of the back surface of the seal chip.   52. The electronic device according to claim 49, wherein a substrate shield layer is formed on the back surface of the substrate.   53. The electronic device according to claim 52, wherein the substrate shield layer covers all of the back surface.

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