JP2016143378A - Parallelization compilation method, parallelization compiler, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate quality maintenance and management of parallelization programs.SOLUTION: A sequential program, which is executed by a single processor system and contains descriptions to be selected or unselected as compiling targets in accordance with input information by means of conditional compiling, is divided into a plurality of macro tasks regardless of the input information. Parallelly executable macro tasks are then assigned to different processor units to produce a parallelization program to be executed by a multi-processor system (S110). Descriptions not selected as compiling targets because of prescribed input information are removed from the parallelization program (S130).SELECTED DRAWING: Figure 2

Description

  The present invention relates to a parallel compilation method, a parallel compiler, and an electronic apparatus.

  In an in-vehicle device in which a multi-core processor is mounted, it is known that throughput is improved by distributing functions to each core (Non-Patent Document 1). A parallel compiler that generates a parallel program that can be processed in parallel by a multi-core processor from a program (sequential program) for a single core processor is known.

K Seo, J Yoon, J Kim, T Chung, K Yi, N Chang, “Coordinated implementation and processing of a unified chassis control algorithm with multi-central processing unit”, JAUTO1346 IMechE, 2009, Vol.224 Part D

  Here, in a sequential program, there are cases where a description to be compiled is selected according to a destination by a conditional compilation switch (conditional compilation). When a parallelized program is generated from such a sequential program using a parallelizing compiler, generally, a part to be compiled is first identified from the sequential program based on a conditional compilation switch, and then the parallel program is determined from the part. A generalized program is generated.

  However, if the part to be compiled is changed, there is a possibility that the data dependency and control dependency between the macro tasks constituting the sequential program may change. For this reason, in a plurality of parallel programs with different destinations generated from the same sequential program, the processing contents assigned to each processor core are generated from the same sequential program and have equivalent functions. It can be very different. As a result, it becomes difficult to maintain quality and manage parallelized programs.

  An object of the present invention is to facilitate the maintenance and management of the quality of a parallelized program.

  A parallelized compilation method according to one aspect of the present invention is a program executed by a single processor system, and includes a conditional description for selecting whether to compile according to input information by conditional compilation. The processing described in the sequential program is divided into a plurality of macro tasks regardless of input information (S210), and the plurality of processor units constituting the multiprocessor system are based on the data dependency between the macro tasks. An extraction procedure (S220) for extracting macrotasks that can be executed in parallel, and a process for assigning each macrotask to any one of the processor units, wherein all or some of the macrotasks that can be executed in parallel are different processors. Assigned to a unit and executed by a multiprocessor system A scheduling procedure for static scheduling (S110), the generating a parallelized program that.

  According to such a configuration, a parallelized program is generated from the sequential program in a state including all conditional descriptions. Then, by setting the input information, it becomes possible to remove a portion that is not subject to compilation from the conditional description in the parallelized program.

  For this reason, no matter what input information is set, processes other than the process corresponding to the conditional description (a process that is always executed regardless of the contents of the input information) are always assigned to the same processor unit. . In other words, even when multiple types of parallelized programs with different destinations are generated by setting the input information, the commonality of each type of parallelized program can be further enhanced. This makes it easy to maintain and manage the quality of parallelized programs.

  In addition, the code | symbol in the parenthesis described in this column and a claim shows the correspondence with the specific means as described in embodiment mentioned later as one aspect, Comprising: The technical scope of this invention is shown. It is not limited.

It is a block diagram which shows the structure of PC in which the automatic parallelizing compiler was installed. It is a flowchart of an automatic parallelization process. It is a flowchart of a soft structure analysis process. It is a block diagram which shows the structure of a vehicle-mounted apparatus. It is explanatory drawing of the sequential program in the specific example 1, allocation information, and a comparison program. 10 is a table showing processing times and the like of processing described in the sequential program in specific example 1; 10 is a table showing a verification result of performance of a comparison program generated in specific example 1; It is explanatory drawing of the sequential program and MTG in the specific example 2. FIG. It is explanatory drawing of MTG and the allocation information in the specific example 2. 10 is a table showing processing times and the like of processing described in the sequential program in specific example 2. 10 is a table showing parallel execution times of comparison programs generated in specific example 2; 10 is a table showing verification results of the performance of a comparison program generated in specific example 3. It is explanatory drawing of the sequential program in the specific example 4. 10 is a table showing arguments of conditional compilation switches in specific example 4. 10 is a table showing argument compile switch values corresponding to various types in specific example 4. It is explanatory drawing of the comparison program produced | generated by the specific example 4. It is explanatory drawing of the comparison program produced | generated by the specific example 4.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiment of the present invention is not limited to the following embodiment, and can take various forms as long as they belong to the technical scope of the present invention.

[About this embodiment]
1. About the automatic parallelizing compiler The automatic parallelizing compiler of this embodiment has a function of generating a parallel processing program for a multiprocessor system for an embedded system from a source program (sequential program) for a single processor system for an embedded system. doing.

1-1. Design concept of automatic parallelizing compiler The automatic parallelizing compiler of this embodiment has the following functions.
(1) Multigrain parallel processing (2) Static scheduling code insertion at compile time (3) Dynamic scheduling code generation at runtime (4) Realization of hierarchical macro data flow (5) Split / fusion of macro tasks, Loop Extraction of parallelism such as distribution / interchange (6) Improvement of data transfer efficiency by data localization (7) Power reduction by compiler 1-2. Internal processing of automatic parallelizing compiler The automatic parallelizing compiler has three stages of Front End (FE), Middle Path (MP), and Back End (BE). Each stage is independent as an execution form, and code is exchanged by an intermediate language generated from FE and MP.

  Note that FE is a part that generates an intermediate language that can be parsed in MP by performing lexical analysis and syntax analysis on the source code of the sequential program. The intermediate language generated by the FE is basically expressed by a parse tree having four operands, forms one block as a whole, and is not structured.

MP is a part that performs control dependency analysis, data dependency analysis, optimization, and the like, and performs coarse grain, medium grain, and near fine grain parallel processing using the data.
The BE is a part that reads the parallelized intermediate language generated by the MP and generates an actual machine code. This part has BE that generates parallel Fortran code for OpenMP and C code in addition to BE that generates assembler code of the target multi-core architecture. Furthermore, the part has a BE that outputs codes corresponding to various architectures, such as a BE that generates a parallelized code including memory allocation and data transfer by a parallelized API described later.

1-3. Parallelism analysis of automatic parallelizing compiler The automatic parallelizing compiler converts sequential programs into three types of coarse-grained tasks (macrotasks (MT)): basic blocks (BB), repetitive blocks (RB), and subroutine blocks (SB). Performs macro data flow processing to be divided.

However, the macro data flow processing has a problem that the utilization efficiency of the processor does not increase depending on the shape of the program, and sufficient coarse grain parallelism cannot be extracted.
Therefore, the automatic parallelizing compiler expands the conventional single-layer macro data flow processing method and employs hierarchical macro data flow processing that hierarchically uses the macro data flow processing inside the MT. In hierarchical macro data flow processing, MT is defined hierarchically and parallelism between macro tasks is analyzed for macro tasks in each hierarchy.

<Generation of macro flow graph (MFG)>
The automatic parallelizing compiler first analyzes the control dependency and the data dependency between macrotasks for the generated macrotasks of each layer. The analysis result is represented as a macro flow graph (MFG).

<Generation of macro task graph (MTG)>
MFG expresses control dependency and data dependency between macro tasks, but does not express parallelism. In order to extract parallelism, it is necessary to perform the earliest feasible condition analysis considering both control dependency and data dependency for each macro task. The earliest executable condition is a condition in which the MT can be executed at the earliest time, and is obtained from the following execution condition.

(1) If MTi is data-dependent on MTj, MTi cannot be executed until MTj has been executed.
(2) If the conditional branch destination of MTj is determined, MTi that is dependent on MTj can be executed even if execution of MTj is not completed.

Therefore, the general form of the earliest feasible condition is as follows.
(MTj on which MTi depends on control branches to MTi)
AND
((MTk where MTi is data-dependent (0 ≦ k ≦ | N |) ends) OR (determines that MTk is not executed))
The earliest executable condition of the macro task is represented by a macro task graph (MTG).

1-4. Multi-grain parallel processing In addition to the conventional loop parallelization, the automatic parallelizing compiler uses coarse-grained task parallelism that uses parallelism between coarse-grained tasks between loops and subroutines, and near-parallel processing that uses parallelism between statements. Multi-grain parallel processing that effectively combines fine-grain parallel processing (Reference 1 (Hiroki Honda, Masahiko Iwata, Hironori Kasahara, “Parallelity detection method between Fortran coarse-grained tasks”, IEICE Transactions, 1990))).

<Coarse grain task parallel processing>
The automatic parallelizing compiler generates a macro flow graph (MFG) that expresses the control dependency and data dependency between MTs such as BB, RB, SB, etc., and further, between MTs extracted from MFG by the earliest executable condition analysis Is expressed as a macrotask graph (MTG) (Reference 1, Reference 2 (Kasahara, Goda, Yoshida, Okamoto, Honda, “Macro Task Generation Method for Fortran Macro Data Flow Processing”), Science Theory 1992, Vol. J75-DI, No. 8, pp. 511-525)).

Thereafter, the automatic parallelizing compiler assigns the MT on the MTG to a processor group (PG) in which one or more processor elements (PE) are grouped.
<Medium-grain parallel processing>
If the MT assigned to the PG can be processed in parallel at the DOALL loop or iteration level, the MT is subjected to medium-grain parallel processing by the processors in the processor cluster. This medium-grain parallel processing is parallel processing using parallelism between DO loop iterations, and is the most common parallel processing in a multiprocessor.

<Near Fine Grain Parallel Processing>
Parallel processing for statement-level near-fine-grain tasks is called near-fine-grain parallel processing. As a result, statements that do not depend on can be executed in parallel, and the execution time is shortened.

1-5. Macrotask scheduling In coarse-grained task parallel processing, macrotasks generated at each level are assigned to PGs and executed. There are the following dynamic scheduling and static scheduling as scheduling methods for determining which PG a macro task is assigned to, and these are selected based on the shape of the macro task graph, non-determinism during execution, and the like.

<Dynamic scheduling>
When there is execution-time uncertainty such as conditional branching, a macrotask is assigned to a PG at the time of execution by dynamic scheduling. The dynamic scheduling routine operates the macro task execution management table according to the end of the macro task or the determination of the branch direction, and checks the earliest executable condition of each macro task.

  If the macro task can be executed, the macro task is put into the ready queue. The macrotasks in the ready queue are sorted according to their priorities, and the first macrotask in the ready queue is assigned to an idle processor cluster.

  Also, when generating dynamic scheduling code, a centralized scheduling method in which one dedicated processor performs scheduling and a distributed scheduling method in which the scheduling function is distributed to each processor can be used according to the number of processors used and the synchronization overhead of the system. it can.

<Static scheduling>
On the other hand, static scheduling is used when the macrotask graph has only data-dependent edges, and the automatic parallelizing compiler determines the assignment of macrotasks to PGs during compilation.

  Static scheduling can be effectively used for scheduling fine-grained tasks because it eliminates runtime scheduling overhead and minimizes data transmission and synchronization overhead.

  In the case of static scheduling, the task cost estimate value of the automatic parallelizing compiler is applied to the task cost. However, it is also possible to perform task scheduling at the actual cost by using the automatic profile parallel feedback function of the automatic parallelizing compiler. It is.

  When the profile automatic feedback function is used, as a first phase, the sequential program is decomposed into MTs, and a profiler function is inserted for each MT to generate a sequential program. This profiler function measures the task execution cost (clock cycle) and the number of task executions. By executing the sequential program in which the profiler function is inserted once on the target machine, a file having information on the task execution cost and the task execution number on the target machine is output.

Then, in the second phase, the parallelized program scheduled based on the actual cost is generated using the output file and the sequential program as input.
1-6. Data localization An automatic parallelizing compiler can perform cache optimization over the entire program. After analyzing the parallelism between loops, etc., if the automatic parallelizing compiler finds that there is data dependence between the loops, it tries to optimize the cache globally between the loops with dependence (Reference 3 (Patent No. 3). No. 4,177,681)).

  Specifically, the array accessed in each loop is investigated, and the same divided loop is allocated to the same processor by adjusting so as to access the same array portion. As a result, in the same divided loop, all the array data is reused on the cache.

In addition, this localization technology
(1) When a local memory or a distributed shared memory of an arbitrary size is provided, a local memory close to the processor is accessed before being accessed using DMA (DTU) (see Reference 4 (Japanese Patent No. 4476267)). Alternatively, it is preloaded into the distributed shared memory and reused throughout the program.

  (2) When the destination memory is full, when the DTU of the destination processor is informed by the synchronization flag that the data has been flushed to the shared memory or the like according to the flushing priority from the memory, it is automatically freed Transfer data to memory.

  (3) Data that will be reused in the future, but will not be used for a while, and if the memory area needs to be opened, the DTU saves the data to the centralized shared memory behind the task execution by the CPU. Reload by use.

It has evolved to local memory management and data transfer technology (Reference 5 (UK Patent No. 2478874)).
1-7. Generation of a parallelized program Parallelized programs are generated by an automatic parallelizing compiler using an automatic parallelizing API (see Reference 7 (Waseda University, "Optimally Scheduled Advanced Multiprocessor Application Program Interface", 2008)). Alternatively, parallelization can be done with source-to-source, such as parallelized Fortran.

  In this case, the automatic parallelizing compiler can execute the parallelized program on various platforms, so that the C or Fortran directive part for each processor is executed at runtime using the automatic parallelizing API standard interpretation system described later. Convert to library call. Thereafter, the automatic parallelizing compiler compiles the code for each processor with a sequential compiler to generate a binary, and when this binary is linked, the parallelized program can be executed on the target multiprocessor.

2. Next, features of the sequential program for the embedded system will be described, and a parallelization method by the automatic parallelizing compiler of this embodiment will be described. Note that the embedded system may be, for example, an in-vehicle device or an electronic device other than the in-vehicle device. The sequential program may be automatically generated by model-based design (as an example, automatically generated by MatWork (registered trademark) or Simulink (registered trademark) of MathWork).

  The automatic parallelizing compiler is composed of conditional branches and assignment statements, and performs inline expansion and renaming on sequential programs with fine processing to extract parallelism. In addition, task scheduling for conditional branch concealment is performed in order to comply with real-time characteristics, and static scheduling is performed so as to reduce overhead. Further, an automatic profile feedback function may be applied to perform static scheduling at an actual cost.

  In a sequential program, conditional compilation (selection to the preprocessor) performs conditional compilation to select a description to be compiled according to various types of embedded systems with different destinations, functions, hardware configurations, etc. May be. In such a case, by setting information corresponding to one of the types (information indicating the destination) as an argument of each conditional compilation switch of the sequential program, the binary code corresponding to the type can be obtained from the sequential program. Generated.

  On the other hand, the automatic parallelizing compiler of this embodiment ignores the selection of the compilation target by conditional compilation, performs macro task division, parallelism extraction, static scheduling, etc. for all parts of the sequential program. Generate a parallelized program. Thereafter, a description that is not subject to compilation is identified from the parallelized program by conditional compilation, and binary data for operating the multi-core processor is generated without the description.

2-1. Operating Environment of Automatic Parallelizing Compiler The automatic parallelizing compiler 1 is a storage medium configured as, for example, an optical disk such as a DVD, CD-ROM, USB memory, or memory card (registered trademark), a magnetic disk, a semiconductor memory, or the like. 18 is provided to the user in the state stored in 18 (see FIG. 1). Of course, it may be provided to the user via the network.

  The personal computer (PC) 10 in which the automatic parallelizing compiler 1 is installed operates as an automatic parallelizing compiling device. The PC 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a reading unit 17, and the like.

The display 11 displays the video signal received from the CPU 13 as a video to the user.
The input device 16 includes a keyboard and a mouse, and outputs a signal corresponding to the operation to the CPU 13 when operated by the user.

The reading unit 17 is a part that reads data from the storage medium 18 in which the automatic parallelizing compiler 1 or the like is stored.
The RAM 15 is a readable / writable volatile memory, the ROM 14 is a read-only nonvolatile memory, and the HDD 12 is a readable / writable nonvolatile memory. In the ROM 14 and the HDD 12, programs that are read and executed by the CPU 13 are stored in advance.

  The RAM 15 is a storage area for temporarily storing the program when the CPU 13 executes the program stored in the ROM 14 or the HDD 12 or a storage area for temporarily storing work data. Used.

  Further, the CPU 13 reads the OS from the HDD 12 and executes it, and executes various programs recorded on the HDD 12 as processes on the OS. In this process, the CPU 13 receives an input of a signal from the input device 16 as necessary, outputs a video signal to the display 11, and controls data read / write to the RAM 15 and the HDD 12.

  In addition, the automatic parallelizing compiler 1 read from the storage medium 18 via the reading unit 17 is installed in the PC 10, and the automatic parallelizing compiler 1 is stored in the HDD 12 and executed as a process on the OS. One of the applications.

  This automatic parallel compilation device is used for developing a parallel program for an embedded system such as an in-vehicle device. However, the present invention is not limited to this, and can be used, for example, for developing parallel programs for embedded systems for various uses such as information appliances, and for developing parallel programs for other uses other than embedded systems.

2-2. Automatic Parallelization Processing Next, automatic parallelization processing for generating a parallelized program based on a sequential program that is subjected to conditional compilation will be described with reference to the flowchart of FIG. By the conditional compilation, binary data mounted on the embedded system of the type corresponding to the argument value referenced by the conditional compilation switch is generated from the sequential program. Further, this process is started in response to an instruction from the user by the automatic parallelizing compiler 1 operating on the PC 10.

  In S100, the automatic parallelizing compiler 1 specifies a conditional description that is a target of selection as to whether or not to compile by conditional compilation among sequential programs based on the conditional compilation switch described in the sequential program, The conditional description is divided into one or more conditional blocks. Each conditional block is divided into one macro task (conditional macro task).

  Here, a set of conditional compilation switches that collectively select whether or not to compile according to the value of an argument may be a conditional block, or the selection target Each of a plurality of series of descriptions described above may be a conditional block. A combination of the series of descriptions may be a conditional block. For a specific example of the conditional block setting method, refer to specific example 4 described later.

  In S105, the automatic parallelizing compiler 1 executes a software structure analysis process (see FIG. 3) to generate an MTG. Then, one of the types of the embedded system that operates by the sequential program (in other words, the value of the argument of the conditional compilation switch corresponding to one of the types) is selected, and the process proceeds to S110.

  In S110, the automatic parallelizing compiler 1 performs static scheduling corresponding to the currently selected type based on the MTG generated by the software structure analysis process. Thereby, macro tasks that can be executed in parallel are assigned to different PGs (information indicating the result of the assignment is assigned information), and a parallelized program (hereinafter referred to as a comparison program) is generated. At this time, the comparison program is generated corresponding to each type. That is, a plurality of comparison programs having the same contents are generated corresponding to each type by static scheduling corresponding to one type. Hereinafter, the type corresponding to the comparison program is set as the final type.

  In the comparison program, a conditional compilation switch having the same content as the conditional compilation switch set in the conditional description corresponding to the description in the sequential program is set for the description corresponding to each conditional macrotask. . Therefore, if the argument of the conditional compilation switch of the comparison program is set to a value corresponding to any type, a parallelized program corresponding to the type is obtained.

  Further, the automatic parallelizing compiler 1 specifies the actual cost (processing time as an example) when executing each macrotask by the profile automatic feedback function in the static scheduling so that the processing load of each PG becomes approximately the same. A macro task that can be executed in parallel may be assigned. Further, the automatic parallelizing compiler 1 may identify a macrotask that is not a compilation target in the selected type based on the conditional compilation switch, and may perform static scheduling on the assumption that there is no processing load on the macrotask.

  At this time, since the automatic parallelizing compiler 1 operates the parallelized program on various platforms, the runtime library uses the automatic parallelizing API standard interpretation system to execute the parallelized program to which the automatic parallelizing API is added. It may be converted into an implemented parallelized program.

  In S115, the automatic parallelizing compiler 1 determines whether or not the static scheduling corresponding to all types of embedded systems operating by sequential programs has been completed. If an affirmative determination is obtained (S115: Yes), the process proceeds to S120. If a negative determination is obtained (S115: No), another type for which static scheduling is not performed is selected. Select and move to S110.

  In S120, the automatic parallelizing compiler 1 verifies the performance of all the comparison programs generated in S110 to S115, selects appropriate static scheduling based on the verification result, and shifts the processing to S125. At this time, static scheduling capable of generating a comparative program having the best performance may be selected, or static scheduling capable of generating a comparative program having a predetermined performance may be selected (details will be described later). ).

  In S125, the automatic parallelizing compiler 1 determines whether or not the static scheduling has been successfully selected. Specifically, for example, if there is only one static scheduling capable of generating the best performance comparison program, the selection may be successful, and if not, the selection may be failed. . If static scheduling having a certain performance exists, the selection may be successful, and if not, the selection may be failed. If an affirmative determination is obtained (S125: Yes), one of the embedded system types operating by the sequential program is selected and the process proceeds to S130. If a negative determination is obtained ( S125: No), the process proceeds to S145.

  In S130, the automatic parallelizing compiler 1 analyzes the compiler switch generated by the selected static scheduling and described in the comparison program (selected program) corresponding to the selected type, and performs processing according to the analysis result. Execute pre-pro processing to be performed. At this time, based on the conditional compilation switch, a description that is not subject to compilation is specified for the type selected from the selected programs, and the process proceeds to S135.

  In S135, the automatic parallelizing compiler 1 generates binary data for operating the multi-core processor from the description to be compiled in the selected program, and proceeds to S140.

  In S140, the automatic parallelizing compiler 1 determines whether binary data corresponding to all types has been generated. If an affirmative determination is obtained (S140: Yes), the present process is terminated. If a negative determination is obtained (S140: No), another type for which binary data has not been generated is selected. Then, the process proceeds to S130.

  On the other hand, in S145, the automatic parallelizing compiler 1 notifies that the selection of the static scheduling has failed via the display 11 or the like. At this time, as the verification result of the performance of the comparison program, for example, the parallel execution time and reduction rate of each comparison program, and the maximum parallel execution time and minimum reduction rate in the comparison program generated by each static scheduling (details will be described later) Etc. may be displayed. Thereafter, the automatic parallelizing compiler 1 ends this processing.

2-3. Software Structure Analysis Processing Next, software structure analysis processing for generating MTG from a sequential program will be described using the flowchart of FIG. This processing is executed by automatic parallelization processing.

  In S200, the automatic parallelizing compiler 1 performs inline expansion (replaces the description for calling the subroutine with the description of the process defined in the subroutine) for the sequential program, and proceeds to S205. A sequential program for an embedded system is generally finely processed and difficult to parallelize with a coarse granularity. However, by performing inline expansion, the parallelism within the subroutine can be effectively utilized.

  In S205, the automatic parallelizing compiler 1 renames the local variable. For example, in a sequential program automatically generated from a Simulink model, the same local variable may be used repeatedly in many places to reduce ROM usage. As a result, the parallelism cannot be extracted sufficiently. Therefore, the local variables being reused are renamed.

  Specifically, the automatic parallelizing compiler 1 specifies a plurality of processing blocks in which local variables with the same name are used in each function of the sequential program, and each local block with a unique name in each specified processing block. Modify the sequential program so that variables are used.

  The processing block may be, for example, a collection of descriptions including a loop processing, a branch processing statement such as an if statement or a switch-case statement, and an assignment statement accompanying the statement. In addition, for example, a collection of descriptions corresponding to each block in the Simulink model that generated the sequential program may be used as a processing block.

  In S210, the automatic parallelizing compiler 1 divides the sequential program that has been subjected to these processes into macro tasks. As described above, the conditional block is divided into one macro task (conditional macro task). Then, an MFG is generated by analyzing data dependency and control dependency between the macro tasks, and the process proceeds to S215.

  In S215, the automatic parallelizing compiler 1 identifies a macro task that branches to a different macro task as a start task based on the control dependency indicated by the MFG. Further, the automatic parallelizing compiler 1 identifies the macro task that is executed first among the macro tasks that are executed in common among all of the series of processes that are sequentially executed starting from the start task as the end task. .

  Then, the automatic parallelizing compiler 1 executes the specified start task, the end task in the process starting from the start task, and all the processes executed after the start task and before the end task is executed. The macro task is merged into one macro task (task fusion), and the process proceeds to S220.

  In order to make the granularity of the macro task fine, among the macro tasks that are commonly executed in all of a plurality of series of processes that are sequentially executed starting from the start task as in the process in S215, It is preferable to specify a macro task to be executed as a termination task. However, the present invention is not limited to this, and any one of these macrotasks executed after the second may be specified as a termination task.

  Sequential programs for embedded systems (especially in-vehicle devices) have few loop structures, so it may be possible to apply near fine-grain parallelism or coarse-grained task parallelism. 1 applies coarse-grained task parallelization.

  In the sequential program, the cost of each macrotask is about several tens of clocks. However, when dynamic scheduling is performed by the automatic parallelizing compiler 1, an overhead of several tens to several hundreds of clocks is usually generated. For this reason, dynamic scheduling is not suitable for sequential programs.

  However, since a macrotask having a conditional branch is dynamically determined at the time of execution of the macrotask, static scheduling that assigns a processor core at the time of compilation cannot be applied as it is.

  Therefore, the automatic parallelizing compiler 1 performs task fusion by fusing a macro task having a conditional branch and a macro task at the branch destination into one coarse-grained task (Block task) by a task fusion algorithm. By performing task fusion, the MFG has no control dependency, and static scheduling is possible.

  In S220, the automatic parallelizing compiler 1 analyzes the earliest executable condition of each macro task based on the MFG subjected to task fusion, and generates an MTG. Then, this process ends.

3. Next, the configuration of the in-vehicle device 20 that operates according to the parallelized program generated by the automatic parallelizing compiler 1 of the present embodiment will be described (see FIG. 4). Of course, the automatic parallelizing compiler 1 is capable of generating parallelized programs that operate not only the in-vehicle device 20 but also various electronic devices having the same configuration.

The in-vehicle device 20 includes a multi-core processor 21, a communication unit 22, a sensor unit 23, an input / output port 24, and the like.
The multi-core processor 21 includes a ROM 21a, a RAM 21b, and a plurality of PEs 21c, 21d, etc.

  The ROM 21a stores a parallelized program 21a-1 (binary data) generated by the automatic parallelizing compiler 1. The multi-core processor 21 operates according to the parallelized program 21a-1 and performs overall control of the in-vehicle device 20.

The RAM 21b is a part accessed by the PEs 21c, 21d, etc.
The communication unit 22 is a part that communicates with another ECU connected via an in-vehicle LAN or the like.

Moreover, the sensor part 23 is a site | part comprised from the various sensors for detecting states, such as a control object.
The input / output port 24 is a part that transmits and receives various signals for controlling the control target.

[Specific examples]
Next, a specific example of processing for generating a parallelized program by the automatic parallelizing compiler 1 of the present embodiment will be described. In the following description, description such as process A is made, which means a description of a series of processes including various operations, assignments, branch processes, function calls, and the like.

1. About Specific Example 1 In Specific Example 1, a comparison program is generated based on a sequential program 300 that is subjected to conditional compilation corresponding to two types of embedded systems (A specification and B specification), and the performance of each comparison program is verified. (See FIG. 5).

  In Specific Example 1, a parallelized program that is executed by a multi-core processor having two PEs (first and second cores) is generated, and each macrotask is assigned to these cores.

  In the sequential program 300, “processing C1 and C2” is a conditional description, and the conditional compilation switch 301 selects one of “processing C1” and “processing C2” as a compilation target. Specifically, in the case of the A specification (“CSW = A”), the processing C1 is selected, and in the case of the B specification (“CSW ≠ A”), the processing C2 is selected as the target of compilation (see FIG. 6). .

  The automatic parallelizing compiler 1 identifies each of “processing C1 and C2” of the sequential program 300 as a conditional block in S100 of the automatic parallelizing processing. Of course, “processing C1 and C2” may be specified as one conditional block.

In S105 (software structure analysis process), the automatic parallelizing compiler 1 generates an MTG using each of “Processes A to C2” as a macro task.
In S110 to S115, the automatic parallelizing compiler 1 performs static scheduling A corresponding to the A specification and static scheduling B corresponding to the B specification based on the sequential program 300.

In FIG. 5, 310 indicates allocation information generated by static scheduling A, and 311 indicates allocation information generated by static scheduling B.
“Processing A”, “Processing B”, “Processing C1”, and “Processing C2” in the allocation information 310 and 311 indicate macrotasks corresponding to the processes in the sequential program. In each static scheduling, for example, the processing time of each process is regarded as a processing load. In static scheduling A, the processing load of “processing C2” is regarded as having no processing load of “processing C1” in static scheduling B.

  Four comparison programs AA to BB are generated by the static scheduling. The comparison programs AA and AB are generated by static scheduling A. The final type of the comparison program AA is A specification, and the final type of the comparison program AB is B specification. The comparison programs BA and BB are generated by static scheduling B. The final type of the comparison program BA is A specification, and the final type of the comparison program BB is B specification.

  In FIG. 5, 320 indicates comparison programs AA and AB, and 322 indicates comparison programs BA and BB. When the value of “CSW” that is an argument of the conditional compilation switches 321 and 323 in the comparison programs 320 and 322 is set, one of the comparison programs AA to BB is generated.

  In S120, the automatic parallelizing compiler 1 verifies the performance of the comparison programs AA to BB generated in S110 to S115, and selects the optimal static scheduling based on the verification result. At this time, the parallel execution time and the reduction rate of each of the comparison programs AA to BB are calculated, and the performance is verified based on them.

  The parallel execution time means the maximum value of the total processing time of the macrotasks assigned to each core (PG) in the comparison program. Needless to say, when calculating the sum, the processing time of a macrotask that is not subject to compilation is 0 in the final type of the comparison program.

  The reduction rate is an estimation result of a difference in performance between a multi-core processor that is operated by a comparison program and a single-core processor that is operated by a sequential program of the same type as the comparison program. The reduction rate is the sum of the parallel execution time of the comparison program and the processing time of each process executed by the single-core processor operated by the sequential program that has been subjected to conditional compilation corresponding to the final type of the comparison program (total processing) Time) and the ratio (%). The reduction rate is calculated by (1-parallel program parallel execution time / total processing time) × 100.

  The table of FIG. 6 shows the processing times of “Processes A to C2”, and the table of FIG. 7 shows the parallel execution times and reduction rates calculated for the comparison programs AA to BB. The total processing time for the A-specific sequential program is 240 μs, and the total processing time for the B-specific sequential program is 190 μs.

  In the comparison programs AA and AB generated by the static scheduling A, the maximum parallel execution time (maximum parallel execution time) is 120 μs, and the minimum reduction rate (minimum reduction rate) is 37%. On the other hand, in the comparison programs BA and BB generated by the static scheduling B, the maximum parallel execution time is 140 μs, and the minimum reduction rate is 42%.

  For this reason, when the optimum static scheduling is selected based on the parallel execution time, the maximum parallel execution time of the static scheduling A is relatively small. For this reason, it is determined that the comparison program generated by the static scheduling A has relatively good performance, and the static scheduling A is selected.

  On the other hand, when the optimal static scheduling is selected based on the reduction rate, the minimum reduction rate of static scheduling B is relatively large. For this reason, it is determined that the comparison program generated by the static scheduling B has relatively good performance, and the static scheduling B is selected.

  In principle, static scheduling may be selected based on the maximum parallel execution time, and if the maximum parallel execution time of each static scheduling is the same (or similar), static scheduling may be selected based on the minimum reduction rate. . Conversely, in principle, static scheduling may be selected based on the minimum reduction rate, and if the minimum reduction rate of each static scheduling is the same (or similar), static scheduling may be selected based on the maximum parallel execution time. .

Similarly, when there are three or more types, static scheduling may be selected based on the maximum parallel execution time and the minimum reduction rate.
2. About Specific Example 2 In specific example 2, a comparison program is generated based on sequential program 400 that is subjected to conditional compilation corresponding to two types of embedded systems (A specification and B specification), and the performance of each comparison program is verified. (See FIG. 8).

  In the second specific example, a parallelized program to be executed by a multicore processor having two PEs (first and second cores) is generated, and each macrotask is assigned to these cores.

  Further, in the sequential program 400, “processes D1, D2, F, and G” are conditional descriptions, and some of these conditional descriptions are selected as compilation targets by the conditional compilation switches 401 to 403. Is done. Specifically, in the case of the A specification (“CSW = A”), “processing D1, F” is selected, and in the case of the B specification (“CSW ≠ A”), “processing D2, G” is selected ( (See FIGS. 8 and 10).

The automatic parallelizing compiler 1 specifies each of the “processing D1, D2, F, G” of the sequential program 400 as a conditional block in S100 of the automatic parallelization processing.
Of course, “Processing D1 and D2”, which are two processes in which whether or not to compile according to the value of the argument by a set of conditional compilation switch 401, are specified as one conditional block. You may do it. In addition, two processes “process F, G”, which are collectively selected by the two sets of conditional compilation switches 402, 403 as to whether or not to compile according to the value of the argument, are set as one conditional block. You may specify as.

  In S105 (software structure analysis processing), the automatic parallelizing compiler 1 generates an MTG using each of “Processes A to I” as a macro task. Reference numeral 410 in FIG. 8 denotes an MTG generated based on the sequential program 400. In the automatic parallelization process, parallelism is extracted for all processes described in the sequential program 400 regardless of the conditional compilation switch. Therefore, in the MTG 410, all macro tasks to be compiled according to various types are extracted. Data dependence is expressed.

  In S110 to S115, the automatic parallelizing compiler 1 performs static scheduling A corresponding to the A specification and static scheduling B corresponding to the B specification based on the sequential program 400. These static schedulings are performed based on the processing load (processing time as an example) of each macro task (see FIG. 10).

  Reference numeral 411 in FIG. 9 is an MTG based on the sequential program 400, and indicates a macrotask to be compiled in the A specification by a solid line and a macrotask that is not to be compiled by a dotted line. On the other hand, 412 is an MTG based on the sequential program 400, and indicates a macrotask to be compiled in the B specification with a solid line and a macrotask that is not to be compiled with a dotted line.

  In static scheduling A, it is considered that there is no macrotask processing load indicated by a dotted line in MTG 411, and in static scheduling B, it is assumed that there is no macrotask processing load indicated by a dotted line in MTG 412.

  Further, in these static scheduling, a group of a plurality of macrotasks connected by data dependence is specified from the MTG. Specifically, “Processing A, B, D2, I”, “Processing A, B, D1, I”, “Processing A, C, I”, “Processing A, C, F, I” , “Processing A, G, H, I” and “Processing A, H, I” are specified.

  Then, the total processing time of the macrotasks belonging to each group is calculated, and the macrotasks constituting the group having the largest total sum are allocated to the first core. Other macrotasks are assigned to the first or second core so that the maximum processing time (the maximum value of the total processing time of the macrotasks assigned to each core) is minimized.

  In principle, a plurality of macro tasks having data dependence are assigned to the same core, but such macro tasks may be assigned to different cores. In such a case, the processing of the other core is waited until the processing of one core is completed. The total processing time of macrotasks assigned to each core is a time including such a waiting time.

  420 and 421 indicate allocation information generated by static scheduling A, and 422 and 423 indicate allocation information generated by static scheduling B. The allocation information 420 and 422 corresponds to the case where the final type is the A specification, and the allocation information 421 and 423 corresponds to the case where the final type is the B specification. In these allocation information, the macrotasks to be compiled are indicated by solid lines, and the macrotasks that are not targeted are indicated by dotted lines.

  In addition, the description “wait” in the allocation information 420 to 423 indicates that the second core waits for the end of the process while “Process A” and “Process I” are executed by the first core. Show.

  Four comparison programs AA to BB are generated by the static scheduling. The comparison programs AA and AB are generated by static scheduling A. The final type of the comparison program AA is A specification, and the final type of the comparison program AB is B specification. The comparison programs BA and BB are generated by static scheduling B. The final type of the comparison program BA is A specification, and the final type of the comparison program BB is B specification.

  In S120, the automatic parallelizing compiler 1 verifies the performance of the comparison programs AA to BB generated in S110 to S115, and selects the optimal static scheduling based on the verification result. At this time, the parallel execution time of each of the comparison programs AA to BB is calculated, and the performance is verified based on them.

The table of FIG. 10 shows the processing times of the processes A to I, and the table of FIG. 11 shows the parallel execution times calculated for the comparison programs AA to BB.
The maximum parallel execution time of static scheduling A is 200 μs, and the maximum parallel execution time of static scheduling B is 190 μs. For this reason, when the optimum static scheduling is selected based on the parallel execution time, the static scheduling B is selected.

Of course, as in the first specific example, the optimal static scheduling may be selected based on the reduction rate, or the parallel execution time and the reduction rate.
3. About Specific Example 3 In specific example 3, a comparison program is generated based on a sequential program that is subjected to conditional compilation corresponding to three types (A to C specifications) of embedded systems, and the performance of each comparison program is verified. Hereinafter, the performance verification method will be described in detail.

Nine comparison programs AA to AC, BA to BC, and CA to CC are generated by S100 to S115 of the automatic parallel processing.
The comparison programs AA to AC are generated by static scheduling A corresponding to the A specification. The final type of the comparison program AA is A specification, the final type of the comparison program AB is B specification, and the final type of the comparison program AC is C specification.

  The comparison programs BA to BC are generated by static scheduling B corresponding to the B specification. The final type of the comparison program BA is A specification, the final type of the comparison program BB is B specification, and the final type of the comparison program BC is C specification.

  The comparison programs CA to CC are generated by static scheduling C corresponding to the C specification. The final type of the comparison program CA is A specification, the final type of the comparison program CB is B specification, and the final type of the comparison program CC is C specification.

  In S120, the automatic parallelizing compiler 1 verifies the performance of these comparison programs, and selects the optimum static scheduling based on the verification result. At this time, the parallel execution time and the reduction rate of each comparison program are calculated (see FIG. 12). Then, it is determined whether each static scheduling satisfies the selection condition set based on the parallel execution time and the reduction rate. In the example of FIG. 12, the total processing times of the sequential program of type A specification, the sequential program of type B specification, and the sequential program of type C specification are 100 μs, 50 μs, and 50 μs, respectively. .

  Specifically, for example, the parallel execution time of the comparison program whose final type is the A specification <65 μs, the parallel execution time of the comparison program whose final type is the B specification <35 μs, and the final type is the C specification. It is assumed that the selection condition 1 is set such that the parallel execution time of the comparison program <35 μs.

  In the example described in FIG. 12, the comparison programs BA to BC generated by the static scheduling B satisfy the selection condition 1. For this reason, static scheduling B is selected.

Note that the selection condition 1 can be used when the performance of multi-core processors installed in various embedded systems is different.
Further, for example, the parallel execution time of the comparison program whose final type is A specification <65 μs, and the minimum value of the reduction rate of the comparison program whose final type is B specification and the comparison program whose C type is C specification is relatively large. Assume that selection condition 2 is set.

  In the example described in FIG. 12, the comparison program generated by the static scheduling B satisfies the selection condition 2. For this reason, static scheduling B is selected.

  Selection condition 2 is considered to be used when the performance of multi-core processors installed in various types of embedded systems is about the same, and the processing load of sequential programs of the A specification is larger than that of other types of sequential programs. It is done.

4). About Specific Example 4 In Specific Example 4, based on a sequential program in which conditional compilation corresponding to three types (A to C specifications) of embedded systems is performed using conditional compilation switches 501 to 503 in which a plurality of different arguments are used. A comparison program is generated. Hereinafter, a method of dividing the conditional description 500 of the sequential program into macro tasks will be described in detail (see FIG. 13).

  The conditional compilation switches 501 to 503 use the arguments “NA”, “JC”, and “TM”, respectively. FIG. 14 shows values that can be set for each argument. FIG. 15 shows values to be set for each argument when selecting various types.

In S100 of the automatic parallelization process, the automatic parallelizing compiler 1 specifies each of “processing A to E” described in the conditional description 500 of the sequential program as a conditional block.
In S105 (software structure analysis processing), the automatic parallelizing compiler 1 generates an MTG using each of the “processing A to E” specified as the conditional block as a macro task. The macro tasks corresponding to each of the “processes A to E” are referred to as “macro tasks A to E”, respectively.

  Then, in S110 to S115, the automatic parallelizing compiler 1 performs static scheduling corresponding to each type, assigns “macrotasks A to E” to any PG, and compares the A to C specifications as the final type. Generate a program. The table of FIG. 16 shows descriptions corresponding to “macrotasks A to E” in the comparison program.

  In the comparison program, “Processes A to E” are described corresponding to “Macro Tasks A to E”, and a conditional compilation switch is set for each of these processes. The conditional compilation switch set for each of the “processes A to E” has the same content as the conditional compilation switch set for the process in the conditional description 500 in the sequential program.

For this reason, in the comparison program, when the argument of the conditional compilation switch is set to a value corresponding to the type, the process corresponding to the type is selected as the target of compilation.
In S100, among “Processes A to E” described in the conditional description 500 of the sequential program, “Processes A to C” and “Processes D and E” may be separate conditional blocks.

  In such a case, “macrotasks X and Y” are generated corresponding to each of “processes A to C” and “processes D and E”. In the comparison program, “Processes A to C” are described corresponding to “Macro Task X”, and “Processes D and E” are described corresponding to “Macro Task Y”. Conditional compilation switch is set. The conditional compile switch set for each of “Processes A to C” and “Processes D and E” is also equivalent to the conditional compile switch set for the process in the conditional description 500 in the sequential program. (See FIG. 17).

[effect]
The automatic parallelizing compiler 1 of the present embodiment generates a parallelized program from a sequential program in a state including all conditional descriptions. Then, from the parallelized program, a part that is not subject to compilation in the type corresponding to the parallelized program is removed, and binary code for operating the embedded system of the type (system equipped with a multi-core processor) is generated.

  For this reason, in various types of parallelized programs, processes other than the processes corresponding to conditional descriptions (processes executed in common in all types of parallelized programs) can always be assigned to the same PG. Therefore, the commonality of each type of parallelized program can be further increased, and the maintenance and management of the quality of the parallelized program is facilitated.

  The automatic parallelizing compiler 1 performs static scheduling based on the actual cost (processing load) of the macrotask. Specifically, macrotasks that can be executed in parallel are assigned to different PGs so that the processing loads of the PGs are approximately the same. Thereby, the performance of the multi-core processor that operates according to the parallelized program can be improved.

  Further, the automatic parallelizing compiler 1 performs static scheduling corresponding to one of the types of sequential programs. At this time, it is assumed that there is no processing load for a macro task that is not subject to compilation in the corresponding type. It is regarded. As a result, the best performance can be obtained when a description that is not subject to compilation is removed from the comparison program generated by static scheduling. Therefore, the performance of the parallelized program generated by the automatic parallelizing compiler 1 can be improved.

  The automatic parallelizing compiler 1 performs static scheduling corresponding to each type and generates a plurality of comparison programs corresponding to each type in each static scheduling. Then, the performance of each comparison program is verified, and based on the verification result, a static scheduling that can generate a comparison program with the best performance is selected.

  Further, a part not to be compiled is removed from the comparison program generated by the selected scheduling, and a parallelized program corresponding to each type is generated. As a result, processes common to various types in the parallelized program are always assigned to the same PG, and the commonality of the various types of parallelized programs can be further enhanced.

  In addition, since static scheduling is selected based on the results of verifying the performance of each comparison program, a parallel program with good performance can be generated. Therefore, it is possible to easily maintain and manage the quality of the parallelized program while suppressing a decrease in the performance of the parallelized program.

  Moreover, the automatic parallelizing compiler 1 calculates the parallel execution time and the reduction rate of each comparison program, and verifies the performance of each comparison program based on both or one of them. For this reason, the performance of each comparison program can be grasped with high accuracy, and static scheduling can be selected more appropriately.

  If the automatic parallelizing compiler 1 cannot select the static scheduling, the automatic parallelizing compiler 1 notifies the user to that effect. Thereby, the usability of the automatic parallelizing compiler 1 can be improved.

[Other Embodiments]
As mentioned above, although embodiment of this invention was described, this invention can take a various form, without being limited to the said embodiment.

  (1) In the automatic parallel processing of this embodiment, static scheduling corresponding to all types of sequential compilers is performed. However, the present invention is not limited to this, and static scheduling corresponding to any one type may be performed, and the comparison program generated by the static scheduling may be a parallelized program corresponding to each type. The type may be specified by the user, for example.

  In addition, static scheduling corresponding to a plurality of types corresponding to a part of all types of the sequential compiler is performed, and the performance of each comparison program is verified in the same manner as in this embodiment, and any one of the static scheduling is selected. May be.

Even in such a case, the commonality of various parallel programs can be further increased, and the quality and maintenance of the parallel programs can be facilitated.
(2) The automatic parallelizing compiler 1 of the present embodiment performs inline expansion of the sequential program in S200 of the software structure analysis process and renames local variables in S205. Both or one of these processes is performed. It is good also as composition which does not perform. Even in such a case, the same effect can be obtained depending on the structure of the sequential program.

  (3) The functions of one constituent element in the above embodiment may be distributed as a plurality of constituent elements, or the functions of a plurality of constituent elements may be integrated into one constituent element. Further, at least a part of the configuration of the above embodiment may be replaced with a known configuration having the same function. Moreover, you may abbreviate | omit a part of structure of the said embodiment. In addition, at least a part of the configuration of the above embodiment may be added to or replaced with the configuration of the other embodiment. In addition, all the aspects included in the technical idea specified only by the wording described in the claim are embodiment of this invention.

  (4) In addition to the above-described automatic parallelizing compiler and automatic parallelizing compiling device, the present invention is realized in various forms such as a medium storing the automatic parallelizing compiler and a method corresponding to processing performed by the automatic parallelizing compiler. You can also

[Correspondence with Claims]
The correspondence between the terms used in the description of the above embodiment and the terms used in the description of the claims is shown.

The automatic parallelizing compiler 1 corresponds to an example of a parallelizing compiler, and the in-vehicle device 20 corresponds to an example of an electronic device.
PG corresponds to an example of a processor unit.

  Further, S110 of the automatic parallel processing corresponds to an example of a scheduling procedure and scheduling means, S120 corresponds to an example of a verification procedure, verification means, selection procedure, and selection means, and S145 corresponds to an example of a notification procedure and notification means.

Further, S210 of the software structure analysis process corresponds to an example of a dividing procedure and dividing means, and S220 corresponds to an example of an extracting procedure and extracting means.
The value of the argument of the conditional compilation switch corresponds to an example of input information.

  The parallel execution time corresponds to an example of the maximum processing load of the comparison program, and the reduction rate corresponds to an example of a difference in performance between the multiprocessor system operating according to the comparison program and the single processor system operating according to the sequential program.

  DESCRIPTION OF SYMBOLS 1 ... Automatic parallelizing compiler, 10 ... PC, 11 ... Display, 12 ... HDD, 13 ... CPU, 14 ... ROM, 15 ... RAM, 16 ... Input device, 17 ... Reading part, 18 ... Storage medium, 20 ... In-vehicle device 21 ... multi-core processor, 21a ... ROM, 21b ... RAM, 21c, 21d ... processor element (PE), 22 ... communication unit, 23 ... sensor unit, 24 ... input / output port.

Claims (10)

A process that is executed by a single processor system and that is described in a sequential program that includes a conditional description for selecting whether or not to compile according to input information by conditional compilation. Regardless of the division procedure (S210) to divide into a plurality of macro tasks regardless of
An extraction procedure (S220) for extracting the macrotasks that can be executed in parallel by a plurality of processor units constituting a multiprocessor system based on the data dependency between the macrotasks;
A process of assigning each of the macrotasks to any one of the processor units, wherein all or part of the macrotasks that can be executed in parallel are assigned to different processor units and executed by the multiprocessor system. A scheduling procedure (S110) for performing static scheduling to generate a parallelized program;
A parallelized compiling method characterized by comprising: In the parallel compilation method according to claim 1,
Performing the static scheduling based on the processing load of the macrotask in the scheduling procedure;
Parallelizing compilation method characterized by In the parallel compilation method according to claim 2,
In the scheduling procedure, the static scheduling is performed in response to the predetermined input information, and the macro task processing corresponding to the conditional description that is not subject to compilation in the corresponding input information in the static scheduling. Considering no load,
Parallelizing compilation method characterized by In the parallel compilation method according to any one of claims 1 to 3,
In the scheduling procedure, the static scheduling is performed corresponding to each of two or more types of input information determined in advance, and the parallelized program corresponding to each type of the input information is generated,
Corresponding to the predetermined input information, the conditional program selected not to be compiled by the input information from each of the parallelized programs generated in the static scheduling, As a comparison program,
The parallelized compilation method is:
For each of the static scheduling, a verification procedure (S120) for verifying the performance of the comparison program associated with each type of the input information generated from the parallelized program generated by the static scheduling;
A selection procedure (S120) for selecting any of the static scheduling based on the verification result of the verification procedure;
A parallel compilation method characterized by further comprising: In the parallel compilation method according to claim 4,
In the verification procedure, for each of the comparison programs, for each of the processor units, the sum of the processing loads of the assigned macrotasks is calculated, and the maximum value of these sums is calculated as the comparison program. And the maximum processing load of
Selecting the static scheduling based on the maximum processing load in the selection procedure;
Parallelizing compilation method characterized by In the parallel compilation method according to claim 4,
In the verification procedure, for each of the comparison programs, the multiprocessor system operating according to the comparison program, and the sequential description excluding the conditional description selected not to be compiled by the input information corresponding to the comparison program Estimating the performance difference from the single processor system operating according to the program;
Selecting the static scheduling based on the estimation result of the difference in performance in the selection procedure;
Parallelizing compilation method characterized by In the parallel compilation method according to claim 4,
In the verification procedure, for each of the comparison programs, the sum of the processing loads of the assigned macrotasks is calculated for each of the processor units, and the maximum value of the sum is calculated as the maximum processing of the comparison program. The multiprocessor system that operates according to the comparison program and the single processor that operates according to the sequential program excluding the conditional description selected not to be compiled by the input information corresponding to the comparison program Estimate the performance difference with the system,
Selecting the static scheduling based on the maximum processing load and the estimation result of the performance difference in the selection procedure;
Parallelizing compilation method characterized by In the parallel compilation method according to any one of claims 4 to 7,
In the selection procedure, when the static scheduling cannot be selected, it further includes a notification procedure (S145) for reporting the fact.
Parallelizing compilation method characterized by A process that is executed by a single processor system and that is described in a sequential program that includes a conditional description for selecting whether or not to compile according to input information by conditional compilation. Regardless of the division means (S210) for dividing into a plurality of macro tasks regardless of
Extraction means (S220) for extracting the macrotask that can be executed in parallel by a plurality of processor units constituting a multiprocessor system based on the data dependency between the macrotasks;
A process of assigning each of the macrotasks to any one of the processor units, wherein all or part of the macrotasks that can be executed in parallel are assigned to different processor units and executed by the multiprocessor system. As a scheduling means (S110) for performing static scheduling for generating a parallelized program,
A parallelizing compiler (1) characterized by operating a computer. A process that is executed by a single processor system and that is described in a sequential program that includes a conditional description for selecting whether or not to compile according to input information by conditional compilation. Regardless of the division procedure (S210) to divide into a plurality of macro tasks regardless of
An extraction procedure (S220) for extracting the macrotasks that can be executed in parallel by a plurality of processor units constituting a multiprocessor system based on the data dependency between the macrotasks;
A process of assigning each of the macrotasks to any one of the processor units, wherein all or part of the macrotasks that can be executed in parallel are assigned to different processor units and executed by the multiprocessor system. A scheduling procedure (S110) for performing static scheduling to generate a parallelized program;
An electronic device (20) comprising the multiprocessor system that operates according to the parallelized program generated by the parallelized compiling method.

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