JP2016140602A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a processing load of a microcomputer for a presentation control and a reservation number display.SOLUTION: When a light emission part for presentation and a light emission part for reservation number display are provided, light emission control means achieves a light emission presentation by performing determination processing for determining the light emission presentation at a proper timing, and by performing preparation processing and output processing for every prescribed cycle, the preparation processing preparing light emission driving information and storing it in a light emission driving data storage part, the output processing outputting a driving signal based on the light emission driving information stored in the light emission driving data storage part. In the preparation processing, when in a state to perform the light emission presentation determined by the determination processing, the light emission driving information for presentation to the light emission part for presentation is prepared on the basis of lamp data corresponding to presentations to be performed, and the light emission driving information for reservation number display to the light emission part for reservation number display is prepared corresponding to a reservation number state. Information in which the light emission driving information for presentation and the light emission driving information for reservation number display are synchronized is set as the light emission driving information for one timing of the prescribed cycle.SELECTED DRAWING: Figure 26

Description

  The present invention relates to a game machine such as a ball ball game machine or a revolving game machine, and more particularly to light emission control for presentation or presentation in the game machine.

Japanese Patent No. 4613191

In ball and ball game machines (so-called pachinko game machines) and swing game machines (so-called slot game machines), lighting and flashing operations using light emitting parts using LEDs (Light Emitting Diodes), etc., perform effects associated with the game. There are some which perform various status presentations, error notifications, and guidance displays.
For the operation of the light emitting unit, for example, a microcomputer functioning as an effect control unit supplies drive data to an LED driver circuit or the like. For example, a large number of LEDs are connected to the LED driver, and the LED driver causes each LED to perform a light emission operation by flowing a light emission drive current according to drive data.

  In the above-mentioned patent document 1, the production control unit outputs drive data for light emission driving of a plurality of LEDs to the LED driver as serial data, and the LED driver converts the serial data into parallel data and is connected. Further, a technique for supplying current to each LED is disclosed.

In such a gaming machine, in addition to the control of the original game operation, various effects and display operations using the light emitting unit are performed. is there.
Therefore, an object of the present invention is to reduce the control load of a microcomputer for controlling light emission.

The gaming machine of the present invention includes a light emitting unit for production, a light emitting unit for displaying the number of holdings, and a light emission control means for controlling light emission of each light emitting unit for producing and holding the number of holdings, The light emission control means performs a determination process for determining a light emission effect at an appropriate timing, creates light emission drive information, stores the light emission drive information in the light emission drive data storage unit, and stores the light emission drive data in the light emission drive data storage unit. A light emission effect is realized by performing output processing for outputting a drive signal based on the stored light emission drive information at predetermined intervals. In the creation process, in the state of executing the light emission effect determined in the determination process, the production light emission drive information for the effect light emitting unit is created based on the lamp data corresponding to the effect to be executed, and the number of holds Depending on the state, the number-of-holds-display-light-emitting drive information for the number-of-holds-display light-emitting unit is created, and a combination of the effect-use light-emitting drive information and the number-of-holds-display-light-emitting drive information is one timing in the predetermined period. The emission drive information for the minute.
Thereby, the light emission drive control of each of the light emitting unit for production and the light emitting unit for displaying the number of holdings can be executed collectively.
In the above gaming machine, in the creation process, after generating the light emission drive information for a predetermined size for one timing, the light emission drive information for holding number display is created and specified in the light emission drive information for the effect It is conceivable to generate light emission drive information of a predetermined size for one timing by rewriting the data area with the light emission drive information for holding number display.
That is, a specific data area is prepared, and only a part of the light emission drive information for production is updated to the light emission drive information for holding number display, and light emission drive information obtained by combining the production for display and the number of hold display is generated.
In the above gaming machine, the ramp data is set so that dummy data is arranged in the specific data area of the light emission drive information for presentation. In the creation process, It is conceivable to rewrite dummy data in the specific data area to the light emission driving information for holding number display.
By placing dummy data in the specific data area, it is possible to synthesize the number-of-holds display light emission drive information without affecting light emission control for production.
The above gaming machine includes one or a plurality of light-emitting drivers that supply a light-emission driving current to a light-emitting unit for production and a light-emitting unit for variable symbol identification based on the drive signal output in the output process, One or a plurality of specific light-emitting drivers are connected to a plurality of light-emitting units so as to supply a light-emission driving current to both the light-emitting unit for presentation and the light-emitting unit for holding number display. It can be considered that the light emission drive information that is the basis of the drive signal output to the specific light emission driver includes the effect light emission drive information and the hold number display light emission drive information.
As a result, it is not necessary to separate the light emitting driver for presentation and for displaying the number of holds, and an efficient circuit configuration is possible.

  According to the present invention, the processing for light emission control can be made efficient, and the light emission control processing load can be reduced.

1 is a perspective view of a pachinko gaming machine according to an embodiment of the present invention. It is a front view of the board surface of the pachinko game machine of an embodiment. It is a block diagram of a control configuration of the pachinko gaming machine of the embodiment. 3 is a block diagram of a connection configuration of a driver unit according to the first embodiment. FIG. It is a block diagram of an example of an internal configuration of a driver unit according to the first embodiment. It is explanatory drawing of the light emission aspect of the light emission part for the condition presentation of embodiment. It is explanatory drawing of the LED connection structure with respect to the driver part of embodiment. It is a flowchart of the main control main process of an embodiment. It is a flowchart of the main control timer interruption process of an embodiment. It is a flowchart of the special symbol management process of embodiment. It is a flowchart of the 1st special figure starting port check process of embodiment. It is explanatory drawing of the command of embodiment. It is a flowchart of an effect control main process of the embodiment. It is a flowchart of 1 ms timer interruption processing of effect control of an embodiment. It is a flowchart of the command analysis process in presentation control of an embodiment. It is a flowchart of the command corresponding | compatible process in presentation control of embodiment. It is a flowchart of the command corresponding | compatible process in presentation control of embodiment. It is a flowchart of the scenario registration process in presentation control of an embodiment. It is a flowchart of the scenario deletion process in presentation control of an embodiment. It is a flowchart of the scenario update process in presentation control of an embodiment. It is a flowchart of the sub scenario update process of embodiment. It is explanatory drawing of scenario registration information, lamp data registration information, and motor data registration information of embodiment. It is explanatory drawing of the sound data registration information of embodiment. It is explanatory drawing of the main scenario table of embodiment. It is explanatory drawing of the sub scenario table of embodiment. It is a flowchart of the LED drive data update process of an embodiment. It is a flowchart of the LED drive data set process for status presentation of an embodiment. It is a flowchart of the LED output process of 1st Embodiment. It is explanatory drawing of the registration information of the lamp data of embodiment. It is explanatory drawing of the address table of the lamp data and mask data of embodiment. It is explanatory drawing of the lamp data table and mask data table of embodiment. It is explanatory drawing of the update of lamp data of an embodiment, and an output. It is explanatory drawing of the serial data transmitted to the driver of embodiment. It is explanatory drawing of the serial data transmission to each channel of embodiment. It is explanatory drawing of the serial data transmission operation | movement of the production | presentation control part of embodiment. It is explanatory drawing of 8-bit conversion of the 4-bit lighting data of embodiment. It is a flowchart of the LED driver initialization process of an embodiment. It is a flowchart of the LED driver initialization process of an embodiment. It is a block diagram of the connection structure of the driver part of 2nd Embodiment. It is a block diagram of an example of an internal configuration of a driver unit according to the second embodiment. It is a flowchart of the LED output process of 2nd Embodiment.

Hereinafter, as an embodiment of the gaming machine according to the present invention, a pachinko gaming machine will be taken as an example and described in the following order.
<1. Pachinko machine structure>
<2. Control configuration of pachinko machine>
<3. Overview of operation>
<4. Driver Configuration and Presentation LED of First Embodiment>
<5. Processing of main control unit>
<6. Processing of production control unit>
[6-1: Main processing]
[6-2: 1ms timer interrupt processing]
[6-3: Command analysis processing]
[6-4: Scenario registration / deletion processing]
[6-5: Scenario update process]
[6-6: LED drive data update process]
[6-7: LED output processing of the first embodiment]
[6-8: LED driver initialization processing]
<7. Second Embodiment>
<8. Summary and Modification>

<1. Pachinko machine structure>

First, with reference to FIG. 1 and FIG. 2, the structure of the pachinko gaming machine 1 as an embodiment of the present invention will be schematically described.
FIG. 1 is a front perspective view showing the appearance of a pachinko gaming machine 1 according to the embodiment, and FIG. 2 is a front view of the game board.
The pachinko gaming machine 1 shown in FIGS. 1 and 2 mainly includes a “frame portion” and a “game board portion”.
The “frame portion” includes a front frame 2, an outer frame 4, a glass door 5, and an operation panel 7 described below. The “game board part” comprises the game board 3 of FIG. In the following description, “frame portion” or “frame side” is a generic term for the front frame 2, the outer frame 4, the glass door 5, and the operation panel 7. “Board” or “board side” indicates the game board 3.

As shown in FIG. 1, the pachinko gaming machine 1 has a frame-shaped front frame 2 attached to the front surface of a wooden outer frame 4 so as to be opened and closed. Although not shown, a game board storage frame is formed on the rear surface of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the gaming area 3a formed on the surface of the gaming board 3 faces the front side of the gaming machine in FIG.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the player on the front side through the transparent glass.

The glass door 5 is attached to the front frame 2 by a shaft support mechanism 6 so as to be opened and closed. Then, by operating a door lock release key cylinder (not shown) provided at a predetermined position of the glass door 5, the lock state of the glass door 5 with respect to the front frame 2 is released, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can be released by operating the door lock releasing key cylinder.
Further, on the front side of the glass door 5, light emitting portions 20w are provided in various places as light emitting means on the frame side. The light emitting unit 20w performs, for example, a light emitting operation for production, a light emitting operation for error notification, a light emitting operation according to an operation state, and the like as a light emitting operation by the LED.

An operation panel 7 is provided below the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a shaft support mechanism (not shown).
The operation panel 7 is provided with an upper tray unit 8, a lower tray unit 9, and a firing operation handle 10.

The upper tray unit 8 is formed with an upper tray 8a for storing game balls to be used as bullets. The lower tray unit 9 is formed with a lower tray 9a that stores game balls that cannot be stored in the upper tray 8a.
The upper tray unit 8 is provided with a ball removal button 16 for removing the game balls stored in the upper tray 8a toward the lower tray 9a. The lower tray unit 9 is provided with a ball removal lever 17 for pulling out the game balls stored in the lower tray 9a to the lower side of the gaming machine.
Further, the upper tray unit 8 has a ball lending button 14 for requesting a game ball lending device to a game ball lending device (not shown) and a card for requesting the return of the valuable medium inserted in the game ball lending device. A return button 15 is provided.
The upper tray unit 8 is further provided with production buttons 11 and 12 and a cross key 13. The effect buttons 11 and 12 are push buttons that can be operated by turning on the built-in lamp during a predetermined input acceptance period and can be changed when the built-in lamp is turned on. Further, the cross key 13 is an operator for the player to perform an operation for an operation or an effect setting according to the effect situation.

The firing operation handle 10 is provided on the right end side of the operation panel 7 and is an operator for operating the launching device 32 shown in FIG.
In addition, speakers 25 that sound production effects are provided on both sides of the upper portion of the front frame 2 and in the vicinity of the firing operation handle 10.

  Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or resin board. The game board 3 is provided with a ball guide rail 31 for guiding the launched game ball in a ring shape as a board surface partition member, and a substantially circular area surrounded by the ball guide rail 31 is a game area 3a. It has become.

A liquid crystal display device 32 (LCD: Liquid Crystal Display) is provided at a substantially central portion of the game area 3a.
In the liquid crystal display device 32, for example, three decorative symbols of left, middle, and right are displayed on the background image under the control of an effect control unit 51 described later. Various effect images such as a normal effect, a reach effect, and a super reach effect are also displayed.

Further, a center decoration 35C is provided in the game area 3a so as to surround the display surface of the liquid crystal display device 32.
The center ornament 35C not only exhibits a decorative effect due to its design, but also has an action of protecting the display surface of the liquid crystal display device 32 from surrounding game balls. Furthermore, the center decoration 35C also functions as a member that enables the right and left shots of the flow path of the game ball depending on the strength or stroke length of the game ball. That is, the flow path of the game ball launched to the upper part of the game area 3a via the ball guide rail 31 flows down either the left game area 3b or the right game area 3c divided by the center decoration 35C. In the case of so-called left hit, the game ball flows down the left game area 3b, and in the case of right hit, the game ball flows down the right game area 3c.

In addition, a lower left decoration 35L is provided below the left game area 3b to exhibit a decorative effect and define a range as the left game area 3b.
Similarly, a lower right decoration 35R is provided below the right game area 3c, which exhibits a decorative effect and defines a range as the left game area 3b.
In the game area 3a (the left game area 3b and the right game area 3c), nails 49 and windmills 47 are provided at various places to form various flow paths for the game balls.
In addition, a center stage 35S is provided below the liquid crystal display device 32, and exhibits a decorative effect and functions as a play area for a game ball.
Although not shown in the drawing, the center ornament 35C is provided with a movable body accessory that provides a visual effect in an appropriate place.

In the vicinity of the upper right edge of the game area 3a, a symbol display unit 33 is provided by a dot display formed by arranging a plurality of LEDs.
In the symbol display unit 33, a first special symbol display unit, a second special symbol display unit, and a normal symbol display unit are formed by a predetermined dot area, and the first special symbol, the second special symbol, and the normal symbol are displayed. Each variation display operation (variation display operation for setting variation start and variation stop as one set) is performed.
The liquid crystal display device 32 variably displays the decorative symbol by the image in synchronization with the variation display of the first and second special symbols by the symbol display unit 33 in time.

A winning device having an upper start port 41 (first special symbol start port) is provided below the center ornament 35C, and a lower start port 42a (second special symbol start port) is further provided below that. A variable winning device 42 is provided.
Inside the upper start opening 41 and the lower start opening 42a, detection sensors (upper start opening sensor 71 and lower start opening sensor 72 shown in FIG. 3) for detecting the passage of the game ball are formed.

  The upper starting port 41 is a winning port related to the starting condition of the variable display operation of the first special symbol in the symbol display unit 33, and does not have a starting port opening / closing means (means for opening or expanding the starting port). It is a type winning device.

The normal variation winning device 42 having the lower starting port 42a is configured as a winning rate variation type winning device capable of changing the winning rate of the game ball at the starting port by the starting port opening / closing means. That is, it is a so-called electric tulip type winning device including a pair of left and right movable blades (movable members) 42b that can open or enlarge the lower start port 42a.
The lower start opening 42 a of the normal variation winning device 42 is a winning opening relating to the start condition of the variable display operation of the second special symbol in the symbol display unit 33. The winning rate of the lower start port 42a varies depending on the operating state of the movable blade piece 42b. That is, it is configured such that winning is easy when the movable blade piece 42b is open, and winning is difficult or impossible when the movable blade piece 42b is closed.

In addition, a plurality of general winning ports 43 are provided on the left and right sides of the normal variation winning device 42. A detection sensor (general winning opening sensor 74 shown in FIG. 3) for detecting the passage of the game ball is formed inside each general winning opening 42.
In addition, a normal symbol start port 44 including a gate (specific passage region) through which a game ball can pass is provided on the lower side of the right game region 3c. The normal symbol starting port 44 is a winning port related to a normal symbol variation display operation in the symbol display unit 33, and a sensor (gate sensor 73 shown in FIG. 3) for detecting a passing game ball is formed in the normal symbol starting port 44. Has been.

A first special variable winning device 45 (special electric accessory) is provided along the flow path from the normal symbol starting port 44 to the normal variable winning device 42 in the right game area 3c.
The first special variable winning device 45 is configured to close / open the first big winning opening 45a by a retractable opening door 45b. In addition, a sensor for detecting the passage of the game ball to the first big prize opening 45a (the first big prize port sensor 75 in FIG. 3) is formed inside.
The lower right decoration 35R bulges from the surface of the game board 3 around the first grand prize winning opening 45a, and the upper side of the bulged portion and the upper surface of the open door 45b guide downstream of the right flow path 3c. Forming part. Therefore, when the opening door 45b is drawn into the board, the game ball that has reached the downstream guide portion easily enters the first big winning opening 45a.

A second special variable winning device 46 (special electric accessory) is provided below the normal variable winning device 42. The second special variable winning device 46 is configured to close / open the second large winning port 46a on the inside by an open door 46b that is pivotally supported at the lower part and can be opened and closed. In addition, a sensor (second big prize port sensor 76 in FIG. 3) for detecting the passage of the game ball to the second big prize port 46a is formed therein.
The second big prize opening 46a is opened by opening the open door 46b. In this state, the game balls that have flowed down the left game area 3b or the right game area 3c will enter the second big prize opening 50 with a high probability.

As described above, the upper starting port 41, the lower starting port 42a, the normal symbol starting port 44, the first large winning port 45a, the second large winning port 46a, and the general winning port 43 are formed in the game area of the board as winning ports. Has been.
In the pachinko gaming machine 1 according to the present embodiment, when a winning is made to a winning port other than the normal symbol starting port 44 among these winning ports, per winning ball set for each winning port. The number of prize balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the upper start opening 41 and the lower start opening 42a are set to three, the first big winning opening 45a and the second big winning opening 46a are set to 13, the general winning opening 43 is set to 10 and the like.
Note that the game balls that have not won the prize holes are discharged from the game area 3 a through the out port 48.
Here, “winning” means that the winning opening takes the game ball inside, or the game ball passes through the gate. Actually, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated that a “winning” has occurred in that winning opening. The game ball related to the winning is also referred to as “winning ball”.

On the board as described above, the center ornament 35C, the lower left ornament 35L, the lower right ornament 35R, the center stage 35S, the first special variable winning device 45, the second special variable winning device 46, and a movable object not shown in the figure. Although not shown in detail, light emitting units 20b, 20Z, 20H, and 20J using LEDs, for example, are provided at various places as light emitting means on the panel side.
The light emitting unit 20b performs a light emitting operation for production and a light emitting operation for error notification.
The light emitting units 20Z, 20H, and 20J are light emitting units for presenting various situations.
The light emitting unit 20Z performs a light emitting operation for identifying a varying symbol. There are three light emitting units 20Z corresponding to, for example, the first special symbol, the second special symbol, and the normal symbol, and for each corresponding symbol, for example, when the symbol variation is stopped, changing, and hitting A light emitting operation for identifying is performed.
The light emitting unit 20H performs a light emission operation for displaying the number of holds. The light emitting unit 20H displays, for example, a maximum of four reserved numbers for the first special symbol variation, and displays a maximum of four reserved numbers for the second special symbol variation, for example, a total of eight are provided. The hold number is displayed in the light emission state.
The light emitting unit 20J performs a light emitting operation for game state notification. The required number of light emitting units 20J is provided (three in this example), and in each of the light emitting states, notifications such as during a big hit, during probability change, during a short time, etc. are made.
In this example, the light emitting units 20Z, 20H, and 20J are provided on the board side, but all or part of the light emitting units 20Z, 20H, and 20J may be provided on the frame side.

Hereinafter, for the sake of explanation, the board-side light emitting unit 20w and the frame-side light emitting unit 20b may be referred to as “production light-emitting units”.
The light emitting unit 20Z may be referred to as a “fluctuating symbol identifying light emitting unit”, the light emitting unit 20H may be referred to as a “holding number display light emitting unit”, and the light emitting unit 20J may be referred to as a “game state notification light emitting unit”.
Furthermore, the light emitting units 20Z, 20H, and 20J may be collectively referred to as “situation presentation light emitting unit”.

<2. Control configuration of pachinko machine>

Next, the configuration of the control system of the pachinko gaming machine 1 according to the present embodiment will be described. FIG. 3 is a schematic block diagram of the internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 of the present embodiment mainly has a main control board 50, an effect control board 51, a liquid crystal control board 52, a payout control board 53, a launch control board 54, and a power supply board 58 as the boards forming the control configuration. Is provided.

The main control board 50 is equipped with a microcomputer or the like, and performs overall control related to the entire game operation of the pachinko gaming machine 1. In the following description, a component of the main control board 50 including a microcomputer mounted on the main control board 50 is referred to as a “main control unit 50”.
The effect control board 51 is equipped with a microcomputer or the like, receives an effect control command from the main control unit 50, and performs control for executing various effect operations using image display, light emission, sound output, and movable object. I do. Hereinafter, the structure of the effect control board 51 including the microcomputer mounted on the effect control board 51 is referred to as an “effect control unit 51”.

The liquid crystal control board 52 is equipped with a microcomputer, a video processor, and the like, and receives display control commands from the effect control unit 51 to control display operations by the liquid crystal display device 32.
The payout control board 53 performs payout control of prize balls by the game ball payout device 55 connected to the pachinko gaming machine 1.
The launch control board 54 controls the launch operation of the game ball by the launch device 56 provided in the player's pachinko gaming machine 1.
The power supply board 58 performs AC / DC conversion and further DC / DC conversion from an external power supply (for example, AC 24 V), and supplies an operation power supply voltage Vcc to each unit. The power supply path is not shown.

First, the main controller 50 and its peripheral circuits will be described.
The main control unit 50 includes a microprocessor incorporating a CPU 100 (hereinafter referred to as “main control CPU 100”), a ROM 101 (hereinafter referred to as “main control ROM 101”), and a RAM 102 (hereinafter referred to as “main control RAM 102”). A microcomputer is configured.
The main control CPU 100 executes various calculations and control processes according to the progress of the game based on the control program.
The main control ROM 101 stores a game operation control program by the main control CPU 100 and various data necessary for game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processing, and as a buffer area for various input / output data and processing data.
Although not shown, the main control unit 50 includes an interface circuit with each unit, a random number generation circuit that generates random numbers for lottery related to special symbol variation display, a CTC (Counter Timer Circuit) for various time counting, An interrupt controller circuit for giving an interrupt signal to the control CPU 100 is also provided.

As described above, the main control unit 50 receives each winning means in the game area on the board (upper start port 41, lower start port 42a, normal symbol start port 44, first big win port 45a, second big win port 46a, general It is configured to receive a detection signal of a sensor provided at the winning opening 43).
That is, the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76 are sent to the main control unit 50. Supplied.
These sensors (71 to 76) are configured by detection switches that detect a game ball that has entered, but specifically, contactless switches such as photoswitches and proximity switches, and contact points such as microswitches. It can consist of switches.

  The main control unit 50 receives the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76. Depending on the process. For example, lottery processing, symbol variation control, prize ball payout control, effect control command transmission control, external data transmission processing, and the like are performed.

The main control unit 50 is connected to a normal electric accessory solenoid 77 that opens and closes the movable wing piece 42b of the lower start port 42, and the main control unit 50 transmits a control signal according to the progress of the game to perform normal electric operation. The driving operation of the accessory solenoid 77 is executed, and the opening / closing operation of the movable blade piece 42b is executed.
Further, the main control unit 50 has a first grand prize opening solenoid 78 that opens and closes the opening door 45b of the first big prize opening 45 and a second big prize that opens and closes the opening door 46b of the second big prize opening 46. A mouth solenoid 79 is connected. The main control unit 50 drives and controls the first big prize opening solenoid 78 or the second big prize opening solenoid 79 in accordance with the so-called jackpot situation, and opens the first big prize opening 45 or the second big prize opening 46. Is executed.

  In addition, a symbol display unit 33 is connected to the main control unit 50, and a control signal is transmitted to the symbol display unit 33 to execute various symbol displays (LED OFF / ON / flashing). Thereby, the display operation in the 1st special symbol display part 80 in the symbol display part 33, the 2nd special symbol display part 81, and the normal symbol display part 82 is performed.

  The main control unit 50 is connected to a frame external terminal board 57. The main control unit 50 can transmit information related to game progress to a hall computer (not shown) via the frame external terminal board 57. The information related to the game progress is information such as jackpot winning information, prize ball number information, symbol variation display execution number information, and the like. The hall computer is a management computer that comprehensively manages pachinko hall gaming machines, and is installed outside the gaming machine.

In addition, a payout control board 53 is connected to the main control unit 50. Connected to the payout control board 53 are a launch control board 54 for controlling the launch device 56 and a game ball payout device 55 for paying out game balls.
The main control unit 50 transmits a payout control command (payout control command for designating the number of prize balls) to the payout control board 53. The payout control board 53 controls the game ball payout device 55 in accordance with the control command to cause the game ball to be paid out.
The payout control board 53 can transmit information (payout state signal) regarding the payout operation state to the main control unit 50. The main controller 50 monitors whether or not the game ball payout device 55 is functioning normally based on this payout state signal. Specifically, it is monitored whether or not a problem such as clogged balls or insufficient payout of prize balls has occurred during the prize ball payout operation.

  The main control unit 50 transmits an effect control command including information related to the special symbol variation display to the effect control unit 51. The transmission of the effect control command from the main control unit 50 to the effect control unit 51 is executed by one-way communication. This is to prevent an unauthorized signal due to an illegal act from the outside from being input to the main control unit 50 via the effect control unit 51.

Next, the production control unit 51 and its peripheral circuits will be described.
The effect control unit 51 includes a microprocessor incorporating a CPU 200 (hereinafter referred to as “effect control CPU 200”), a ROM 201 (hereinafter referred to as “effect control ROM 201”), and a RAM 202 (hereinafter referred to as “effect control RAM 202”). A microcomputer is configured.
The effect control CPU 200 performs arithmetic processing for various effect operations and controls each effect means based on the effect control program and the effect control command received from the main control unit 50. In the case of the pachinko gaming machine 1 of the present embodiment, the effect means is the liquid crystal display device 32, the light emitting units 20w and 20b, the speaker 25, and a movable body accessory that is not shown.
The effect control CPU 200 also performs control for presenting various situations. Specifically, this is light emission control of the light emitting units 20Z, 20H, and 20J.
The effect control ROM 201 stores a control program of the effect operation by the effect control CPU 200 and various data necessary for effect operation control.
The effect control RAM 202 is used as a work area used by the effect control CPU 200 for various arithmetic processes, a table data area, a buffer area for various input / output data and processing data, and the like.
Although illustration is omitted, the production control unit 51 gives an interrupt signal to the interface circuit with each unit, a random number generation circuit for generating random numbers for lottery for production, CTC for various time counting, and the production control CPU 200. An interrupt controller circuit and a sound source IC for sound production are also provided.
The main role of the effect control unit 51 is to receive an effect control command from the main control unit 50, to select an effect based on the effect control command, to transmit a liquid crystal control command to the liquid crystal display device 32, and to hear sound from the speaker 45. It becomes output control, light emission control of the light emission parts 20w, 20b, 20Z, 20H, and 20J (LED), operation control of a movable body accessory, etc.

  The effect control unit 51 transmits an effect control command to the liquid crystal display device 32, and the effect control command is sent to the liquid crystal control board 52 via the liquid crystal interface board 66.

The liquid crystal control board 52 performs display control of the liquid crystal display device 32. Although not shown, the liquid crystal control board 52 includes a VDP (Video Display Processor), an image ROM, a VRAM (Video RAM), a liquid crystal control CPU, a liquid crystal control ROM, and a liquid crystal control RAM.
The VDP performs overall control of video output processing such as image development processing and image drawing.
The image ROM stores image data (effect image data) on which the VDP performs image expansion processing.
The VRAM is an image memory area that temporarily stores image data developed by the VDP.
The liquid crystal control CPU outputs control data necessary for the VDP to perform display control.
The liquid crystal control ROM stores a program describing the display control operation procedure of the liquid crystal control CPU and various data necessary for the display control.
The liquid crystal control RAM functions as a work area and a buffer memory.

  With these configurations, the liquid crystal control board 52 generates various image data based on the liquid crystal control command from the effect control board 51 and outputs the image data to the liquid crystal display device 32. As a result, various effect images are displayed on the liquid crystal display device 32.

In addition, a frame driver unit 61 and a panel driver unit 62 are connected to the effect control unit 51.
The frame driver unit 61 performs light emission driving for the LEDs of the lamp unit 63 on the frame side. In addition, the lamp part 63 generally shows the light emission part 20w provided in the frame side as shown in FIG.
The panel driver unit 62 performs light emission driving for the LEDs of the lamp unit 64 on the panel side. Note that the lamp portion 64 is a general view of the light emitting portions 20b, 20Z, 20H, and 20J provided on the panel side as shown in FIG.

A motor driver unit 70 is connected to the effect control unit 51.
The motor driver unit 70 drives the movable body accessory motor 65 to execute the operation of the movable body accessory provided on the panel side.
As the movable body accessory motor 65, for example, a stepping motor is used.

In this embodiment, the frame driver unit 61 is a first system drive signal output unit, the panel driver unit 62 is a second system drive signal output unit, and the motor driver unit 70 is a third system drive signal output unit. .
Although details will be described later with reference to FIG. 4, in the case of the present embodiment, the effect control unit 51 (effect control CPU 200) uses the serial data transmission channels ch1, ch2, and ch3 to transmit light emission drive data and motor drive data. The serial data is output to the frame driver unit 61, the panel driver unit 62, and the motor driver unit 70.
For example, a part of the panel driver unit 62 may operate as the motor driver unit 70 to drive each LED of the lamp unit 64 and the movable body accessory motor 65.

Further, the effect control unit 51 controls the sound source IC 59 so that the speaker 25 outputs a desired sound. A sound data ROM 69 is connected to the sound source IC 59, and the sound source IC 59 acquires necessary sound data (sound data of a phrase to be reproduced) from the sound data ROM 69 and outputs a sound signal.
The sound source IC 59 obtains a predetermined number (number of channels) of audio signals by mixing phrases of a plurality of channels. As shown in FIG. 1, in the case of this example, since a plurality of speakers 25 are provided, the number of output channels of the sound source IC 59 can be, for example, two channels of Lch and Rch (stereo output). Through the above mixing, phrases of a plurality of channels instructed to be reproduced from the effect control unit 51 can be reproduced simultaneously.

The output audio signal from the sound source IC 59 is amplified by the amplifier unit 67 and then given to the speaker 25.
In FIG. 3, for convenience of illustration, the number of output channels of the sound source IC 59 is set to one. It is possible to reproduce sound.
In this example, the sound source IC 59 is provided separately from the effect control unit 51, but the sound source IC 59 can also be provided in the effect control unit 51.

The effect control unit 51 is connected to an operation unit 60 that can be operated by the player, and can receive an operation detection signal from the operation unit 60. The operation unit 60 refers to the effect buttons 11 and 12 and the cross key 13 described with reference to FIG. 1 and their operation detection mechanisms.
The effect control unit 51 can perform various effect controls according to the operation detection signal from the operation unit 60.

  The production control unit 51 determines a production pattern by lottery or uniquely from a plurality of types of production patterns prepared in advance based on the production control command sent from the main control unit 50, and performs various productions at necessary timing. Control means. Thereby, the display of the effect image by the liquid crystal display device 32 corresponding to the effect pattern, the reproduction of the sound from the speaker 25, and the lighting and blinking driving of the LEDs in the lamp units 63 and 64 (light emitting units 20w, 20b, 20Z, 20H, and 20J). The operation of the movable body accessory by the movable body accessory motor 65 is realized, and various production patterns are developed in time series. Thereby, the “production scenario” is realized.

The effect control command defines a function by a 2-byte structure consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish between MODE and EVENT, MODE Bit 7 is ON, and EVENT Bit 7 is OFF.
When these pieces of information are transmitted as valid, a strobe signal is output corresponding to each of the mode (MODE) and the event (EVENT). That is, when there is a command to be transmitted, the main control CPU 100 sets and outputs mode (MODE) information for transmitting the command to the effect control unit 51, and the first strobe signal after a predetermined time has elapsed from this setting. Send. Furthermore, event (EVENT) information is set and output after the elapse of a predetermined time from the transmission of the strobe signal, and the second time of the strobe signal is transmitted after the elapse of the predetermined time from this setting.
The strobe signal is controlled by the main control CPU 100 to be in an active state for a predetermined period during which the effect control CPU 200 can reliably receive a command.
The effect control unit 51 (effect control CPU 200) generates an interrupt based on the input of the strobe signal and executes a control program for command reception interrupt processing, and the effect control command is acquired in this interrupt processing. .

<3. Overview of operation>

An outline of the operation of the pachinko gaming machine 1 will be described.
[Design variation display game]
In the pachinko gaming machine 1, a big hit lottery is performed by a random lottery in the main control unit 50 on condition that a predetermined start condition, specifically, a game ball wins the upper start opening 41 or the lower start opening 42. Based on the lottery result, a special symbol (identification symbol for notifying the jackpot lottery result) is displayed in a variable manner on the first special symbol display unit 80 or the second special symbol display unit 81 to start a special symbol variation display game. The result is displayed on the special symbol display section (80 or 81) after a predetermined time has elapsed.

In the present embodiment, the big hit lottery based on the winning at the upper start opening 41 and the big hit lottery based on the winning at the lower starting opening 42 are performed independently. For this reason, the big hit lottery result regarding the upper start port 41 is derived and displayed on the first special symbol display unit 80 side, and the big hit lottery result regarding the lower start port 42 is derived and displayed on the second special symbol display unit 81 side.
For the sake of explanation, the special symbol variation display game on the first special symbol display unit 80 side is referred to as “first special symbol variation display game”, and the special symbol variation display game on the second special symbol display unit 81 side is referred to as “second special symbol variation display game”. This is referred to as a “display game”. However, the first and second special symbols are collectively referred to as “special symbols”, and the first and second special symbol variation display games are collectively referred to as “special symbol variation display games”.

  When the special symbol variation display game is started, a decoration symbol variation display game for variably displaying the decoration symbol (game symbol) on the liquid crystal display device 32 is started, and various effects appear along with this. Is done. When the lottery result is displayed on the first and second special symbol display sections (80, 81), the result is also displayed on the liquid crystal display device 32 by the decorative symbol. That is, in this decorative symbol variation display game, an effect display reflecting the lottery result in the special symbol variation display game, that is, an effect reflecting the jackpot lottery result appears.

  For example, when the result of the special symbol variation display game is “big hit”, the result of the decorative symbol variation display game is also an effect reflecting “big hit”. Further, the special symbol indicating the big hit is stopped and displayed in a predetermined display form on the special symbol display section (80, 81), and the liquid crystal display device 32 displays the “left”, “middle”, and “right” display areas. , In a predetermined display mode in which the decorative symbols reflect the big hit lottery result on the winning effective line (for example, in the display areas of “left”, “middle”, and “right”, the three decorative symbols are “7”, “7”, “ 7 ”display state).

When this “big hit” is reached, for example, the first big prize opening solenoid 78 or the second big prize opening solenoid 79 is driven, and the opening operation of the first big prize opening 45 or the second big prize opening 46 in a predetermined pattern is performed. A special game state (big hit game) that is executed and is more advantageous to the player than the normal game state occurs. In this jackpot game, the big prize opening is determined until either the opening time of the big prize opening elapses for a predetermined time or until a predetermined number of game balls are won in the big prize opening. A round game such as closing time is repeated a predetermined number of times.
When the big hit game is started, an opening effect for informing that the big win is started is performed first, and after the opening effect is finished, the round game is performed for the specified number of rounds. In addition, during the round game, a round effect corresponding to each round is performed. Then, after the specified number of rounds is finished, an ending effect for notifying that the jackpot is finished is performed, and thereby the jackpot game is finished.

  In this way, the special symbol variation display game and the decorative symbol variation display game have substantially the same game time (from the start timing of the variation display to the stop display timing), and reflect the result of the special symbol variation display game. Since the thing is expressed in the decorative symbol variation display game, the two symbol variation display games can be regarded as equivalent symbol games. For the sake of explanation, the two symbol variation display games may be simply referred to as “symbol variation display game”.

  In addition, based on the fact that the game ball has passed through the gate 44 (normal symbol start opening), the main control unit 50 performs a lottery per assistance by random number lottery. In accordance with the lottery result, the normal symbol represented by the LEDs of the normal symbol display unit 82 is variably displayed and the normal symbol variation display game is started. After a predetermined time has elapsed, the result is determined by whether the LED is lit or not lit. Stop display by combination.

  When “subsidiary hit” is reached, the ordinary electric accessory solenoid 77 is activated, the movable wing piece 42b is opened, the lower start opening 42 is opened or enlarged, and the game ball is likely to flow (open start opening). State), and an auxiliary gaming state (hereinafter referred to as “open-game”) that is more advantageous to the player than the normal gaming state occurs. In this open electric game, the movable wing piece 42b is released for a predetermined time (for example, 0.2 seconds) or until a predetermined number (for example, 4) of game balls are won, and then for a predetermined time (for example, (0.5 seconds) The operation of closing the movable blade piece 42b is repeated a predetermined number of times. It should be noted that the special symbol variation display game is also performed in the same manner when the game ball wins the lower start opening 42 during the open-circuit game, and the decorative symbol variation display game is performed accordingly.

Here, during the special symbol variation display game, the normal symbol variation display game, the big hit game, or the general electric open game, the upper start port sensor 71, the lower start port sensor 72, or the gate sensor 73 When a detection signal is input and the start condition is satisfied, game information to be used for the winning lottery is acquired based on the detection signal, and this is used as data related to the start right for causing each variable display game to be played. As (holding data), except for those related during the variable display, it is possible to hold and store up to a predetermined upper limit maximum number of stored memories (for example, up to 4). In order to make this number of holds clear to the player, a hold indicator provided as an icon image on the screen of the hold number display unit 20H or the liquid crystal display device 32 is lit up.
Normally, a variation display game for each held ball is executed in the order in which the held balls are generated. In the present embodiment, the same number as the maximum number of reserved storage is handled as the upper limit predetermined number, and up to four pieces of reserved data relating to the first special symbol and the second special symbol are stored, respectively, and fluctuations in the special symbol or the normal symbol Hold as fixed number of times.

[Game state]
The pachinko gaming machine 1 according to the present embodiment is configured to be capable of generating a plurality of types of gaming states.
First, the pachinko gaming machine 1 according to the present embodiment includes a “probability variation (hereinafter referred to as“ probability variation ”) function” that the main control unit 50 (CPU 100) serves as its function unit. There are two types: a probability changing function related to a special symbol (hereinafter referred to as “special symbol probability changing function”) and a probability changing function related to a normal symbol (hereinafter referred to as “normal symbol probability changing function”).

The special symbol probability changing function is advantageous over the normal gaming state by changing the probability of winning a big hit from a low probability (for example, 1/399) to a high probability (for example, 1 / 9.9). This is a function that generates a “high probability state”. Under this high probability state, the jackpot lottery probability is high, so that the jackpot is likely to occur.
The normal symbol probability changing function is more advantageous than the normal gaming state by changing from a low probability (for example, 1/256) to a high probability (for example, 255/256) that the lottery probability per auxiliary is a predetermined probability (normal probability). This is a function that generates a "probability per auxiliary change state". Under this sub-probability variation condition, the per-subsidence lottery probability is high, so sub-prone is more likely to occur, and open-circuit games occur more frequently. It will be in the operating rate improvement state which the operating rate of the piece 42b improves.

  In addition, the pachinko gaming machine 1 of the present embodiment includes a “variable time reduction (hereinafter referred to as“ time reduction ”) function” that the main control unit 50 serves as a functional unit. There are two types of time-shortening functions relating to special symbols (hereinafter referred to as “special symbol time-shortening functions”) and time-shortening functions relating to normal symbols (hereinafter referred to as “normal symbol time-shortening functions”).

The special symbol time reduction function shortens the average time required for one special symbol fluctuation display game (the time from when the special symbol starts to change until it is fixedly displayed. That is, the special symbol fluctuation time) This is a function for generating a “short time state”. Under the special symbol short-time state, the average variation time of the special symbol in one special symbol variation display game is shortened, and the lottery number improvement state is improved in which the number of big lotteries per unit time is improved as compared with the normal gaming state.
In the pachinko gaming machine 1, the special symbol variation display time may be shortened due to the difference in the number of holds, but in this case, the special symbol time-short state does not occur and is caused by other control processing. Is.

  The normal symbol time shortening function shortens the average time required for one normal symbol fluctuation display game (the time from the start of normal symbols to the final display, that is, the normal symbol fluctuation time). This is a function for generating a “short-time state”. Under the normal symbol short-time state, the average variation time of the normal symbol in one normal symbol fluctuation display game is shortened, and the lottery number improvement state is improved in which the number of lotteries per auxiliary time per unit time is improved as compared with the normal game state. .

In addition, the pachinko gaming machine 1 according to the present embodiment includes an “open extension function” in which the main control unit 50 serves as its function unit.
The opening extension function is a function of generating an “open extension state” in which the movable blade piece 42 b is opened and the number of times of opening is extended. This open extended state is referred to as a so-called “electric chew support state”. Under the open extended state, the opening operation period (starting port open state time) of the movable blade piece 42b is extended from 0.2 seconds to 1.7 seconds, for example, and the number of times of opening and closing is changed from 1 to 2 times, for example. The operation rate is improved and the operation rate of the movable wing piece 42b per unit time is improved compared to the normal game state.

By operating one or more types of the functions as described above, it is possible to change the internal gaming state of the gaming machine.
Here, in this embodiment, the operation start conditions of the normal symbol probability changing function, the normal symbol short-time function, and the open extension function are the same as the operation start conditions of the special symbol short-time function, and each function operates at the same opportunity. Will do.

[About hits]
In the pachinko gaming machine 1 of the present embodiment, “15R low base non-probable big hit”, “15R low base probable big hit” are selected as the types of wins to be drawn in the special symbol variation display game, that is, the hit types to be the big hit lotteries. There are multiple types of hits such as “Big hit”, “15R low base probability variation β big hit”, “15R high base probability variation big hit”, “2R low base probability variation big hit”, and “Small hit”.

<4. Driver Configuration and Presentation LED of First Embodiment>

Next, the driver configuration as the first embodiment will be described. The frame driver unit 61 (first system) and the panel driver unit 62 (second system) to which light emission drive data and motor drive data are supplied as serial data by the serial data transmission channels ch1, ch2, and ch3 of the effect control unit 51 described above. The configuration of the motor driver unit 70 (third system).

FIG. 4 shows a frame driver unit 61, a panel driver unit 62, and a motor driver unit 70 connected to the effect control unit 51.
In the frame driver unit 61 which is the first-system drive signal output means, n LED drivers 90 are connected in parallel to the serial data output channel ch1 of the effect control CPU 200.
As a signal line of the serial data output channel ch1, a reset signal line for supplying a reset signal RESET, a clock line for supplying a clock signal CLK, and serial data DATA as light emission drive data (also referred to as “LED drive data”) are supplied. A data line and an enable signal line for supplying an enable signal ENABLE are provided. Each of these signal lines is connected so as to supply each signal in parallel to n LED drivers 90 constituting the frame driver unit 61.
In each LED driver 90 of the frame driver unit 61, a device ID used as a slave address by the effect control CPU 200 is set. That is, the identifier of each LED driver 90. For the sake of explanation, the device IDs (slave addresses) of the LED drivers 90 are denoted as w1 to w (n) as illustrated.

In the panel driver unit 62 which is the second-system drive signal output means, m LED drivers 90 are connected in parallel to the serial data output channel ch2 of the effect control CPU 200.
Similarly to channel ch1, the signal line of serial data output channel ch2 is a reset signal line for supplying reset signal RESET, a clock line for supplying clock signal CLK, a data line for supplying serial data DATA as light emission drive data, and an enable signal ENABLE. An enable signal line for supplying is provided. Each of these signal lines is connected so as to supply each signal in parallel to m LED drivers 90 constituting the panel driver unit 62.
In each LED driver 90 of the panel driver unit 62, a device ID (identifier of each LED driver 90) used as a slave address by the effect control CPU 200 is set. For the sake of explanation, the device ID (slave address) of each LED driver 90 is represented as b1 to b (m) as shown in the figure.

Further, in the motor driver section 70 which is the third system drive signal output means, p LED drivers 90 are connected in parallel to the serial data output channel ch3 of the effect control CPU 200.
Similarly, the signal line of the serial data output channel ch3 supplies a reset signal line for supplying a reset signal RESET, a clock line for supplying a clock signal CLK, a data line for supplying serial data DATA as motor drive data, and an enable signal ENABLE. An enable signal line is provided. Each of these signal lines is connected so as to supply each signal in parallel to p motor drivers 90M constituting the motor driver unit 70.
In each motor driver 90M of the motor driver unit 70, a device ID (identifier of each motor driver 90M) used as a slave address by the effect control CPU 200 is set. For the sake of explanation, the device ID (slave address) of each motor driver 90M is described as mt1 to mt (p) as shown in the figure.

As each LED driver 90 in the frame driver unit 61 and the panel driver unit 62, for example, “LV5236V (manufactured by Sanyo Semiconductor Co., Ltd.)” which is a 24-channel LED driver can be used, and 24 current terminals are provided. Therefore, one LED driver 90 can supply LED drive current to a maximum of 24 lines. Specifically, for example, 8 series R (red) LED drive current supply, 8 series G (green) LED drive current supply, 8 series B (blue) LED drive current supply, and light emission of 8 full-color LEDs It can be driven. Here, one “series” refers to one LED connected to one current terminal or a group of a plurality of LEDs connected in series or in parallel to one current terminal. Yes.
The number n of LED drivers 90 in the frame driver unit 61 is determined by the number of LED sequences arranged on the frame side (the number of sequences of the light emitting unit 20w). Therefore, n may be 1 or may be 2 or more. The frame driver unit 61 has one or a plurality of LED drivers 90.
The number m of LED drivers 90 in the panel driver unit 62 is determined by the number of LED sequences (number of sequences of the light emitting units 20b, 20Z, 20H, and 20J) arranged on the panel side. Accordingly, m may be 1 or may be 2 or more. The panel driver unit 62 has one or a plurality of LED drivers 90.

FIG. 5A shows a schematic configuration example of a main part of the LED driver 90.
The LED driver 90 includes a serial bus interface 91, an address setting unit 92, a data buffer / PWM controller 93, a D / A converter 94, and drive current source circuits 95-1 to 95-24.
The drive current source circuits 95-1 to 95-24 are current sources that perform the 24 series drive current outputs from the current terminals 96-1 to 96-24, respectively.

The LED driver 90 receives an enable signal ENABLE, a clock signal CLK, and serial data DATA from the effect control CPU 200 with respect to the serial bus interface 91. The serial bus interface 91 takes in the serial data DATA at the timing of the clock signal CLK during the period specified by the enable signal ENABLE. The serial bus interface 91 converts the captured serial data into parallel data and transfers the parallel data to the data buffer / PWM controller 93.
Although the format of the serial data will be described later with reference to FIG. 33, the effect control CPU 200 transmits the LED drive data by designating the slave address.
The data buffer / PWM controller 93 performs slave address confirmation for the parallel data transferred from the serial bus interface 91. When it is confirmed that the slave address included in the parallel data matches the own slave address (either w1 to w (n) or b1 to b (m)) set in the address setting unit 92 The LED drive data included in the parallel data is stored as valid data in a designated register.

When the data buffer / PWM controller 93 fetches each series of LED drive data, the data buffer / PWM controller 93 uses the values corresponding to the luminance information (gradation values) indicated by the LED drive data as 24 series drive control values as D / A. Output to the converter 94.
The D / A converter 94 converts a value corresponding to the luminance information into an analog signal, which is used as a control signal to each of the current source circuits 95-1 to 95-24.

24 series of LEDs 120 are connected to all (or part of) the current terminals 96-1 to 96-24. Although the drawing shows a simplified state in which one LED 120 is connected to one series of current terminals 96, a configuration in which a plurality of LEDs are connected to one series of current terminals 96 (for example, series connection) is also possible. Of course this is possible.
In each series (current terminals 96-1 to 96-24), the power supply voltage Vcc is applied to the series connection of the LED 120 and the resistor R. Current is supplied to each series of LEDs 120 by the current source circuits 95-1 to 95-24 to emit light.
That is, each of the current source circuits 95-1 to 95-24 operates so that a drive current having a current amount corresponding to the signal supplied from the D / A converter 94 flows through the corresponding series of LEDs 120.

Specifically, such LED drive control is described for one series. The data buffer / PWM controller 93 converts the digital data string corresponding to the pulse duty corresponding to the gradation value of the series to the D / A converter 94. The D / A converter 94 converts the digital data string into a pulse signal as an analog signal and supplies the pulse signal to the current source circuit 95 of the series. The output of the current source circuit 95 is controlled by the H / L of the pulse signal, and for example, outputs currents of 0 mA and 5 mA. For example, in such an operation, a driving current having an average current value corresponding to the gradation value flows to the LED 120 as a result.
In this embodiment, the current value is set to, for example, 0 mA and 5 mA by the PWM driving method, and gradation control is performed (integrally) in the time axis direction. Needless to say, the current value may actually be changed according to the gradation. Regardless of duty control or level control, appropriate gradation expression can be realized by setting the average current value per unit time to a level corresponding to the gradation.

Each motor driver 90M in the motor driver unit 70 may have the same configuration as the LED driver 90. For example, “LV5236V (manufactured by Sanyo Semiconductor Co., Ltd.)” can also be used.
The number p of motor drivers 90M in the motor driver unit 70 is determined by the number of motors of the movable body accessory. Therefore, p may be 1 or may be 2 or more. The motor driver unit 70 includes one or a plurality of motor drivers 90M.

A movable body accessory motor 65 for driving the movable body accessory is connected to the motor driver 90M.
FIG. 5B shows an example in which, for example, a stepping motor 121 as the movable body accessory motor 65 is connected to all (or part of) the current terminals 96-1 to 96-24 of a certain motor driver 90M. FIG. 5B shows only the current terminals 96-1 to 96-24, but the internal configuration of the motor driver 90M is the same as that of FIG. 5A.
Here, a drive current is supplied to the four-phase stepping motor 121 through current terminals 96-1 to 96-4, current terminals 96-5 to 96-8,..., Current terminals 96-21 to 96-24, respectively. A configuration example is shown.
The driver having the configuration shown in FIG. 5A is a circuit that outputs a current instructed by a given command (serial data) from the current terminals 96-1 to 96-24. Therefore, as shown in FIG. It can also be used as a motor driver 90M for a physically movable body drive device such as a solenoid.
The operation of the movable body accessory is finely set according to the production scenario, and the production control unit 51 controls the driving direction, the driving amount, and the like accordingly. The movable body using the motor driver 90M in the motor driver unit 70 is used. By driving the accessory, it becomes possible to control the movable object accessory by serial data together with each light emitting part (LED 20b) of the lamp part 64, and the control process and configuration can be made efficient.

  In one LED driver 90, a method may be adopted in which a part of current terminals are used for LED driving and another part of current terminals is used for driving a stepping motor, a solenoid, or the like.

As described above, the LED driver 90 is driven so that each LED 120 emits light with a designated luminance in accordance with the serial data DATA received from the effect control CPU 200. The motor driver 90M drives the stepping motor 121 according to the serial data DATA.
Each of the first, second, and third system drive signal output means (the frame driver unit 61, the panel driver unit 62, and the motor driver unit 70) outputs a drive signal to one or more effect units. A plurality of LED drivers 90 or motor drivers 90M are included, and serial data from the effect control unit 51 is transmitted in parallel to each LED driver 90 and motor driver 90M in one system. Each LED driver 90 and motor driver 90M acquires drive data (serial data) including its own ID (slave address).
As will be described later, in the present embodiment, the effect control unit 51 (effect control CPU 200) converts serial data of one transmission unit into drive signal output means (frame driver unit 61) for the first system and the second system for light emission control. , About the serial data of the transmission unit is transmitted to the frame driver unit 61 and the panel driver unit 62 after the transmission to the frame driver unit 62 is completed. A transmission process for outputting to the driver unit 61 and the panel driver unit 62 almost simultaneously is performed.

By the way, in the present embodiment, the board driver unit 62 performs LED light emission driving for the light emitting units 20Z, 20H, and 20J for status presentation in addition to LED light emission driving for the light emitting unit 20b for presentation.
FIG. 6 shows an example of the light emission operation of the situation presentation light emitting units 20Z, 20H, and 20J.

FIG. 6A shows an example of the light emission operation of the variation symbol identifying light emitting unit 20Z. As the variation symbol identifying light emitting unit 20Z, three light emitting units 20Z-1, 20Z-2, and 20Z-3 are provided. Each of the light emitting units 20Z-1, 20Z-2, and 20Z-3 performs a light emitting operation that represents a variation state corresponding to each of the first special symbol, the second special symbol, and the normal symbol.
For example, the light emission mode is such that “blinking” is fluctuating, “lighting” is stopped (winning), and “lighting off” is stopped (disconnected).
Therefore, when none of the first special symbol, the second special symbol, and the normal symbol is changed, the light emitting units 20Z-1, 20Z-2, and 20Z-3 are all in the off state.
When the variation of the first special symbol is started, the light emitting unit 20Z-1 starts blinking, and when the variation is successful, the light emitting unit 20Z-1 is turned on.
When the variation of the second special symbol is started, the light emitting unit 20Z-2 starts blinking. When the variation is successful, the light emitting unit 20Z-2 is turned on.
Further, when the variation of the normal symbol is started, the light emitting unit 20Z-3 starts blinking, and when the variation is successful, the light emitting unit 20Z-3 is turned on.

FIG. 6B is an example of the light emission operation of the light emission unit 20H for the number of hold display. As the number-of-holds display light emitting unit 20H, eight light emitting units 20H-1 to 20H-8 are provided.
The number of holds for the first special symbol variation display game (up to 4) is displayed with the four light emitting units 20H-1 to 20H-4. That is, among the light emitting units 20H-1 to 20H-4, the number of light emitting units 20H corresponding to the number of holdings is turned on.
The number of reserves (maximum 4) for the second special symbol variation display game is displayed with the four light emitting units 20H-5 to 20H-8. That is, among the light emitting units 20H-5 to 20H-8, the number of light emitting units 20H corresponding to the number of holdings is turned on.

FIG. 6C shows another example of the hold number display different light emitting section 20H. In this example, four light emitting units 20H-11 to 20H-14 are provided, and the number of holds for the first special symbol variation display game is displayed by two of the light emitting units 20H-11 and 20H-12. 20H-13 and 20H-14 are used to display the number of holds for the second special symbol variation display game.
For example, the number of holdings “0” to “4” by the two light emitting units 20H is displayed as follows.
・ 0 ... off: off ・ 1 ... on: off ・ 2 ... on: on ・ 3 ... blinking: on ・ 4 ... blinking: blinking

FIG. 6D shows an example of the light emitting operation of the gaming state notification light emitting unit 20J. As the gaming state notification light emitting unit 20J, for example, three light emitting units 20J-1, 20J-2, and 20J-3 are provided in accordance with the gaming states of “big hit”, “probable change”, and “short time”.
During the big hit, the light emitting unit 20J-1 is lit.
During the probability change, the light emitting unit 20J-2 is lit.
During the time, the light emitting unit 20J-2 is lit.
This is an example, and when providing a gaming state to be notified, the number of gaming state notification light emitting units 20J to be mounted may be changed as appropriate.
When there are a plurality of winning types, a plurality of gaming state notification light emitting units 20J may be provided so as to correspond to the respective winning types.

These status presentation light emitting units 20Z, 20H, and 20J are driven to emit light by, for example, the LED driver 90 in the board driver unit 62.
FIG. 7 shows an example in which the symbol identification light emitting unit 20Z and the hold number display light emitting unit 20H are connected to the LED driver 90 whose slave address is “b2”. The LED driver 90 is also connected with an effect light emitting unit 20b.

Connected to the current terminals 96-1 to 96-8 of the LED driver 90 are eight LEDs 120 corresponding to the light emitting units 20H-1 to 20H-8 as the holding number display light emitting unit 20H one by one. Has been.
For example, the LED 120 functioning as the light emitting unit 20H-1 and a resistor R are connected in series to the current terminal 96-1, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, the LED 120 functioning as the light emitting unit 20H-2 and a resistor R are connected in series to the current terminal 96-2, and the other end of the resistor R is connected to the first power supply voltage VCC1.
Similarly, one LED 120 functioning as the light emitting units 20H-3 to 20H-8 and a resistor R are connected in series to each of the current terminals 96-3 to 93-8 and connected to the first power supply voltage VCC1.

In addition, in the current terminals 96-9 to 96-11 of the LED driver 90, three LEDs 120 corresponding to the light emitting units 20Z-1 to 20Z-3 as the symbol identifying light emitting unit 20Z are provided one by one. It is connected.
For example, the LED 120 functioning as the light emitting unit 20Z-1 and a resistor R are connected in series to the current terminal 96-9, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, the LED 120 functioning as the light emitting unit 20Z-2 and a resistor R are connected in series to the current terminal 96-10, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, the LED 120 functioning as the light emitting unit 20Z-3 and a resistor R are connected in series to the current terminal 96-11, and the other end of the resistor R is connected to the first power supply voltage VCC1.

Further, the LED 120 that functions as the effect light emitting unit 20b is connected to the current terminals 96-12 to 96-20 of the LED driver 90.
For example, three LEDs 120 and a resistor R are connected in series to the current terminals 96-12 to 96-17, respectively, and the other end of the resistor R is connected to the second power supply voltage VCC2.
Two LEDs 120 and a resistor R are connected in series to the current terminals 96-18 to 96-20, respectively, and the other end of the resistor R is connected to the second power supply voltage VCC2.
In this example, the current terminals 96-21 to 96-24 are unused.

As the operating power supply voltage of the LED driver 90, the first power supply voltage VCC1 (for example, 5V) is used.
As described above, the LED driver 90 having the slave address “b2” is connected to the situation-presenting light emitting units (20Z, 20H) and the effect light-emitting unit 20b.
In the serial data DATA transmitted from the effect control unit 51 to the LED driver 90, in addition to the light emission drive data for the light emission effect, the light emission drive data for symbol identification, and the number of holdings are displayed. Light emission drive data is included. As a result, the LED driver 90 drives the LEDs 120 connected to the current terminals 96-12 to 96-20 to emit light based on the light emission drive data for the light emission effect, and based on the light emission drive data for symbol identification. The LED 120 connected to the current terminals 96-9 to 96-11 is driven to emit light, and the LED 120 connected to the current terminals 96-1 to 96-8 is driven to emit light based on the emission drive data for displaying the number of holdings. .

Here, since the LED driver 90 is driven at a relatively low voltage (for example, 5 V), the first power supply voltage VCC1 is prepared. On the other hand, although the light emission drive current is made to flow by using the second power supply voltage (12V) for the light emitting unit 20b for production, the light emitting unit 20b for production is often connected in series with a plurality of LEDs due to decorative demands. This is because a somewhat high voltage (for example, 12 V) is required as a power source for the drive current.
Therefore, power supply lines for the first and second power supply voltages VCC1 and VCC2 are prepared as peripheral circuits of the LED driver 90 that drives the light emitting unit 20b for performance.

Here, considering the symbol identifying light emitting unit 20Z and the reserved number displaying light emitting unit 20H, light emission for one presentation can be realized by one LED 120. As described above, when one LED is connected to each of the current terminals 96-1 to 96-11, each of the light emitting units 20 H-1 to 20 H-8 as the reserved number display light emitting unit 20 H, and for symbol identification The light emitting units 20Z-1 to 20Z-3 as the light emitting unit 20Z can sufficiently function.
Then, 12V is not necessary as a power source for light emission driving of the symbol identifying light emitting unit 20Z and the holding number display light emitting unit 20H, but if it is driven at 12V, a resistor R having a large resistance value is required and heat is applied. End up.
It is conceivable to prepare another power supply (third power supply voltage) as a countermeasure against this heat, but this makes the peripheral circuit of the LED driver 90 complicated.

Therefore, in the present embodiment, the first power supply voltage VCC1 used as the power source by the LED driver 90 is used as a power source for light emission driving of the symbol identifying light emitting unit 20Z and the reserved number display light emitting unit 20H. .
By doing in this way, it is not necessary to arrange a resistor R having a large resistance value to be connected to the LED 120 of the symbol identifying light emitting portion 20Z and the reserved number displaying light emitting portion 20H, and it is also appropriate as a heat countermeasure.
Further, since the third power supply voltage is not introduced, the peripheral circuit of the LED driver 90 is not complicated.

The LED driver 90 with the slave address “b2” drives the symbol identifying light emitting unit 20Z and the holding number display light emitting unit 20H in addition to the effect light emitting unit 20b. For example, the slave address “b3” has the slave address “b3”. The LED driver 90 drives the gaming state notification light emitting unit 20J in addition to the effect light emitting unit 20b.
Although illustration is omitted, the LED driver 90 has three current terminals 96-1 to 96-3 corresponding to the light emitting units 20 J-1 to 20 J-3 as the gaming state notification light emitting unit 20 J. The LEDs 120 are connected one by one.
That is, for example, the LED 120 functioning as the light emitting unit 20J-1 and the resistor R are connected in series to the current terminal 96-1, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, the LED 120 functioning as the light emitting unit 20J-2 and a resistor R are connected in series to the current terminal 96-2, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, the LED 120 functioning as the light emitting unit 20J-3 and a resistor R are connected in series to the current terminal 96-31, and the other end of the resistor R is connected to the first power supply voltage VCC1.
In addition, a plurality of LEDs 120 each functioning as an effect light emitting unit 20 b and a resistor R are connected in series to all or part of the current terminals 96-4 to 96-24 of the LED driver 90 with the slave address “b3”. The current drive is performed by the second power supply voltage VCC2.
In this way, the LED driver 90 with the slave address “b3” also takes measures against heat and prevents the peripheral circuits from becoming complicated.

In the serial data DATA transmitted from the effect control unit 51 to the LED driver 90 with the slave address “b3”, in addition to the light emission drive data for the light emission effect, the light emission drive data for informing the gaming state is included. To be included. Thereby, the LED driver 90 drives the LED 120 connected after the current terminal 96-4 to emit light based on the light emission driving data for light emission effect, and also uses the current terminal based on the light emission driving data for gaming state notification. The LED 120 connected to 96-1 to 96-3 is driven to emit light.

<5. Processing of main control unit>

Hereinafter, control processing according to the present embodiment will be described. First, main processing by the main control unit (main control board) 50 will be described here.
FIG. 8 is a flowchart showing main processing of the main control unit 50. The main process starts when the power is turned on without operating the initialization switch (not shown), such as when recovering from a power failure, and when the initialization switch is turned on. May turn on. In any case, when the pachinko gaming machine 1 is powered on, the power board 58 supplies a voltage to each control board. In this case, the main control unit 50 (main control CPU 100) starts the main process shown in FIG.

In the main control side main process, the main control CPU 100 first executes a necessary initial setting process before starting the game operation in step S11. For example, it first sets itself to the interrupt disabled state, sets to a predetermined interrupt mode (interrupt mode 2), and initializes the register values in the CPU including each part of the microcomputer.
Next, in step S12, the main control CPU 100 determines the state (ON, OFF) of a RAM clear signal that is an output signal of a RAM clear switch that is input via an input port (not shown). The RAM clear signal is a signal that determines whether or not to initialize all the areas of the RAM. The RAM clear signal usually has a value corresponding to the ON / OFF state of the initialization switch operated by the store clerk of the pachinko parlor.

When the RAM clear signal is in the ON state, the main control CPU 100 advances the process from step S12 to S16, and performs zero clear of the entire area of the RAM. Therefore, the value of the backup flag set at the time of power-off becomes zero together with other checksum values.
Subsequently, in step S17, the main control CPU 100 transmits a “RAM clear display command” for notifying that the RAM area has been cleared to zero to each control board as an initialization command. In step S18, for example, 30 seconds is stored in the RAM clear notification timer as a time for notifying that the RAM has been cleared.

Next, in step S19, the main control CPU 100 initializes a CTC that outputs an interrupt signal for starting a timer interrupt operation, and sets the CPU to an interrupt enabled state.
Thereafter, as the processing of steps S20, S21, and S22, the interrupt disabled state and the interrupt enabled state are repeated until an interrupt occurs, and various random number update processes are executed during that time. In the various random number update processing in step S21, random numbers used for changing initial values (start values) of various random numbers used for special symbol fluctuation display and normal symbol fluctuation display, and fluctuations used for selection of fluctuation patterns. Update pattern random numbers.
The various random numbers used for the special symbol variation display and the normal symbol variation display are, for example, random numbers related to jackpot lottery circulating through a predetermined numerical range by increment processing (special symbol determination random numbers used for symbol lottery). Or a random number related to a lottery per assistance (a random number for judging per assistance used in winning lottery per assistance). The random numbers used for changing the initial value include an initial value random number for special symbol determination, an initial value random number for auxiliary hit determination, and the like.

The main control RAM 102 has a special symbol determination random number counter initial value generation counter and a special symbol determination random number counter as various random number counters used for symbol lottery related to big hit lottery, auxiliary lottery, or variation pattern lottery. There are provided a counter for generating an initial value for an auxiliary per-determining counter, a random counter for determining an auxiliary per-prompt, a random number 1 for variation pattern, a random number 2 counter for variation pattern, and the like. These counters serve as random number generation means for generating random numbers in software.
In the various random number update processing in step S21, two initial value generation counters for generating initial values of the special symbol determination random number counter and the auxiliary hit determination random number counter, a variation pattern random number 1 counter, and a variation pattern random number 2 The counter is updated to generate the above various soft random numbers. For example, if the range of values that can be taken as the variation pattern random number 1 counter is 0 to 238, a value is acquired from the count value storage area for generating the value of the variation pattern random number 1 in the main control RAM 102, and the acquired value is 1 Are stored in the original count value storage area. At this time, if the result of adding 1 to the acquired value is 239, 0 is stored in the original random number counter storage area. Other initial value generation random number counters are updated in the same manner. The main control CPU 100 is configured to repeatedly execute various random number update processes except during the intermittently executed timer interrupt process.

The above describes the case where it is determined in step S12 that the RAM clear switch is ON. Next, the case where the RAM clear switch is OFF will be described. For example, at the time of recovery from a power failure state, the initialization switch (RAM clear signal) is in an OFF state. In such a case, the main control CPU 100 advances the process from step S12 to S13, and determines the backup flag value. The backup flag is set to the ON state when the power is shut off, and is reset to the OFF state in the first timer interrupt processing after the power is restored.
Therefore, when the power is turned on or when recovering from a power failure, the backup flag should normally be in the ON state. However, the backup flag is reset (OFF) if the predetermined processing is not completed before the power is cut off for some reason. Therefore, when the backup flag is in the OFF state, the main control CPU 100 advances the process from step S13 to S16, and returns the operation of the gaming machine to the initial state.

On the other hand, if the backup flag is in the ON state, the main control CPU 100 advances the process from step S13 to S14, and executes a checksum calculation for calculating a checksum value. Here, the checksum operation is an 8-bit addition operation for the work area of the main control RAM 102.
When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the main control RAM 102. This SUM address stores a checksum value obtained by the same checksum calculation when the power is shut off. The stored calculation result is maintained by the backup power source together with other data of the main control RAM 102. Therefore, originally, both should match according to the determination in step S14.
However, there may be a case where the checksum operation cannot be executed when the power is turned off, or even if it can be executed, the data in the work area is damaged after the checksum operation of the main process is executed. In such a case, the determination result in step S14 is inconsistent.
When data corruption is detected due to the discrepancy of the determination results, the main control CPU 100 proceeds to the processing from step S14 to S16, executes the RAM clear processing, and returns the operating state of the gaming machine to the initial state.

If the checksum value obtained by the checksum calculation in step S14 matches the stored value at the SUM address, the main control CPU 100 proceeds to step S15, and returns the stack pointer before power-off based on the backup data. A game restoration process necessary for starting a game from the processing state at the time of power-off is executed.
When the game restoration process at step S15 is completed, the process proceeds to the process at step S19, the CTC is initialized and the CPU is set in the interrupt enabled state. In the meantime, various random number update processes described above are executed (steps S20 to S22).

  Next, timer interrupt processing of the main control CPU 100 will be described. FIG. 9 shows the timer interrupt process of the main control CPU 100. This main control timer interrupt process is activated by interruption every predetermined time (about 4 ms) from the CTC, and is interrupted and executed during execution of the main process described above.

  When a timer interrupt occurs, the main control CPU 100 saves the contents of the register in the stack area, and first performs a power supply abnormality check process for monitoring the power supply state from the power supply board 58 in step S51 of FIG. In this power abnormality check process, it is mainly monitored whether the power is normally supplied. Here, for example, when an abnormality such as a power interruption occurs, a backup process for storing predetermined game information in the RAM at the time of power interruption is performed so that the game can be restored without any trouble when the power is restored.

  In step S52, the main control CPU 100 performs a timer management process for managing a timer used for gaming operation control. Timer values of various timers (for example, special symbol accessory operation timer) used for game operation control of the pachinko gaming machine 1 are managed (updated) by this processing.

In step S53, the main control CPU 100 performs input management processing. In this input management process, information detected by various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. Here, the detection information by the various sensors includes, for example, an upper start opening sensor 71, a lower start opening sensor 72, a gate sensor (ordinary symbol start opening sensor) 73, a first large winning opening sensor 75, and a second large winning opening sensor 76. This is ON / OFF information (winning detection information) of a switch signal output from a winning detection switch such as the general winning opening sensor 74.
Through the processing in step S53, it is monitored for each interrupt whether or not a winning is detected (winning has occurred) at each winning opening. The “winning counter” is a counter provided corresponding to each winning opening and counting the number of game balls (winning balls) won. In the present embodiment, in a predetermined area of the main control RAM 102, an upper start opening winning counter for the upper starting opening 41, a lower starting opening winning counter for the lower starting opening 42a, a normal symbol starting opening winning counter for the gate 44, A first grand prize winning counter for the first grand prize winning opening 45a, a second big winning prize winning prize counter for the second big winning prize opening 46a, a general winning prize winning counter for the general winning opening 43, and the like are provided. .
Further, in this input management process, it is also monitored whether or not there is an illegal prize based on whether or not the detection information from the prize detection switch has won a prize during a period in which the prize should be allowed. For example, when the first and second big prize opening sensors 75 and 76 detect a game ball even though the big hit game is not being played, the prize detection information is invalidated by invalidating the prize detection information. In order to notify the outside of the fact, a predetermined error process is performed in an error management process in step S55 described later.

  In step S54, the main control CPU 100 performs a timer interrupt random number management process for periodically updating the random numbers related to each variation display. In this periodic random number update process, a special symbol determination random number or auxiliary per-subject determination random number is updated (+1 is added for each interrupt), and a process for changing the start value of the random number counter is performed each time the random number counter makes a round. For example, the value of the special symbol judgment random number counter is updated (added by +1) within a predetermined range, and the special symbol judgment random number counter initial value generation counter value is read each time the special symbol judgment random number counter makes one round, The value of the generation counter is stored in a special symbol determination random number counter. As a result, the start value of the special symbol determination random number counter is changed according to the value of the generation counter, so that the count value of the special symbol determination random number counter is random while the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process for monitoring whether there is an abnormality in the gaming operation state. In this error management process, as abnormalities in the gaming operation state, for example, monitoring whether or not a break has occurred between the boards, monitoring whether or not there was an illegal winning, etc., these operation abnormalities (errors) occurred In such a case, predetermined error processing corresponding to the error is performed.
As error processing, for example, the progress of a predetermined game operation (for example, a game ball payout operation or game ball launch operation) is stopped, or an error notification command is transmitted to the effect control unit 51, and an error is generated by the effect means. Or that the occurrence has occurred.

In step S56, the main control CPU 100 performs prize ball management processing. In this prize ball management process, the data stored in the input management process in step S53 is grasped, the above-mentioned prize counter is confirmed, and if there is a prize, a payout control command for designating the number of prize balls is issued. Transmit to the substrate 53.
Upon receiving this payout control command, the payout control board 53 controls the game ball payout device 55 to perform a payout operation for the designated number of prize balls. Thereby, the number of winning balls corresponding to each winning opening is paid out. The number of winning balls corresponding to a winning opening is the predetermined number of winning balls per winning ball set for each winning opening × the number of winning balls corresponding to the value of the winning counter.

  In step S57, the main control CPU 100 performs normal symbol management processing. In this normal symbol management process, a lottery per auxiliary in the normal symbol variation display is performed, and based on the lottery result, the variation pattern of the normal symbol and the stop display mode of the normal symbol are determined, or the blinking is repeated every predetermined time. Create symbol data (data for LED blinking display during normal symbol variation), or create data for stop display (data for LED blinking display during normal symbol stop display) if normal symbol is not varying Or

In step S <b> 58, the main control CPU 100 performs normal electric accessory management processing. In this ordinary electric accessory management process, generation of an excitation signal for solenoid control for the ordinary electric accessory solenoid 77 and its data (solenoid control data) based on the lottery result of the auxiliary symbol lottery in the normal symbol management process in step S57. Set up. Based on the data set here, an excitation signal is output to the ordinary electric utility solenoid 77 in a solenoid management process in step S64 described later, whereby the operation of the movable blade piece 42b is controlled.
In step S59, the main control CPU 100 performs special symbol management processing. In this special symbol management process, the big hit lottery in the special symbol variation display is mainly performed, and based on the lottery result, the variation pattern of the special symbol (look-ahead variation pattern, variation pattern at the beginning of variation), special stop symbol, etc. decide.
In step S60, the main control CPU 100 performs a special electric accessory management process. In this special electric utility management process, when the big hit lottery result is “big hit” or “small win”, a setting process necessary to execute and control the hit game corresponding to the win is performed.

In step S61, the main control CPU 100 performs a right-handed notification information management process. In this right-handed notification information management process, for example, a right-handed instruction is given in situations where right-handed is advantageous, such as when the first and second big prize winning holes 45a and 46a are opened or when the movable blade piece 42b is driven. A process for making a “launch position guidance effect (right-handed notification effect)” for performing the notification appears. Specifically, the right-handed instruction is an effect operation instructing the player to aim at the right game area 3c. For example, an image prompting the player to “right-hand” is displayed on the main liquid crystal display device 32M. Or a right-handed message sound is generated from the speaker 25.
When a right-handed notification effect is performed, in this right-handed notification information management process, a “right-handed instruction command” instructing execution of a right-handed notification effect is transmitted to the effect control unit 51 as an effect control command. Then, the production control unit 51 performs execution control of right-handed notification using an image or sound.
In step S62, the main control CPU 100 performs LED management processing. This LED management process is a process of outputting display data for normal symbol display and first and second special symbol displays to the symbol display unit 33. By this processing, normal symbol and special symbol change display and stop display are performed. The normal symbol display data created in the normal symbol management process in step S57 and the special symbol display data created in the special symbol display data update process in the special symbol management process in step S59 are the LED management process. Is output.

In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management process, the operation state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. The operating state information includes that a big hit game has occurred (condition device has been activated), that a small hit game has occurred, that a symbol variation display has been executed (a special symbol variation display game has started or ended) , Information such as winning information (information indicating that the player has won a winning opening or a big winning opening and information on the number of winning balls) is included.
In step S64, the main control CPU 100 performs solenoid management processing. In this solenoid management process, an excitation signal output process for the ordinary electric accessory solenoid 77 based on the solenoid control data created in the ordinary electric accessory management process in step S58, and a special electric accessory management process in step S60. Excitation signal output processing for the first and second big prize opening solenoids 78 and 79 based on the solenoid control data is performed. Thereby, the movable wing piece 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower start port 42a and the big winning ports 45a and 46b are opened and closed.

  After completing the above steps S51 to S64, the main control CPU 100 restores the saved register contents and sets the interrupt permitted state in step S65. As a result, the timer interrupt process is terminated, the process returns to the main process on the main control side in FIG. 6 before the interruption, and the main control main process is performed until the next timer interruption occurs.

Next, the special symbol management process in step S59 of FIG. 9 will be described. FIG. 10 is a flowchart showing details of the special symbol management process in step S59.
10, in step S71, the main control CPU 100 first performs a first special symbol starting port check process on the first special symbol side (upper starting port 41 side), and then in step S72, the second special symbol side (lower starting port). 42a side)) is performed.

  Next, the main control CPU 100 determines the state of the small hitting flag in step S73. This small hitting flag is a flag for designating whether or not a small hit game is in progress. When the flag is ON, it indicates that the small hit game is in progress and the flag is OFF. If it is, it means that it is not in the small hit game.

  When the small hitting flag is OFF, the main control CPU 100 determines the state of the condition device operation flag in step S74. The condition device operation flag is a flag that specifies whether or not a big hit game is being played. When the flag is ON, it indicates that a big hit game is being played, and when the flag is OFF. Indicates that it is not a big hit game.

When the condition device operation flag is in the OFF state, the main control CPU 100 branches the process in step S75 in order to perform a process according to the process state indicating the behavior of the special symbol.
That is, if the process proceeds to step S75 because it is neither a small hit game nor a big hit game, the special symbol is placed under a variable state. Depending on which of the states is, processing relating to the variable display operation of the special symbol corresponding to each is performed.
On the other hand, in the case of a small hit game or a big hit game, the special symbol is not placed in a variable state, so the process proceeds to step S79 without performing the processing related to the special symbol variable display operation.
Here, “Waiting” indicates that the behavior of the special symbol is in a standby state for the next change, and “Waiting” indicates that the behavior of the special symbol is changing (variation display). “Checking” indicates that the special symbol has been changed and is stopped (confirmed) and is being displayed (during the special symbol checking time).

  Specifically, if the special symbol operation status is “standby”, the process proceeds from step S75 to S76, and if the special symbol variation start process is “in variation”, the process proceeds from step S75 to S77. If the special symbol variation processing is “confirming”, the process proceeds from step S75 to S78, and the special symbol confirmation time processing is performed. By these processes, a variation display operation for setting a variation start and a variation stop of the special symbol as a special symbol variation display game is realized.

  In step S79, the main control CPU 100 performs a special symbol display data update process. In this special symbol display data update process, it is determined whether or not the special symbol is fluctuating, and if it is fluctuating, special symbol data that repeats blinking every predetermined time (for example, 0.5 seconds) is created. If the special symbol is not changing, stop display data is created. The special symbol display data created here is output in the LED management process (step S62) of FIG.

Next, the first special figure starting port check process in step S71 described above will be described.
FIG. 11 is a flowchart showing details of the first special figure starting port check process in step S71. The first special figure starting opening check process serves as a winning process executed based on establishment of a predetermined starting condition, and the winning check process for the upper starting opening 41 related to the first special symbol variation display game is performed. Done.

The main control CPU 100 first determines in step S71 whether or not a winning (winning ball) has been detected at the upper start opening 41. When the winning of the upper start opening 41 is detected, it is determined in step S82 whether or not the number of reserved balls of the first special symbol is 4 or more. That is, it is determined whether or not the number of reserved balls of the first special symbol (hereinafter referred to as “first special figure reserved balls”) is less than the maximum number of reserved memories (here, an upper limit of four).
If the winning of the upper start opening 41 is not detected in step S81, the first special figure start opening check process is exited without doing anything.

When the number of first special figure reservation balls is 4 or more, the process proceeds to step S95. On the other hand, if the number of reserved balls is less than 4, the number of reserved balls is incremented by 1 (+1) in step S83.
Next, in step S84, various random numbers used for the first special symbol variation display game based on the first special diagram reservation ball (a jackpot determination random number, a special symbol determination random number, a variation pattern random number 1, and a variation pattern random number) The current value of the random number counter 2) is acquired and stored in the reserved storage area of the main control RAM 102, respectively. In this reserved storage area, the above-mentioned various random values (predetermined game information related to the symbol game) acquired as reserved data, with the predetermined number of memories as the upper limit until the variable display operation of the first special symbol is provided. The starting conditions are established in order (winning order. However, in this embodiment, the number of first special figure holding balls, which is the maximum number of reserved memories, is reserved and stored).
In the reserved storage area of the main control RAM 102, reserved storage areas corresponding to the first special symbol and the second special symbol are provided, and it is possible to store the reserved data corresponding to the number of reserved balls.

The special symbol determination random number, the variation pattern random number 1, and the variation pattern random number 2 are extracted from the corresponding random number counters. Since these random number values are updated randomly in the main process executed between the interrupt process that occurs intermittently and the interrupt process in the count value storage area corresponding to each provided in the main control RAM 102, The value is obtained as it is. On the other hand, the jackpot determination random number value is extracted from a random number generation circuit (a jackpot determination random number counter: not shown) that generates a random number in hardware. The random number generation circuit is a counter that counts the jackpot determination random number. When a detection signal of a game ball is input from the upper start opening sensor 71 or the lower start opening sensor 72, the random number generation circuit latches the count value at this timing, and the latched value is stored in a register built in the random number generation circuit. The count value is stored in the microcomputer. The main control CPU 100 stores this count value as a jackpot determination random number value in a predetermined storage area (a special electric accessory activation determination random number latch buffer) provided separately from the reserved storage area of the main control RAM 102, and is necessary. The random number value for determining the big hit stored from the random number latch buffer for determining the operation of the special electric accessory is read out at a proper timing.
In this embodiment, the jackpot determination random number value at the time of winning is stored in the special electric accessory operation determination random number latch buffer and the corresponding reserved storage area. When a buffer is not provided, it may be stored in the reserved storage area as it is, and the jackpot determination random number value in the corresponding reserved storage area may be read at a necessary timing.

  Next, in step S86, prefetch prohibition data for prohibiting prefetch determination is acquired as winning command data for creating a pending addition command, and “first special figure prefetch prohibition condition” for prohibiting prefetch determination on the first special symbol side. Whether or not is established is determined. The first special figure prefetch prohibition condition is a condition for prohibiting a prefetch notice regarding the first special symbol, that is, a prefetch notice for the first special figure holding ball. In the present embodiment, the prohibition condition is that the gaming state is either the short-time state or the probable variation states A to C, and in the case of any of these gaming states, the pre-reading notice regarding the first special symbol is prohibited (pre-reading) (Preliminary lottery is prohibited).

If the first special figure prefetch prohibition condition is satisfied, the process proceeds to step S95.
If the first special figure prefetch prohibition condition is not established, the process proceeds to step S87, where the first special figure random number determination table is acquired. The jackpot determination random number value stored in () is acquired, and the random number determination process in step S89 is performed.
In the random number determination process, a “winning lottery” relating to a special symbol variation display game (here, the first special symbol variation display game) is performed using a random number for jackpot determination.

Next, in step S90, the main control CPU 100 acquires the first special symbol design table selection table, acquires the special symbol determination random number stored in the main control RAM 102 in step S91, and in step S92 the special stop symbol. Perform data creation processing.
In the special stop symbol data creation process, using the winning lottery result of the random number determination process and the random number value for special symbol determination, the “symbol lottery” relating to the special symbol variation display game (here, the first special symbol variation display game) is performed. Do.

In step S93, the main control CPU 100 performs start port winning random number determination processing. In this starting opening winning random number determination process, based on the data (special symbol determination data and variation pattern selection offset) obtained in the stop symbol data generation process in step S92, the winning command data used for generating the pending addition command (Second byte (EVENT): lower byte) is acquired, and winning command data (lower byte (EVENT)) is created in step S94, and a pending addition command based on the number of held balls (upper byte (MODE)) in step S95 Is transmitted to the effect control unit 51 in step S96.
As a result, the first special figure starting opening check process is exited, and the second special symbol starting opening check process in step S72 of FIG. 10 is performed. Since the second special symbol start opening check process is the same as that of FIG. 11 with respect to the second special symbol, detailed description thereof is omitted.

The main processing, timer interrupt processing, and special symbol management processing of the main control unit 50 (main control CPU 100) have been described so far, but the main control unit 50 sequentially transmits necessary commands to the effect control unit 51.
As examples of commands, FIG. 12A shows a part of a variation pattern command and a winning command for winning a lottery in a special symbol variation display game, and FIG. 12B shows a part of a symbol designation command.
The variation pattern command and the winning command are configured such that the variation pattern type is defined by the upper byte and the lower byte, and the upper byte is different depending on the deviation / hit.
The symbol designating command has a configuration in which the first and second special symbols are indicated in the upper byte and the hit type is specified in the lower byte.

<6. Processing of production control unit>
[6-1: Main processing]

Then, the process of the production | presentation control part 51 is demonstrated. As the processing of the effect control unit 51, mainly processing performed every 16 ms on the main loop (hereinafter also referred to as “16 ms processing”) and interrupt processing performed every 1 ms (hereinafter referred to as “1 ms timer interrupt processing”). Say).
First, main processing including 16 ms processing will be described here.
FIG. 13 shows the main process of the effect control unit 51. The production control unit 51 (production control CPU 200) starts the main process of FIG. 13 when the power is turned on to the gaming machine main body.
In this main process, the effect control CPU 200 first performs a necessary initial setting process before starting the game operation in step S101. For example, as an initial setting process, command reception interrupt setting, movable object starting point return processing, CTC initial setting, timer interrupt permission, initial setting of CPU internal register values including each part of the microcomputer, and the like are performed.

When the initial setting process in step S101 is completed, the processes in steps S102 to S119 are repeatedly performed as the normal operation process.
In other words, in this example, the effect control CPU 200 performs the ID check in step S102 and the random number update in step S119 every loop, and performs the processing of steps S105 to S118 (16 ms processing) every 16 ms.

In the ID check in step S102, the effect control CPU 200 confirms the ID of itself or each connected part set on the system. If an ID abnormality is detected for some reason, system stop processing is performed as step S103.
In normal times when there is no problem with the ID, the effect control CPU 200 performs the processing of step S104 and subsequent steps. That is, the effect control CPU 200 determines whether or not the value of the interrupt counter for determining whether to execute the 16 ms process is greater than “15”. This interrupt counter is a counter that is incremented in step S207 of the 1 ms timer interrupt process of FIG. Therefore, when the value of the interrupt counter is larger than “15”, it means that the processing timing is 16 ms.

When the value of the interrupt counter is “15” or less, the effect control CPU 200 proceeds from step S104 to S119, performs an effect soft random number update process, finishes one main process, and then repeats the process from step S102. I do.
On the other hand, if the value of the interrupt counter is equal to or greater than “16”, the effect control CPU 200 executes the processes of steps S105 to S118, and then updates the effect soft random number in step S119 to perform one main process. The process from step S102 is performed again.

Thus, every 16 ms counted by the interrupt counter, the effect control CPU 200 performs the 16 ms processing from step S105.
In that case, first, in step S105, the interrupt counter is reset to zero. Thereafter, the counting up to the next 16 ms processing is performed again.
In step S106, the effect control CPU 200 performs error processing. The error processing includes error processing timer processing during a RAM clear error, an accessory error, a right-handed error, etc., scenario registration processing for error notification when various errors occur, error scenario after error notification Clearing processing will be performed.
Next, in step S107, the effect control CPU 200 performs a demo process. In this demonstration processing, processing such as playback sound control, demonstration movie execution, scenario registration of an accessory origin correction, and its command set are performed. In the customer waiting state or the like, the demonstration movie display is executed by executing the scenario set in the demonstration process.

In step S108, the effect control CPU 200 performs command analysis processing. In this command analysis process, the effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer, and reads out this command if the effect control command is stored. . Then, an effect control process corresponding to the read effect control command is performed. Details will be described later with reference to FIGS.
In step S109, the effect control CPU 200 performs input detection processing. In this input detection process, an input is detected by operating the operation elements (the effect buttons 11 and 12 and the cross key 13) of the operation unit 60. When an input is detected, a process corresponding to the operation is performed.
In step S110, effect control CPU200 performs a scenario update process. In this process, the main scenario and subscenario are updated. At that time, registration of lighting patterns of the lamp units 64 and 65, registration of sound to be reproduced, registration of motor operation for driving the movable body accessory, and the like are also performed. Details will be described later with reference to FIGS.
In step S111, the effect control CPU 200 performs sound reproduction processing. The effect control CPU 200 outputs data such as a phrase number and volume to the sound source IC based on sound data registered as a sound channel in the work based on the scenario data. Thereby, the reproduction output of the sound effect, music / sound, etc. from the speaker 25 is performed.
In step S112, the effect control CPU 200 performs an accessory error process. Here, a position error determination such as a return of the origin of the movable object is not performed.

In step S113, the effect control CPU 200 initializes the LED driver 90. The initialization of the LED driver 90 is a process of outputting a default value to a register that is not used in the LED driver 90. For example, initialization is performed for each LED driver 90 of the frame driver unit 61 and each LED driver 90 of the panel driver unit 62.
In step S113, the effect control CPU 200 updates the LED drive data. Here, processing for creating LED drive data is performed based on the lamp data registered as a lamp channel in the work based on the scenario data. Details will be described later with reference to FIG.
In step S114, the effect control CPU 200 performs LED output processing. That is, the effect control CPU 200 sends light emission drive data (LED drive data) for the LED driver 90 from the serial data output channels ch1 and ch2 to each LED driver 90 of the frame driver unit 61 and each LED driver 90 of the panel driver unit 62. ) Is output. Details will be described later with reference to FIG.

In step S116, the effect control CPU 200 performs checksum calculation and storage for the work area of the effect control RAM 202, and in step S117, saves backup data.
In step S118, the scenario update counter is reset to zero. The scenario update counter is a counter that is incremented by a 1 ms timer interrupt process described later.
The 16 ms processing as described above is performed every 16 ms in the main loop processing of FIG.

[6-2: 1ms timer interrupt processing]

Next, the 1 ms timer interrupt process will be described with reference to FIG. The effect control CPU 200 executes the 1 ms timer interrupt process of FIG. 14 in response to an interrupt request generated every 1 ms by the time count.
In this 1 ms timer interrupt process, first, in step S201, it is determined whether or not a checksum is being calculated according to a test command from the main control CPU 100. If the checksum is not being calculated, the effect control CPU 200 proceeds to the input process in step S202.

The input process in step S202 is a process for every 1 ms for performing input detection by operating the operator together with the input detection process in step S109 of FIG. For example, in this input process, when an edge is detected in the signal waveform of the operation detection signal of the operation element, the input counter is reset, and thereafter, the input counter is counted up during a period in which no edge occurs. In the 1 ms timer interrupt process, input information (H or L of the input signal waveform) is detected, and the input counter is reset or incremented depending on the presence or absence of an edge. In step S109 in the main loop process (16 ms process), when the input counter value is 16 or more and the input information has changed from the previous time, the input change is recognized.
Such input processing (S202) and input detection processing (S109) can prevent erroneous input recognition due to noise chattering. In addition, since an input counter is used and, in this embodiment, for example, a 16-bit counter can be used to count up to 65535 ms (about 65 seconds), so-called long press can be detected.

In step S203, the effect control CPU 200 performs a motor operation update process. In this case, the effect control CPU 200 performs a process of creating motor drive data based on the motor data registered as a motor channel in the work (motor data registration information described in FIG. 22C) based on the scenario data. This is motor drive data output to the motor driver 90M of the motor driver unit 70 in order to drive and control the movable body accessory motor 65. In the present embodiment, the LED drive data is updated every 16 ms in step S114, while the motor drive data is updated every 1 ms.
In step S204, the effect control CPU 200 outputs motor drive data. In this step S204, serial data as drive data for the stepping motor 121 as the movable body accessory motor 65 is output to the motor driver 90M of the motor driver unit 70.

In step S205, the effect control CPU 200 executes each process according to the value of the interrupt counter. The interrupt counter is reset to zero in step S105 of the 16 ms process described above and incremented in step S207 of the 1 ms timer interrupt process. Therefore, when step S205 is executed in the 1 ms timer interrupt process, the value of the interrupt counter is 0-15.
According to the interrupt counter values 0 to 15, the process of step S205 is defined as case 0 to case 15. For example, in this embodiment, in case 0, a WDT (watchdog timer) clear signal is turned ON. In cases 1 to 3, the motor driver 90M is initialized. In case 8, the WDT clear signal is turned OFF.

In step S206, the effect control CPU 200 outputs an effect control command to the liquid crystal control board 52. For example, one command (2 bytes) is transmitted in one 1 ms timer interrupt process. That is, a 2-byte effect control command as a mode and an event is transmitted.
Thereafter, the effect control CPU 200 increments the interrupt counter in step S207, and increments the scenario update counter in step S208. If the value of the scenario update counter is less than 100, the 1 ms timer interrupt process ends.
Since the scenario update counter is reset to zero in step S118 of the 16 ms process as described above, the value of the scenario update counter does not normally exceed 100. The value of 100 or more is a case where the 16 ms process is not executed due to a calculation abnormality, a process response abnormality or the like, or the progress of a certain process in the 16 ms process is stopped. In such a case, an infinite loop is entered, and the time-up process is performed by WDT.

When it is determined that the checksum is being calculated in step S201 when entering the 1 ms timer interrupt process, the effect control CPU 200 advances the process to step S210 and clears the WDT. In step S211, an effect control command is transmitted to the liquid crystal control board 52. In step S212, the interrupt counter is incremented and the 1 ms timer interrupt process is completed.

[6-3: Command analysis processing]

Next, the command analysis process performed in step S108 of FIG. 8 as a 16 ms process will be described with reference to FIGS. The effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer as the command analysis processing in step S108. If the effect control command is stored, this command is stored. Is read. As this specific process, the processes of steps S301 to S308 in FIG. 15 are performed.

In the effect control unit 51, a command reception buffer that captures the effect control command transmitted from the main control unit 50 is prepared in the effect control RAM 202, for example. In step S301 of FIG. 15, the effect control CPU 200 first checks the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address.
The light pointer is updated in response to the command reception, and the received effect control command is stored in the address indicated by the light pointer accordingly. The read pointer is updated when reading from the command reception buffer is performed (step S302). Therefore, if the read pointer is not the write pointer, the effect control command that has not been read is stored in the command reception buffer. Therefore, if the read pointer is not the write pointer, the process goes to step S302, and the effect control CPU 200 loads 1-byte command data from the address indicated by the read pointer in the command reception buffer. In this case, the read pointer is incremented for the next reading (loading).

As described above, one presentation control command is formed of two bytes, one byte as a mode and one byte as an event. In step S303, the effect control CPU 200 confirms whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit 7 out of 8 bits (Bit 0 to Bit 7).
If it is the mode, the process proceeds to step S304 as a process for receiving the upper data of the command, and the read command data is saved in the register “command HI byte”. Also, the “command LO byte” register is cleared. Then, the process returns to step S301.
Even if the read pointer is not equal to the write pointer, the effect control command that has not yet been read is stored in the command reception buffer. Therefore, the process proceeds to step S302, and the effect control CPU 200 uses the read pointer in the command reception buffer. Load 1 byte of command data from the indicated address. In addition, the read pointer is incremented.
If the read command is an event, the process proceeds from step S303 to S305 as processing for receiving lower-order data of the command, and the read command data is saved in the register “command LO byte”.

The command data of the mode and the event is saved in the registers “command HI byte” and “command LO byte”, so that the effect control CPU 200 takes in one command.
Therefore, the effect control CPU 200 performs processing according to the fetched command in step S306. A specific example will be described later with reference to FIGS.

  The read pointer = write pointer is when the effect control command that has not yet been captured by the effect control CPU 200 does not exist in the command reception buffer. Therefore, since new acquisition is unnecessary, the process proceeds to step S307. In this case, it is confirmed whether 100 ms has elapsed while waiting for a symbol command. If it is not such a situation, the command analysis processing of FIG. 15 is finished. On the other hand, if 100 ms has elapsed while waiting for a symbol command, symbol fluctuation processing due to a missing command is performed in step S308.

An example of the command response processing in step S306 will be described with reference to FIGS.
FIG. 16A shows basic processing as command response processing. In response to the reception of the 2-byte effect control command, the effect control CPU 200 first confirms in step S321 in FIG. 16A whether or not it is currently in the test mode. If it is in the test mode, all the production scenarios are cleared, the sound output is stopped, and the LEDs in the lamp units 63 and 64 are turned off in step S322. In step S323, the test mode ends.
These processes are not performed unless in the test mode.
Then, the effect control CPU 200 performs a process for the acquired effect control command as step S330.

  As the effect control command, for example, a special symbol variation pattern designation command, a special symbol designation command, a holding ball subtraction command, a holding ball addition command, an error display designation command, a jackpot start designation command, etc. are variously set. In step S330, the effect control CPU 200 performs a process specified by the program in response to the received command. Here, specific processing is illustrated by giving seven effect control commands to FIGS. 16B to 16E and FIGS. 17A to 17C.

FIG. 16B shows a process S330a when a variation pattern command is fetched as the command process in step S330.
In this case, the effect control CPU 200 performs a process of setting a symbol command waiting state in step S331. This is because the effect control CPU 200 controls the variation display of the symbols by sequentially receiving the variation pattern command and the symbol commands.

FIG. 16C shows a process S330b in the case where a symbol designation command is fetched as the command process in step S330.
In this case, the effect control CPU 200 first confirms whether or not the variation pattern command has been received in step S332. If it has not been received, the process ends.
When the symbol designating command is received, if the variation pattern command has already been received, the process proceeds to step S333, and first, scenario registration for the operation of correcting the accessory origin is performed. In step S334, the symbol variation flag is set. The symbol variation flag is provided corresponding to each of the first special symbol, the second special symbol, and the normal symbol, and each flag represents a variation state. For example, a first special symbol variation flag FZ1, a second special symbol variation flag FZ2, and a normal symbol variation flag FZ3 each having two bits are prepared, and each of them indicates whether it is varying, stopped (winning), or stopped (disconnected). Here, as the fluctuation starts, the corresponding symbol fluctuation flag (any one of FZ1, FZ2, and FZ3) is set to a value indicating “in fluctuation”.
In the case of winning, the symbol variation flag is set to a value indicating “stopped (winning)” for a predetermined time at the end of symbol variation, and then a value indicating “stopped (out)” until symbol variation is started. Set to
In step S335, the effect control CPU 200 performs variation start processing. Thereafter, the change pattern command is deleted in step S336 in response to the start of change.

FIG. 16D shows a process S330c when a power-on command is captured as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S337. For example, the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the checksum storage area are cleared.
Then, in step S338, an error release command is transmitted, in step S339 the accessory error information is cleared, in step S340, the accessory operation is stopped, in step S341, a power-on scenario is registered, and in step S342, the power is transmitted to the liquid crystal control board 52. Perform a set of commands sequentially.

FIG. 16E shows a process S330d when a RAM clear command is fetched as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S343. For example, the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the checksum storage area are cleared.
In step S344, an error cancel command is transmitted, and in step S345, a RAM clear error set and an error notification timer are set. In step S346, information related to the lottery process in the effect control RAM 202 is cleared. In step S347, information related to the scenario is cleared. In step S348, an initial power-on display (RAM clear) command to be transmitted to the liquid crystal control board 52 is set.

FIG. 17A shows a process S330e in the case where a hold addition command is fetched as the command process in step S330.
In this case, the effect control CPU 200, in step S350, corresponds to either the first special symbol variation display game or the second special symbol variation display game, the holding number register (the first reservation number set in the effect control RAM 202 or The value of the hold number in the register area as the second hold number) is read and added. In step S351, a command for displaying the hold number is set for the liquid crystal control board 52, and in step S352, the updated value as the first hold number or the second hold number is set.

FIG. 17B shows a process S330f when the hold addition command is fetched as the command process in step S330.
In this case, the effect control CPU 200, in step S360, corresponds to either the first special symbol variation display game or the second special symbol variation display game, the holding number register (the first reservation number set in the effect control RAM 202 or The value of the number of reservations in the register area as the second reservation number) is read and subtracted. In step S361, a command for displaying the hold number is set on the liquid crystal control board 52, and in step S362, the updated value as the first hold number or the second hold number is set.

FIG. 17C shows a process S330g when a state notification command is fetched as the command process in step S330.
In this case, the effect control CPU 200 sets a gaming state notification flag in step S371. As the gaming state notification flag, for example, flags FJ1, FJ2, and FJ3 indicating “big hit”, “probably changing”, and “short in time” are prepared. In step S371, the effect control CPU 200 sets any corresponding gaming state notification flag in accordance with the gaming state indicated by the state notification command.

[6-4: Scenario registration / deletion processing]

Next, scenario registration / deletion processing will be described. The scenario is data defining various operations to be executed such as production control and error processing. The scenario data to be executed is registered in the work area of the effect control RAM 202 as scenario registration information. The scenario registration information shown in FIG. 22A will be described later. As scenario registration information, 64 scenario channels from 0 to 63 are prepared. Scenarios registered in these 64 scenario channels can be executed simultaneously. Hereinafter, the scenario channel is indicated by “sCH”.
The scenario registration process is a process for registering a scenario having a scenario number requested to be registered in an arbitrary scenario channel in the scenario registration information. In principle, any scenario channel of sCH0 to sCH63 may be used.

  Scenario registration to be described below is called and executed when necessary, for example, in the process of error processing in step S106, demo processing in step S107, command analysis processing in step S108, and the like. For example, step S333 in FIG. 16C and step S341 in FIG. 16D described above are an example of the case where scenario registration is executed.

As the processing in FIG. 18, the effect control CPU 200 performs processing for registering the scenario number corresponding to the scenario specified on the command or program and the value of the standby time (delay) in the work (scenario registration information).
In step S401, the effect control CPU 200 first checks whether or not the scenario number to be registered this time is normal. If the scenario number is not possible, the process ends without doing anything.

  If the scenario number is appropriate, effect control CPU 200 sets variable B to zero in step S402. The variable B is a variable used for sequentially searching for an empty channel among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether it is an empty channel).

In step S403, the effect control CPU 200 confirms whether or not the “additional pointer” + B scenario channel is empty. The additional pointer is a pointer set in step S407 described later when scenario registration is performed. At the time when the processing of FIG. 18 is started, the value of the additional pointer is a value indicating the scenario channel next to the scenario channel registered last time. Note that the initial value of the additional pointer (the value when the processing of FIG. 18 is performed for the first time from the initial state) is zero.
If the “addition pointer” + B scenario channel is not empty, the effect control CPU 200 increments the variable B in step S404.
If B <64 is not satisfied in step S405, the processing in FIG. This is a case where all scenario channels have been searched but scenario registration is impossible because there are no free channels.
At a time point when all scenario channels have not been searched (confirmation of whether or not they are free channels), B <64 in step S405. In that case, the confirmation process of step S406 is performed, and if the value of “addition pointer” + B is not equal to or greater than the value “64” exceeding the maximum value of the scenario channel sCH, the process returns to step S403.
If the value of “addition pointer” + B is “64” or more, correction processing for the value of the addition pointer is performed in step S407. Specifically, when the value of “addition pointer” + B becomes “64”, a process of subtracting “64” from the value of the addition pointer is performed. Then, the process returns to step S403.

According to the processing in steps S403 to S407, it is sequentially confirmed from the scenario channel next to the previously registered scenario channel whether or not the scenario channel is empty.
That is, the scenario channel sCH that is confirmed every time step S403 is performed sequentially advances one by one due to the increment of the variable B in step S404.
Since variable B is zero-reset in step S402 and incremented in step S404, if B <64 is not satisfied in step S405 (that is, if variable B reaches 64), step S403 has already been performed. This process is performed 64 times. This is a case where all the scenario channels sCH0 to sCH63 have been examined and it is determined that there is no free space. Therefore, the process of FIG.

Further, since the value of the “addition pointer” is a value indicating the next scenario channel of the scenario channel registered last time, the “addition pointer” + B even when B <64 when all the scenario channels are not yet confirmed. (That is, the number of the scenario channel sCH to be checked next) may be “64” or more. Specifically, the value of “addition pointer” + B is 63 at the time of immediately preceding step S403, and after confirming the scenario channel sCH63, the variable B is incremented in step S404. In this state, the scenario channel sCH64 that does not exist next is designated.
Therefore, this point is confirmed in step S406, and if the value of “addition pointer” + B is “64”, in step S407, correction of the addition pointer is performed to return the scenario channel to be confirmed next to “sCH0”. Do. That is, the value of “addition pointer” + B is set to “0” by setting the value of the addition pointer to −64. Thus, in the next step S403, it is confirmed whether or not the scenario channel sCH0 is empty.

If an empty scenario channel is found in the process of step S403 at a certain time, the presentation control CPU 200 proceeds to step S408, and sets a scenario number and a waiting time (delay) in the empty scenario channel. In addition, the data necessary for other scenario management is cleared to zero.
In step S409, the additional pointer is updated to the value of the registered scenario channel + 1. That is, the value of the scenario channel next to the scenario channel registered this time is stored as an additional pointer so that it can be used for the next registration process. In this embodiment, since the scenario channel is 64 channels sCH0 to sCH63, the maximum value of the additional pointer is 63.

  According to the processing of FIG. 18, at the time of scenario registration, an empty channel is searched from the scenario channel next to the scenario channel that was registered last time. The initial value of the additional pointer is “0”, and is subsequently updated in step S407 according to the registration. In many cases, according to this process, scenario registration is performed using the scenario channel sCH0 in order. . When the scenario is registered, the availability is confirmed from the scenario channel next to the previous registered channel. Therefore, in most cases, an empty channel can be found quickly, and the scenario registration process can be executed efficiently. As a result, the processing burden on the effect control CPU 200 is reduced.

  As a modification of the process, the value of the additional pointer updated in step S407 may be set as the number of the scenario channel that has been registered, and 1 may be substituted for variable B in step S402. In this case, however, it is determined in step S405 whether B ≦ 65.

Next, scenario deletion processing will be described. This is a process for deleting a scenario registered in a certain scenario channel of the work.
FIG. 19A shows processing of the effect control CPU 200 when a certain scenario is deleted from the scenario registration information.
The effect control CPU 200 starts the process of FIG. 19A based on the value of a scenario number to be deleted (a main scenario number (mcNo) described later) designated on the command or program gram. First, in step S421, the effect control CPU 200 confirms whether or not the scenario number related to the deletion request is normal. If the scenario number is not possible, the process ends without being deleted.

  If the scenario number is appropriate, effect control CPU 200 sets variable B to zero in step S422. The variable B in this case is a variable used for searching for a channel in which the scenario to be deleted is registered among the scenario channels sCH0 to sCH63. Further, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether or not a scenario to be deleted is registered).

In step S423, the effect control CPU 200 confirms whether or not the scenario registered in the B area, that is, the scenario channel sCH (B) is the scenario number to be deleted. If the scenario registered in the scenario channel sCH (B) is not the scenario number to be deleted, the variable B is incremented in step S424, and it is confirmed in step S425 that B <64, and the process of step S423 is performed. Do.
According to the processing of steps S423 and F424, the scenario to be deleted is searched in order from the scenario channel sCH0 to the scenario channel sCH63.
If the scenario registered in the scenario channel sCH (B) is the scenario number to be deleted in step S423, the process proceeds to step S426, and the scenario registered in the B area, that is, the scenario channel sCH (B) is deleted. Perform the process.
As described above, the process of deleting the scenario with the requested scenario number from the work (scenario registration information) is performed.
If it is determined in step S425 that B <64 is not satisfied, that is, if the variable B reaches 64, all the scenario channels sCH0 to sCH63 have been searched, but the scenario to be deleted has not been registered. Therefore, the process is finished.

FIG. 19B shows processing for deleting a certain range of scenarios. This process is performed when a deletion scenario is specified by a range.
The effect control CPU 200 first sets a variable B to zero in step S431 when a deletion is designated within a range of a certain scenario number on a command or program. The variable B in this case is a variable used to search for a channel in which a scenario corresponding to the deletion target range is registered among the scenario channels sCH0 to sCH63. Further, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether or not a scenario corresponding to the deletion target range is registered).

In step S432, the effect control CPU 200 confirms whether or not the scenario registered in the B area, that is, the scenario channel sCH (B), is a scenario number within the range to be deleted. If the scenario registered in the scenario channel sCH (B) is a scenario number within the range to be deleted, the scenario registered in the scenario channel sCH (B) is deleted in step S433. Then, the process proceeds to step S434.
If the scenario registered in the scenario channel sCH (B) is not a scenario number within the range targeted for deletion, the process proceeds to step S434 without performing step S433.
The effect control CPU 200 increments the variable B in step S434, confirms that B <64 in step S435, and returns to step S432. If the variable B has reached 64, the processing has been completed for all scenario channels sCH0 to sCH63, and the scenario range deletion processing is completed.
As described above, one or more scenarios in the scenario number range are deleted from the work (scenario registration information).

FIG. 19C shows processing for deleting all registered scenarios. For example, it is a process called when a scenario is unavoidably deleted due to circumstances on the system. Do not delete scenarios that are targeted for protection.
When it is requested to delete all scenarios, the effect control CPU 200 first sets the variable B to zero in step S441. The variable B in this case is a variable used for confirming the scenario channel in which the scenario to be protected is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been confirmed (confirmation of whether or not a scenario to be protected is registered).

In step S442, the effect control CPU 200 confirms whether or not the scenario registered in the B region, that is, the scenario channel sCH (B), is a scenario to be protected. If it is a scenario to be protected, it is not deleted. On the other hand, if it is not a scenario to be protected, the scenario registered in the scenario channel sCH (B) is deleted in step S443.
In step S444, the variable B is incremented. If B <64 in step S445, the process returns to step S442. If the variable B has reached 64, the processing has been completed for all the scenario channels sCH0 to sCH63, and thus the scenario all deletion processing ends.
As described above, all scenarios other than the scenario to be protected are deleted from the scenario registered as scenario registration information in the work.

[6-5: Scenario update process]

Next, the scenario update process performed in step S110 of the 16ms process of the main process will be described. In the scenario update process, the main scenario and the sub-scenario are updated as described with reference to FIGS.

First, the structure of scenario registration information will be described with reference to FIGS. FIG. 22A shows the structure of scenario registration information as a main scenario and a sub-scenario. This scenario registration information is set using the work area of the effect control RAM 202.
In the present embodiment, as described above, the scenario registration information includes 64 channels of scenario channels sCH0 to sCH63. Scenarios registered in each scenario channel sCH can be executed simultaneously.

  As shown in the figure, information that can be registered in each scenario channel sCH includes sub-scenario timer (scTm) and previous time (scPrevTm) used in the sub-scenario update process, and sub-scenario execution line (sound / motor sub-scenario table execution line) scIx), sub scenario execution line lmp (lmpIx) indicating the execution line of the ramp sub scenario table, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating the execution line of the main scenario table, main There are a scenario number (mcNo), a main scenario option (mcOpt) that is optional data that can be added to the main scenario, a user option (userFn), a waiting time (delay), and a checksum (checkSum).

When starting production of sound output by the speaker unit 59, light emission by the lamp units 63 and 64, and driving of the movable body accessory by the movable body accessory motor 65, the standby time (delay) and the main scenario number (scNo) are set as scenarios. It registers in an empty scenario channel among channels sCH0 to sCH63.
The waiting time (delay) indicates the time from registration to the scenario channel sCH until the scenario is started. The waiting time (delay) is decremented by 1 every 16 ms processing. When the waiting time (delay) is 0, processing corresponding to the registered data is executed.

FIG. 24 shows examples of scenario numbers 1, 2, and 3 as a part of the main scenario table. As the scenario of each scenario number, the main scenario timer (msTm) value is described as time data in each line (row) of the scenario, and the sub-scenario number (scNo) and option (OPT) can be described. . That is, in the main scenario table, a sub-scenario (and optional in some cases) to be executed is designated as the time by the main scenario timer (msTm). In the last line of the scenario, a scenario data end code D_SEEND or a scenario data loop code D_SELOP is described.
Since the value of the main scenario timer (msTm) is incremented by 1 in the scenario update process performed in the 16 ms process from the start of the main scenario, “1” indicates 16 ms. The scenario table of each scenario number advances to the next line when the time of the main scenario timer (msTm) in a certain line has elapsed. The time data of each line indicates the timing when the line ends.
For example, in the case of scenario number 2, the operation of sub-scenario number 2 is specified as a time of 1500 × 16 ms, the operation of sub-scenario number 20 is specified as the next time of 500 × 16 ms, and the operation is performed as the next time of 2000 × 16 ms. The operation of scenario number 21 is designated. The next line is the scenario data end code D_SEEND. In the case of the scenario data end code D_SEEND, this scenario is deleted from the scenario registration information (work) (see step S617 in FIG. 20 described later).

Next, the structure of the lamp data registration information will be described with reference to FIG. 22B. As the lamp data registration information, a scenario selected from the lamp sub-scenario table, that is, information indicating a rendering operation (lighting pattern) by the lamp units 63 and 64 is registered. This lamp data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the ramp data registration information has 16 channels of ramp channels dwCH0 to dwCH15. Priorities are set for each of the ramp channels dwCH0 to dwCH15, and the priority increases in order from the ramp channels dwCH0 to dwCH15. Therefore, the scenario (lamp sub-scenario) registered in the ramp channel dwCH15 is executed with the highest priority. For example, if a scenario is registered in the ramp channels dwCH3 and dwCH10, the scenario registered in the ramp channel dwCH10 is preferentially executed.
The ramp channel dwCH0 is mainly used for a lamp effect associated with BGM (Back Ground Music), the lamp channel dwCH15 is used for an error-related lamp effect, and the lamp channels dwCH1 to dwCH14 are used for a normal effect.

  As shown in the figure, information that can be registered in each lamp channel dwCH includes a registered lighting number (lmpNew) indicating the number of the registered lighting pattern, an execution lighting number (lmpNo) indicating the number of the lighting pattern to be executed, and a lamp sub-scenario. There are an offset indicating an execution line (offset), an execution time (time), and a checksum (checkSum).

  FIG. 25A shows an example of lamp sub-scenario numbers 1, 2, and 3 as a part of the lamp sub-scenario table. For each number of lamp sub-scenarios, time data (time) values are described in each line (row) of the scenario, and lamp channels and lamp numbers indicating various lighting patterns are described. In the last line, a lamp scenario data end code D_LSEND is described.

In this ramp sub-scenario table, the time data (time) of each line indicates the time at which the line is started after the sub-scenario is started.
When the main scenario timer (msTm) and the time data in the table are compared every 16 ms and they match, the lamp number of that line is registered in the lamp data registration information of FIG. 22B. The registered ramp channel dwCH is the channel indicated in the line.
For example, it is assumed that the scenario number 2 shown in FIG. 24 is registered and the sub-scenario number 2 is referenced in the certain scenario channel sCH described above. In the lamp sub-scenario number 2 shown in FIG. 25A, the lamp channel 5 (dwCH5) and the lamp number 5 are described as time data (time) = 0 on the first line. In this case, when the main scenario timer (msTm) = 0, the information on the first line is first registered in the lamp channel dwCH5 of the lamp data registration information in FIG. 22B as the registered lighting number (lmpNew) = 5. The value of the sub-scenario execution line lmp (lmpIx) in the scenario registration information is updated to the value of the next line (second line). This is a registration for performing the lighting pattern operation of the lighting number 5 with a relatively low priority of the lamp channel dwCH5.
For the second line, the same processing is performed when it becomes 500 × 16 ms. That is, the registered lighting number (lmpNew) = 6 (that is, the lighting pattern 6 lighting instruction) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) has the same value for two consecutive lines, the processing for each line is started simultaneously.
In the LED drive data update process to be described later, LED drive data is created based on the lamp data registration information updated in this way.

Next, the structure of the motor data registration information will be described with reference to FIG. 22C. As motor data registration information, information indicating a scenario selected from the sound / motor sub-scenario table is registered. This motor data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the motor data registration information is assumed to have eight channels of motor channels mCH0 to mCH7.
Information that can be registered in each motor channel mCH includes execution operation number (no), registration operation number (noNew), operation count (lcnt), excitation counter (tcnt), execution step (step), operation line as shown in the figure. (Offset), parent (migration source) / child (migration destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) ), Current input information (currentSw), software switch information (softSw), and software count (softCnt).

FIG. 23 shows sound data registration information. As the sound data registration information, information indicating a scenario selected from the sound / motor sub-scenario table is registered. This sound data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the sound data registration information has 16 channels of sound channels aCH0 to aCH15.
Information that can be registered in each sound channel aCH includes volume transition amount (frzVq), volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0), stereo (frzSt) as shown in the figure. ), Loop (frzLp), phrase number hi (frzHi), and phrase number low (frzLo).

FIG. 25B shows an example of sound / motor sub-scenario numbers 1 and 2 as a part of the sound / motor sub-scenario table. As the sound / motor sub-scenario of each number, the time data (time) value (ms) is described in each line (row) of the scenario, and BGM, warning sound, error sound, sound control, motor, solenoid / User option information is described. In the last line, a scenario data end code D_SEEND is described.
Regarding this sound / motor sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (initially 0), the time data (time) value of this sound / motor sub-scenario table is set to the sub-scenario timer ( scTm). The time data (time) of each line indicates the timing when the line ends. The sub-scenario timer (scTm) describes the absolute time. Therefore, the time data value to be set is a value of (time data of the relevant line) − (time data of the previous line).
The BGM data of the line is composed of information registered in the sound data registration information such as the BGM phrase number and volume value, and is set in the sound channel aCH0 (aCH1 in the case of stereo) in the sound data registration information. .
The notice sound data of the line is composed of information registered in the sound data registration information such as the phrase number and volume value of the notice sound, and is set in the space where the sound channels aCH2 to aCH14 are vacant.
The error sound data of the line includes information registered in sound data registration information such as the error sound phrase number and volume value, and is set in the sound channel aCH15.
The sound control data is channel information in the lower 6 bytes and control information in the upper 2 bytes.
The motor data is configured to indicate the motor operation pattern number in one byte per motor. An operation pattern number is set in the motor channel corresponding to the motor number.

In the motor operation update process described as step S203 in FIG. 14, motor drive data is created based on the motor data registration information updated in the scenario update process in FIGS.
In the sound reproduction process in step S111 in FIG. 13, reproduction output is performed based on the sound data registration information updated in the scenario update process in FIGS.

Scenario update processing using each of the above information will be described with reference to FIGS.
In the scenario update process of FIG. 20 executed as step S110 of the 16 ms process of FIG. 13, the effect control CPU 200 performs the processes of steps S601 to S616 for each of the scenario channels sCH0 to sCH63 as the loop process LP1. The scenario channel to be processed each time in the loop processing will be described as “sCHn”.

  The effect control CPU 200 confirms the standby time (delay) of the scenario channel sCHn in step S601. If the standby time (delay) = 0 is not satisfied, the value of the standby time (delay) is decremented by −1 (decrement) in step S602. In step S615, a checksum of data related to the scenario channel sCHn is calculated and stored. In step S616, the scenario channel sCHn related data is backed up. This completes one process for the scenario channel sCHn.

On the other hand, if it is confirmed in step S601 that the standby time (delay) = 0, the effect control CPU 200 proceeds to step S603 and executes the main scenario number (mcNo) registered in the scenario channel sCHn and the main scenario execution. The address of the main scenario table corresponding to the line (mcIx) is specified.
In step S604, it is confirmed whether or not the execution line of a certain main scenario number in the main scenario table indicated by the identified address is the last line in which the end code D_SEEND (see FIG. 24) is described.
If it is the last line in which the end code is described, the processing to be executed in the scenario registered in the scenario channel sCHn has been completed, so in step S617, the scenario registered in the scenario channel sCHn. Is deleted from the scenario registration information (work).
Note that the scenario registration deletion in this case is a normal deletion corresponding to the end of the scenario. It is added that the scenario deletion described above with reference to FIG. 19 is a process for deleting, for example, an unfinished scenario from the scenario registration information (work) other than the normal deletion.

If the line in the main scenario table is not an end code in step S604, the effect control CPU 200 proceeds to step S605, and first sets the option (OPT) of the line in the main scenario option (mcOpt) of the scenario channel sCHn. To do. Next, in step S606, it is confirmed whether or not the scenario number is 0. If it is not 0, 0 is assigned to the user option (userFn) in step S607.
In step S608, the sub-scenario specified by the scenario channel sCHn is updated. The sub-scenario update will be described later with reference to FIG.

In step S609, the effect control CPU 200 increments the main scenario timer (msTm) by +1. In step S610, the value of the main scenario timer (msTm) is compared with the time data of the corresponding line in the main scenario table (see FIG. 24: described in msTm). As described above, the time data of each line in the main scenario table defines the end timing of the line. Therefore, if the value of the main scenario timer (msTm) is equal to or greater than the time data described in the relevant line of the main scenario table, the processing for that line ends and the next line is targeted. In this case, the process proceeds from step S610 to S611, and the main scenario execution line (mcIx) of the scenario channel sCHn is incremented by 1. That is, next time, the next line is targeted.
In that case, it is checked in step S612 whether or not the next line is designated as a loop. In the main scenario table of FIG. 24, scenario number 1 shows an example in which the final line is the scenario data loop code D_SELOP. If the loop is specified in this way, the main scenario execution line ( Set loop line to mcIx).

In step S614, the effect control CPU 200 performs a clear process according to the end of one line. That is, main scenario timer (msTm), sub-scenario timer (scTm), previous time (scPrevTm), sub-scenario execution line (scIx), sub-scenario execution line lmp (lmpIx), main scenario option (mcOpt), user option (userFn) Clear the delay time.
Then, the checksum process in step S615 and the backup process in step S616 are performed, and one process for the scenario channel sCHn is completed.
As the scenario update process, the above process is executed for each of the scenario channels sCH0 to sCH63 as the loop process LP1.

The sub-scenario update process performed in step S608 is shown in detail in FIG. 21A.
Based on the main scenario timer (msTm), the scenario channel sCHn, and the sub-scenario number (scNo) described in the main scenario table, the sub-scenario update process of FIG. 21A is performed.

First, in step S621, the effect control CPU 200 confirms whether or not the scenario channel sCHn indicates any of 0 to 63, that is, whether or not it is an appropriate value. If the scenario channel sCHn is 64 or more, the update process is impossible and the process of FIG. 21A ends.
If the scenario channel sCHn is an appropriate value, the effect control CPU 200 identifies the address of the lamp sub scenario table (see FIG. 25A) corresponding to the sub scenario number (scNo) and the sub scenario execution line lmp (lmpIx) in step S622. .

In step S623, the effect control CPU 200 first sets 0 to the lamp channel dwCH in order to update the lamp data registration information. That is, first, the lamp channel dwCH0 is designated.
In step S624, the main scenario timer (msTm) and the time data (time) in the lamp sub-scenario table are compared. The time data (time) in the lamp sub-scenario table indicates the time (ms) at which the line (the line indicated by the sub-scenario execution line lmp (lmpIx)) is started. Therefore, if the time of the main scenario timer (actually, the time of msTm × 16 ms) is equal to or greater than the time data (time), the processing for that line is performed. In that case, it is checked in step S625 whether the value of the ramp channel dwCH is normal (within the range of dwCH0 to dwCH15). If it is an abnormal value, the process ends. If it is a normal value, it is checked in step S626 if the current line is a line in which the lamp scenario data end code D_LSEND is described.

If it is not the line in which the lamp scenario data end code D_LSEND is described, the effect control CPU 200 acquires the lamp channel dwCH and the lamp stag wave described in the line in step S627, and in step S628, acquires the lamp channel dwCH. Register the lighting pattern number.
The lighting pattern number registration process is shown in FIG. 21B. In this case, first, in step S651, the effect control CPU 200 determines whether or not the value of the lamp channel dwCH described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If it is a normal value, it is determined in step S652 whether or not the ramp number described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If both the lamp channel dwCH and the lamp number are normal values, the registered lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH in the lamp data registration information of the work in step S653. To do. That is, the lamp number acquired from the relevant line in the lamp sub-scenario table is set in the registered lighting number (lmpNew), and “0” is set in the execution lighting number (lmpNo).
21B is performed in step S628, the effect control CPU 200 increments the value of the sub-scenario execution line lmp (lmpIx) by 1 in step S629, increments the value of the ramp channel dwCH by 1 in step S630, and returns to step S624. .

When the time of the main scenario timer does not reach the time data (time) of the line indicated by the sub-scenario execution line lmp (lmpIx) in step S624, and the lamp scenario data end code D_LSEND is confirmed in step S626 The process of the effect control CPU 200 proceeds to step S631.
In step S631, it is confirmed whether or not the sub-scenario timer (scTm) is zero. If not 0, the process proceeds to step S639 without registering sound and motor. In this case, the value of the sub-scenario timer (scTm) is decremented in step S640, and the processing of FIG. 21A is completed.

If the sub-scenario timer (scTm) = 0 at the time of step S631, the effect control CPU 200 advances the process to step S632, and registers the sub-scenario number described in the main scenario table and the scenario channel sCHn currently being processed. The address of the sound / motor sub-scenario table corresponding to the executed sub-scenario execution line (scIx) is specified.
In step S633, the production control CPU 200 determines whether or not the line indicated by the sub-scenario execution line (scIx) in the corresponding sound / motor sub-scenario number table is a line describing the scenario data end code D_SEEND. If it is confirmed and the scenario data end code D_SEEND is described, the process ends.
If the scenario data end code D_SEEND is not described, the production control CPU 200 substitutes a value obtained by subtracting the previous time (scPrevTm) from the time data (time) of the line in step S634 in the sub-scenario timer (scTm). To do. Also, the time data (time) of the line is substituted for the previous time (scPrevTm).

Then, the effect control CPU 200 performs sound registration in step S635, and performs motor registration in step S636. Although not described in detail, the information on the corresponding line of the corresponding sub-scenario number in the sound / motor sub-scenario table illustrated in FIG. 25B, the arbitrary motor channel of the motor data registration information in FIG. 22C, and the sound data registration information in FIG. The process of registering to an arbitrary sound channel is performed. In step S637, the solenoid / user option information described in the line is also registered in the scenario registration information.
In step S638, the value of the next line is set as the value of the sub-scenario execution line (scIx). If the sub-scenario timer (scTm) is not 0 in step S639, the sub-scenario timer (scTm) is decremented in step S640 and the process ends.

In step S110 in FIG. 13, the processes in FIGS. 20 and 21 are performed as described above, and the scenario registration information, lamp data registration information, motor data registration information, and sound data registration information on the work are sequentially updated. The effect control according to the scenario is executed by performing the effect control according to this.

[6-6: LED drive data update process]

The LED drive data update process in step S114 of FIG. 13 will be described.
This process is a process for creating LED drive data with reference to the lamp data table corresponding to the lighting number (registered lighting number (lmpNew), execution lighting number (lmpNo)) registered in the lamp data registration information. . As described above, the lamp number indicating the lighting pattern originally set in the lamp sub-scenario table is set as the lighting number of the lamp data registration information. The lamp number has been described as the number indicating the lighting pattern, but specifically indicates the lamp data number of the lamp data table described in FIG. 31A.

FIG. 26 shows the LED drive data update process.
In step S701, the effect control CPU 200 clears the LED drive data that has been output data until then.
As the loop process LP2, the processes of steps S702 to S720 are performed for each of the lamp channels dwCH0 to dwCH15 of the lamp data registration information. Hereinafter, the lamp channel to be processed will be described as “dwCHn”.

In step S702, the effect control CPU 200 checks whether or not the execution lighting number (lmpNo) and the registered lighting number (lmpNew) in the target lamp channel dwCHn match. Since the lighting pattern number is registered as in step S653 of FIG. 21B, they do not match at first. If they do not match, the lighting is started, and the value of the registered lighting number (lmpNew) is substituted into the execution lighting number (lmpNo) in step S703. In step S704, the execution line (ofset) is set to 0, and the execution time (time) is set to 0.
Note that if the execution lighting number (lmpNo) and the registered lighting number (lmpNew) match, the above steps S703 and S704 have already been performed, and these processes are unnecessary.

Regarding the information registered in a certain lamp channel dwCH, after the registration, the LED drive data to be output to each LED driver 90 is created for each occasion of the LED drive data update process.
FIG. 29A shows a state where registration is performed on the ramp channels dwCH0, dwCH5, and dwCH8 in the ramp data registration information of the workpiece shown in FIG. 22B. The state in this figure is an example of the state at time t0 in FIG. 29B.
That is, the information on the lamp channels dwCH0 and dwCH5 is reflected in the LED drive data before time t0. For the lamp channel dwCH0, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) have already been matched, and the execution line (ofset) has advanced to 3 (third line). Also, for the lamp channel dwCH5, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) have already been matched, and the execution line (ofset) has advanced to 2 (second line). At time t0, the lamp channel dwCH8 is immediately after registration, and the execution lighting number (lmpNo) and the registration lighting number (lmpNew) are not matched. Thereafter, the processes in steps S703 and S704 are performed.

As described above, in the present embodiment, priority is set for the ramp channels dwCH0 to dwCH15, and the priority increases in order from the ramp channels dwCH0 to dwCH15. As shown in FIG. 29A, the lamp channel dwCH15 having a high priority is used for error notification. Lamp channels with high priority, such as the lamp channels dwCH12, dwCH13, dwCH14, etc. are used for relatively highly reliable performances such as continuous notices and final notices. The lamp channel with medium priority is used for moving body effects, and the lamp channel with relatively low priority is used for effects with relatively low reliability, such as conversation notices and step-up notices. Channels are used for ramp effects that are synchronized with normal fluctuations, reach, and the like.
Because of such priority setting, when the operations of a plurality of lamp channels dwCH overlap as shown in FIG. 29B, a lighting operation of a lamp channel with a high priority is executed. For example, from time t0, the lighting operation based on the lamp channels dwCH0 and dwCH5 is limited, and the LED drive data is generated so that the lighting based on dwCH8 is performed. In order not to reflect the information of the lamp channel having a low priority, mask data described later is used.

Subsequently, in step S705 of FIG. 26, the effect control CPU 200 confirms whether or not the value of the execution lighting number (lmpNo) is within the normal range. The normal range is a range where numbers exist as lamp data in the lamp data table shown in FIG. 31A.
If the execution lighting number (lmpNo) is abnormal, the process proceeds to step S719. In the case of an empty channel in which the lamp channel dwCHn is not registered, the process proceeds to step S719 as abnormal here.

If the execution lighting number (lmpNo) is normal, the process proceeds to step S706. In step S706, the effect control CPU 200 specifies the address of the lamp data table corresponding to the execution lighting number (lmpNo) and execution line (ofset) registered in the lamp channel dwCHn.
In step S707, the execution lighting number (lmpNo) registered in the lamp channel dwCHn and the address of the mask data table are specified.
To specify the address, the effect control CPU 200 refers to a lamp data address table as shown in FIG. In this lamp data address table, the address of the lamp data number for realizing each lighting pattern, for example, entire flashing, right flashing, left flashing, and accessory lighting is shown. The numbers on the left side of FIG. 30 are the lamp numbers shown in the lamp sub-scenario table of FIG. 25A. For example, in the column of lamp data address of lamp number 2, the lamp data numbers for performing the entire blinking lighting pattern are shown. The stored address is described.
In the address field of mask data, an address where mask data necessary for executing the lighting pattern of the lamp data number is stored is stored. For example, when a lighting pattern of blinking on the right side of the lighting number 5 is performed, a center case mask is required, but an address of mask data for performing the center case mask is described.

FIG. 31A shows lamp data 1 and 2 as part of the lamp data table.
Each line in each number of lamp data describes time data and lighting data as a timer (frame). The timer (frame) defines the time for generating the LED drive data based on the lighting data of each line.
The lighting data is described corresponding to each LED driver 90. In FIG. 4, it is assumed that there are n LED drivers 90 in the frame driver unit 61 and m LED drivers 90 in the panel driver unit 62. In this case, each line of lamp data is shown in FIG. 31A. , Lighting data is described corresponding to each of the (n + m) LED drivers 90. In the figure, the correspondence with each LED driver 90 is indicated by w1 to w (n) and b1 to b (m) as slave addresses of the LED driver 90.
As the lighting data, 4 bits (0h to Fh) are assigned to one current terminal 96 (one series of LED drive current generation) of the LED driver 90 described in FIG. 4 and FIG. Hexadecimal notation is shown), and the luminance of 16 gradations is designated. As described in FIG. 5, the LED driver 90 has 24 current terminals 96-1 to 96-24. Therefore, one piece of lighting data is information of (4 × 24) bits as “FFFF000055550000AAAAAAAA (h)”. If the lighting data for the LED driver 90 (w1) is “FFFF00000000000000055550000 (h)”, as shown in the first line of the lamp data 1 shown in the drawing, the current terminals 96-1 to 96 of the LED driver 90 (w1). -4 outputs a driving current for emitting the maximum luminance “F”, the current terminals 96-5 to 96-16 and 96-21 to 96-24 are non-emitting (minimum luminance), and the current terminals 96-17. ... 96 to 20 is information for designating output of a drive current having a luminance of “5”.
In the lamp data, such lighting data is set for each of the LED drivers 90 (w1 to w (n), b1 to b (m)) and is set for each line. Thus, a predetermined light emission pattern that changes in time series is shown. (In the figure, the lighting data is illustrated only in part. The blank portion is not shown, and the lighting data is actually described.)

By the way, in the example of FIG. 31A, a part of the area (area Azh, Aj) corresponding to the LED driver 90 having the slave addresses “b2” and “b3” is hatched. In the hatched areas Azh and Aj, dummy data (for example, all “0”) is described.
These areas Azh and Aj are data areas corresponding to the current terminals to which the LED 120 as the status presentation light emitting unit is connected in the LED driver 90 with the slave addresses “b2” and “b3”.

As described with reference to FIG. 7, the LED driver 90 with the slave address “b2” corresponds to the light emitting units 20H-1 to 20H-8 as the holding number display light emitting units 20H at the current terminals 96-1 to 96-8. The LED 120 is connected. Further, LEDs 120 corresponding to the light emitting units 20Z-1 to 20Z-3 as the symbol identifying light emitting unit 20Z are connected to the current terminals 96-9 to 96-11.
In the ramp data table of FIG. 31A, an area of (4 × 11) bits corresponding to the current terminals 96-1 to 96-11 of the slave address “b2” is an area Azh indicated by hatching, and this area Azh includes Dummy data is arranged.

Further, as described above, the LED driver 90 with the slave address “b3” has the LEDs 120 corresponding to the light emitting units 20J-1 to 20J-3 as the gaming state notification light emitting units 20J at the current terminals 96-1 to 96-3. Is connected.
In the ramp data table of FIG. 31A, an area of (4 × 3) bits corresponding to the current terminals 96-1 to 96-3 of the slave address “b3” is an area Aj indicated by hatching, and this area Aj includes Dummy data is arranged.

  The dummy data of these areas Azh and Aj is replaced with light emission drive data for status presentation (for gaming status notification, for holding number display, for gaming status notification) in the process of step S721 described later.

FIG. 31B shows mask data 1 to 5 as examples of the mask data table. Each mask data is a mask for driving the light emitting unit 20w on the frame side, a mask for driving the light emitting unit 20b on the board side, an entire mask, a mask for the center case, and a mask for the accessory For this reason, a necessary mask pattern is stored.
The mask data 1 to 5 indicate that the current terminals 96-1 to 96-24 of the LED drivers 90 (w1 to w (n) and b1 to b (m)) are turned off “0h” and no mask is used. The data is indicated by “Fh”.
For example, with respect to the mask data 1, for the LED driver 90 (w1 to w (n)) in the frame driver unit 61, “0000... 00 (h)” and the current terminals 96-1 to 96- The LED driver 90 (b1 to b (m)) of the panel driver unit 62 is set to “FFFF... FF (h)” and current terminals 96-1 to 96-24. No mask is set for. That is, the data specifies that only the light emitting unit 20w on the frame side is masked. (Note that the mask data 4 and 5 are not shown with data values)

  In each mask data, the areas Mzh and Mj corresponding to the areas Azh and Aj in which dummy data is arranged in the ramp data are all set to “Fh” indicating no mask. That is, in the mask data, an area of (4 × 11) bits corresponding to the current terminals 96-1 to 96-11 of the slave address “b2” and the current terminals 96-1 to 96-3 of the slave address “b3”. No mask is set for the (4 × 3) bit area corresponding to.

In steps S706 and S707 in FIG. 26, an address corresponding to the lamp channel dwCHn being processed is specified in the lamp data table and the mask data table.
Subsequently, in step S708, the effect control CPU 200 obtains a timer (frame) of the relevant line (the line indicated by the execution line (offset) of the current target lamp channel dwCHn) in the lamp data table, and substitutes it for the variable Dtime. .

  In step S709, the effect control CPU 200 develops the corresponding lighting data and mask data specified in steps S706 and S707, and generates LED drive data. Although this process will be described later, the lighting data and mask data for the lamp channel dwCHn currently being processed are reflected in the LED drive data to be output.

In step S710, the execution time (time), which is information of the ramp channel dwCHn, is incremented by one.
In step S711, the variable Dtime is compared with the execution time (time). The timer (frame) of the currently executing line is assigned to the variable Dtime. The execution time (time) is incremented by 1 in step S710 for each LED drive data update process (every 16 ms). Therefore, if Dtime ≦ time, the current line end timing is reached. If Dtime ≦ time is not satisfied, it is determined that the current line has not yet been terminated, and the process advances from step S711 to S719. If Dtime ≦ time, the process proceeds from step S711 to S712 as the end of the current line.
The effect control CPU 200 resets the execution time (time) to 0 in step S712. In step S713, the execution line (offset) value is incremented by one. In other words, the next line is targeted.
In step S714, the effect control CPU 200 specifies the address of the lamp data table corresponding line corresponding to the execution line (offset). In steps S715 and S717, it is confirmed whether an end code (D_DTEND) or a loop code (LMP_LP) is described in the line.
If the end code (D_DTEND) is described, the registered lighting number of the lamp channel dwCHn is updated to 0 in step S716. In other words, it indicates that the processing corresponding to the registration of the lamp channel dwCH is completed on the work.
If the loop code (LMP_LP) has been described, the value of the execution line (offset) is updated to the loop destination address in step S718.

In step S719, the effect control CPU 200 calculates the checksum of the LED drive data at the time of the lamp channel dwCHn. In step S720, the backup data is saved.
This completes the LED data update for one lamp channel dwCHn. As the loop processing LP2, the above processing is sequentially performed up to the ramp channels dwCH0 to dwCH15.

The LED drive data in each lamp channel dwCHn is updated in step S709, and this is the following process.
FIG. 32A schematically shows an output data buffer (light emission drive data storage unit) for storing LED drive data generated by developing lighting data and mask data.
The output data buffer is prepared corresponding to each LED driver 90 (w1 to w (n), b1 to b (m)), similarly to the lamp data table and the mask data table. One square shown in the figure indicates a buffer area of information of (4 × 24) bits corresponding to one LED driver 90.

For such an output data buffer, in step S709, a process of developing the mask data with AND (logical product) and developing the lighting data with OR (logical sum) is performed. This is sequentially performed in step S709 for each of the lamp channels dwCH0 to dwCH15 by loop processing (LP2).
For example, at the time t0 shown in FIG. 29, the output data buffer is AND-expanded with the mask data of the lamp data 2 (see FIG. 30: no mask), and the lighting data of the third line of the lamp data 2 is OR-expanded. After the state, the mask data of the lamp data 5 (see FIG. 30: center case mask) is AND expanded, and the lighting data of the second line of the lamp data 5 is OR expanded.
As described above, in the mask data, 0h (= 0000) is extinguished and Fh (= 1111) is no mask. Therefore, expanding the mask data with AND means that the bit to be extinguished (masked) is set to “0” in the output data buffer value up to that point, and the bits not masked are not changed.
Further, when the lighting data is expanded OR, the lighting data of the lamp channel dwCH being processed is reflected in the output data buffer after masking.
By sequentially performing this process for the lamp channels dwCH0 to dwCH15, the LED drive data that is prioritized for the higher-numbered lamp channels is formed on the output data buffer.

  As described above, in the lamp data registration information (see FIG. 22B), when a plurality of types of lamp data corresponding to a plurality of light emission effects are set in a plurality of hierarchies set with a priority order, the order of priority is low. By reflecting the lamp data and creating the LED drive data for the light emission effect, it is possible to generate the LED drive data for the light emission effect reflecting the priority order with a simple process.

In the loop processing LP2 of FIG. 26, when the LED drive data based on the lamp data specified by the lamp channels dwCH0 to dwCH15 is generated, the effect light emitting units 20w and 20b are based on a plurality of types of lamp data as the LED drive data. It can be said that the light emission driving information for performance is generated.
However, at this time, the LED drive data on the output data buffer of FIG. 32A includes the (4 × 11) -bit region DBzh corresponding to the current terminals 96-1 to 96-11 of the slave address “b2” and the slave address “b3”. The (4 × 3) -bit region DBj corresponding to the current terminals 96-1 to 96-3 of FIG. 4B is a state where dummy data of the regions Azh and Aj of the ramp data table is expanded, and is still used for presenting the situation. The light emission drive information for status presentation (for changing symbol identification, for holding number display, for gaming state notification) for the light emitting units 20Z, 20H, and 20J is not reflected.

  Therefore, in step S721 in FIG. 26, the production control CPU 200 generates light emission drive information for status presentation (for changing symbol identification, for holding number display, for gaming state notification), and expands it in the output data buffer for output. On the data buffer, LED driving data for one timing obtained by combining the light emission driving information for presentation and the light emission driving information for situation presentation is created.

A processing example of step S721 will be described with reference to FIG.
In step S731, the effect control CPU 200 checks the symbol variation flag. As described in the description of FIG. 16C, the effect control CPU 200 sequentially receives the first special symbol variation flag FZ1, the second special symbol variation flag FZ2, and the normal symbol variation flag FZ3 according to the symbol designation command from the main control unit CPU100. Is set. In step S731, these symbol variation flags (FZ1, FZ2, FZ3) are confirmed, and in response to each symbol variation flag, in step S732, corresponding to the current terminals 96-9 to 96-11 of the slave address “b2” (4 X3) Bit light emission drive data is set. In step S733, this is expanded into the corresponding area on the output data buffer (that is, the last 4 × 3 bits of the area DBzh).

In this case, the gradation values for the light emitting units 20H-1, 20H-2, and 20H-3 for variation symbol identification are set, but when lighting each, “Fh: (= 1111)”, When the light is off, “0h (= 0000)” is set. In the case of blinking, “Fh” and “0h” are alternately set at every predetermined timing. Therefore, if the symbol variation flag indicates blinking, is this time set to “Fh”? , “0h” is managed separately.
Then, the gradation values (4 × 3 bits) for the three light emitting units 20H-1, 20H-2, and 20H-3, which are set to “0h” or “Fh”, are displayed on the output data buffer in the second half of the region DBzh. To 4 × 3 bits. At this time, when the light is on (“Fh”), OR expansion is performed, and when the light is off (“0h”), AND expansion is performed. Since the dummy data is all 0 data, each gradation value for the light emitting units 20H-1, 20H-2, and 20H-3 is reflected in the LED drive data on the output data buffer.
When the dummy data is “0h” as in this example, the gradation values for the light emitting units 20H-1, 20H-2, and 20H-3 are either “0h” or “Fh”. Alternatively, OR expansion may be performed on the region DBzh.
However, in the case of OR expansion, when the dummy data (“0h”) is rewritten to some value due to noise or the like, the indefinite data is output. On the other hand, if the light is extinguished ("0h") and AND expansion is performed as described above, the value is "0h" when the light is off ("0h") regardless of the value of the dummy data. it can. In other words, when the light is turned on (“Fh”), OR expansion is performed, and when the light is turned off (“0h”), AND expansion is performed, so that the light emitting units 20H-1, 20H-2,. LED drive data that correctly reflects each gradation value for 20H-3 can be generated on the output data buffer.

  Subsequently, the production control CPU 200 checks the number of holds in step S734. As described in the description of FIGS. 17A and 17B, the effect control CPU 200 sequentially updates the first hold number and the second hold number in accordance with the hold addition command and the hold subtraction command from the main control unit CPU 100. ing. In step S734, the first hold number and the second hold number are confirmed. In step S725, the current terminals 96-1 to 96-8 of the slave address “b2” are associated with the values (4 × 8). ) Set the bit emission drive data. Then, in step S736, this is expanded into the corresponding area on the output data buffer (that is, the 4 × 8 bits in the first half of the area DBzh).

  In this case, the gradation values for the light emission units 20H-1 to 20H-8 for displaying the number of holdings are set. For each of these, “Fh” is set to be turned on, and “0h” is set to be turned off. . Then, the gradation values (4 × 8 bits) for the eight light emitting units 20H-1 to 20H-8 that are set to “0h” or “Fh”, respectively, are displayed on the output data buffer as 4 × 8 in the first half of the region DBzh. The bit is OR expanded (in the case of “Fh”) or AND expanded (in the case of “0h”). Since the dummy data is all 0 data, the gradation values for the light emitting units 20H-1 to 20H-8 are reflected in the LED drive data on the output data buffer by this development.

  Subsequently, the effect control CPU 200 checks the gaming state notification flag in step S737. As described in the description of FIG. 17C, the effect control CPU 200 sequentially indicates, for example, the flags FJ1, FJ2, “Jacking big”, “Probably changing”, and “Short in time” in response to the state notification command from the main control unit CPU100. FJ3 is set. In step S7317, these gaming state notification flags (FJ1, FJ2, FJ3) are confirmed, and in step S738, corresponding to each gaming state notification flag, corresponding to the current terminals 96-1 to 96-3 of the slave address “b3”. Light emission drive data of (4 × 3) bits is set. In step S739, this is expanded into a corresponding area on the output data buffer (ie, 4 × 3 bits of area DBj).

In this case, the gradation values for the light emitting units 20J-1, 20J-2, and 20J-3 for notifying the gaming state are set. For each of these, “Fh” is set to be turned on, and “Gh” is set to be turned off. 0h ".
Then, the gradation values (4 × 3 bits) for the three light emitting units 20J-1, 20J-2, and 20J-3, which are set to “0h” or “Fh”, are displayed on the output data buffer as 4 in the region DBj. X3 bit OR expansion (when "Fh") or AND expansion (when "0h"). Since the dummy data is all 0 data, the gradation values for the light emitting units 20J-1, 20J-2, and 20J-3 are reflected in the LED drive data on the output data buffer by this development.

In step S740, the effect control CPU 200 calculates a checksum of the developed LED drive data. In step S741, backup data is stored.
The above processing of FIG. 27 is performed as step S721 of FIG. In this state, on the output data buffer of FIG. 32, the production light emission drive information for the production light emitting units 20w, 20b and the situation presentation for the situation presentation light emitting units 20Z, 20H, 20J (for variation symbol identification, The LED drive data for one timing in which the light emission drive information for holding number display and gaming state notification is combined is generated and stored.

[6-7: LED output processing of the first embodiment]

The LED drive data generated by the LED data update process as described above is actually output to each LED driver 90 in step S115 of FIG.
In the present embodiment, the effect control CPU 200 abbreviates the serial data of one transmission unit of the LED drive data to the first and second system drive signal output means (the frame driver unit 61 and the panel driver unit 62). Output simultaneously.
For example, as shown in FIG. 32B, LED drive data is transmitted to the LED drivers 90 (w1 to w (n)) of the frame driver unit 61 through the serial data transmission channel ch1, and the panel driver unit 62 is transmitted through the serial data transmission channel ch2. LED drive data is transmitted to the LED driver 90 (b1 to b (m)).
In the present embodiment, the LED drive data is transmitted simultaneously in parallel through the serial data transmission channels ch1 and ch2, but it is not always necessary.

FIG. 33 shows a serial data structure of LED drive data transmitted to one LED driver 90.
For example, the LED drive data is transmitted to each of the LED drivers 90 (w1 to w (n), b1 to b (m)) shown in FIG. 32B as serial data having the structure of FIG. FIG. 33 shows the serial data DATA and the enable signal ENABLE described in FIGS.
This serial data is sequentially transmitted byte by byte during a period when the enable signal ENABLE is turned on. In other words, each byte of serial data having this structure is a transmission unit.

The serial data DATA includes a 1-byte slave address, a 1-byte data setting start register address (SX), 1-byte write data to the address (SX), and write data to the address (SX + 1). -Consists of a total of 26 bytes of write data to address (SX + 23).
Such serial data DATA is taken into the LED driver 90 during a period defined by the enable signal ENABLE.

The “slave address” is a device ID of each LED driver 90, and is a 1-byte code that identifies w1-w (n) or b1-b (m).
“Data setting start register address (SX)” is information for designating the head of a register for fetching data in the LED driver 90. For example, it is the designation information of the internal register of the data buffer / PWM controller 93 of FIG. In the LED driver 90 employed in the present embodiment, for example, registers (8 bits each) of register addresses 00h to 2Ch are prepared for capturing serial data. Among them, 24 registers (8 bits each) of register addresses 15h to 2Ch are registers (gradation) for inputting lighting data (PWM gradation instruction data) corresponding to 24 current terminals 96-1 to 96-24. Value setting unit). Therefore, the register address 15h is designated as the “data setting start register address (SX)”.
As “write data to address (SX)”, write data to the register at the register address (“15h” in this embodiment) specified by “data setting start register address (SX)”, that is, current terminal LED drive data corresponding to 96-1 is set.
As “write data to address (SX + 1)”, write data to the register at register address + 1 (“16h” in this embodiment) specified by “data setting start register address (SX)”, that is, current LED drive data corresponding to the terminal 96-2 is set.
The same applies to the following, and “write data to address (SX + 23)” is a register address +23 (“2Ch” in this embodiment) specified by “data setting start register address (SX)”. Write data, that is, LED drive data corresponding to the current terminals 96-24 is set.

These write data have an 8-bit structure, but as described above, one lighting data has a 4-bit structure of “0h (= 0000)” to “Fh (= 1111)”. Four bits represent 16 gradations of brightness. On the other hand, each register (8 bits each) of the register addresses 15h to 2Ch for inputting the PWM gradation instruction data can correspond to 256 gradations with 8 bits.
In the case of the present embodiment, since the lighting data is data of 16 gradations, the lighting data is set in the upper 4 bits as 8-bit write data to each register of the register addresses 15h to 2Ch. Yes. This point will be described later.
In addition, although it has been described that the LED driver 90 is initialized in step S113 of FIG. 13, specifically, this is a transmission process in which default values are set in the registers at unused register addresses 00h to 14h. This point will also be described later.

The LED drive data output process performed in step S115 of the 16 ms process will be described with reference to FIG.
In step S801 in FIG. 28, the effect control CPU 200 specifies the head address of the LED drive data (output data buffer in FIG. 32A) of the serial data output channels ch1 and ch2 corresponding to the start value.
The start value is the value of the LED driver 90 that is transmitted first. In this embodiment, transmission is first performed from the serial data output channels ch1 and ch2 to the LED driver 90 (w1) and the LED driver 90 (b1), respectively. The head address where the LED drive data is stored and the head address where the b1 LED drive data is stored are specified.

  Next, in step S802, the effect control CPU 200 specifies the slave addresses of the serial data output channels ch1 and ch2 corresponding to the start value. That is, the address code indicates “w1” and “b1”.

Then, as loop processing LP3, the processing of steps S803 to S815 is executed in a loop for the number of driver numbers.
The serial data output channel ch1 transmits to the n LED drivers 90 of the frame driver unit 61, and the serial data output channel ch2 transmits to the m LED drivers 90 of the panel driver unit 62. The number of times of the loop processing is n times or m times (value with larger n and m). If n <m, then m times.

In step S803, the effect control CPU 200 turns on the enable signal ENABLE in the serial data output channels ch1 and ch2.
In step S804, the production control CPU 200 transmits the data of the first transmission unit (1 byte) as the output of the serial data DATA of the serial data output channels ch1 and ch2, that is, the serial data structure shown in FIG. 33 in this case. Sends and outputs the slave address of the first byte. The serial data output channels ch1 and ch2 are simultaneously transmitted in parallel.
When the transmission of one transmission unit is performed, in steps S805 and S806, completion of transmission output for each serial data output channel ch1 and ch2 is waited.

When the transmission output completion for the serial data output channels ch1 and ch2 is confirmed, the effect control CPU 200, in step S807, sets the data setting start register address (SX) (this example) as the next one transmission unit (1 byte) data transmission. 15h) is transmitted and output. Also in this case, data transmission is performed simultaneously on the serial data output channels ch1 and ch2.
When the transmission in one transmission unit is performed, in steps S808 and S809, the completion of transmission output for each serial data output channel ch1 and ch2 is awaited.

When the transmission output completion for the serial data output channels ch1 and ch2 is confirmed in steps S808 and S809, the effect control CPU 200 performs register transmission (SX = 15h) to data transmission in one transmission unit (1 byte) in step S810. Write data (= LED drive data) to (SX + 23 = 2Ch) is transmitted and output.
First, 1-byte LED drive data transmission to the register address (15h) is simultaneously performed in parallel for the serial data output channels ch1 and ch2. In steps S811 and S812, the transmission output completion for the serial data output channels ch1 and ch2 is awaited.
If transmission completion is confirmed, transmission of step S810 will be performed byte by byte until it is confirmed in step S813 that a total of 24 bytes, that is, completion of LED drive data transmission from register addresses 15h to 2Ch is confirmed. Therefore, next, 1-byte LED drive data transmission to the register address (16h) is performed for the serial data output channels ch1 and ch2. Further, after confirming the transmission, LED drive data is transmitted to the register address (17h). Thereafter, transmission completion standby → LED drive data transmission to register address (18h) → transmission completion standby → LED drive data transmission to register address (19h) → transmission completion standby →→ LED to register address (2Ch) The process of driving data transmission → transmission completion waiting is performed.

When the transmission output of 24 bytes for the LED drive data is completed, the serial data output to one LED driver 90 having the structure of FIG. 33 is completed. In step S814, the enable signal ENABLE is turned off, and the target slave address is incremented by one. Then, one loop process is completed.
FIG. 34 shows data transmitted in the above one loop process. In the serial data output channels ch1 and ch2, a slave address, a data setting start register address, and LED drive data LPDT1, LPDT2,.
Such transmission is performed, and LED drive data is set in the LED driver 90. On the LED driver 90 side, each current terminal 96-1 is based on the light emission luminance (16 gradations from 0h to Fh) indicated in the LED drive data LPDT1, LPDT2,. The current amount of .about.96-24 is controlled, and the LEDs 120 of each series connected to the current terminals 96-1 to 96-24 emit light.

Subsequently, as the second loop process, the processes of steps S803 to S815 are similarly performed for the LED driver 90 (w2) and the LED driver 90 (b2). Further, thereafter, as the third loop process, the processes of steps S803 to S815 are similarly performed for the LED driver 90 (w3) and the LED driver 90 (b3).
Thereafter, the loop process LP3 is repeated until transmission to all of the LED drivers 90 (w (n)) and LED drivers 90 (b (m)). If n <m, after completing serial data transmission to all the n LED drivers 90 of the frame driver unit 61, only the remaining LED drivers 90 of the panel driver unit 62 are subjected to steps S803 to S815. Processing will be performed.
The serial data output to the (n + m) LED drivers 90 as shown in FIG. 32B is executed in m times of loop processing LP3, and the LED drive data output (the processing in step S115 in FIG. 13) is completed. If the number of LED drivers 90 to be mounted is different, the number of loops naturally changes.
In the above example, two serial data output channels ch1 and ch2 are used. However, when three or more serial data output channels are used, serial data transmission is performed simultaneously in parallel. You can do that.

As in the processing of FIG. 28 described above, in the present embodiment, the effect control CPU 200 performs drive signal output means (frame driver) for the first system (serial data output channel ch1) and the second system (serial data output channel ch2). The unit 61 and the panel driver unit 62) transmit serial data of one transmission unit simultaneously. Then, after the transmission is completed, the next serial data of one transmission unit is transmitted substantially simultaneously to the drive signal output means of the first system and the second system. Through such processing, LED drive data is transmitted to each LED driver 90.
As a result, the time required for the entire serial data transmission operation can be shortened, and the processing load on the rendering control CPU 200 can be reduced.

The reason for this will be explained.
FIG. 35 shows the write timing of the clock signal CLK, transmission data, TDRE (transmission data empty flag), and transmission data used by the effect control CPU 200 for serial data transmission to the transmission data register.
The transmission data corresponds to the above-described slave address, data setting start register address, and LED drive data LPDT1, LPDT2,. Here, 8 bits as one transmission unit are shown as data d0 to d7.

When the effect control CPU 200 transmits 8-bit data in one transmission unit in each of steps S804, S807, and S810 in FIG. 28, it writes 8-bit transmission data in the transmission data registers in the respective serial data output channels ch1 and ch2. The transmission data written to the transmission data register is transmitted and output one bit at each timing of the clock signal CLK.
Here, TDRE becomes “0” when transmission data is written in the transmission data register, indicating that valid data exists in the transmission data register. When the data in the transmission data register is actually output for transmission (loading to the transmission shift register) and transmission is started, it becomes “1”, indicating that there is no valid data in the transmission data register.
Therefore, as the transmission process of the effect control CPU 200, after confirming that the TDRE is “1”, the 8-bit transmission data is written to the transmission data register, and the next 8-bit transmission data is written next. Wait until TDRE becomes “1”. That is, the next transmission data cannot be processed during the period shown as the standby time TW in FIG.

Regarding serial data transmission, conventionally, serial data of one transmission unit (8 bits) is transmitted from one serial data output channel to, for example, the first-system drive signal output means, and after the transmission is completed, from the next transmission channel The transmission operation is performed such that serial data of one transmission unit (8 bits) is transmitted to the drive signal output means of the second system. For example, the processing corresponding to steps S804 to S806 in FIG.
(ST1) Slave address output from ch1 (write to transmission data register)
(ST2) Transmission output completion waiting (ST3) Data setting start register address output from ch1 (writing to transmission data register)
(ST4) Transmission output completion waiting (ST5) LED drive data LPDT1 output from ch1 (writing to transmission data register)
(ST6) Transmission output completion standby (ST7) LED drive data LPDT2 output from ch1 (ST8) Transmission output completion standby ... Omission ...
(ST51) LED drive data LPDT24 output from ch1 (ST52) Transmission output completion standby (ST53) Slave address output from ch2 (ST54) ch2 transmission output completion standby (ST55) Data setting start register address output from ch2 (ST56) Transmission output completion LED drive data LPDT1 output from standby (ST57) ch2 (ST58) Transmission output completion standby (ST59) LED drive data LPDT2 output (ST60) transmission output completion standby from ch2 ... Omission ...
(ST103) LED drive data LPDT24 output from ch2 (ST104) Transmission output completion waiting.
In this case, a waiting time is generated for each transmission of one transmission unit in each of the serial data output channels ch1 and ch2, and transmission processing efficiency is poor.
In contrast, in this embodiment,
(S804) Slave address output from ch1 and ch2 (write to transmission data register)
(S805, S806) By performing transmission processing on both serial data output channels ch1 and ch2 at the same time, such as ch1 and ch2 transmission output completion waiting, the processing becomes efficient.
The same applies to the processing in steps S807 to S809 and the processing in steps S810 to S812.

Then, transmission to one LED driver 90 is 26 bytes for each transmission channel in one loop process (26 writes to the transmission data register). If simultaneous processing is not executed for each of the serial data output channels ch1 and ch2, the total standby time is approximately (52 × TW) in one loop processing period. In the case of this embodiment, this can be remarkably shortened to approximately (26 × TW) in one loop processing period.
In the LED drive data output process of step S115 of FIG. 13, the serial data output process can be made more efficient in this way, so that the processing load on the effect control CPU 200 is greatly reduced.

In the present embodiment, the LED drive data transmitted as serial data is data indicating the light emission luminance (gradation), and realizes light emission drive of 16 gradations with, for example, 4 bits as described above. By making such gradation control possible, more various effects can be realized.
In this embodiment, an example of 16 gradations has been described, but it is needless to say that multiple gradations may be used.

The pachinko gaming machine 1 according to the present embodiment includes a frame (front frame 2, outer frame 4 and glass door 5) and a game board (game board 3) attached to the frame. The first-system drive signal output means (frame driver section 61) includes a plurality of driver circuits (LED drivers) that output LED drive signals to a lamp section 63 (light emitting section 20w) that is an effect means provided in the front frame 2. 90), and the second-system drive signal output means (board driver part 62) is LED driven by the lamp part 64 (light emitting parts 20b, 20Z, 20H, 20J) which is the effect means provided in the game board 3. It is composed of a plurality of driver circuits (LED drivers 90) that output signals.
With this configuration, all the LED drivers 90 of the frame driver unit 61 correspond to the light emitting unit 20w on the frame side, and all the LED drivers 90 of the panel driver unit 62 correspond to the light emitting unit 20b on the panel side. Therefore, it is possible to realize the simplification of wiring, the efficiency improvement, the ease of production control setting, and the like.

By the way, in the present embodiment, in step S810, the lighting data having the 4-bit structure as described above is converted into 8-bit data and output as serial data in one transmission unit.
This bit conversion will be described with reference to FIG. FIG. 36A shows an example of 4 × 24-bit lighting data transmitted to one LED driver 90. That is, this is an example of data corresponding to one square of the output data buffer in FIG. 32A. The first “F8h” (“h” is omitted in the figure) is lighting data to be transmitted to the register addresses 15h and 16h of the LED driver 90, that is, “Fh” is a current written to the register address 15h of the LED driver 90. The lighting data as the gradation value for the terminal 96-1, and “8h” is the lighting data as the gradation value for the current terminal 96-2 to be written to the register address 16h. The next “0Fh” similarly corresponds to the register addresses 17h and 18h. The same applies to the following, and the last “00h” corresponds to the register addresses 2Bh and 2Ch.

Here, when considered by dividing into 8 bit units as the internal processing unit of the effect control CPU 200 as “F8h” “0Fh”... “00h” in FIG. 36A, the upper 4 bits (for example, “F8h” "Fh" is lighting data for an odd register address (for example, register address 15h), and lower 4 bits (for example, "8h" for "F8h") is lighting data for an even register address (for example, register address 16h). It becomes.
Here, “odd register address” and “even register address” are examples according to the register design of the LED driver 90. For the sake of convenience, the transmission destination is merely assumed to be the register addresses 15h to 2Ch.
In this case, for the lighting data to the odd register addresses (15h, 17h... 2Bh), the effect control CPU 200 masks the lower 4 bits of the 8-bit data and transmits it to the LED driver 90. On the other hand, for the lighting data to the even register address (16h, 18h... 2Ch), the effect control CPU 200 masks the upper 4 bits of the 8-bit data and shifts the 4-bit shift to the LED driver 90. Send. That is, as a result, 4-bit lighting data is converted into 8-bit and transmitted.

As this bit conversion, the case of “F8h” is shown in FIGS. 36B and 36C.
FIG. 36B shows a process when the lighting data “Fh” is transmitted to the register address 15 h. The lighting data extracted from the output data buffer in FIG. 32A is “F8h” = “11111000”, which is two lighting data of 4 bits each. The lower 4 bits are masked for this data. For example, AND is performed using mask data “F0h” = “11110000”. As a result, serial data “11110000” = “F0h” to be transmitted to the register address 15h is obtained as illustrated. In this case, the drive current output of the maximum gradation value (F0h) is performed from the current terminal 96-1.
On the other hand, FIG. 36C shows a process when the lighting data “8h” is transmitted to the register address 16h. As described above, the lighting data extracted from the output data buffer in FIG. 32A is “F8h” = “11111000”. The upper 4 bits are masked for this data. For example, AND is performed using mask data “0Fh” = “00001111”. As a result, data “00001000” is obtained as illustrated. Further, in this case, serial data “10000000” = “80h” to be transmitted to the register address 16h is obtained by shifting the data by 4 bits. In this case, a driving current output having an intermediate gradation value (80h) is performed from the current terminal 96-1.

As described above, in the present embodiment, the effect control unit 51 has, for example, the light emission luminance information of the second bit number (for example, 4 bits) that is smaller than the first bit number (for example, 8 bits) in the effect control ROM 201. (Lighting data) is stored in the form of a lamp data table or the like. Then, the production control CPU 200 converts the light emission luminance information of the second bit number into the first bit number to generate LED drive data, and the LED drive data is converted into serial data to the LED driver 90 which is a light emission drive signal output means. Send.
The fact that the 8-bit PWM data can be input to the register addresses 15h to 2Ch of the LED driver 90 enables LED light emission control of 256 gradations if it is 8-bit lighting data. However, 256 gradations are not necessary for the control of the light emitting units 20w and 20b used for the light emission effect of the gaming machine of the present embodiment. Specifically, 16 gradations of “00h”, “10h”, “20h”,... “F0h” are sufficient.
Therefore, in this embodiment, the lighting data has a 4-bit structure, and 16 gradations are expressed. When outputting to the LED driver 90, 4 bits are converted into 8 bits and transmitted.

By doing in this way, the production control unit 51 can greatly reduce the data capacity of the lighting data stored in the internal ROM (production control ROM 201), and the memory capacity consumption can be suppressed.
Further, in recent years, general-purpose LED drivers of high-performance type such as 256 gradations have a higher production volume and are more advantageous in price. Therefore, for example, when 16 gradations are required, it is more cost-effective to use a 256 gradation LED driver than to use an LED driver having 16 gradation control capability, and is stable. Availability is also good. This provides manufacturing and cost advantages.
As described above, the effect control CPU 200 arranges the 4-bit lighting data in the upper 4 bits of the 8 bits, and generates 8-bit LED drive data (serial data to be transmitted).
Thus, LED driving data of 16 gradations can be generated by the upper 4 bits arrangement, and the processing is very simple processing as in the examples of FIGS. 36B and 36C, for example. For this reason, the processing load of bit number conversion hardly poses a problem.

In the above example, the lighting data converted into 8 bits is assumed to be “00h”, “10h”, “20h”... “F0h”, but the following example is also conceivable.
In this case, when the 4-bit lighting data is “Fh”, the 8-bit serial data “F0h” has the maximum control brightness, but the LED driver 90 can handle “FFh”. Therefore, the lower 4 bits of “F0h” of the 8-bit serial data may be converted to “1111” and “FFh” (= 11111111) may be transmitted. That is, the serial data to be transmitted is “00h”, “10h”, “20h”,... “E0h”, “FFh”. In this way, it is possible to execute light emission with the maximum brightness on the light emission drive capability of the LED driver 90.
For “10h”, “20h”,... “F0h” other than “00h”, the lower 4 bits may be converted to “1111” and transmitted as “1Fh”, “2Fh”, “FFh”. . Thereby, the light emission brightness in each gradation can be increased, and the effect can be improved.
Further, the example in which the 4-bit lighting data is 8 bits has been described so far, but this is an example. The first bit number (for example, 8 bits) is determined according to the design on the LED driver side. The second bit number (for example, 4 bits) may be set according to the gradation to be expressed. For example, 1 bit may be used for 2 gradations, 2 bits for 4 gradations, 3 bits for 8 gradations, and so on.
In this embodiment, LED drive data is transmitted as serial data output. However, the process of converting the second bit number of lighting data into the first bit number and transmitting it to the light emission driver is performed in parallel. The present invention can also be applied to data output or wireless transmission output. In this case, when there is a difference between the gradation capability of the transmission destination and the desired gradation expression, the data storage capacity of the transmission source can be reduced.

[6-8: LED driver initialization processing]

In step S1113 in FIG. 13, the LED driver 90 is described as being initialized, but this is a transmission process in which default values are set in the registers at unused register addresses 00h to 14h.
As described above, the register addresses 15h to 2Ch of the LED driver 90 are registers in which lighting data (gradation values) corresponding to the current terminals 96-1 to 96-24 are written, respectively. Data is written in each register as follows.

00h: PWM cycle setting data is set in 3 bits out of 8 bits, and master / slave setting data is set in 1 bit.
01h: Setting data of fade-in speed per gradation is set by 3 bits out of 8 bits and fade-out speed is set by 3 bits.
02h: Red LED current value data is set in 5 bits of 8 bits.
03h: Current value data of the green LED is set in 5 bits out of 8 bits.
04h: Current value data of blue LED is set in 5 bits out of 8 bits.
05h: Six bits out of eight bits set ON / OFF setting data for current terminals 96-1 to 96-6.
06h: Six bits out of eight bits set ON / OFF setting data of current terminals 96-7 to 96-12.
07h: Six bits out of eight bits set ON / OFF setting data of current terminals 96-13 to 96-18.
08h: Six bits out of eight bits set ON / OFF setting data of current terminals 96-19 to 96-24. The registers at the register addresses 05h to 08h serve as on / off setting units for the current terminals 96-1 to 96-24.
09h to 0Eh: For each of the four output terminals, any one of “PWM output priority”, “fade output priority”, and “forced on / off output priority” is selected and set for each of the four output terminals. The six resistors from 09h to 0Eh correspond to 24 current terminals 96-1 to 96-24.
0Fh to 11h: Three registers (24 bits in total) are set to enable / disable the fade function of 24 current terminals 96-1 to 96-24.
12h to 14h: The three current registers (24 bits in total) are used to forcibly turn on / off the 24 current terminals 96-1 to 96-24.

In the initialization process of the LED driver 90, default values are set in these registers (00h to 14h). The default values are as follows: Note that “0x” represents hexadecimal notation as in “h”. In order to distinguish between the register address value and the data value (default value), “0x” and “h” are used separately.
00h: 0x00: Initial setting of PWM cycle 01h: 0x00: No fade-in / fade-out slope 02h: 0x1F: Initial setting of red LED current value 03h: 0x1F: Initial setting of green LED current value 04h: 0x1F ... Initial setting of blue LED current value 05h: 0x77 ... On setting of current terminals 96-1 to 96-6 06h: 0x77 ... On setting of current terminals 96-7 to 96-12 07h : 0x77 ... ON setting of current terminals 96-13 to 96-18 08h: 0x77 ... ON setting of current terminals 96-19 to 96-24 09h: 0x00 ... PWM output priority 0Ah: 0x00 ... PWM output priority 0Bh: 0x00 ... PWM output priority 0Ch: 0x00 ... PWM output priority 0Dh: 0x00 ... PWM Output priority 0Eh: 0x00 ... PWM output priority 0Fh: 0x00 ... Fade function disabled 10h: 0x00 ... Fade function disabled 11h: 0x00 ... Fade function disabled 12h: 0x00 ... Forced on / off setting All off 13h: 0x00 ... All forced on / off settings off 14h: 0x00 ... All forced on / off settings off

The default values as described above are set for each LED driver 90 (w1 to w (n), b1 to b (m)) in step S113 of the 16 ms process of FIG.
FIG. 37 shows an example of the LED driver initialization process. FIG. 37 shows an initialization process for one LED driver 90. In step S113, the process of FIG. 37 is sequentially performed for each LED driver 90 (w1 to w (n), b1 to b (m)).

In step S901, the effect control CPU 200 turns on the enable signal (ENABLE) corresponding to the LED driver 90 that performs initialization. For example, the first slave address (for example, w1) is first targeted. In step S902, the slave address of the target LED driver 90 is output.
Further, the effect control CPU 200 outputs a data setting start register address in step S903. In this case, since data is written to the register addresses “00h” to “14h”, the data setting start register address = 00h.
In step S904, the effect control CPU 200 sequentially transmits data of default values corresponding to the register addresses “00h” to “14h”. In this process, the above-described default values are written in the register addresses “00h” to “14h” of the target LED driver 90. That is, the LED driver 90 is initialized.
When the above is completed, the enable signal (ENABLE) is turned off in step S905, and the slave address is incremented by 1 in step S906. That is, the next LED driver 90 can be designated. Then, the initialization process for one LED driver 90 is completed.

In this embodiment, as described above, two systems of serial data output are performed as the serial data output channels ch1 and ch2.
Although FIG. 37 shows the initialization process for one LED driver 90, for example, (n + m) LED drivers 90 (w1 to w (n), b1 to b (m)) are processed by the process of FIG. Initialization may be performed sequentially one by one.

  However, the LED drivers 90 (w1 to w (n), b1 to b (m) of the frame driver unit 61 and the panel driver unit 62 are performed by performing substantially simultaneous transmission using the serial data output channels ch1 and ch2. ) Can be made more efficient. That is, the same method as the LED drive data transmission described above can be adopted. For example, transmission is performed in parallel using serial data output channels ch1 and ch2, as in the example of LED drive data output in FIG. 32B. A processing example in that case is shown in FIG.

As the processing of FIG. 38, the effect control CPU 200 identifies the slave addresses of the serial data output channels ch1 and ch2 in step S951. In accordance with an example similar to FIG. 32B, an address code indicating “w1, b1” is specified.
Then, as loop processing LP5, the processing of steps S952 to S964 is executed in a loop for the number of driver numbers. If n <m, the loop process LP5 is performed m times.

In step S952, the effect control CPU 200 turns on the enable signal ENABLE in the serial data output channels ch1 and ch2.
In step S953, the production control CPU 200 transmits the data of the first transmission unit (1 byte) as the output of the serial data DATA of the serial data output channels ch1 and ch2, that is, in this case, the serial data structure shown in FIG. Sends and outputs the slave address of the first byte. The serial data output channels ch1 and ch2 are simultaneously transmitted in parallel.
When the transmission of one transmission unit is performed, in steps S954 and S955, the completion of transmission output for each serial data output channel ch1 and ch2 is waited.

When the transmission output completion for the serial data output channels ch1 and ch2 is confirmed, the effect control CPU 200 transmits and outputs the data setting start register address (SX) as data transmission of the next one transmission unit (1 byte) in step S956. To do. Since writing is performed to the register addresses 00h to 14h, SX = 00h is set. Also in this case, data transmission is performed simultaneously in parallel for the serial data output channels ch1 and ch2.
When the transmission in one transmission unit is performed, in steps S957 and S958, completion of transmission output for each serial data output channel ch1 and ch2 is awaited.

When it is confirmed in steps S957 and S958 that transmission output for the serial data output channels ch1 and ch2 is completed, the effect control CPU 200 performs register transmission (00h) to (14h) as data transmission of one transmission unit (1 byte) in step S959. Send default data to).
First, 1-byte default data transmission to the register address (00h) is simultaneously performed in parallel for the serial data output channels ch1 and ch2. In steps S960 and S961, the transmission output completion for the serial data output channels ch1 and ch2 is awaited.
If transmission completion is confirmed, transmission of step S959 is performed byte by byte until completion of transmission of default data from register addresses 00h to 14h is confirmed in step S962. Therefore, next, 1-byte default data transmission to the register address (01h) is performed for the serial data output channels ch1 and ch2. Further, after the transmission confirmation, default data transmission to the register address (02h) is performed. Thereafter, transmission completion standby → default data transmission to register address (03h) → transmission completion standby → default data transmission to register address (04h) → transmission completion standby— → default data transmission to register address (14h) → The process of waiting for transmission completion is performed.

  When the transmission output of default data to the register addresses 00h to 14h is completed, the enable signal ENABLE is turned off in step S963, and the target slave address is incremented by +1. Then, one loop process is completed.

Subsequently, as the second loop process, the processes of steps S952 to S964 are similarly performed for the LED driver 90 (w2) and the LED driver 90 (b2). Further, thereafter, as the third loop process, the processes of steps S952 to S964 are similarly performed for the LED driver 90 (w3) and the LED driver 90 (b3).
The LED driver initialization process of FIG. 38 is completed when the processes of steps S952 to S964 are performed m times. That is, initialization by outputting default data to the (n + m) LED drivers 90 is completed. Of course, if the number of LED drivers 90 mounted is different, the number of loops may be different.
In the above example, two serial data output channels ch1 and ch2 are used. However, when three or more serial data output channels are used, serial data (default data) are simultaneously used in parallel. What is necessary is just to make it transmit.

  As in the process of FIG. 38 described above, the drive signal output means (frame driver unit) of the first system (serial data output channel ch1) and the second system (serial data output channel ch2) also for the initialization process of the LED driver 90 61 and the board driver unit 62) transmit serial data of one transmission unit simultaneously. Then, after the transmission is completed, the next serial data of one transmission unit is transmitted substantially simultaneously to the drive signal output means of the first system and the second system. By performing the initialization process of the LED driver 90 in such a process, the time required for the entire initialization process can be shortened, and the processing load on the effect control CPU 200 can be reduced.

In the present embodiment, as described above, each LED driver 90 is initialized by serial data transmission of default data as initial setting data. As a result, each LED driver 90 has a gradation value indicated by the LED drive data. Accordingly, the LED 120 connected to the current terminals 96-1 to 96-24 is set to a state where the LED 120 is turned off, turned on, and a light emission drive signal for realizing light emission luminance at the time of lighting is output.
That is, the above-mentioned default value (= on data) is always set by the initialization process for the register addresses 05h to 08h, which are on / off setting units for the current terminals 96-1 to 96-24, 1 to 96-24 are all turned on, and the PWM priority is set by setting default values of the register addresses 09h to 14h, and the fade function and the forced on / off function are invalidated. Therefore, each LED driver 90 performs PWM control based on the gradation values (lighting data values) written in the register addresses 15h to 2Ch, which are gradation value setting units, and current terminals 96-1 to 96-24. Then, a light emission drive current having a current amount corresponding to the gradation from the current is passed.

That is, in the LED drive data output process of FIG. 28 performed in step S115 of FIG. 13, 16 of “00h” “10h” “20h”... “F0h” as LED drive data written to the register addresses 15h to 2Ch. Gradation data is transmitted, but when transmitting LED drive data, only data of 16 gradations of “00h”, “10h”, “20h”... “F0h” is transmitted. The controlled lighting (10h to F0h) is executed.
When this is viewed from the production control CPU 200 side, it means that all of the light emission brightness control at the time of turning off, turning on, and turning on can be executed by the lighting data of 0h to Fh.
As a result, the effect control CPU 200 can realize the LED light emission control with simple lighting data setting, the processing load is small, and the data capacity required for the control can be reduced to only the lighting data. Reduction of consumption is also realized.

In summary, the effect control unit 51 performs a process in which the register addresses 05h to 08h, which are on / off setting units, are always set to on, and generates LED drive data including gradation values according to the gaming state. By transmitting to the LED driver 90 and setting the gradation values to the register addresses 15h to 2Ch which are gradation value setting units, 16 gradations of “00h”... “F0h” at the time of LED drive data transmission By simply transmitting the data, it is possible to execute control from turning off to lighting with gradation controlled.
In the present embodiment, initialization processing is performed every 16 ms as processing for always setting the register addresses 05h to 08h, which are on / off setting sections, but is turned off only by transmitting 16-gradation data. In order to control from the gradation to the lighting with gradation control, it is only necessary that the register addresses 05h to 08h are always set to ON. Therefore, for example, the effect control CPU 200 may perform initialization processing at the beginning of power-on, for example, and only set the register addresses 05h to 08h to ON. This is also an example of processing in which the on / off setting unit is always on.

  In the above embodiment, the LED driver 90 is a gaming state that defines the first register (register addresses 15h to 2Ch) in which the LED driving data that changes according to the gaming state is set, and the operation of the LED driver 90. And a second register (register addresses 00h to 14h) in which fixed data (initialization data) that does not change is set. Then, the effect control unit 51 sets the LED drive data of the first register every predetermined cycle (every 16 ms processing), and sets the fixed data of the second register every predetermined cycle (every 16 ms processing). From the viewpoint of each LED driver 90, initialization data is set in the second register every 16 ms, and LED drive data (gradation value) is set in the first register every 16 ms.

In the case of the present embodiment, the set values of the register addresses 00h to 14h are always the above-described default values during the game. Therefore, the process for setting the default value in the second register as the initialization process may be performed once at the time of startup. However, the set values of the register addresses 00h to 14h may be destroyed or lost due to noise or the like, and the operation of the LED driver 90 may not be the operation intended by the LED drive data. On the other hand, in the present embodiment, by performing the initialization process periodically, even if the set values of the register addresses 00h to 14h are destroyed, they can be restored immediately and become the original initialization state. Thereby, an accurate LED light emission operation based on LED drive data is always executed. Thus, the output operation of the light emission drive signal based on the LED drive data can be stably maintained in a normal state.

<7. Second Embodiment>

Next, the driver configuration as the second embodiment will be described. Note that configurations and processes that are the same as those in the first embodiment are omitted, and only different points will be described.
FIG. 39 shows a connection configuration of the effect control unit 51 (effect control CPU 200) and the LED driver 130 in the same format as in FIG. 4 in the first embodiment.
In this example, the effect control CPU 200 also uses three serial data output channels ch1, ch2, and ch3. Two systems (frame driver unit 61 and panel driver unit 62) are provided as the LED driver 130, and one system is provided as the motor driver 130M. (Motor driver unit 70) is provided.
Serial data transmission to the plurality of LED drivers 130 as the frame driver unit 61 is performed by the serial data output channel ch1.
Serial data transmission to the plurality of LED drivers 130 as the panel driver unit 62 is performed by the serial data output channel ch2.
Serial data is transmitted to a plurality of motor drivers 130M as the motor driver unit 70 through the serial data output channel ch3.

The signal lines of the serial data output channels ch1, ch2, and ch3 include a latch signal line that supplies a latch signal LATCH, a clock line that supplies a clock signal CLK, an enable signal line that supplies an enable signal ENABLE, light emission drive data, or a motor. A data line for supplying serial data DATA as drive data is provided.
The latch signal LATCH, the clock signal CLK, and the enable signal ENABLE line are supplied in parallel to the plurality of LED drivers 130 (or motor driver 130M) constituting the frame driver unit 61 (or the panel driver unit 62 and the motor driver unit 70). Is done. On the other hand, the serial data DATA is the head LED driver 130 (or motor driver 130M) of the plurality of LED drivers 130 (or motor driver 130M) constituting the frame driver unit 61 (or the panel driver unit 62 and the motor driver unit 70). ) And sequentially transferred to the subsequent LED driver 130 (or motor driver 130M).
That is, each LED driver 130 (or motor driver 130M) in one system has serial data DATA input / output sequentially connected in series, and serial data DATA from the effect control CPU 200 is the first LED in one system. The data is sequentially transferred from the driver 130 (or motor driver 130M) to the terminal LED driver 130 (or motor driver 130M), and each LED driver 130 (or motor driver 130M) receives serial data based on the latch signal from the effect control CPU 200. It is configured to capture DATA.

As each LED driver 130 and motor driver 130M, for example, “BD7851FP (manufactured by ROHM)” which is a 16-bit constant current LED driver can be used, and for example, 16 constant current terminals are provided.
Therefore, a single LED driver 130 can output a maximum of 16 LED driving currents. One “series” refers to a group of one or more LEDs connected in series or in parallel to one current output terminal.
The number of LED drivers 130 in the frame driver unit 61 is determined by the number of LED sequences arranged on the frame side (the number of sequences of the light emitting units 20w).
The number of LED drivers 130 in the panel driver unit 62 is determined by the number of LED sequences (number of sequences of the light emitting units 20b, 20Z, 20H, and 20J) arranged on the panel side.
The number of motor drivers 130M in the motor driver unit 70 is determined by the number of motors of the movable body accessory.

FIG. 40 shows a schematic configuration example of a main part of the LED driver 130. In the following, description of the configuration of the motor driver 130M is omitted, but it is the same as the LED driver 130.
The LED driver 130 includes a 16-bit shift register 131, a latch unit 132, an output gate unit 133, and constant current terminals 139-1 to 139-16.
16 series of LEDs 120 are connected to all (or part of) the constant current terminals 139-1 to 139-16. Note that the drawing shows a simplified state in which one LED 120 is connected to one series of constant current terminals 139, but a configuration in which a plurality of LEDs are connected to one series of constant current terminals 139 (for example, series connection). ) Is also possible.

In the LED driver 130, the serial data DATA is supplied to the terminal 134 and the clock signal CLK is input to the terminal 135 with respect to the shift register 131.
The serial data DATA from the effect control CPU 200 is supplied to the terminal 134 of the leading LED driver 130 of each system. The terminal 134 of the second and subsequent LED drivers 130 of each system is connected to the terminal 136 of the previous LED driver 130.
The shift register 131 is composed of, for example, 16 stages of D flip-flop circuits, and takes in the serial data DATA from the terminal 134 at the timing of the clock signal CLK and shifts the data held in each D flip-flop circuit to the subsequent stage. Go. The output of the 16th stage D flip-flop circuit is supplied from the terminal 136 to the shift register 131 from the terminal 134 of the next LED driver 130.

Each LED driver 130 is supplied with a latch signal LATCH from the effect control CPU 200 from the terminal 137 to the latch unit 132. The latch unit 132 latches the values of the 16 D flip-flop circuits in the shift register 131 at the timing when the latch signal LATCH is input. 16-bit data is latched.
The 16-bit data latched by the latch unit 132 is supplied to the output gate unit 133.
Note that the LED driver 130 of each system has a configuration in which serial data DATA is sequentially transferred. The effect control CPU 200 receives the LED drive data (16 bits) for the last LED driver 130, the LED drive data (16 bits) for the previous LED driver 130, ... the LED drive data (16 bits) for the first LED driver 130. Output sequentially. Each LED driver 130 is supplied to itself by outputting a latch signal LATCH in parallel to all LED drivers 130 in the system at the timing when 16-bit LED drive data is transferred to the first LED driver 130. Further, 16-bit LED drive data can be taken into the latch unit 132.

When the enable signal ENABLE from the terminal 138 is ON, the output gate unit emits light from the LEDs 120 connected to the constant current terminals 139-1 to 139-16 based on the 16-bit data latched by the latch unit 132. To supply current. Each latched 16-bit bit becomes a current control value for each of the 16 constant current terminals 139-1 to 139-16.
With such a configuration, each LED driver 130 drives a maximum of 16 connected LEDs 120.

Note that some of the LED drivers 130 of the panel driver unit 62 perform LED light emission driving for the light emitting units 20Z, 20H, and 20J for situation presentation in addition to LED light emission driving for the light emission unit 20b for presentation. That is, in some LED drivers 130, any one of the light emitting units 20Z, 20H, and 20J is connected to any one of the constant current terminals 139-1 to 139-16.
Although the detailed description is omitted because it is substantially the same, in practice, in some LED drivers 130, as described in FIG. 7, the symbol identifying light emitting unit 20Z, the holding number displaying light emitting unit 20H, Any of the gaming state notification light emitting units 20J is connected.
In this case, as in FIG. 7, when a plurality of LEDs 120 as the production light emitting unit 20 b are connected in series, the second power supply voltage (for example, 12 V) is connected as a power supply for light emission driving, As the light emitting unit 20Z, the holding number display light emitting unit 20H, and the gaming state notification light emitting unit 20J, one LED 120 is used, and the first power supply voltage VCC1 (for example, 5V) used as the power source by the LED driver 130 is used. What is necessary is just to be connected so that it may be used as a power supply for light emission drive.

In the second embodiment, the effect control CPU 200 sends serial data of one transmission unit to the first and second system drive signal output means (the frame driver unit 61 and the panel driver unit 62) substantially simultaneously. To output automatically.
The LED output processing as the second embodiment will be described with reference to FIG.
Similarly to the case described in the first embodiment, the LED drive data generated in the LED data update process in step S114 in FIG. 13 is output to each LED driver 130 in the process in step S115.
The LED drive data generated by the LED data update process includes dummy data arranged in the area corresponding to the constant current terminal to which the light emitting units 20Z, 20H, and 20J for presentation are connected in the original lamp data. Then, the dummy data is updated by the processing as shown in FIG. 27, so that the light emission drive information for presentation and the light emission drive information for status presentation (for symbol identification, for holding number display, for game state notification) are synthesized. It has been made.

In step S851, the effect control CPU 200 specifies the head address of the LED drive data (for example, the output data buffer corresponding to the output data buffer of FIG. 32A of the first embodiment) in each of the serial data output channels ch1 and ch2. In the first embodiment, the LED drive data for one LED driver 90 is an example of 4 × 24 bits, but in the second embodiment, the LED drive data for one LED driver 130 is 16 bits, for example. Become.
In step S852, the effect control CPU 200 turns off the latch signal LATCH of the serial data output channels ch1 and ch2. In step S853, the enable signal ENABLE of each serial data output channel ch1 and ch2 is turned on.

Then, as the loop process LP4, the processes of steps S854 to S857 are repeated as many times as necessary.
For the sake of explanation, it is assumed that the number of LED drivers 130 is five for the frame driver unit 61 and six for the panel driver unit 62. That is, the serial data output channel ch1 transmits to the five LED drivers 130, and the serial data output channel ch2 transmits to the six LED drivers.
Note that writing to the transmission data register is performed 8 bits at a time, while 16-bit data is transmitted to one LED driver 130. Therefore, two transmissions are required for one LED driver 130. Therefore, writing to the transmission data register is 10 times for the serial data output channel ch1 and 12 times for the serial data output channel ch2.
As the loop processing LP4, the loop is performed as many times as the number of LED drivers 130 (six) and the number of transmissions of the serial data output channel ch2 (= 12 times).

As the loop process LP4, the effect control CPU 200 outputs serial data DATA (8-bit writing to the transmission data register) as transmission in one transmission unit of the serial data output channel ch1 in step S854.
At substantially the same time, the serial data DATA of the serial data output channel ch2 is output (8-bit writing to the transmission data register) in step S855.
As described above, the serial data output channels ch1 and ch2 simultaneously transmit serial data DATA (16 bits × number of LED drivers) of each system.
In steps S856 and S857, the effect control CPU 200 waits for the completion of transmission of the serial data DATA in the serial data output channels ch1 and ch2.
When transmission is completed, the processing of steps S854 and S855 is performed again.

Note that due to the difference in the number of LED drivers 130, a serial data output channel is generated that completes the output of all data before others. In the above example, the serial data output channel ch1 is completed by performing step S854 10 times, and the serial data output channel ch2 is completed by performing step S855 12 times.
Therefore, in this example, for the serial data output channel ch1, there is a case where the serial data output in step S854 is not performed at the number of loops after completion.
Note that it is natural to control the clock signal CLK (for example, mask) so that the data shift in the shift register 131 is not performed except during actual serial data transmission.

When the transmission is completed (in the above example, the loop processing LP4 is completed 12 times as loop processing LP4), the latch signal LATCH of the serial data output channels ch1 and ch2 is turned on in step S860. As a result, serial data DATA (16-bit LED drive data) is captured in all the LED drivers 130. When the latch is performed, in step S861, the latch signal LATCH of the serial data output channels ch1 and ch2 is turned off.
At this point, the enable signal ENABLE is on. For example, the output gate unit 133 of each LED driver 130 drives the constant current terminals 139-1 to 139-16 by the LED drive data latched by the latch unit 132 when the enable signal ENABLE from the terminal 138 is OFF. It is said that. Therefore, the effect control CPU 200 turns off the enable signal ENABLE in step S862. Accordingly, each LED driver 130 performs light emission driving of the connected LED 120 based on the LED driving data written this time.

Also in the second embodiment, the effect control CPU 200 has the first system (serial data output channel ch1) and the second system (serial data output channel ch2) drive signal output means (frame driver unit 61, panel driver unit 62). Transmits serial data simultaneously.
Then, after the transmission is completed, each LED driver 130 is caused to execute a latch.
As a result, the time required for the entire serial data transmission operation can be shortened, and the processing load on the rendering control CPU 200 can be reduced.

For example, conventionally, the processing corresponding to steps S854 to S860 in FIG.
(ST1) Serial data transmission of ch1 (writing to transmission data register)
(ST2) Ch1 transmission output completion waiting ... The above is the required number of loops (STx) ch1 latch signal LATCH is on

(STx + 1) ch2 serial data transmission (writing to transmission data register)
(STx + 2) ch2 transmission output completion waiting ... The above is performed as the required number of times of the loop (STy) ch2 latch signal LATCH on.
In this case, a waiting time occurs in each of the serial data output channels ch1 and ch2, and the transmission processing efficiency is poor.
In contrast, in this embodiment,
(S854, S855) Serial data transmission start from ch1 and ch2 (S856, S857) Ch1 and ch2 transmission output completion wait (S860) Both serial data output channels ch1 simultaneously, such as the latch signal LATCH on of ch1 and ch2 , Ch2 is performed, the processing is made efficient.

Particularly in the case of the second embodiment, serial data for one system of drive signal output means (frame driver unit 61, panel driver units 62A and 62B) is the number of LED drivers 130 included in the system × 16. A unit of bits.
Therefore, the entire standby time is until the serial data transfer to the drive signal output means having the largest number of LED drivers 130 is completed. That is, in the above example, data transmission to all the serial data output channels ch1 and ch2 can be completed within the time required for the serial data output channel ch2 having the largest number of LED drivers 130.
Thereby, the total time required for serial data transmission can be remarkably shortened as compared with the case of performing output to individual drive signal output means and standby.

Desirably, the number of LED drivers 130 in the drive signal output means of each system should be the same. Alternatively, the same number may be provided by providing dummy drivers. Then, the effect control CPU 200 can start serial data transmission from the two serial data output channels ch1 and ch2 at the same time, complete the transmission at the same time, can be latched at the timing immediately after that, and the processing becomes easy.
In FIG. 41, after confirming the completion of transmission in each of the serial data output channels ch1 and ch2 in steps S856 and S857, the latches of all systems are executed in step S860. However, in reality, the serial data output has been completed. The serial data output channel may be latched on.
When the LED driver 130 has three or more systems, for example, the frame driver unit, the first panel driver unit, and the second panel driver unit 62 are connected to the serial data output channels ch1, ch2, and ch3, respectively. In this case, the processing of FIG. 41 may be performed for the three serial data output channels ch1, ch2, and ch3. The same applies to the case of four or more systems.

In the second embodiment, the drive signal output means (frame driver section 61) of the first system sends an LED drive signal to the lamp section 63 (light emitting section 20w) which is an effect means provided in the front frame 2. It comprises a plurality of driver circuits (LED drivers 130) for output. Second-system drive signal output means (the board driver section 62 is a plurality of driver circuits (LED drivers 130) that output LED drive signals to the lamp section 64 (light emitting section 20b), which is an effect means provided in the game board 3. It consists of
With this configuration, all the LED drivers 130 of the frame driver unit 61 correspond to the light emitting unit 20w on the frame side, and all the LED drivers 130 of the panel driver unit 62 correspond to the light emitting units 20b, 20Z, 20H, and 20J on the panel side. Accordingly, it is possible to realize simplification of wiring, efficiency, ease of production control setting, and the like.

<8. Summary and Modification>

According to the pachinko gaming machine 1 of the above embodiment, the processing for light emission control can be made efficient, and the light emission control processing load can be reduced.
In addition, the pachinko gaming machine 1 according to the embodiment includes a light emitting unit 20w and 20b for production, a light emitting unit for presenting a situation (light emitting unit for symbol identification 20Z, light emitting unit 20H for holding number display, and light emitting unit 20 for game state notification ), And a light emission control means (effect control unit 51) for controlling the light emission of each light emitting unit for production and presentation of the situation. The effect control unit 51 as the light emission control means performs a determination process (scenario update process S110) for determining a light emission effect at an appropriate timing, creates light emission drive information, and stores the light emission drive information as a light emission drive data storage unit (output). A creation process (LED drive data update process S114) stored in the data buffer) and an output process (LED output process S115) for outputting a drive signal based on the light emission drive information stored in the light emission drive data storage unit are performed at predetermined intervals. A light emission effect is realized by performing (every 16 m processing). In the creation process, in the state in which the determined light emission effect is executed, effect light emission drive information (effect LED drive data) for the effect light emitting units 20w and 20b is obtained based on the lamp data corresponding to the effect to be executed. Create (steps S701 to S720 in FIG. 26). Further, according to the game situation, the situation presentation light emission drive information (variable symbol identification, hold number display, game status notification LED drive data) for the situation presentation light emitting units 20Z, 20H, 20J is created (S721). ), The combination of the production light emission drive information and the situation presentation light emission drive information is used as light emission drive information (LED drive data) for one timing in the predetermined period.
As a result, the light emission drive control of the light emission unit for production and the light emission unit for situation presentation (for changing symbol identification, holding number display, and game state notification) is executed in a common output process, so production control The processing of the unit 51 is made efficient, so that the processing burden can be reduced and the speed of processing can be realized. This is because there is no need to output the LED drive data for the fluctuating symbol identification, the hold number display, and the game state notification at a different timing from the LED drive data for presentation, and a separate output process is performed for presenting these situations. This is because it does not have to be performed.
In addition, by using a common output process, a light emitting unit (LED 120) for presentation and a light emitting unit (LED 120) for presenting a situation (for changing symbol identification, for holding number display, for game status notification) are used as a common LED driver. It is easy to control when connecting to 90 (130). This is because it is not necessary to separately transfer the LED drive data for presenting the situation to the specific LED driver 90 (130).

The pachinko gaming machine 1 according to the embodiment includes a main control unit 50 that outputs a control command related to a game operation, and the effect control unit 51 creates light emission drive information and stores the light emission drive information in light emission drive data. In the creation process stored in the section, in the state where the light emission effect determined in the determination process is executed based on the control command, the light emission drive information for the effect for the light emission unit for the effect is generated based on the lamp data corresponding to the effect to be executed. create. In addition, according to the gaming situation notified by the control command, the situation presentation light emission drive information for the situation presentation light emitting unit is created. A combination of the production light emission drive information and the situation presentation light emission drive information is used as light emission drive information (LED drive data) for one timing in the predetermined period.
As a result, efficient processing is realized for the effect light emission by the effect instruction from the main control unit 50 and the light emission for presenting the situation (symbol variation state, number of holds, game state) notified from the main control unit 50. The That is, when the main control unit 50 sequentially instructs a light emission effect and the main control unit 50 sequentially indicates a game situation, the effect control unit 51 can efficiently perform the light emission control process for the effect and the situation presentation. .

Further, in the embodiment, in the state where the plurality of light emission effects determined in the determination process are executed, the production light emission drive information for the effect light emitting unit is created based on a plurality of types of lamp data corresponding to the effect to be executed. . That is, the light emission drive information for production reflecting the light production effects of a plurality of layers is generated based on the lamp data registration information (see FIG. 22B) of the lamp channels dwCH0 to dwCH15. In addition, according to the game situation (symbol variation state, the number of holds, the game situation), the light emission drive information for status presentation to the light emitting units 20Z, 20H, 20J Data) and a combination of the production light emission drive information and the situation presentation light emission drive information is used as light emission drive information (LED drive data) for one timing in the predetermined cycle.
Accordingly, it is possible to efficiently execute light emission driving based on a plurality of designated various types of light emission effects, light emission driving for changing symbol identification, display of the number of holds, and game state notification.

In the embodiment, the production control unit 51 selects the lamp data based on the timer management defined by the light emission production determined in the determination process in the creation process, and produces the light emission for production based on the selected lamp data. Production light emission drive information for the production is created. That is, in the processing of FIGS. 20 and 21, lamp data is selected based on the timer management based on the designated main scenario and sub-scenario, and the light emission driving information for effect is executed so that the light effect represented in the lamp data is executed. Create In addition to this, the situation presentation light emission drive information for the situation presentation light emitting unit is created according to the game situation, and the combination of the production light emission drive information and the situation presentation light emission drive information for one timing in the predetermined period. Light emission drive information (LED drive data).
As a result, the light emission effect defined in the scenario is appropriately realized, and the light emission drive control of the light emitting unit for presenting the situation can also be efficiently executed.

Also, in the creation process, after generating the light emission drive information for the production of a predetermined size for one timing, the light emission drive information for situation presentation (for changing symbol identification, for holding number display, for game state notification) is created, By rewriting the specific data area (DBzh, DBj in FIG. 32) in the light emission drive information for production with the light emission drive information for status presentation, light emission drive information of a predetermined size for one timing is generated (FIG. 26, FIG. 26). (See FIG. 27).
That is, by preparing a specific data area and only updating a part of the light emission drive information for production with the light emission drive information for changing symbol identification, the light emission drive information that combines the production for production and the situation presentation can be generated. The light emission drive data for performing the light emission drive for both the production and the situation presentation can be generated by an easy process.

In addition, lamp data is set so that dummy data is arranged in the specific data area (DBzh, DBj in FIG. 32) of the light emission drive information for effect. That is, the areas Azh and Aj in FIG. In the creation process, the dummy data in the specific data area is rewritten with the light emission driving information for variation symbol identification.
By arranging dummy data as the data of the lamp data areas Azh and Aj arranged in the specific data areas DBzh and DBj, the light emission drive information for situation presentation is synthesized without affecting the light emission control for the production. it can. For this reason, it is easy to synthesize light emission drive data for presentation and situation presentation, and an increase in processing load can be avoided.

Further, in the pachinko gaming machine 1, light is emitted to the light emitting unit 20b for effect and the light emitting units 20Z, 20H, and 20J for status presentation based on the drive signal (LED drive data) output in the output process of the effect control unit 51. One or a plurality of LED drivers 90 (130) for supplying a driving current are provided. For example, the LED driver 90 has slave addresses “b2” and “b3”.
These specific LED drivers 90 (b2) and (b3) include a plurality of LEDs 120 so as to supply a light emission driving current to both the light emitting unit 20b for performance and the light emitting units 20Z and 20H (or 20J) for presenting the situation. Is connected. Correspondingly, in the production process of the production control unit 51, production light emission drive information and status presentation are included in the light emission drive information that is the basis of the drive signal output to the specific LED driver 90 (b2) (b3). Light emission driving information is included. For example, on the output data buffer, a part of the area corresponding to the LED drivers 90 (b2) and (b3) is set as specific data areas DBzh and DBj, and the light emission drive information for situation presentation is arranged.
Thereby, there is no need to separate the LED driver 90 for presentation and for situation presentation (for changing symbol identification, for holding number display, for gaming state notification), and an efficient circuit configuration is possible.

Further, in the production process of the production control unit 51, a state in which a plurality of types of lamp data corresponding to a plurality of light emission productions determined in the decision process based on the control command are set in a plurality of hierarchies in which priorities are set (see FIG. In the lamp data dwCH0 to dwCH15 of the lamp data registration information of 22B), the light emission driving information for effects for the light emitting section for effects is displayed in order from the lamp data designated in the hierarchy (lamp channel) having the lowest priority. By updating to a value corresponding to, production light emission drive information reflecting priority is created (loop processing LP2 in FIG. 26).
That is, when a plurality of types of lamp data corresponding to a plurality of lighting effects are set in a plurality of hierarchies with priorities set, the light emission driving information for effects reflecting the lamp data is overwritten in order from the lowest priority. By creating as described above, it is possible to realize the presentation control reflecting the priority order with a simple process, and further, by combining the light emission driving signal for the situation presentation with the light emission driving information for the presentation, the light emitting section for the presentation and the situation presentation The control of the light emitting unit can be easily shared.

Further, in the production process of the production control unit 51, in the state of executing the light emission production determined in the determination process based on the control command, three gradations for the production light emitting unit based on the lamp data corresponding to the production to be executed. The light emission drive information for presentation that expresses the above gradation values is created, and the light emission for situation presentation that expresses two gradations of lighting and extinguishing with respect to the light emitting unit for situation presentation according to the gaming situation notified by the control command Drive information is created, and light emission drive information obtained by combining these is generated.
In particular, the light emission drive information for performance is generated as data of 3 gradations or more (for example, 16 gradations), and an effect of enhancing game play is possible by expressing a large number of gradations. On the other hand, since 2 gradations are sufficient for the purpose of situation presentation, the situation presentation light emission drive signal is generated as information of two gradations of light emission / extinguishment, thereby facilitating generation of light emission drive information for situation presentation. To do. For example, the light emission drive information for situation presentation can be easily generated assuming that “0” or “F” is sufficient.

  Also, in this case, a specific data area (DBzh, DBj in FIG. 32) is prepared, and only for updating the presentation light emission drive information for the situation presentation, for the presentation and the situation presentation. The synthesized light emission drive information is generated. In particular, for the specific data area, the light emission drive information that combines the effect and the identification can be generated simply by updating the binary for situation presentation (for example, “0” or “F”). Further, for example, by using a binary value of “0” or “F”, it is possible to easily incorporate the light emission drive information for situation presentation into a specific area having the number of bits that can express three or more gradations.

In the pachinko gaming machine 1 according to the embodiment, in the output process of the effect control unit 51, the light emission drive data storage unit stores the plurality of LED drivers 90 including the specific LED drivers 90 (b2) and (b3). A drive signal based on the light emission drive information for one timing is output from a predetermined serial port (ch2).
Accordingly, a plurality of light emitting units are connected to a specific LED driver 90 so as to generate a light emission drive current for both the light emitting unit 20b for presentation and the light emitting units 20Z and 20H (or 20J) for presenting the situation. Correspondingly, the light emission drive control of the light emitting unit for presentation and the light emitting unit for situation presentation is executed in a common output process. In addition, it is possible to realize light emission driving including production and presentation by a single port output.
In other words, even when the specific LED driver 90 (b2) (b3) adopts a circuit configuration in which both the light-emitting unit for presentation and the light-emitting unit for situation presentation are driven to emit light, the specific LED driver 90 ( It is possible to prevent the light emission control for b2) and (b3) from becoming complicated.

  Further, by generating the light emission drive information for one timing so that the light emission drive information based on the drive signal output to the specific light emission driver includes the effect light emission drive information and the situation presentation light emission drive information. At each timing, light emission drive information obtained by synthesizing the light emission drive information for presentation and the light emission drive information for situation presentation is generated, and the stage light emission and the situation presentation scheduled issue by the specific LED driver 90 (b2) (b3) are appropriately executed. be able to.

In the pachinko gaming machine 1 according to the embodiment, the specific LED driver 90 (b2) (b3) operates with the first power supply voltage VCC1 as the power supply voltage, and is connected to the specific LED driver 90 (b2) (b3). A second power supply voltage VCC2 higher than the first power supply voltage VCC1 is connected to the effected light emitting section 20b in order to flow a light emission driving current, and light is emitted to the light emitting sections 20Z and 20H (or 20J) for situation presentation. The first power supply voltage VCC1 is connected in order to flow the drive current.
In the production light-emitting section, a plurality of LEDs 120 are connected in series due to demands for decoration, and a high voltage (for example, 12 V) is necessary for the power source of the drive current. The LED driver 90 is driven at a relatively low voltage (for example, 5V). Considering the situation-presenting light emitting units 20Z, 20H, and 20J here, it can be usually realized by one LED, and 12V is not necessary for the power supply. Conversely, if it is driven at 12V, a large resistance is required and heat is applied. End up. Also, providing another power source complicates the circuit. Therefore, by using the first power supply voltage VCC1 for the light emission drive of the status presentation light emitting units 20Z, 20H, and 20J, it is possible to prevent heat and circuit complexity.

In addition, the light emitting unit 20b for presentation connected to the specific LED driver 90 (b2) (b3) has a plurality of LEDs 120 connected in series, and the light emitting units 20Z, 20H (or 20J) for presenting the situation One LED 120 is connected.
It is preferable to use a series connection of a plurality of LEDs for the effect light emitting unit 20b for the purpose of enhancing the playability and for the light emission range. In this case, it is preferable to apply a method using the second power supply voltage VCC2 in order to perform sufficient light emission driving.
In addition, the effect control unit 51 is configured such that the light emitting unit 20b for production emits light with a resolution of three gradations or more, and the light emitting units 20Z and 20H (or 20J) for situation presentation emit light with two gradations of lighting and extinguishing. Outputs LED drive data for controlling the light emission of each light emitting section.
The light emitting unit 20b for performance preferably has a resolution of 3 gradations or more for the effect of enhancing game play. On the other hand, since the situation-providing light emitting units 20Z and 20H (or 20J) can sufficiently present the situation by lighting / flashing / extinguishing, there are only two gradation levels of lighting and extinguishing. The drive information can be easily generated.

Although the embodiment has been described above, the present invention is not limited to the example given in the embodiment, and various modifications and application examples are conceivable.
As the lamp units 63 and 64 using LEDs or the like, an example of one system (one serial data output channel) on the frame side and one system on the panel side is given, but it is of course not limited thereto. A plurality of systems may be provided for the frame-side lamp unit 63, and a plurality of systems may be provided in the panel-side lamp unit 64.
Further, the light emitting unit 20b on the board side and the light emitting unit 20w on the frame side may be mixed in one system.
Moreover, the LED driver 90 which drives the light emission part 20w by the side of a frame and the light emission parts 20Z, 20H, and 20J for presentation may be provided.
The situation presentation light emitting unit also includes an error notification light emitting unit (for example, an error notification LED). That is, the same light emission control as that of the above-described variation symbol identifying light emitting unit 20Z, the hold number display light emitting unit 20H, and the gaming state notification light emitting unit 20J can be performed on the error notification light emitting unit.

In addition, serial data transmission of LED drive data in the embodiment is serial data transmission for other drive control, for example, serial to motor driver unit 70M (130M) for driving movable body accessory motor 65 such as a stepping motor or solenoid. It can also be applied to data transmission.
Moreover, although the present invention has been shown as being applied to a ball game machine such as the pachinko gaming machine 1, it can also be applied to a spinning-type game machine (so-called slot machine).
For example, serial data transmission of LED drive data may be performed by using the decoration LED on the front side of the casing of the slot machine and the backlight LED of the reel as the first system and the second system, respectively. Alternatively, the upper part and the lower part on the front side of the housing may be divided into serial data transmission systems. In addition, on the one or more serial data transmission systems, the light emission drive of the light-emitting section for situation presentation can be performed in the same manner as in the embodiment.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 20w, 20b Light emission part 20H Reservation number display part 20J Game state alerting part 20Z Fluctuation symbol identification part 32 Liquid crystal display device 33 Symbol display part 41 Upper start opening 42 Normal variation winning device 42a Lower start opening 43 General winning opening 44 Gate 45 First special variable winning device 46 Second special variable winning device 50 Main control board 50
51 Production control board 51
52 LCD control board 61 Frame driver part 62 Panel driver part 63, 64 Light emitting part 90, 130 LED driver 120 LED
200 Production control CPU
201 Production control ROM
202 Production control RAM

Claims (4)

A light emitting part for production;
A light emitting unit for displaying the number of holds;
Light emission control means for controlling the light emission of each light emitting part for the production and the number of hold display,
With
The light emission control means includes
While performing a determination process to determine the lighting effect at an appropriate timing,
Creation processing for creating light emission drive information and storing the light emission drive information in a light emission drive data storage unit;
An output process for outputting a drive signal based on the light emission drive information stored in the light emission drive data storage unit;
Is configured to achieve a light-emitting effect by performing a predetermined cycle,
In the creation process, in the state of executing the light emission effect determined in the determination process, the production light emission drive information for the effect light emitting unit is created based on the lamp data corresponding to the effect to be executed, and the number of holds Depending on the state, the number-of-holds-display-light-emitting drive information for the number-of-holds-display light-emitting unit is created, and a combination of the effect-use light-emitting drive information and the number-of-holds-display-light-emitting drive information is one timing in the predetermined period. A game machine with light emission drive information for minutes. In the creation process, after generating the light emission drive information for presentation of a predetermined size corresponding to one timing, the light emission drive information for holding number display is created, and a specific data area in the light emission drive information for presentation is displayed in the hold number display The gaming machine according to claim 1, wherein the light emission drive information of a predetermined size for one timing is generated by rewriting the light emission drive information for use. The lamp data is set so that dummy data is arranged in the specific data area of the light emission drive information for production,
The gaming machine according to claim 2, wherein in the creation process, dummy data in the specific data area is rewritten with the light emission driving information for holding number display. Based on the drive signal output in the output process, one or a plurality of light emission drivers for supplying a light emission drive current to the light emitting unit for production and the light emitting unit for variable symbol identification,
The one or a plurality of specific light emitting drivers are connected to the plurality of light emitting units so as to supply the light emission driving current to both the light emitting unit for presentation and the light emitting unit for displaying the number of holds.
2. In the creation process, the light emission drive information that is a basis of a drive signal output to the specific light emission driver includes the effect light emission drive information and the hold number display light emission drive information. The gaming machine according to claim 3.

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