JP2016140109A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of performing a decimation output by addition and/or addition average between pixels connected with different vertical signal lines without causing increase in circuit scale, operation speed, or power consumption.SOLUTION: The solid-state image pickup device includes: a pixel array unit; an ADC circuit provided in correspondence to each of vertical signal lines; and a switching unit for switching an analog signal to be output through each vertical signal line to a digital signal with either one of an ADC circuit provided in correspondence to a signal line to which an analog signal is transmitted and an ADC circuit provided in correspondence to a signal line other than a signal line to which an analog signal is transmitted.SELECTED DRAWING: Figure 13

Description

  The present technology relates to a solid-state imaging device.

  The pixel addition method in the solid-state imaging device includes an FD addition method in which the charges of the pixels are summed and output on the floating diffusion (hereinafter referred to as FD) of the pixel, and a plurality of pixel signals are simultaneously read out to the readout line. Source follower addition method for adding in load MOS circuit connected to read signal line, counter addition method for performing digital addition in counter circuit in column ADC circuit, and multiple capacitors in input stage of comparator in column ADC circuit A capacity addition system that connects in parallel and adds signals of a plurality of vertical signal lines is known.

  Here, pixel addition in the thinning-out readout of the Bayer array will be described with reference to FIGS. FIG. 29 is a diagram illustrating an example of pixel addition performed by the column ADC circuit when a Bayer array is used as the color filter array, and FIG. 30 is a timing chart at the time of pixel addition in the column ADC circuit of FIG. FIG. 31 is a readout image when the column ADC circuit of FIG. 29 is used.

  In the Bayer array shown in FIG. 29, G color filters that are also used as the main component of the luminance signal are arranged in a checkered pattern every other pixel, and the other R and B color filters are arranged in the vertical and horizontal directions for the remaining pixels. A checkered arrangement of pitches is used, and the R and B color filters are arranged at an angle of one pixel. Further, the pixel array shown in FIG. 2 is a pixel unit (hereinafter referred to as an FD sharing pixel unit) that shares FD by connecting 4 pixels of 2 × 2 in the vertical and horizontal directions via a floating diffusion (hereinafter abbreviated as FD). It constitutes.)

  When performing addition / addition averaging in the configuration of FIG. 29, for example, R1 and R2, G1 and G3, G2 and G4, B1 and B2, R3 and R4, G5 and G7, G6 and G8, and B3 and B4 , Sharing the same vertical signal line and sequentially inputting pixels of the same color in the vertical direction to the column ADC circuit, performing A / D conversion by the column ADC circuit of each column, and then performing addition / addition averaging by a counter (for example, , See Patent Document 1).

  For example, as shown in FIG. 30, first, the pixel R1 and the pixel R3 are selected, the pixel signal of the pixel R1 is output to the vertical signal line VSL1, and the pixel signal of the pixel R3 is output to the vertical signal line VSL2. Next, the pixel R2 and the pixel R4 are selected, the pixel signal of the pixel R2 is output to the vertical signal line VSL1, and the pixel signal of the pixel R4 is output to the vertical signal line VSL2.

  That is, the pixel signals of the pixels R1 and R2 are sequentially output to the vertical signal line VSL1, and the pixel signals of the pixels R3 and R4 are sequentially output to the vertical signal line VSL2. Accordingly, the pixel signals of the pixels R1 and R2 are all counted by the counter CNT1, and the pixel signals of the pixels R3 and R4 are both counted by the counter CNT2.

  Similarly, by sequentially selecting other pixels and outputting them to the vertical signal line, the digital data added by the counter in each counter is output.

  FIG. 31A shows a read image in a state of being added by the column ADC circuit, and an image output from the column ADC circuit corresponds to a state in which the number of pixels in the vertical direction is thinned by half.

  Thereafter, the A / D conversion values of the pixels output from the column ADC circuit are transmitted to the subsequent logic signal processing circuit, where they are added and averaged in the horizontal direction. FIG. 31B is a read image in a state of being added by the logic signal processing circuit, and the image output from the logic signal circuit is a state in which the number of pixels is thinned in half in both the vertical and horizontal directions. It corresponds to.

  Incidentally, in recent years, in solid-state imaging devices, white is sometimes used as the main component of the luminance signal in the color arrangement of the color filter array (see, for example, Patent Document 2).

  FIG. 32 is an example of a color arrangement of a color filter array including white. In the color arrangement shown in the figure, white filters are arranged in a checkered pattern every other pixel, and filters of other RGB colors are arranged on the remaining pixels on average. More specifically, the R and B color filters are arranged in a checkered pattern with two vertical and horizontal pixel pitches, the R and B color filters are arranged at an oblique pixel shift, and the remaining pixels are G color filters. Yes. At this time, the G filters are arranged in an oblique stripe shape.

  In such a color arrangement, it is difficult to add and average by the column ADC circuit, so the A / D conversion value of the pixel output from the column ADC circuit is transmitted to the logic signal processing circuit in the subsequent stage. By processing, vertical addition / addition averaging and horizontal addition / addition averaging are performed.

JP 2006-033454 JP 2010-136226 A

  When the addition / addition averaging is performed by the logic signal processing circuit while using the color arrangement shown in FIG. 29, all 16 pixels are selected in the 4 × 4 pixel arrangement, and each of the vertical signal lines is supported. The column ADC circuit provided in this way performs A / D conversion and performs addition / addition averaging. That is, it is necessary to operate all the column ADC circuits even at the time of thinning output, and power consumption applied to the column ADC circuits is not reduced.

  Further, since the addition / addition average value obtained by the A / D conversion needs to be transmitted to the subsequent logical signal processing unit and the horizontal addition / addition averaging must be performed, the subsequent logical signal processing unit receives the received value. Therefore, it is necessary to mount a circuit and a line memory for processing the above, which increases the circuit scale, operation speed, and power consumption. Of course, these disadvantages in the logic signal processing unit can be said to be the same in the case of the color array of the filter array including white shown in FIG.

  Further, in the above-described conventional FD addition method, source follower addition method, counter addition method, and capacitance addition method, when the color arrangement shown in FIG. 32 is adopted, addition / reduction between pixels connected to different vertical signal lines is performed. It was physically difficult to perform thinning output by addition averaging. In the case of the capacity addition method, it is possible to perform thinning output by addition / addition averaging between pixels connected to adjacent vertical signal lines, but it cannot be performed by switching to an output method that does not perform thinning. .

  The present technology has been made in view of the above problems, and performs thinning output by addition / addition averaging between pixels connected to different vertical signal lines without increasing the circuit scale, operation speed, and power consumption. An object of the present invention is to provide a solid-state imaging device capable of satisfying the requirements.

  One aspect of the present technology includes a plurality of pixels arranged in a matrix, including a first pixel and a second pixel, a length direction along the column direction, and a first signal. A plurality of signal lines including a line and a second signal line; a first comparator for comparing a first analog signal output from the first pixel through the first signal line with a reference signal; , A second comparator for comparing the second analog signal output from the second pixel through the second signal line with the reference signal, a first counter, a second counter, A first switch that connects the output terminal of the first comparator and the input terminal of the first counter, and a first switch that connects the output terminal of the first comparator and the input terminal of the second counter. 2 switches, wherein the first switch and the second switch are selectively connected. A body imaging apparatus.

  The above-described solid-state imaging device includes various modes such as being implemented in a state of being incorporated in another device or being implemented together with another method. In addition, the present technology provides an imaging system including the solid-state imaging device, a control method having a process corresponding to the configuration of the above-described device, a program that causes a computer to realize a function corresponding to the configuration of the above-described device, and a computer that records the program It can also be realized as a readable recording medium, a method for manufacturing the solid-state imaging device, and the like.

  According to the present technology, there is provided a solid-state imaging device capable of performing thinning output by addition / averaging between pixels connected to different vertical signal lines without increasing the circuit scale, operation speed, and power consumption. can do.

It is a block diagram which shows the structure of a solid-state imaging device. It is a figure explaining 1st Example of a column process part. It is a table | surface which shows the correspondence of ON / OFF of the switch concerning 1st Example. It is a figure which shows an example of the circuit which implement | achieves the switch concerning 1st Example concretely. It is a truth table of the control signal concerning the 1st example. It is a figure explaining 2nd Example of a column process part. It is a table | surface which shows the correspondence of ON / OFF of the switch concerning 2nd Example. It is a figure which shows an example of the circuit which implement | achieves the switch concerning 2nd Example concretely. It is a truth table of the control signal concerning the 2nd example. It is a circuit diagram which shows an example of the basic pixel circuit of a CMOS image sensor. It is a figure explaining FD sharing pixel unit. It is a circuit diagram which shows an example of the circuit structure of a FD shared pixel unit. It is a figure explaining the structure of the color filter array concerning 1st Example, and a column process part. It is a timing chart concerning the addition operation of the first embodiment. It is a figure which shows the read-out image in the addition operation demonstrated referring FIG. It is a timing chart which shows the addition operation of 1st Example performed adjusting a gain. It is a figure of the read-out image obtained as a result of the gain adjustment shown in FIG. It is a figure explaining the structure of the color filter array concerning 2nd Example, and a column process part. It is a timing chart concerning the addition operation of 2nd Example. It is a figure which shows the read-out image in the addition operation demonstrated referring FIG. It is a timing chart which shows the addition operation of 2nd Example performed adjusting a gain. It is a figure of the read-out image obtained as a result of the gain adjustment shown in FIG. It is a figure explaining the structure of the color filter array and column process part concerning 3rd Example. It is a timing chart concerning the addition operation of 3rd Example. FIG. 25 is a diagram showing a read image in the addition operation described with reference to FIGS. It is a timing chart which shows the addition operation of 3rd Example performed adjusting a gain. It is a figure of the read-out image obtained as a result of the gain adjustment shown in FIG. It is a figure explaining the connection relation concerning a 3rd modification. It is a figure which shows an example of the pixel addition performed by the column ADC circuit at the time of using a Bayer arrangement | sequence as a color filter array. 32 is a timing chart at the time of pixel addition in the column ADC circuit of FIG. 31. FIG. 32 is a read image when the column ADC circuit of FIG. 31 is used. FIG. It is an example of the color arrangement | sequence of the color filter array containing white.

Hereinafter, embodiments of the present technology will be described in the following order.
(1) Configuration of solid-state imaging device:
(2) First embodiment of pixel addition:
(3) Second embodiment of pixel addition:
(4) Third embodiment of pixel addition:
(5) Various modifications:

(1) Configuration of solid-state imaging device:
FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device. In this embodiment, a CMOS image sensor which is a kind of XY address type solid-state imaging device will be described as an example of the imaging device.

  In the following description, it is assumed that NMOS is used for all the pixels of the CMOS image sensor. However, this is only an example, and the device that is the subject of the present technology is not limited to the MOS solid-state imaging device. For example, a semiconductor for physical quantity distribution detection that reads out signals by address control, in which multiple unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix All embodiments to be described later can be applied to all of the apparatuses in the same manner.

  The solid-state imaging device 100 includes a pixel unit in which a plurality of pixels including a light receiving element that outputs a signal corresponding to the amount of incident light is two-dimensionally arranged in a matrix, and a signal output from each pixel is a voltage signal. A / D converters (ADC; Analog Digital Converter) are provided in parallel in a column.

  Here, column parallel means that the same number of A / D converters as vertical signal lines (an example of column signal lines) arranged in parallel to the vertical columns of pixels constituting the image sensor are connected to each vertical signal line. It is arranged in parallel so as to correspond to one-to-one, and means that one A / D conversion unit is associated with one line (one vertical signal line).

  As a typical example in which ADC circuits are provided in parallel in a column, a column type in which an analog signal processing unit and an ADC circuit are provided for each vertical signal line in a portion called a column region provided on the output side of the imaging unit, and sequentially read to the output side belongs to.

  In addition to the column type (column parallel type), a mode in which one ADC circuit is assigned to a plurality of adjacent (for example, two) vertical signal lines, or every N (N is a positive integer; between A mode in which one ADC circuit is assigned to N vertical signal lines (N-1) is also possible.

  In any configuration other than the column type, since a plurality of vertical signal lines share one ADC circuit, a switching circuit that supplies pixel signals for a plurality of columns supplied from the pixel array unit 30 to one ADC circuit ( Switch). Depending on the subsequent processing, a separate measure such as providing a memory for holding the output signal is required.

  As the A / D conversion method, various methods are considered from the viewpoint of circuit scale, processing speed (acceleration), resolution, and the like. For example, a slope integration type or a ramp signal comparison type (hereinafter referred to as the present specification). (Referred to as a reference signal comparison type).

  In the reference signal comparison type A / D conversion method, the analog signal to be A / D converted is compared with a ramp-like reference signal (ramp wave) whose value gradually changes, and the duration of the comparison process is counted. The digital value of the analog signal to be subjected to A / D conversion is acquired based on the count value obtained by doing so. In this embodiment, a ramp signal comparison type A / D conversion method is used.

  When a reference signal comparison type A / D conversion method is employed, a plurality of reference signal generation units may be provided. For example, a reference signal generation unit that supplies a reference signal to an odd-numbered column in a vertical signal line and a reference signal generation unit that supplies a reference signal to an even-numbered column are provided, or provided in parallel (for each vertical signal line). It is also possible to do.

  However, providing a plurality of reference signal generation units increases the circuit scale and power consumption. Therefore, in this embodiment, the reference signal generation unit is provided in common for all the columns, and the column type ADC circuit provided in correspondence with each vertical signal sequence uses the reference signal generated from the reference signal generation unit in common. It is as composition to do.

  Hereinafter, a specific example of the solid-state imaging device will be described with reference to FIG. In FIG. 1, the solid-state imaging device 100 includes a color filter array 10 and a semiconductor substrate 20.

  The semiconductor substrate 20 includes a pixel array unit 30, a vertical driving unit 40, a horizontal driving unit 50, a timing control unit 60, a column processing unit 70, a reference signal generation unit 80, and an output circuit 90. Yes. If necessary, a digital operation unit may be provided in front of the output circuit 90. The digital arithmetic unit is provided, for example, when performing a process of thinning out pixel signals in the horizontal direction or the vertical direction by addition or addition averaging.

  The pixel array unit 30 is provided with a color filter array 10 in which filter colors are divided corresponding to each pixel on the light receiving surface side, and pixels PXL included in photodiodes as photoelectric conversion elements are arranged in a matrix. . The specific circuit configuration of the pixel PXL and the color arrangement of the color filter array 10 will be described in detail later.

  In the pixel array section 30, n pixel drive lines HSLn (n is an integer of 2 or more) and m vertical signal lines VSLm (m is an integer of 2 or more) are wired. The pixel drive lines HSLn are wired at equal intervals along the horizontal direction (pixel arrangement direction / horizontal direction of the pixel row) in the figure, and the vertical signal lines VSLm are arranged in the vertical direction (pixel arrangement direction / vertical direction of the pixel column). ) At equal intervals.

  One end of the pixel drive line HSLn is connected to an output end corresponding to each row of the vertical drive unit 40. One end of the vertical signal line VSLm is connected to an ADC circuit corresponding to each vertical signal line VSLm in the column processing unit 70. Note that specific wiring of the pixel drive line HSLn and the vertical signal line VSLm will be described together with the description of a unit pixel described later.

  A drive control unit including a vertical drive unit 40, a horizontal drive unit 50, a timing control unit 60, and the like is provided outside the pixel array unit 30, and performs control to sequentially read signals from each pixel constituting the pixel array unit 30.

  The timing control unit 60 includes a timing generator and a communication interface. The timing generator generates various clock signals based on an externally input clock (master clock). The communication interface receives data instructing an operation mode given from the outside of the semiconductor substrate 20 and outputs data including internal information of the solid-state imaging device 100.

  Based on the master clock, the timing controller 60 generates a clock having the same frequency as the master clock, a clock obtained by dividing the clock by two, a low-speed clock obtained by dividing the clock, and the like, for example, vertical drive To the unit 40, the horizontal driving unit 50, the column processing unit 70, and the like.

  The vertical drive unit 40 includes a shift register, an address decoder, and the like, and includes a vertical address setting unit for controlling row addresses and a row scanning control unit for controlling row scanning. The vertical drive unit 40 can perform readout scanning and sweep-out scanning.

  The readout scan is a scan that sequentially selects unit pixels from which signals are read out. This scanning is basically performed in order in units of rows. However, when thinning out pixels by adding or averaging the outputs of a plurality of pixels having a predetermined positional relationship, the scanning is performed in a predetermined order described later. .

  The sweep-out scan is a scan that resets the unit pixels belonging to the row or pixel combination to be read ahead of the readout scan by the time of the shutter speed before the row or pixel combination to be read by the readout scan. is there.

  The horizontal driving unit 50 sequentially selects the ADC circuit of the column processing unit 70 in synchronization with the clock output from the timing control unit 60 and guides the signal to the horizontal signal line (horizontal output line) Ltrf.

  The horizontal drive unit 50 defines, for example, a horizontal readout column (selects individual ADC circuits in the column processing unit 70) and a column according to a readout address defined by the horizontal address setting unit. A horizontal scanning unit that guides each signal of the processing unit 70 to the horizontal signal line Ltrf is provided.

  By the selective scanning by the horizontal scanning unit, the pixel signals subjected to signal processing by each ADC circuit configuring the column processing unit 70 are sequentially output to the output circuit 90 via the horizontal signal line Ltrf.

  The reference signal generation unit 80 includes a DAC (Digital Analog Converter), and is a saw-tooth that changes in time stepwise from the initial value supplied from the timing control unit 60 in synchronization with the count clock supplied from the timing control unit 60 A waveform (ramp waveform) is generated and supplied to each ADC circuit of the column processing unit 70 as a reference signal. Hereinafter, the reference signal generation unit 80 may be referred to as a DAC 80.

  Note that the reference signal generation unit 80 can adjust the inclination of the reference signal by adjusting the cycle of the count clock. For example, when the clock divided by 1 / m with respect to the reference clock is used, the inclination is reduced. 1 / m can be set. At this time, if the count clock supplied to a counter (described later) included in the ADC circuit is left as a reference, the count value becomes m times. That is, the count value in the counter described later can be adjusted by adjusting the cycle of the count clock.

  For example, when an analog value for two pixels is sequentially counted by an ADC circuit as will be described later, the A / D conversion range is doubled to make the generated count value an addition average for two pixels. This can be achieved. When the reference signal of the reference signal generation unit 80 is used, for example, the A / D conversion range can be doubled by making the slope of the reference signal twice that of a normal clock.

  The column processing unit 70 includes an ADC circuit 71m (m is an integer of 2 or more) provided for each vertical signal line VSLm, converts an analog signal output from each vertical signal line VSLm into a digital signal, and a horizontal driving unit. 50 is output to the horizontal signal line Ltrf according to the control of 50. In the following description, when the ADC circuit 71m and its internal configuration (comparator 72m, counter 73m, memory 74m) are described without a number corresponding to m, the description is common to the ADC circuits. .

  In the present embodiment, the ADC circuit 71 includes a comparator (comparator) 72, a counter 73, and a memory 74, as shown in FIGS. The ADC circuit 71 is an example of an A / D conversion unit.

  The comparator 72 receives the reference signal generated by the reference signal generation unit 80 and the analog pixel signal output from the pixel through the vertical signal line, and compares the reference signal with the pixel signal. The comparator 72 outputs a high-level or low-level signal according to the magnitude relationship between the reference signal and the pixel signal. When the magnitude relationship between the reference signal and the pixel signal is switched, the output becomes the high level. Invert between low levels.

  The counter 73 is supplied with a clock from the timing control unit 60 and counts the time from the start to the end of A / D conversion (counting operation valid period). The start and end timing of A / D conversion can be specified based on the start timing of the change of the reference signal and the output inversion of the comparator 72. This is because the output inversion of the comparator 72 corresponds to the comparison start and comparison completion of the reference signal and the pixel signal.

  The count value generated by the counter 73 is a digital value, which is digital data corresponding to an analog pixel signal input from the pixel to the column processing unit 70 through the vertical signal line VSLm. The digital data generated by the counter 73 is held (latched) in the memory 74.

  Note that when the count value is generated using the reset component, the counter 73 performs, for example, down-counting while the analog signal corresponding to the reset component is output from the vertical signal line VSLm according to the control of the timing control unit 60. While the operation is performed and an analog signal corresponding to the signal component is output from the vertical signal line, an up-count opposite to that for the reset component is performed. The count value generated in this way is a digital value corresponding to the difference between the signal component and the reset component, and is a signal component calibrated with the reset component.

  The output circuit 90 performs a process of converting a signal corresponding to the color array of the color filter array 10 output from the pixel array unit 30 via the column processing unit 70 into a signal corresponding to the color array by arithmetic processing. Do.

  FIG. 2 is a diagram for explaining a first embodiment of the column processing unit 70. In the figure, for the sake of simplicity, only two vertical signal lines are shown, and only two ADC circuits included in the column processing unit 70 are also shown.

  In the figure, the column processing unit 70 includes ADC circuits 711 and 712 and a switch circuit SWa. Each ADC circuit 71 includes a comparator 72, a counter 73, and a memory 74. The comparator 72 and the counter 73 included in each ADC circuit 71 are connected via the switch circuit SWa. The functions of the comparator, counter, and memory are as described above.

  The switch circuit SWa includes switches SWa11, SWa12, SWa21, and SWa22. The comparator 721 and the counter 731 are connected via the switch SWa11, and the comparator 722 and the counter 732 are connected via the switch SWa22. The comparator 721 and the counter 732 are connected via the switch SWa12, and the comparator 722 and the counter 731 are connected via the switch SWa21.

  That is, the switch circuit SWa includes a switch connecting a comparator and a counter provided corresponding to the same vertical signal line, a comparator provided corresponding to one of a pair of adjacent vertical signal lines, and the other And a switch for connecting between the counters arranged corresponding to the.

  By connecting these two types of switches, a counter provided corresponding to one vertical signal line and a counter provided corresponding to the other vertical signal line among a pair of adjacent vertical signal lines. And either one of them can be selectively counted.

  Specifically, if the switch SWa11 is turned on, the analog signal of the pixel connected to the vertical signal line VSL1 can be digitally converted and held by the counter 731. If the switch SWa12 is turned on, the vertical signal line VSL1 is held. The analog signal of the pixel connected to can be digitally converted by the counter 732 and held.

  If the switch SWa22 is turned on, the analog signal of the pixel connected to the vertical signal line VSL2 can be digitally converted and held by the counter 732, and if the switch SWa21 is turned on, the analog signal is connected to the vertical signal line VSL2. The analog signal of the pixel can be digitally converted by the counter 731 and held.

  Furthermore, the count while the switch SWa11 is turned on and the count while the switch SWa21 is turned on are added together by counter addition, so that the pixel value of the pixel connected to the vertical signal line VSL1 and the vertical signal line VSL2 The counter 731 can generate digital data obtained by adding together the pixel values of the pixels connected to.

  Similarly, the count while the switch SWa22 is turned on and the count while the switch SWa12 is turned on are added together by counter addition, so that the pixel value of the pixel connected to the vertical signal line VSL1 and the vertical signal line The counter 732 can generate digital data obtained by adding together the pixel values of the pixels connected to the VSL2.

  Note that the counter addition can be realized by continuing the count using the count value of the one pixel signal as the initial value of the count of the other pixel signal after the count of the one pixel signal is completed.

The on / off control of the switches SWa11, SWa12, SWa21, and SWa22 is performed according to the control of the timing control unit 60 (switching control unit) that is performed through the SW control line.
FIG. 3 is a table showing the on / off correspondence of the switches SWa11, SWa12, SWa21, and SWa22.

  As shown in the figure, the switch SWa11 and the switch SWa12 are alternatively turned on, and the switch SWa22 and the switch SWa21 are alternatively turned on. On the other hand, the on / off of the switch SWa11 and the switch SWa22 is interlocked, and the on / off of the switch SWa12 and the switch SWa21 is also interlocked.

  Hereinafter, the column processing unit 70 connected in such a manner that the outputs can be interchanged between the ADC circuits corresponding to a pair of adjacent vertical signal lines is referred to as a “cross wiring type column processing unit”. is there.

  As described above, by appropriately selecting a counter in charge of A / D conversion with a switch, digital data obtained by adding together pixel values of pixels respectively connected to a pair of adjacent vertical signal lines is stored in one counter. Can be generated.

  The switch circuit SWa is formed as a part of the column processing unit 60 and is arranged in the column portion (outside the pixel array). That is, the switch circuit SWa is not particularly limited in arrangement, and has an advantage that it can be handled in various combinations depending on the pixel arrangement. Further, since the input destination of a digital value called a comparator (comparator) output that can only take either High / Low is switched, care of noise at the time of switching is easy.

  FIG. 4 is a diagram illustrating an example of a circuit that specifically realizes the switches SWa11, SWa12, SWa21, and SWa22. The switch shown in the figure has a complementary switch configuration in which an NMOS transistor and a PMOS transistor are combined.

  These complementary switches are controlled by a control signal transmitted through two control lines La1 and La2. Hereinafter, the control signal transmitted through the control line La1 is referred to as CROSS, and the control signal transmitted through the control line La2 is referred to as XCROSS.

  The complementary switch is an analog switch including two complementary MOS field effect transistors, and its source-drain circuit is arranged in parallel between the input terminal and the output terminal of the switch to control the switch. It is an analog switch that can directly apply a control signal to the gate of one channel type MOS field effect transistor and can apply it to the gate of the other channel type MOS field effect transistor via a negator. .

  The control signals CROSS, XCROSS are signals obtained by logically inverting positive and negative, and the output of the comparator provided corresponding to one vertical signal line is applied to the same one vertical signal line according to the state of the signal. It is possible to input to a counter provided correspondingly or input to a counter provided corresponding to the other vertical signal line.

FIG. 5 is a truth table of the control signals XCROSS and CROSS.
As shown in the figure, when the control signal XCROSS transmitted through the control line La1 is positive logic (High) and the control signal CROSS transmitted through the control line La2 is negative logic (Low), the switch SWa11. , SWa22 is turned on, and switches SWa12, SWa21 are turned off.

  At this time, the output of the comparator provided corresponding to one vertical signal line is input to the counter provided corresponding to the same vertical signal line. That is, an analog pixel signal output from one vertical signal line is converted into digital data as a count value in a counter provided corresponding to the same one vertical signal line.

  On the other hand, when the control signal XCROSS transmitted through the control line La1 is negative logic and the control signal CROSS transmitted through the control line La2 is positive logic, the switches SWa11 and SWa22 are turned off and the switches SWa12 and SWa21 are switched on. Turn on.

  At this time, the output of the comparator provided corresponding to one vertical signal line is input to the counter provided corresponding to the other vertical signal line. That is, an analog pixel signal output from one vertical signal line is converted into digital data as a count value in a counter provided corresponding to the other vertical signal line.

  According to the complementary switch described above, a switch circuit can be realized with a simple circuit configuration by a combination of a PMOS field effect transistor and an NMOS field effect transistor. In addition, a switch circuit can be incorporated in a process for manufacturing a CMOS LSI.

  FIG. 6 is a diagram for explaining a second embodiment of the column processing unit 70. In the figure, for the sake of simplicity, only two vertical signal lines are shown, and only two ADC circuits included in the column processing unit 70 are also shown.

  In the figure, the column processing unit 70 includes ADC circuits 711 and 712 and a switch circuit SWb. The ADC circuit 71 includes a comparator 72, a counter 73, and a memory 74. The comparator 72 and the counter 73 included in the ADC circuit 71 are connected via the switch circuit SWb. The functions of the comparator, counter, and memory are as described above.

  The switch circuit SWb includes switches SWb11, SWb12, SWb22, and SWb23. The comparator 721 and the counter 731 are connected via the switch SWb11, and the comparator 722 and the counter 732 are connected via the switch SWb22. The comparator 721 and the counter 732 are connected via the switch SWb12, and the counter 733 included in the comparator 722 and the ADC circuit 713 (not shown) is connected via the switch SWb23.

  That is, the switch circuit SWb includes a switch for connecting a comparator and a counter provided corresponding to the same one vertical signal line, a comparator provided corresponding to one vertical signal line, and the one vertical signal line. And a switch for connecting a counter provided corresponding to a vertical signal line adjacent to one side of the signal line. Note that the one side mentioned here is, for example, the right side in FIG. 6 and is the same side for all the vertical signal lines provided in one solid-state imaging device.

  Therefore, either the counter provided corresponding to the vertical signal line or the counter provided corresponding to the vertical signal line provided adjacent to one side of the vertical signal line is selected and counted. Can be performed.

  When the switch SWb11 is turned on, the analog signal of the pixel connected to the vertical signal line VSL1 can be digitally converted and held by the counter 731. When the switch SWb12 is turned on, the analog signal is connected to the vertical signal line VSL1. The analog signal of the pixel thus obtained can be digitally converted and held by the counter 732.

  If the switch SWb22 is turned on, the analog signal of the pixel connected to the vertical signal line VSL2 can be digitally converted and held by the counter 732, and if the switch SWb23 is turned on, the vertical signal line VSL3 (not shown) is held. The analog signal of the pixel connected to can be digitally converted and held by a counter 733 (not shown).

  Further, if the count while the switch SWb12 is turned on and the count while the switch SWb22 is turned on are added together by counter addition, the pixel value of the pixel connected to the vertical signal line VSL1 and the vertical signal line VSL1 The counter 732 can generate digital data obtained by adding together the pixel values of the pixels connected to the vertical signal line VSL2 provided adjacent to the right side.

  Similarly, if the count while the switch SWb23 is turned on and the count while the switch SWb33 (not shown) is turned on are added together by counter addition, the pixel value of the pixel connected to the vertical signal line VSL2 Digital data obtained by adding the pixel values of the pixels connected to the vertical signal line VSL3 (not shown) can be generated by the counter 733 (not shown). Note that the vertical signal line VSL3 (not shown) is a vertical signal line provided adjacent to the right side of the vertical signal line VSL2, and the counter 733 (not shown) is a counter provided corresponding to the vertical signal line VSL3. .

Each switch is controlled to be turned on / off according to the control of the timing control unit 60 (switching control unit) performed through the SW control line.
FIG. 7 is a table showing the on / off correspondence relationship of the switches SWb11, SWb12, SWb22, and SWb23. Note that the on / off correspondence relationship between the switches SWb11, SWb12, SWb22, and SWb23 is periodically applied to the switches provided on the right side of the switches SWb11, SWb12, SWb22, and SWb23. For example, the above-described switch SWb33 (not shown) has the same ON / OFF correspondence relationship as the switch SWb11.

  As shown in the figure, the switch SWb11 and the switch SWb12 are alternatively turned on, and the switch SWb22 and the switch SWb23 are alternatively turned on. On the other hand, the on / off of the switch SWb11 and the switch SWb22 is linked, and the on / off of the switch SWb12 and the switch SWb23 is also linked.

  In the following description, a column processing unit connected so that the output of each vertical signal line can be shifted to a vertical signal line adjacent to one side of the output is sometimes referred to as a “shift wiring type column processing unit”.

  As described above, the A / D conversion of the pixel signal of the pixel connected to each vertical signal line is shifted to one side from the counter provided corresponding to the vertical signal line and the vertical signal line. Generate digital data by summing pixel values of pixels connected to two adjacent vertical signal lines by selectively performing between counters provided corresponding to the provided vertical signal lines. Can do.

  Note that the switch circuit SWb is formed as a part of the column processing unit 60 as in the case of the above-described cross wiring column processing unit, and is arranged in the column portion (outside the pixel array). That is, the switch circuit SWb is not particularly limited in arrangement, and has an advantage that it can be handled in various combinations depending on the pixel arrangement. Further, since the input destination of a digital value called a comparator (comparator) output that can only take either High / Low is switched, care of noise at the time of switching is easy.

  FIG. 8 is a diagram illustrating an example of a circuit that specifically realizes the switches SWb11, SWb12, SWb22, and SWb23. The switch shown in the figure has a complementary switch configuration in which an NMOS transistor and a PMOS transistor are combined as in the case of FIG. 4 described above.

FIG. 9 is a truth table of the control signals XCROSS and CROSS.
As shown in the figure, when the control signal XCROSS transmitted through the control line Lb1 is positive logic (High) and the control signal CROSS transmitted through the control line La2 is negative logic (Low), the switch SWb11 , SWb22 is turned on, and switches SWb12, SWb23 are turned off. Therefore, the output of the comparator provided corresponding to each vertical signal line is input to the counter provided corresponding to the same vertical signal line. That is, the analog pixel signal output from each vertical signal line is converted into digital data as a count value in a counter provided corresponding to the same vertical signal line.

  On the other hand, when the control signal XCROSS transmitted through the control line Lb1 is negative logic (Low) and the control signal CROSS transmitted through the control line Lb2 is positive logic (High), the switches SWb11 and SWb22 are turned off. The switches SWb12 and SWb23 are turned on. Therefore, the output of the comparator provided corresponding to each vertical signal line is input to the counter provided corresponding to the vertical signal line provided adjacent to the right side. That is, the analog pixel signal output from each vertical signal line is converted into digital data as a count value in a counter provided corresponding to the vertical signal line provided adjacent to the right side.

  According to the complementary switch described above, a switch circuit can be realized with a simple circuit configuration by combining a PMOS field effect transistor and an NMOS field effect transistor, as in the case of the column processing unit on the cross wiring side. In addition, a switch circuit can be incorporated in a process for manufacturing a CMOS LSI.

  Next, a specific circuit configuration of the unit pixel will be described. The pixel PXL of the present embodiment has a configuration in which the floating diffusion FD is shared by a plurality of pixels (for example, 4 pixels). Hereinafter, a basic pixel configuration will be described first, and then the floating diffusion FD is converted to 4 pixels. The configuration shared in the above will be described.

  FIG. 10 is a circuit diagram showing an example of a basic pixel circuit of a CMOS image sensor composed of four transistors. The pixel circuit shown in the figure includes a photodiode PXL1 as a light receiving element, a transfer transistor PXL2 as a transfer element, a reset transistor PXL3 as a reset element, an amplification transistor PXL4, and a selection transistor PXL5.

  The photodiode PXL1 photoelectrically converts incident light into an amount of electric charges (here, electrons) corresponding to the amount of light.

  The transfer transistor PXL2 is connected between the cathode of the photodiode PXL1 and the floating diffusion FD as an output node. The transfer transistor PXL2 is turned on when a transfer signal is input to its gate (transfer gate) through the transfer control line Ltrg. When the transfer transistor PXL2 is turned on, the signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiode PXL1 are transferred to the floating diffusion FD.

  The reset transistor PXL3 has a drain connected to the power supply line LVDD and a source connected to the floating diffusion FD. In the reset transistor PXL3, a reset signal is input to the gate from the vertical driving unit 40 through the reset control line Lrst. Prior to the charge transfer from the photodiode PXL1, the reset transistor PXL3 is turned on when a reset pulse is given, and the charge of the floating diffusion FD is discarded to the power supply line LVDD, thereby changing the potential of the floating diffusion FD to the potential of the power supply line LVDD. Reset to.

  The gate of the amplification transistor PXL4 is connected to the floating diffusion FD. The amplification transistor PXL4 is connected to the vertical signal line VSL via the selection transistor PXL5.

  The selection transistor PXL5 is turned on when a control signal (address signal or select signal) is input to its gate through the selection control line Lsel.

  When the selection transistor PXL5 is turned on, the amplification transistor PXL4 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the vertical signal line VSL. The voltage output from each pixel through the vertical signal line VSL is output to the column processing unit 70.

  Next, a pixel circuit that shares the floating diffusion FD with a plurality of pixels will be described. Hereinafter, a plurality of pixels sharing the floating diffusion FD will be referred to as an FD sharing pixel unit.

  FIG. 11 is a diagram illustrating the FD sharing pixel unit. In the figure, a pixel array is configured by 4 × 4 16 pixels, each of which is configured by a combination of FD shared pixel units U1 to U4 configured by 2 × 2 4 pixels. Each FD sharing pixel unit shares the FD at the center thereof, the vertical signal line VSL1 is connected to the FDs of the FD sharing pixel units U1 and U3, and the vertical signal line VSL2 is connected to the FD sharing pixel units U2 and U4. Connected to FD.

  In each FD shared pixel unit, among a plurality of pixels belonging to the same row, pixels having a common positional relationship with respect to the FD in each FD shared pixel unit are driven by the same pixel drive line. Pixels that do not share a positional relationship with reference to are driven by different pixel drive lines.

  Specifically, in FIG. 11, the pixels P11 to P14, the pixels P21 to P24, the pixels P31 to P34, and the pixels P41 to P44 belong to the same row, and the pixel P11 to P14 is taken as an example. And the pixel P13 are driven by the same pixel drive line, and the pixel P12 and the pixel P14 are driven by the same pixel drive line.

  Of course, the combination of the pixel and the pixel drive line described here is an example, and it goes without saying that various changes can be made. For example, by simultaneously driving two or more of a plurality of pixels sharing the FD, a value obtained by adding the analog values of the two pixels is generated in the FD, and the analog value obtained by the FD addition is output to the vertical signal line. You can also

Next, a specific circuit configuration of the FD sharing pixel unit will be described.
FIG. 12 is a circuit diagram illustrating an example of a circuit configuration of the FD sharing pixel unit.

In the figure, the FD sharing pixel unit U is composed of pixels P11, P12, P21, and P22.
In the FD sharing pixel unit U, each unit pixel includes one photodiode PD11, PD12, PD21, PD22 and one transfer transistor Ttrs11, Ttrs12, Ttrs21, Ttrs22.

  Transfer control lines Ltrg1 and Ltrg2 are wired to the row where the pixels P11 and P12 are arranged, and transfer control lines Ltrg3 and Ltrg4 are wired to the row where the pixels P21 and P22 are arranged.

  The transfer control line Ltrg1 is connected to the gate of the transfer transistor Ttrs11 of the pixel P11 in the first column, and the transfer control line Ltrg2 is connected to the gate of the transfer transistor Ttrs12 of the pixel P12 in the first column. The transfer control line Ltrg3 is connected to the gate of the transfer transistor Ttrs21 of the pixel P21 in the second column, and the transfer control line Ltrg4 is connected to the gate of the transfer transistor Ttrs22 of the pixel P22 in the second column.

  The transfer control lines Ltrg1, Ltrg2, Ltrg3, and Ltrg4 can be individually driven by the vertical driving unit 40, and the charge output from the photodiode of each unit pixel to the floating diffusion FD can be individually controlled for each unit pixel. .

  On the other hand, the FD sharing pixel unit U includes one floating diffusion FD, one reset transistor Tres, one amplification transistor Tamp, and one selection transistor Tsel for the four pixels P11, P12, P21, and P22. .

  The reset control line Lrst is connected to the gate of the reset transistor Tres, and the selection control line Lsel is connected to the gate of the selection transistor Tsel.

  That is, the reset of the floating diffusion FD, the amplification of the voltage accumulated in the floating diffusion, and the output of the signal to the vertical signal line VSL are executed in common in the FD sharing pixel unit U.

  Note that the FD sharing pixel circuit described above is an example, and the number of unit pixels sharing the FD and the arrangement of the unit pixels can be changed as appropriate. For example, the number of unit pixels sharing the FD may be 3 × 3 9 pixels or 8 × 8 64 pixels. The unit pixels sharing the FD may be configured to share the FD among 4 pixels of 1 × 4, that is, 4 pixels arranged in a vertical row, or 4 pixels of 4 × 1, that is, 4 pixels arranged in a horizontal row. The FD may be shared.

(2) First example of pixel addition:
Next, a first example of pixel addition will be described. In the first embodiment, a color filter array including white is employed, and the above-described cross wiring type is employed for the column processing unit.

  FIG. 13 is a diagram illustrating the configuration of the color filter array and the column processing unit according to the first embodiment. The color filter array shown in the figure shows 4 × 4 16 pixels for the sake of simplicity.

  In the color filter array shown in the figure, W (white) filters with the highest output level are arranged in a checkered pattern, and R (red) and B (blue) filters are arranged in a checkered pattern with a vertical and horizontal pixel pitch. In addition, the R and B filters are arranged at an oblique pixel shift, and the remaining pixels are G (green) filters. At this time, the G filters are arranged in an oblique stripe shape.

  Specifically, the W filter is arranged in a checkered pattern, the R filter is arranged in the fourth column of the second row and the second column of the fourth row, and the B filter is arranged in the third and third rows of the first row. Arranged in the first column. The arrangement of these R filters and B filters is a checkered arrangement with a two-pixel pitch.

  Then, G filters are arranged at the remaining pixel positions. Of course, the color arrangement of the color filter array including white is not limited to this, and it goes without saying that various color arrangements can be adopted.

In the pixel array, 4 pixels of 2 × 2 in length and width form an FD shared pixel unit.
Specifically, the upper left four pixels (G1, G2, W1, W2) constitute one FD shared pixel unit, and the lower left four pixels (B2, R2, W5, W6) constitute one FD shared pixel unit. Configure. These FD shared pixel units are connected to the vertical signal line VSL1 through each shared FD.

  The upper right four pixels (B1, R1, W3, W4) constitute one FD shared pixel unit, and the lower right four pixels (G3, G4, W7, W8) constitute one FD shared pixel unit. . These FD shared pixel units are connected to the vertical signal line VSL2 through the shared FD.

  The pixel signal output through the vertical signal line VSL1 is input to the comparator 721. The comparator 721 determines the magnitude of the reference signal and the pixel signal input from the DAC 80. For example, when a ramp wave that gradually increases is used as the reference signal, the comparator 721 outputs Low when the reference signal is smaller than the pixel signal, and outputs High when the reference signal becomes equal to or higher than the pixel signal.

  On the other hand, the pixel signal output through the vertical signal line VSL 2 is input to the comparator 722. The comparator 722 determines whether the reference signal and the pixel signal input from the DAC 80 are large or small. For example, when a ramp wave that gradually increases is used as the reference signal, the comparator 722 outputs Low when the reference signal is smaller than the pixel signal, and outputs High when the reference signal becomes equal to or higher than the pixel signal.

  The output terminal of the comparator 721 is connected to a counter 731 provided corresponding to the vertical signal line VSL1 through the switch SWa11 and connected to a counter 732 provided corresponding to the vertical signal line VSL2 through the switch SWa12. Yes. The vertical signal line VSL2 is a vertical signal line arranged adjacent to the vertical signal line VSL1.

  The output terminal of the comparator 722 is connected to a counter 732 provided corresponding to the vertical signal line VSL2 through the switch SWa22, and connected to a counter 731 provided corresponding to the vertical signal line VSL1 through the switch SWa21. The vertical signal line VSL1 is a vertical signal line arranged adjacent to the vertical signal line VSL2.

  The switches SWa11, SWa12, SWa22, and SWa21 are controlled to be turned on and off by an SW control signal that the timing control unit 60 outputs through the SW control line. These switches are turned on and off to satisfy the relationship shown in FIG.

FIG. 14 is a timing chart according to the addition operation of the first embodiment.
First, the addition operation of white pixels that are the main components of luminance will be described. To add white pixels, the switches SWa11 and SWa22 are turned on, and the switches SWa12 and SWa21 are turned off.

Then, the pixel W1 and the pixel W3 are selected, the pixel signal of the pixel W1 is output to the vertical signal line VSL1, and the pixel signal of the pixel W3 is output to the vertical signal line VSL2. Next, the pixel W2 and the pixel W4 are selected, the pixel signal of the pixel W2 is output to the vertical signal line VSL1, and the pixel signal of the pixel W4 is output to the vertical signal line VSL2.
That is, the pixel signals of the pixels W1 and W2 are sequentially output to the vertical signal line VSL1, and the pixel signals of the pixels W3 and W4 are sequentially output to the vertical signal line VSL2.

  Here, since the switches SWa11 and SWa22 are on and the switches SWa12 and SWa21 are off, the pixel signals of the pixels W1 and W2 are both counted by the counter 731 and the pixel signals of the pixels W3 and W4 are both Is also counted by the counter 732.

  Further, the counter 731 continues the count without being initialized until the count of the pixel signals of both the pixels W1 and W2 is completed under the control of the timing control unit 60. Therefore, the count value of the counter 731 is digital data corresponding to the sum of the pixel signals of the pixels W1 and W2.

  Similarly, the counter 732 continues counting without being initialized until the counting of both pixel signals of the pixels W3 and W4 is completed under the control of the timing control unit 60. Therefore, the count value of the counter 732 is digital data corresponding to the sum of the pixel signals of the pixels W3 and W4.

  In other words, the timing control unit 60 does not initialize the counters 731 and 732 to count the count value until the count for the two pixels to be added is completed, and the count value for the two pixels to be added is finished. Is output to the memories 741 and 742 (see FIG. 2), the count values of the counters 731 and 732 are initialized.

  When the counting of the pixel signals for two pixels is completed, the counters 731 and 732 output the count values to the memories 741 and 742 under the control of the timing control unit 60, respectively.

  As a result, the memory 741 and 742 store digital data obtained by adding the pixels W1 and W2 and digital data obtained by adding the pixels W3 and W4, respectively. The digital data stored in the memories 741 and 742 is output to the output circuit 90 through the horizontal signal line during the addition process executed next under the control of the timing control unit 60.

  For other pixels W5, W6, W7, and W8 which are white pixels, the same addition operation is performed, so that the digital data obtained by adding the pixels W5 and W6 to the memories 741 and 742 and the digital data obtained by adding the pixels W7 and W8 Are respectively stored and output to the output circuit 90 through the horizontal signal line during the addition process executed next under the control of the timing control unit 60.

  Next, the adding operation of R, G, and B pixels will be described. In this embodiment, the addition operation for the white pixels is performed first, and the addition operation for the RGB pixels is performed later. Of course, this order is reversed or performed alternately, or the order is appropriately changed. It goes without saying that it is good.

  To add R, G, and B pixels, first, the switches SWa11 and SWa22 are turned off, and the switches SWa12 and SWa21 are turned on. Then, the pixel G1 and the pixel B1 are selected, the pixel signal of the pixel G1 is output to the vertical signal line VSL1, and the pixel signal of the pixel B1 is output to the vertical signal line VSL2.

  Here, since the switches SWa11 and SWa22 are off and the switches SWa12 and SWa21 are on, the pixel signal of the pixel G1 output through the vertical signal line VSL1 is provided corresponding to the adjacent vertical signal line VSL2. The pixel signal of the pixel B1 counted by the counter 732 and output through the vertical signal line VSL2 is counted by the counter 731 provided corresponding to the adjacent vertical signal line VSL1.

  Next, the switches SWa11 and SWa22 are turned on, and the switches SWa12 and SWa21 are turned off. Then, the pixel B2 and the pixel G3 are selected, the pixel signal of the pixel B2 is output to the vertical signal line VSL1, and the pixel signal of the pixel G3 is output to the vertical signal line VSL2.

  Here, since the switches SWa11 and SWa22 are closed and the switches SWa12 and SWa21 are off, the pixel signal of the pixel B2 output through the vertical signal line VSL1 is counted by the counter 731 and output through the vertical signal line VSL2. The pixel signal of the pixel G3 is counted by the counter 732.

  The counter 731 continues counting until the counting of the two pixels of the pixels B1 and B2 is completed under the control of the timing control unit 60 in the same manner as when white is counted. Therefore, the count value of the counter 731 is the pixel B1, This is digital data corresponding to the sum of the pixel signals of B2.

  Similarly, the counter 732 continues counting until the counting of the two pixels G1 and G3 is completed under the control of the timing control unit 60. Therefore, the count value of the counter 732 is the pixel signal of the pixels G1 and G3. Digital data corresponding to the sum is obtained.

  When the counting of the pixel signals for two pixels is completed, the counters 731 and 732 output the count values to the memories 741 and 742 under the control of the timing control unit 60, respectively.

  That is, the timing control unit 60 does not initialize the counter values 731 and 732 until the counting for two pixels is completed, and initializes the count values of the counters 731 and 732 when the counting for two pixels is completed.

  As a result, the memory 741 and 742 store digital data obtained by adding the pixels B1 and B2 and digital data obtained by adding the pixels G1 and G3, respectively. The digital data stored in the memories 741 and 742 is output to the output circuit 90 through the horizontal signal line during the addition process executed next under the control of the timing control unit 60.

  By performing the same addition operation for the pixels R1, R2, G2, and G4, the memory 741 and 742 store the digital data obtained by adding the pixels R1 and R2 and the digital data obtained by adding the pixels G2 and G4, respectively. Under the control of the timing control unit 60, the signal is output to the output circuit 90 through the horizontal signal line during the addition process to be executed next.

  FIG. 15 is a diagram showing a read image in the addition operation described with reference to FIGS. As shown in FIG. 15A, by performing the above-described addition operation, digital data obtained by adding white pixels adjacent to each other in the diagonal direction is acquired for the white pixels, and two pixels in the diagonal direction are acquired for the RGB pixels. Digital data obtained by adding the pixels of the same color apart is obtained.

  However, as shown in FIG. 15B, the addition value of the white pixel obtained by the addition operation of the timing chart shown in FIG. 14 corresponds to the pixel value at the center of the FD sharing pixel unit, but the addition of the RGB pixels. The value corresponds to a pixel value at a position outside the center of the FD sharing pixel unit.

  Therefore, when performing the addition operation, by adjusting the gain in the A / D conversion, the finally obtained pixel addition value can be adjusted so as to approach the center pixel value of the FD sharing pixel unit. .

  FIG. 16 is a timing chart showing the addition operation of the first embodiment performed while adjusting the gain. The gain adjustment can be realized, for example, by adjusting the inclination of the reference signal generated by the reference signal generation unit 80 as described above. That is, the slope of the reference signal can be reduced to increase the gain, and the slope of the reference signal can be increased to reduce the gain.

  As shown in the figure, a gain of 12 dB is applied when reading out the pixels B1, G1, R2, and G4, and a gain of 0 dB is applied when reading out the pixels W1 to W8 and the pixels B2, G3, R1, and G2. That is, by adjusting one gain of the two pixels added in FIG. 15 to be higher than the other, the position corresponding to the added value is adjusted to be closer to the pixel position having the higher gain. Needless to say, the gain values described here are merely examples and can be arbitrarily adjusted.

  FIG. 17 is a diagram of a read image obtained as a result of the gain adjustment shown in FIG.

  As shown in FIG. 17, when the gain of the pixel B1 is made higher than that of the pixel B2, the position where the added value of the pixel B1 and the pixel B2 corresponds becomes closer to the pixel position of the pixel B1, and the gain of the pixel G1 is made higher than that of the pixel G3. As a result, the position where the added value of the pixel G1 and the pixel G3 corresponds is close to the pixel position of the pixel G1, and the position where the added value of the pixel R1 and the pixel R2 corresponds by setting the gain of the pixel R2 higher than the pixel R1 By approaching the pixel position of the pixel R2, and making the gain of the pixel G4 higher than that of the pixel G2, the position corresponding to the added value of the pixel G2 and the pixel G4 is close to the pixel position of the pixel G4.

  Since the positions corresponding to the added values of the white pixels W1 to W8 originally corresponded to the center of each pixel unit, there is no need to perform gain adjustment in the first embodiment, which is the same as FIG. 15B. Corresponds to the position.

(3) Second embodiment of pixel addition:
Next, a second embodiment of pixel addition will be described. In the second embodiment, a color filter array including white is employed, and the above-described shift wiring type is employed for the column processing unit.

  FIG. 18 is a diagram illustrating the configuration of the color filter array and the column processing unit according to the second embodiment. The color filter array shown in the figure shows 4 × 4 16 pixels as in the first embodiment described above, and W filters having the highest output level are arranged in a checkered pattern, and each of the R and B filters Are arranged in a checkered pattern with a vertical and horizontal two-pixel pitch, the R and B filters are arranged with a diagonal pixel shift, and the remaining pixels are G filters.

  In the pixel array, 4 pixels of 2 × 2 in length and width form an FD shared pixel unit.

  Specifically, the upper left four pixels (B1, R1, W1, W2) constitute one FD shared pixel unit, and the lower left four pixels (G3, G4, W5, W6) constitute one FD shared pixel unit. Configure. These FD shared pixel units are connected to the vertical signal line VSL1 through each shared FD.

  The upper right four pixels (G1, G2, W3, W4) constitute one FD shared pixel unit, and the lower right four pixels (B, R, W7, W8) constitute one FD shared pixel unit. . These FD shared pixel units are connected to the vertical signal line VSL2 through the shared FD.

  Note that the two pixels (B2, R2) shown in the lower left are pixels connected to a vertical signal line VSL0 (not shown) adjacent to the left side of the vertical signal line VSL1, and the counter 731 is turned on when the switch SWb01 is turned on. Will be counted.

  A pixel signal output through a vertical signal line VSL0 (not shown) is input to a comparator 720 (not shown) provided corresponding to the vertical signal line VSL0. The comparator 720 determines whether the reference signal and the pixel signal input from the DAC 80 are large or small. For example, when a ramp wave that increases gradually is used as the reference signal, the comparator 720 outputs Low when the reference signal is smaller than the pixel signal, and outputs High when the reference signal is equal to or higher than the pixel signal.

  The pixel signal output through the vertical signal line VSL1 is input to the comparator 721. The comparator 721 determines the magnitude of the reference signal and the pixel signal input from the DAC 80. For example, when a ramp wave that gradually increases is used as the reference signal, the comparator 721 outputs Low when the reference signal is smaller than the pixel signal, and outputs High when the reference signal becomes equal to or higher than the pixel signal.

  The pixel signal output through the vertical signal line VSL2 is input to the comparator 722. The comparator 722 determines whether the reference signal and the pixel signal input from the DAC 80 are large or small. For example, when a ramp wave that gradually increases is used as the reference signal, the comparator 722 outputs Low when the reference signal is smaller than the pixel signal, and outputs High when the reference signal becomes equal to or higher than the pixel signal.

  The output terminal of the comparator 720 (not shown) is connected through SWb01 to a counter 731 provided corresponding to the vertical signal line VSL1.

  The output terminal of the comparator 721 is connected to a counter 731 provided corresponding to the vertical signal line VSL1 through the switch SWb11 and connected to a counter 732 provided corresponding to the vertical signal line VSL2 through the switch SWb12. Yes. The vertical signal line VSL2 is a vertical signal line arranged adjacent to the right side of the vertical signal line VSL1.

  The output terminal of the comparator 722 is connected to the counter 732 provided corresponding to the vertical signal line VSL2 through the switch SWb22, and connected to the counter 733 provided corresponding to the vertical signal line VSL3 (not shown) through the switch SWb23. ing. The vertical signal line VSL3 is a vertical signal line arranged adjacent to the right side of the vertical signal line VSL2.

  The switches SWb01, SWb11, SWb12, SWb22, and SWb23 are controlled to be turned on / off by the SW control signal output from the timing control unit 60 through the SW control line. These switches are turned on and off so as to satisfy the relationship shown in FIG.

FIG. 19 is a timing chart according to the addition operation of the second embodiment.
First, the addition operation of white pixels that are the main components of luminance will be described. To add white pixels, the switches SWb11 and SWb22 are turned on, and the switches SWb12 and SWb23 are turned off.

Then, the pixel W1 and the pixel W3 are selected, the pixel signal of the pixel W1 is output to the vertical signal line VSL1, and the pixel signal of the pixel W3 is output to the vertical signal line VSL2. Next, the pixel W2 and the pixel W4 are selected, the pixel signal of the pixel W2 is output to the vertical signal line VSL1, and the pixel signal of the pixel W4 is output to the vertical signal line VSL2.
That is, the pixel signals of the pixels W1 and W2 are sequentially output to the vertical signal line VSL1, and the pixel signals of the pixels W3 and W4 are sequentially output to the vertical signal line VSL2.

  Here, since the switches SWb11 and SWb22 are turned on and the switches SWb12 and SWb23 are turned off, the pixel signals of the pixels W1 and W2 are all counted by the counter 731, and the pixel signals of the pixels W3 and W4 are both Is also counted by the counter 732.

  Further, the counter 731 continues the count without being initialized until the count of the pixel signals of both the pixels W1 and W2 is completed under the control of the timing control unit 60. Therefore, the count value of the counter 731 is digital data corresponding to the sum of the pixel signals of the pixels W1 and W2.

  Similarly, the counter 732 continues counting without being initialized until the counting of both pixel signals of the pixels W3 and W4 is completed under the control of the timing control unit 60. Therefore, the count value of the counter 732 is digital data corresponding to the sum of the pixel signals of the pixels W3 and W4.

  In other words, the timing control unit 60 does not initialize the counters 731 and 732 to count the count value until the count for the two pixels to be added is completed, and the count value for the two pixels to be added is finished. Is output to the memories 741 and 742 (see FIG. 2), the count values of the counters 731 and 732 are initialized.

  When the counting of the pixel signals for two pixels is completed, the counters 731 and 732 output the count values to the memories 741 and 742 under the control of the timing control unit 60, respectively.

  As a result, the memory 741 and 742 store digital data obtained by adding the pixels W1 and W2 and digital data obtained by adding the pixels W3 and W4, respectively. The digital data stored in the memories 741 and 742 is output to the output circuit 90 through the horizontal signal line during the addition process executed next under the control of the timing control unit 60.

  For other pixels W5, W6, W7, and W8 which are white pixels, the same addition operation is performed, so that the digital data obtained by adding the pixels W5 and W6 to the memories 741 and 742 and the digital data obtained by adding the pixels W7 and W8 Are respectively stored and output to the output circuit 90 through the horizontal signal line during the addition process executed next under the control of the timing control unit 60.

  Next, the adding operation of R, G, and B pixels will be described. In the second embodiment, the addition operation for the white pixels is performed first, and the addition operation for the RGB pixels is performed later. Of course, this order is reversed or performed alternately, or the order is appropriately changed. Needless to say, it can be replaced.

  To add R, G, and B pixels, first, the switches SWb11 and SWb22 are turned on, and the switches SWb12 and SWb23 (and the switch SWb01) are turned off. Then, the pixel B1 and the pixel G1 are selected, the pixel signal of the pixel B1 is output to the vertical signal line VSL1, and the pixel signal of the pixel G1 is output to the vertical signal line VSL2.

  Here, since the switches SWb11 and SWb22 are turned on and the switches SWb12 and SWb23 are turned off, the pixel signal of the pixel B1 output through the vertical signal line VSL1 is a counter 731 provided corresponding to the vertical signal line VSL1. The pixel signal of the pixel G1 output through the vertical signal line VSL2 is counted by a counter 732 provided corresponding to the vertical signal line VSL2.

  Next, the switches SWb11 and SWb22 are turned off, and the switches SWb12 and SWa23 (and the switch SWb01) are turned on. Then, the pixel B2 and the pixel G3 are selected, the pixel signal of the pixel B2 is output to the vertical signal line VSL0 (not shown), and the pixel signal of the pixel G3 is output to the vertical signal line VSL1.

  Here, since the switches SWb11 and SWb22 are turned off and the switches SWb12 and SWb23 (and the switch SWb01) are turned on, the pixel signal of the pixel B2 output through the vertical signal line VSL0 (not shown) is counted by the counter 731. The pixel signal of the pixel G3 output through the vertical signal line VSL1 is counted by the counter 732.

  The counter 731 continues counting until the counting of the two pixels of the pixels B1 and B2 is completed under the control of the timing control unit 60 in the same manner as when white is counted. Therefore, the count value of the counter 731 is the pixel B1, This is digital data corresponding to the sum of the pixel signals of B2.

  Similarly, the counter 732 continues counting until the counting of the two pixels G1 and G3 is completed under the control of the timing control unit 60. Therefore, the count value of the counter 732 is the pixel signal of the pixels G1 and G3. Digital data corresponding to the sum is obtained.

  When the counting of the pixel signals for two pixels is completed, the counters 731 and 732 output the count values to the memories 741 and 742 under the control of the timing control unit 60, respectively.

  That is, the timing control unit 60 does not initialize the counter values 731 and 732 until the counting for two pixels is completed, and initializes the count values of the counters 731 and 732 when the counting for two pixels is completed.

  As a result, the memory 741 and 742 store digital data obtained by adding the pixels B1 and B2 and digital data obtained by adding the pixels G1 and G3, respectively. The digital data stored in the memories 741 and 742 is output to the output circuit 90 through the horizontal signal line during the addition process executed next under the control of the timing control unit 60.

  By performing the same addition operation for the pixels R1, R2, G2, and G4, the memory 741 and 742 store the digital data obtained by adding the pixels R1 and R2 and the digital data obtained by adding the pixels G2 and G4, respectively. Under the control of the timing control unit 60, the signal is output to the output circuit 90 through the horizontal signal line during the addition process to be executed next.

  FIG. 20 is a diagram showing a read image in the addition operation described with reference to FIGS. As shown in FIG. 20A, by performing the above-described addition operation, digital data obtained by adding white pixels adjacent to each other in the diagonal direction is acquired for the white pixels, and two pixels in the diagonal direction are acquired for the RGB pixels. Digital data obtained by adding the pixels of the same color apart is obtained.

  However, as shown in FIG. 20B, the addition value of the white pixel obtained by the addition operation of the timing chart shown in FIG. 19 corresponds to the pixel value at the center of the FD sharing pixel unit. The value corresponds to a pixel value at a position outside the center of the FD sharing pixel unit.

  Therefore, when performing the addition operation, by adjusting the gain in the A / D conversion, the finally obtained pixel addition value can be adjusted so as to approach the center pixel value of the FD sharing pixel unit. .

  FIG. 21 is a timing chart showing the addition operation of the second embodiment performed while adjusting the gain.

  As shown in the figure, a gain of 6 dB is applied when reading out the pixels B1, G1, R1, and G2, and a gain of 0 dB is applied when reading out the pixels W1 to W8 and the pixels B2, G3, R2, and G4. That is, by adjusting one gain of the two pixels to be added in FIG. 20 higher than the other, the position corresponding to the addition value is adjusted to be closer to the pixel position having the higher gain.

  In order to adjust the added value of the pixels more accurately to correspond to the central pixel value of the FD sharing pixel unit, the gains of the pixels B1, G1, R1, and G2 and the pixels B2, G3, R2, and G4 When the gains of the pixels B2, G3, R2, and G4 are 0 dB so that the ratio to the gain is 3: 1, the gains of the pixels B1, G1, R1, and G2 are set to 6.64 dB.

  FIG. 22 is a diagram of a read image obtained as a result of the gain adjustment shown in FIG.

  As shown in FIG. 22, by making the gain of the pixel B1 higher than that of the pixel B2, the position where the added values of the pixel B1 and the pixel B2 correspond to the pixel position of the pixel B1, and the gain of the pixel G1 is made higher than that of the pixel G3. As a result, the position where the added value of the pixel G1 and the pixel G3 corresponds is close to the pixel position of the pixel G1, and the position where the added value of the pixel R1 and the pixel R2 corresponds by setting the gain of the pixel R2 higher than that of the pixel R1. By approaching the pixel position of the pixel R2, and making the gain of the pixel G4 higher than that of the pixel G2, the position corresponding to the added value of the pixel G2 and the pixel G4 is close to the pixel position of the pixel G4.

  Note that the white pixels W1 to W8 originally corresponded to the center of each pixel unit at the position corresponding to the added value, and thus the gain adjustment is not performed in the second embodiment, and the same position as in FIG. It corresponds to.

(4) Third embodiment of pixel addition:
Next, a third embodiment of pixel addition will be described. In the third embodiment, a conventional Bayer color filter array is employed, and the above-described cross wiring type is employed for the column processing section.

  FIG. 23 is a diagram illustrating the configuration of the color filter array and the column processing unit according to the third embodiment. The color filter array shown in the figure shows 4 × 4 pixels corresponding to 16 pixels as in the first embodiment described above. In the pixel array, 4 pixels of 2 × 2 in length and width form an FD shared pixel unit.

  Specifically, the upper left four pixels (R1, B1, G, G) constitute one FD shared pixel unit, and the lower left four pixels (G2, G4, R, B) constitute one FD shared pixel unit. Configure. These FD shared pixel units are connected to the vertical signal line VSL1 through each shared FD.

  The upper right four pixels (R, B, G1, G3) constitute one FD shared pixel unit, and the lower right four pixels (R2, B2, G, G) constitute one FD shared pixel unit. . These FD shared pixel units are connected to the vertical signal line VSL2 through the shared FD.

  The pixel signal output through the vertical signal line VSL1 is input to the comparator 721. The comparator 721 determines the magnitude of the reference signal and the pixel signal input from the DAC 80. For example, when a ramp wave that gradually increases is used as the reference signal, the comparator 721 outputs Low when the reference signal is smaller than the pixel signal, and outputs High when the reference signal becomes equal to or higher than the pixel signal.

  On the other hand, the pixel signal output through the vertical signal line VSL 2 is input to the comparator 722. The comparator 722 determines whether the reference signal and the pixel signal input from the DAC 80 are large or small. For example, when a ramp wave that gradually increases is used as the reference signal, the comparator 722 outputs Low when the reference signal is smaller than the pixel signal, and outputs High when the reference signal becomes equal to or higher than the pixel signal.

  The output terminal of the comparator 721 is connected to a counter 731 provided corresponding to the vertical signal line VSL1 through the switch SWa11 and connected to a counter 732 provided corresponding to the vertical signal line VSL2 through the switch SWa12. Yes. The vertical signal line VSL2 is a vertical signal line arranged adjacent to the vertical signal line VSL1.

  The output terminal of the comparator 722 is connected to a counter 732 provided corresponding to the vertical signal line VSL2 through the switch SWa22, and connected to a counter 731 provided corresponding to the vertical signal line VSL1 through the switch SWa21. The vertical signal line VSL1 is a vertical signal line arranged adjacent to the vertical signal line VSL2.

  The switches SWa11, SWa12, SWa22, and SWa21 are controlled to be turned on and off by an SW control signal that the timing control unit 60 outputs through the SW control line. These switches are turned on and off to satisfy the relationship shown in FIG.

FIG. 24 is a timing chart according to the addition operation of the third embodiment.
First, the switches SWa11 and SWa22 are turned on, and the switches SWa12 and SWa21 are turned off. Then, the pixel R1 is selected, and the pixel signal of the pixel R1 is output to the vertical signal line VSL1. Here, since the switches SWa11 and SWa22 are on and the switches SWa12 and SWa21 are off, the pixel signal of the pixel R1 is counted by the counter 731.

  Next, the switches SWa11 and SWa22 are turned off, and the switches SWa12 and SWa21 are turned on. Then, the pixel R2 is selected, and the pixel signal of the pixel R2 is output to the vertical signal line VSL2. Here, since the switches SWa11 and SWa22 are turned off and the switches SWa12 and SWa21 are turned on, the pixel signal of the pixel R2 is counted by the counter 731.

  The counter 731 continues counting without being initialized until the counting of the pixel signals of both the pixels R1 and R2 is completed under the control of the timing control unit 60. Therefore, the count value of the counter 731 is digital data corresponding to the sum of the pixel signals of the pixels R1 and R2.

  Next, the pixel G1 is selected without changing the switch, and the pixel signal of the pixel G1 is output to the vertical signal line VSL2. Then, the pixel signal of the pixel G1 is counted by the counter 731.

  Next, the switches SWa11 and SWa22 are turned on, and the switches SWa12 and SWa21 are turned off. Then, the pixel G2 is selected, and the pixel signal of the pixel G2 is output to the vertical signal line VSL1. Then, the pixel signal of the pixel G2 is counted by the counter 731.

  In this manner, by alternately repeating the switching of the opening and closing of the switch and the output of the counter value, the pixel addition value can be sequentially output to the output circuit 90 for the other pixels G4, G3, B2, and B1.

  In the third embodiment, since the comparator 722, the counter 732, and the memory 742 provided corresponding to the vertical signal line VSL2 are not used, the power consumption can be reduced by setting these configurations in the standby state. .

  FIG. 25 is a diagram showing a read image in the addition operation described with reference to FIGS. As shown in FIG. 25A, by performing the above-described addition operation, digital data obtained by adding pixels of the same color that are two pixels apart in the oblique direction with respect to the RGB pixels is acquired.

  However, as shown in FIG. 25B, the added value of the RGB pixels obtained by the addition operation of the timing chart shown in FIG. 24 corresponds to the pixel value at a position outside the center of the FD sharing pixel unit.

  Therefore, when performing the addition operation, by adjusting the gain in the A / D conversion, the finally obtained pixel addition value can be adjusted so as to approach the center pixel value of the FD sharing pixel unit. .

  FIG. 26 is a timing chart showing the addition operation of the third embodiment performed while adjusting the gain.

  As shown in the figure, a gain of 6 dB is applied when reading out the pixels R1, G1, G4, and B2, and a gain of 0 dB is applied when reading out the pixels R2, G2, G3, and B1. That is, by adjusting the gain of one of the two pixels added in FIG. 25 to be higher than the other, the position corresponding to the added value is adjusted to be closer to the pixel position having the higher gain.

  FIG. 27 is a diagram of a read image obtained as a result of the gain adjustment shown in FIG.

  As shown in FIG. 27, by making the gain of the pixel R1 higher than that of the pixel R2, the corresponding position of the added value of the pixel R1 and the pixel R2 approaches the pixel position of the pixel R1, and the gain of the pixel G1 is made higher than that of the pixel G2. As a result, the position corresponding to the added value of the pixel G1 and the pixel G2 approaches the pixel position of the pixel G1, and the position corresponding to the added value of the pixel G4 and the pixel G3 is set to the pixel G4 by setting the gain of the pixel G4 higher than that of the pixel G3. When the gain of the pixel B2 is made higher than that of the pixel B1, the position corresponding to the added value of the pixel B2 and the pixel B1 approaches the pixel position of the pixel B2.

(5) Various modifications: (5-1) First modification:
In the embodiment described above, the FD addition method may be used in combination.
That is, a plurality of pixels are selected from the FD sharing pixel unit, and electric charges are output from the photodiodes of the plurality of pixels to the floating diffusion, and the pixel values are analog-added in advance in the floating diffusion FD and output to the vertical signal line.

  For example, in the first embodiment and the second embodiment described above, if two white pixels belonging to one FD sharing pixel unit are output by FD addition, the processing time required for the output of the white pixels is reduced by half. Can do.

(5-2) Second modification:
In the above-described embodiments and modifications, a case where 16 pixels of 4 × 4 pixels are thinned and output to 4 pixels of 2 × 2 pixels has been described as an example, but, of course, 64 pixels of 8 × 8 pixels are horizontally and vertically 2 pixels. Needless to say, it is possible to correspond to various thinning-out levels, such as thinning-out output to 4 pixels of × 2.

(5-3) Third modification:
In the above-described embodiments and modifications, the comparator and counter corresponding to each vertical signal line are connected by the first switch, and the comparator corresponding to each vertical signal line and the counter corresponding to the adjacent vertical signal line are Are connected by the second switch, but the counter to which the second switch is connected is not necessarily limited to the counter corresponding to the adjacent vertical signal line.

  FIG. 28 is a diagram for explaining a connection relationship according to the third modification. This figure shows the basic configuration similar to that of FIG. 2 with the connection relationship of the switch circuit SWa being changed.

  The switch circuit SWa includes switches SWa11, SWa1m, SWam1, and SWamm. The comparator 721 and the counter 731 are connected via the switch SWa11, and the comparator 72m and the counter 73m are connected via the switch SWamm. The comparator 721 and the counter 73m are connected via a switch SWa1m, and the comparator 72m and the counter 731 are connected via a switch SWam1.

  In other words, the switch circuit SWa includes a switch that connects a comparator provided corresponding to one vertical signal line and a counter, a comparator provided corresponding to the one vertical signal line, and the one vertical signal. And a switch for connecting between the signal line and a counter provided corresponding to a different vertical signal line.

  Therefore, one of the counter provided corresponding to one vertical signal line and the counter provided corresponding to the other vertical signal line is selected from the set of vertical signal lines VSL1 and VSLm. Can be counted. The set of vertical signal lines VSL1 and VSLm may or may not be adjacent to each other.

  Accordingly, the pixel values of the pixels connected to the vertical signal line VSL1 and the pixels connected to the vertical signal line VSLm can be added and output by the counter 731 and the counter 73m.

  Here, the cross wiring type column processing unit 70 has been described as an example, but it goes without saying that the third modification can be applied even to the shift wiring type column processing unit 70. No.

(5-4) Fourth modification:
In the above-described embodiments and modifications, one vertical signal line is provided for each of the two pixel columns, but, of course, one vertical signal line may be provided for each pixel column. A configuration may be adopted in which one vertical signal line is provided for each pixel column that is equal to or greater than one column.

  Note that the present technology is not limited to the above-described embodiments and modifications, and configurations in which the configurations disclosed in the above-described embodiments and modifications are mutually replaced or combinations are changed, known technologies, and the above-described implementations. Configurations in which the respective configurations disclosed in the examples and the modified examples are mutually replaced or combinations are changed are also included. The technical scope of the present technology is not limited to the above-described embodiments, but extends to the matters described in the claims and equivalents thereof.

And this technique can take the following composition.
(1) A pixel array section having a plurality of pixels arranged two-dimensionally in a matrix and a plurality of signal lines arranged along the column direction, and the signal line provided in association with each of the signal lines. An A / D converter that converts an analog signal output from a pixel through a line into a digital signal, and the analog signal output through each signal line are provided in association with a signal line through which the analog signal is transmitted. A switching unit that switches between an A / D conversion unit and an A / D conversion unit that is provided in association with a signal line other than the signal line through which the analog signal is transmitted. A solid-state imaging device.

  (2) The A / D converter includes a comparator that compares a time-varying reference signal and an analog signal obtained from a pixel, and a counter that counts the time until the comparison is completed in the comparator, The switching unit is provided corresponding to each signal line, and a first switch for connecting the output terminal of the comparator and the input terminal of the counter in the A / D conversion unit provided corresponding to each signal line. A second switch for connecting an output terminal of the comparator in the A / D conversion unit and an input terminal of the counter in the A / D conversion unit provided corresponding to another signal line; and the first switch, The solid-state imaging device according to (1), further comprising: a switching control unit that controls switching of the second switch.

  (3) The switching unit corresponds to the analog signal output through one of the two signal lines, the A / D conversion unit provided in association with the one signal line, and the other signal line. The solid-state imaging device according to (1) or (2), wherein an A / D conversion unit provided to switch the digital signal is switched.

  (4) The switching unit is an A / D conversion unit provided for each of the plurality of signal lines in association with the analog signal output through each signal line in association with the signal line to which the analog signal is transmitted. And an A / D conversion unit provided in association with a signal line provided adjacent to one side of the signal line to which the analog signal is transmitted, which switches between the conversion to the digital signal ( The solid-state imaging device according to any one of 1) to (3).

  (5) In the plurality of pixels, a predetermined number of pixels share a floating diffusion, and the switching unit performs analog addition of analog signals of two or more pixels sharing the same floating diffusion in the floating diffusion, and The solid-state imaging device according to any one of (1) to (4), which is output to a signal line.

  (6) The plurality of pixels are provided with a color filter array in which a filter color is divided corresponding to each pixel on the light receiving surface side, and the color filter array includes white filters arranged in a checkered pattern, The blue filters are arranged in a checkered pattern with a vertical and horizontal pixel pitch of 2 pixels, the red and blue filters are arranged with a diagonal pixel shift, and the remaining pixels are green filters (1) to (5) The solid-state imaging device according to any one of the above.

  (7) In the plurality of pixels, a color filter array in which a filter color is divided corresponding to each pixel is provided on a light receiving surface side, and the color filter array includes the color filters arranged in a Bayer array. The solid-state imaging device according to any one of (1) to (6).

  (8) A pixel array unit having a plurality of pixels arranged two-dimensionally in a matrix and a plurality of signal lines arranged along the column direction, and the signal line provided in association with each of the signal lines. A solid-state imaging device control method comprising: an A / D converter that converts an analog signal output from a pixel through a line into a digital signal, wherein the analog signal is output from the signal line through the analog signal. Either an A / D conversion unit provided in association with a transmitted signal line or an A / D conversion unit provided in association with a signal line other than the signal line through which the analog signal is transmitted A control method for a solid-state imaging device, comprising a switching step of switching between conversion to a digital signal.

  (9) A pixel array unit having a plurality of pixels arranged two-dimensionally in a matrix and a plurality of signal lines arranged along the column direction, and the signal line provided in association with each of the signal lines. A control program for a solid-state imaging device, comprising: an A / D converter that converts an analog signal output from a pixel through a line into a digital signal, wherein the analog signal is output through each signal line Either an A / D conversion unit provided in association with a transmitted signal line or an A / D conversion unit provided in association with a signal line other than the signal line through which the analog signal is transmitted A control program for a solid-state imaging device, having a switching function for switching between conversion to a digital signal.

DESCRIPTION OF SYMBOLS 10 ... Color filter array, 20 ... Semiconductor substrate, 30 ... Pixel array part, 40 ... Vertical drive part, 50 ... Horizontal drive part, 60 ... Timing control part, 70 ... Column processing part, 71 ... ADC circuit, 72 ... Comparator 73 ... Counter, 74 ... Memory, 80 ... Reference signal generator, 90 ... Output circuit, 100 ... Solid-state imaging device, 711, 712 ... ADC circuit, 721, 722 ... Comparator, 731, 732 ... Counter, 741, 742 ... Memory, CNT1, CNT2 ... Counter, FD ... Floating diffusion, HSLn ... Pixel drive line, La1 ... Control line, La2 ... Control line, Lb1 ... Control line, Lb2 ... Control line, Lrst ... Reset control line, Lsel ... Selection control Line, Ltrf: horizontal signal line, Ltrg: transfer control line, LVDD: power supply line, Ltrg1, Ltrg2, Ltrg , Ltrg4: transfer control line, PXL: pixel, PD11, PD12, PD21, PD22 ... photodiode, PXL1 ... photodiode, PXL2 ... transfer transistor, PXL3 ... reset transistor, PXL4 ... amplification transistor, PXL5 ... selection transistor, SWa ... switch Circuit, SWb ... Switch circuit, SWa11 ... Switch, SWa12 ... Switch, SWa21 ... Switch, SWa22 ... Switch, SWa23 ... Switch, SWb11 ... Switch, SWb12 ... Switch, SWb22 ... Switch, SWb23 ... Switch, Tamp ... Amplifying transistor, Tres ... Reset transistor, Tsel ... select transistor, Ttrs11 ... transfer transistor, Ttrs12 ... transfer transistor, Ttrs21 ... transfer transistor , Ttrs22 ... transfer transistors, U, U1~U4 ... FD sharing pixel unit, VSL ... vertical signal lines, VSL0 ... vertical signal lines, VSL1 ... vertical signal lines, VSL2 ... vertical signal lines, vslm ... vertical signal lines, 73n ... counter

Claims (4)

A plurality of pixels arranged in a matrix and including a first pixel and a second pixel;
A plurality of signal lines including a first signal line and a second signal line, the length direction being arranged along the column direction;
A first comparator that compares a first analog signal output from the first pixel through the first signal line with a reference signal;
A second comparator that compares the second analog signal output from the second pixel through the second signal line with the reference signal;
A first counter;
A second counter;
A first switch connecting the output terminal of the first comparator and the input terminal of the first counter;
A second switch connecting the output terminal of the first comparator and the input terminal of the second counter;
The imaging device in which the first switch and the second switch are selectively connected.   2. The output of the second comparator when the second switch is connected is higher in gain than the output of the first comparator when the first switch is connected. Imaging device.   The reference signal input to the second comparator when the second switch is connected has a smaller slope than the reference signal input to the first comparator when the first switch is connected. The imaging device according to claim 1 or 2.   The imaging device according to claim 1, wherein the second counter is in a standby state.

Images